Phase-locked loop circuit, control method, charge pump and chip

Abstract

This invention provides a phase-locked loop (PLL) circuit, a control method, a charge pump, and a chip. The circuit includes a frequency and phase detector for receiving a reference clock signal and the output signal of a frequency divider to generate a charge / discharge control signal; a charge pump module for determining charging or discharging based on the charge / discharge control signal, determining the charging or discharging current level, and generating a corresponding charging or discharging current based on the determined charging or discharging and the charging or discharging current level; a loop filter for filtering the charging or discharging current; a voltage-controlled oscillator (VCO) for generating a PLL output signal at a preset frequency; and a frequency divider for dividing the PLL output signal, using the divided signal as the output signal, and inputting it to the frequency and phase detector. The circuit provided by this invention, while implementing the PLL function, reduces spurious emissions in the PLL and improves bandwidth characteristics.

Description

Technical Field

[0001] This invention relates to the field of phase-locked loop (PLL) circuit technology, and more particularly to a PLL circuit, control method, charge pump, and chip. Background Technology

[0002] A phase-locked loop (PLL) is a circuit that synchronizes the output frequency-divided signal generated by a voltage-controlled oscillator (VCO) with an input reference signal in both phase and frequency. In the synchronized state (often called locked), the phase difference between the oscillator's output signal and the input reference signal is either zero or a fixed constant. If the phase difference changes, a feedback control mechanism in the PLL adjusts the oscillator's output to reduce the phase difference and eventually achieve a locked state. In this control system, the phase of the output signal is effectively locked to the phase of the input reference signal, which is why the circuit is called a phase-locked loop.

[0003] The frequency multiplication function of phase-locked loop (PLL) circuits is the most common way to obtain high-frequency clocks. They are widely used to generate clocks required for various applications and play an important role in clock data recovery circuits, wireless transceiver circuits, microprocessors, and MCU chips. However, existing PLL circuits have high spurious emissions and poor bandwidth characteristics. Summary of the Invention

[0004] Based on this, the present invention provides a phase-locked loop circuit, including a frequency and phase detector, a charge pump module, a loop filter, a voltage-controlled oscillator, and a frequency divider.

[0005] The frequency and phase detector is used to receive a reference clock signal and the output signal of the frequency divider, and to generate a charge and discharge control signal based on the reference clock signal and the output signal of the frequency divider.

[0006] The charge pump module is used to receive the charge / discharge control signal, determine charging or discharging according to the charge / discharge control signal, determine the current level of charging or discharging, and generate a corresponding charging current or discharging current according to the determined charging or discharging and the current level of charging or discharging.

[0007] The loop filter is used to filter the charging current or discharging current to obtain a control voltage signal;

[0008] The voltage-controlled oscillator is used to generate a phase-locked loop output signal of a preset frequency according to the control voltage signal;

[0009] The frequency divider is used to divide the output signal of the phase-locked loop, and the divided signal is used as the output signal and input to the frequency and phase detector.

[0010] Optionally, the charge pump module includes a charging circuit, a discharging circuit, and a dynamic unit matching module; the dynamic unit matching module is used to determine the charging current level or the discharging current level according to a preset frequency division coefficient; the charging circuit is used to generate the charging current of the charging current level; and the discharging circuit is used to generate the charging current of the discharging current level.

[0011] Optionally, both the charging circuit and the discharging circuit include a plurality of current mirror units. The dynamic unit matching module is further configured to determine the number of current mirror units in the charging circuit or the discharging circuit that are turned on according to the charging current level or the discharging current level, and to turn on the current mirror units in the charging circuit or the discharging circuit according to the number of units turned on.

[0012] Optionally, the current mirror unit in the charging circuit includes a first P-type field-effect transistor and a first switch. One end of the first switch is connected to a bias voltage, the other end of the first switch is connected to the gate of the first P-type field-effect transistor, the source of the first P-type field-effect transistor is connected to a power supply, and the drain of the first P-type field-effect transistor is connected to the dynamic unit matching module.

[0013] Optionally, the current mirror unit in the discharge circuit includes a first N-type field-effect transistor and a second switch. One end of the second switch is connected to a bias voltage, and the other end of the second switch is connected to the gate of the first N-type field-effect transistor. The source of the first N-type field-effect transistor is grounded, and the drain of the first N-type field-effect transistor is connected to the dynamic unit matching module.

[0014] Optionally, the dynamic unit matching module includes a first dynamic unit matcher and / or a second dynamic unit matcher;

[0015] The first dynamic unit matcher is used to determine the charging current level according to a preset frequency division coefficient, determine the number of current mirror units in the charging circuit to be turned on according to the charging current level, and turn on the current mirror units in the charging circuit according to the number of units turned on.

[0016] The second dynamic unit matching unit is used to determine the discharge current level according to a preset frequency division coefficient, determine the number of current mirror units in the discharge circuit to be turned on according to the discharge current level, and turn on the current mirror units in the discharge circuit according to the number of units turned on.

[0017] Optionally, the dynamic unit matching module includes a first dynamic unit matcher and / or a second dynamic unit matcher;

[0018] The first dynamic unit matcher is used to determine the charging current level according to a preset frequency division coefficient, determine the number of current mirror units in the charging circuit to be turned on according to the charging current level, and randomly turn on the current mirror units in the charging circuit according to the number of turns on.

[0019] The second dynamic unit matching unit is used to determine the discharge current level according to a preset frequency division coefficient, determine the number of current mirror units in the discharge circuit to be turned on according to the discharge current level, and randomly turn on the current mirror units in the discharge circuit according to the number of units turned on.

[0020] Optionally, the charge pump module further includes a third switch and a fourth switch, one end of the third switch being connected to the charging circuit and the other end of the third switch being connected to the loop filter; one end of the fourth switch being connected to the discharging circuit and the other end of the fourth switch being connected to the loop filter.

[0021] Optionally, the phase-locked loop circuit further includes a bias voltage generation circuit, which includes a second P-type field-effect transistor, a second N-type field-effect transistor, a third N-type field-effect transistor, and a reference current source.

[0022] One end of the reference current source is connected to the source of the second P-type field-effect transistor, the drain of the second P-type field-effect transistor is connected to the gate, and the gate of the second P-type field-effect transistor is also connected to one end of the gate of the first switch in the charging circuit.

[0023] The drain of the second N-type field-effect transistor is connected to the other end of the reference current source. The gate of the second N-type field-effect transistor is connected to the gate of the third N-type field-effect transistor. The source of the second N-type field-effect transistor is grounded to the source of the third N-type field-effect transistor. The gates of the second N-type field-effect transistor and the gate of the third N-type field-effect transistor are connected to one end of the discharge circuit where the second switch is connected to the bias voltage.

[0024] The present invention also provides a phase-locked loop control method, comprising the following steps:

[0025] Obtain a reference clock signal and a frequency divider signal, and generate a charge / discharge control signal based on the phase difference between the reference clock signal and the frequency divider signal;

[0026] The charging or discharging is determined according to the charging or discharging control signal, the charging or discharging current level is determined according to the preset frequency division coefficient, and the corresponding charging current or discharging current is generated according to the determined charging or discharging and the charging or discharging current level.

[0027] The charging current or discharging current is filtered to obtain a control voltage signal;

[0028] A phase-locked loop output signal of a preset frequency is generated based on the control voltage signal;

[0029] The frequency-divided signal is obtained by dividing the output signal of the phase-locked loop.

[0030] The present invention also provides a charge pump, which is used to receive the charge / discharge control signal, determine charging or discharging according to the charge / discharge control signal, determine the current level for charging or discharging, and generate a corresponding charging current or discharging current according to the determined charging or discharging and the current level for charging or discharging.

[0031] The present invention also provides a chip comprising the phase-locked loop circuit or the charge pump described in any of the above technical solutions.

[0032] The beneficial effects of this invention are as follows: A frequency and phase detector receives a reference clock signal and the output signal of a frequency divider, and generates a charge / discharge control signal based on the reference clock signal and the output signal of the frequency divider; a charge pump module receives the charge / discharge control signal, determines charging or discharging based on the charge / discharge control signal, determines the charging or discharging current level, and generates a corresponding charging current or discharging current based on the determined charging or discharging and the charging or discharging current level; a loop filter filters the charging current or discharging current to obtain a control voltage signal; a voltage-controlled oscillator generates a phase-locked loop output signal of a preset frequency based on the control voltage signal; while realizing the phase-locked loop function, it reduces spurious signals in the phase-locked loop and improves bandwidth characteristics. Attached Figure Description

[0033] Figure 1 This is a circuit block diagram of the phase-locked loop circuit according to the first embodiment of the present invention;

[0034] Figure 2 This is a circuit diagram of the phase-locked loop circuit according to the first embodiment of the present invention;

[0035] Figure 3 This is a schematic block diagram of the charge pump module according to the first embodiment of the present invention;

[0036] Figure 4 This is a circuit diagram of the charge pump module according to the first embodiment of the present invention;

[0037] Figure 5 This is a schematic flowchart of the phase-locked loop control method according to the second embodiment of the present invention. Detailed Implementation

[0038] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0039] It should be noted that when a component is said to be "fixed to" another component, it can be directly attached to the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0041] Figure 1 This is a circuit block diagram of the phase-locked loop circuit according to the first embodiment of the present invention. It should be noted that if substantially the same result is achieved, the circuit of the present invention is not necessarily identical. Figure 1 The circuit schematic shown is for reference only. Figure 1 As shown, the phase-locked loop circuit includes a phase-frequency detector (PFD), a charge pump module (CP), a loop filter (LPF), a voltage-controlled oscillator (VCO), and a frequency divider (DIV).

[0042] The frequency and phase detector (PFD) is used to receive a reference clock signal and the output signal of the frequency divider, and to generate a charge and discharge control signal based on the reference clock signal and the output signal of the frequency divider.

[0043] The charge pump module CP is used to receive the charge and discharge control signal, determine charging or discharging according to the charge and discharge control signal, determine the current level of charging or discharging, and generate a corresponding charging current or discharging current according to the determined charging or discharging and the current level of charging or discharging.

[0044] The loop filter LPF is used to filter the charging current or discharging current to obtain a control voltage signal;

[0045] The voltage-controlled oscillator (VCO) is used to generate a phase-locked loop output signal of a preset frequency based on the control voltage signal.

[0046] The frequency divider DIV is used to divide the output signal of the phase-locked loop, and the divided signal is used as the output signal and input to the frequency and phase detector.

[0047] It should be noted that the charge / discharge control signal is generated based on the reference clock signal and the output signal of the frequency divider. Specifically, the charge / discharge control signal is generated based on the phase difference between the reference clock signal and the output signal of the frequency divider.

[0048] In one implementation, the phase-locked loop circuit includes a phase-frequency discriminator (PFD), a charge pump module (CP), a loop filter (LPF), a voltage-controlled oscillator (VCO), and a frequency divider (DIV). The phase-frequency discriminator detects the phase difference between the input reference clock (clkin) and the divided feedback clock (clkdiv), and outputs a control signal (UP) or (DN). The UP signal controls the charge pump module to charge, and the DN signal controls the charge pump module to discharge. The output current of the charge pump passes through the loop filter to obtain the control voltage (Vc) of the VCO. Vc adjusts the output clock frequency of the VCO. The adjusted output clock frequency (clkout) is divided by the frequency divider and returns to the phase-frequency discriminator, thus forming a feedback loop.

[0049] In some embodiments, the loop filter LPF includes capacitor C1, capacitor C2 and resistor R1. One end of resistor R1 is connected to the output terminal of the charge pump module, the other end of resistor R1 is connected to one end of capacitor C1, the other end of capacitor C1 is connected to one end of capacitor C2, and the other end of capacitor C2 is connected to the input terminal of the voltage-controlled oscillator.

[0050] As one implementation method, the circuit diagram of the phase-locked loop circuit is as follows: Figure 2 As shown, Figure 2 In this context, clkin is the input reference clock, clkdiv is the divided feedback clock, and the loop filter LPF includes capacitors C1 and C2 and resistor R1. The transfer function of the loop filter LPF is...

[0051]

[0052] The gain of the phase-locked loop circuit can be approximated as follows:

[0053]

[0054] The zero point of the gain of a phase-locked loop circuit is

[0055]

[0056] The second pole of the gain of a phase-locked loop circuit is

[0057]

[0058] The phase margin PM of the phase-locked loop circuit is

[0059]

[0060]

[0061] The unity-gain bandwidth of a phase-locked loop circuit is

[0062]

[0063] Natural frequency

[0064]

[0065] Damping factor

[0066]

[0067] Among them, I cp K represents the output current of the charge pump module. vco is the gain of the voltage-controlled oscillator, and N is the frequency division coefficient.

[0068] For a phase-locked loop circuit used for frequency multiplication, considering that the input reference comes from a high-precision crystal oscillator with excellent phase noise performance, the loop bandwidth should be designed to be as close as possible to 1 / 20 of the input reference, because this provides the best phase noise suppression effect for the ring oscillator VCO.

[0069] The loop bandwidth and damping factor of a phase-locked loop (PLL) circuit are negatively correlated with the frequency division factor N. As the frequency division factor N increases, to ensure the bandwidth ω... c If it remains unchanged, I should be increased appropriately. cp Based on the charge pump current segmentation technology, the loop characteristics of the phase-locked loop circuit can be kept at an optimal value within a wide frequency division coefficient range. In other words, the phase-locked loop circuit can achieve a wide output frequency range while ensuring performance.

[0070] In some embodiments, the charge pump module includes a charging circuit, a discharging circuit, and a dynamic unit matching module; the dynamic unit matching module is used to determine the charging current level or the discharging current level according to a preset frequency division coefficient; the charging circuit is used to generate the charging current of the charging current level; the discharging circuit is used to generate the charging current of the discharging current level.

[0071] As one implementation method, the principle block diagram of the charge pump module is as follows: Figure 3 As shown. Figure 3 The charge pump module includes a charging circuit 301, a discharging circuit 302, and a dynamic unit matching module 303.

[0072] In some embodiments, both the charging circuit and the discharging circuit include a plurality of current mirror units. The dynamic unit matching module is further configured to determine the number of current mirror units in the charging circuit or the discharging circuit that are turned on according to the charging current level or the discharging current level, and to turn on the current mirror units in the charging circuit or the discharging circuit according to the number of current mirror units turned on.

[0073] As an example, the current mirror units in the charging or discharging circuit are randomly turned on according to the corresponding number of turns. By randomly turning on the current mirror units, the mismatch between the current mirror units can be eliminated, that is, the mismatch between the charging current and the discharging current can be eliminated.

[0074] As one implementation method, the circuit schematic of the charge pump module is as follows: Figure 4 As shown, Figure 4 In this context, clkin is the input reference clock, and the dynamic cell matching module includes a first dynamic cell matcher DEM1 and a second dynamic cell matcher DEM2.

[0075] In some embodiments, the current mirror unit in the charging circuit includes a P-type field-effect transistor and a switch. One end of the switch is connected to a bias voltage, the other end of the switch is connected to the gate of the P-type field-effect transistor, the source of the P-type field-effect transistor is connected to a power supply, and the drain of the P-type field-effect transistor is connected to the dynamic unit matching module.

[0076] As an example, the charging circuit includes P-type field-effect transistors PM1 to PMK and switches SWP0 to SWPK, where K is the number of current mirror units. The gates of P-type field-effect transistors PM1 to PMK are respectively connected to one end of switches SWP1 to SWPK, and the other end of switches SWP1 to SWPK is connected to the bias voltage Vbiasp. The sources of P-type field-effect transistors PM1 to PMK are all connected to the power supply voltage VDD, and the drains are connected to the corresponding interfaces of the dynamic unit matching module.

[0077] In some embodiments, the current mirror unit in the discharge circuit includes an N-type field-effect transistor and a switch. One end of the switch is connected to a bias voltage, and the other end of the switch is connected to the gate of the N-type field-effect transistor. The source of the N-type field-effect transistor is grounded, and the drain of the N-type field-effect transistor is connected to the dynamic unit matching module.

[0078] As an example, the discharge circuit includes N-type field-effect transistors NM1 to NMK, with the gate terminals of NM1 to NMK respectively connected to one end of switches SWN1 to SWNK, and the other end of switches SWN1 to SWNK connected to a bias voltage Vbiasn. The sources of NMOS transistors NM1 to NMK are all grounded, and their drains are connected to the corresponding interfaces of the dynamic unit matching module.

[0079] In some embodiments, the dynamic unit matching module includes a first dynamic unit matcher and a second dynamic unit matcher;

[0080] The first dynamic unit matcher is used to determine the charging current level according to a preset frequency division coefficient, determine the number of current mirror units in the charging circuit to be turned on according to the charging current level, and turn on the current mirror units in the charging circuit according to the number of units turned on.

[0081] The second dynamic unit matching unit is used to determine the discharge current level according to a preset frequency division coefficient, determine the number of current mirror units in the discharge circuit to be turned on according to the discharge current level, and turn on the current mirror units in the discharge circuit according to the number of units turned on.

[0082] It should be noted that the dynamic unit matching module includes a first dynamic unit matcher and a second dynamic unit matcher, that is, the dynamic unit matching module includes two DEM (dynamic unit matching) logics and frequency multiplication coefficient logic controls.

[0083] In some embodiments, the dynamic unit matching module includes a first dynamic unit matcher and / or a second dynamic unit matcher;

[0084] The first dynamic unit matcher is used to determine the charging current level according to a preset frequency division coefficient, determine the number of current mirror units in the charging circuit to be turned on according to the charging current level, and randomly turn on the current mirror units in the charging circuit according to the number of turns on.

[0085] The second dynamic unit matching unit is used to determine the discharge current level according to a preset frequency division coefficient, determine the number of current mirror units in the discharge circuit to be turned on according to the discharge current level, and randomly turn on the current mirror units in the discharge circuit according to the number of units turned on.

[0086] It should be noted that the dynamic unit matching module includes a first dynamic unit matcher and / or a second dynamic unit matcher, meaning that the dynamic unit matching module includes a first dynamic unit matcher and a second dynamic unit matcher, or the dynamic unit matching module includes either a first dynamic unit matcher or a second dynamic unit matcher.

[0087] In some embodiments, the charge pump module further includes a third switch and a fourth switch, one end of the third switch being connected to the charging circuit and the other end of the third switch being connected to the loop filter; one end of the fourth switch being connected to the discharging circuit and the other end of the fourth switch being connected to the loop filter.

[0088] It should be noted that when the dynamic unit matching module includes a first dynamic unit matcher and a second dynamic unit matcher, one end of the third switch is indirectly connected to the charging circuit through the first dynamic unit matcher, and one end of the fourth switch is indirectly connected to the discharging circuit through the second dynamic unit matcher; when the dynamic unit matching module includes only the first dynamic unit matcher, one end of the fourth switch is directly connected to the discharging circuit through the second dynamic unit matcher; when the dynamic unit matching module includes only the second dynamic unit matcher, one end of the third switch is directly connected to the charging circuit through the first dynamic unit matcher.

[0089] In some embodiments, the charge pump module further includes a switch SWP0 and a switch SWN0, one end of the switch SWP0 being connected to the first dynamic unit matcher and the other end of the switch SWP0 being connected to the loop filter; one end of the switch SWN0 being connected to the second dynamic unit matcher and the other end of the switch SWN0 being connected to the loop filter.

[0090] It should be noted that the dynamic unit matching module inputs the frequency multiplication coefficient DIV<1:N> into the logic section, and after logic operation, obtains the control signal SEL<1:K>, which is used to control the switching on and off of the P-type field-effect transistor and the N-type field-effect transistor.

[0091] In one implementation, the first dynamic unit matched circuit DEM1 receives current from P-type field-effect transistors PM1 to PMK. Controlled by the clock clkin, the random current mirror unit is turned on, allowing current to flow in and resulting in current I. cpp Current I cpp The current flows in from one end of switch SWP0, which is controlled by the output signal UP of the frequency and phase detector; the second dynamic unit matching circuit DEM2 receives current from N-type field-effect transistors NM1 to NMK, which is controlled by clock clkin, and the random current mirror unit is turned on, allowing current to flow in, resulting in current Icpn, and current I... cpn The current flows out from one end of switch SWN0, which is controlled by the output signal DN of the frequency and phase detector; the other end of switch SWN0 is connected to the other end of SWN0, ultimately resulting in the output current I. cp It is then fed to the loop filter.

[0092] As an example, P-type field-effect transistors all have the same dimensions, and therefore all have the same output current, i.e., I0. P1 =I P2 =…=I PK Since all N-type field-effect transistors have the same dimensions, their corresponding output currents are also the same, i.e., I0. N1 =I N2 =…=I NK And all of them are related to the current I of the reference current source.u same.

[0093] In some embodiments, the phase-locked loop circuit further includes a bias voltage generation circuit, which includes a P-type field-effect transistor PB0, an N-type field-effect transistor NB0, an N-type field-effect transistor NB1, and a reference current source.

[0094] One end of the reference current source is connected to the source of the P-type field-effect transistor PB0, the drain of the P-type field-effect transistor PB0 is connected to the gate, and the gate of the P-type field-effect transistor PB0 is also connected to the other end of the switch in the charging circuit.

[0095] The drain of the N-type field-effect transistor NB0 is connected to the other end of the reference current source. The gate of the N-type field-effect transistor NB0 is connected to the gate of the N-type field-effect transistor NB1. The source of the N-type field-effect transistor NB0 and the source of the N-type field-effect transistor NB1 are grounded. The gates of the N-type field-effect transistor NB0 and the gate of the N-type field-effect transistor NB1 are connected to one end of the switch in the discharge circuit.

[0096] As an example, several current mirror units in the charging circuit and the P-type field-effect transistor PB0 in the bias voltage generation circuit together form a current mirror, with each current mirror unit being an output branch of the current mirror; several current mirror units in the discharging circuit and the N-type field-effect transistors NB0 and NB1 in the bias voltage generation circuit together form a current mirror, with each current mirror unit being an output branch of the current mirror.

[0097] It should be noted that the bias voltage generation circuit provides bias voltages for P-type field-effect transistors PM1 to PMK and N-type field-effect transistors NM1 to NMK, respectively. Figure 4 The BIAS in the circuit refers to the bias voltage generation circuit.

[0098] As one implementation method, the required current Icp is determined based on the given frequency division coefficient DIV<1:N> range, and the current level of the charge pump module is determined. Then, the corresponding number of current mirror units are randomly selected from PM1~PMK and NM1~NMK using the dynamic unit matching module. Since mismatch can be considered as independent and identically distributed events, the more samples available for random selection, the better the effect of mismatch suppression. Based on this, the mismatch between CP charging current and discharging current can be effectively reduced on the basis of multiple levels, and spurious emissions can be effectively suppressed.

[0099] As an example, assuming the frequency division factor ranges from 8 to 128, the output current of the charge pump module can be divided into four levels: 8–15, 16–31, 32–63, and 64–128. The corresponding output current of the charge pump module is I. cp 2I cp 4I cpand 8I cp , among which, I P =I N =I u =I cp There are a total of 8 groups of current mirror units in the P-type and N-type field-effect transistors in the charge pump module. When the frequency division factor is 20, the corresponding charge pump current is 2Icp, which requires 2 current mirror units. The first and second dynamic unit matchers of the dynamic unit matching module randomly select 2 current mirror units from PM1 to PM8 and NM1 to NM8 respectively, so as to obtain two currents with high matching degree.

[0100] The phase-locked loop (PLL) circuit provided in this embodiment of the invention receives a reference clock signal and the output signal of a frequency divider through a frequency detector. Based on the phase difference between the reference clock signal and the output signal of the frequency divider, a charge / discharge control signal is generated. The charge / discharge control signal is received through a charge pump module, which determines whether to charge or discharge based on the control signal. The current level for charging or discharging is determined based on a preset frequency division coefficient, and a corresponding charging current or discharging current is generated based on the determined charging or discharging and the current level. A loop filter is used to filter the charging current or discharging current to obtain a control voltage signal. A voltage-controlled oscillator (VCO) generates a PLL output signal of a preset frequency based on the control voltage signal. Multiple charge pump charging and discharging current levels are set. For different frequency division coefficients, the optimal characteristics of the PLL loop are ensured while reducing charge pump noise. Based on the multiple current levels, a dynamic unit matching technology is adopted to eliminate the mismatch between the charging current and discharging current in the charge pump module, effectively suppressing spurious signals and improving bandwidth characteristics.

[0101] A schematic flowchart of the phase-locked loop control method according to the second embodiment of the present invention is shown below. Figure 5 As shown, the phase-locked loop control method includes the following steps:

[0102] S501, acquire the reference clock signal and the frequency division signal, and generate a charge / discharge control signal based on the phase difference between the reference clock signal and the frequency division signal;

[0103] S502, determine charging or discharging according to the charging or discharging control signal, determine the charging or discharging current level according to the preset frequency division coefficient, and generate the corresponding charging current or discharging current according to the determined charging or discharging and the charging or discharging current level.

[0104] S503, the charging current or discharging current is filtered to obtain a control voltage signal;

[0105] S504, Generate a phase-locked loop output signal of a preset frequency according to the control voltage signal;

[0106] S505, divide the frequency of the phase-locked loop output signal to obtain the divided frequency signal.

[0107] The third embodiment of the present invention provides a charge pump, which is used to receive the charge and discharge control signal, determine charging or discharging according to the charge and discharge control signal, and further used to determine the current level of charging or discharging, and generate a corresponding charging current or discharging current according to the determined charging or discharging and the current level of charging or discharging.

[0108] In one implementation, the charge pump includes a charging circuit, a discharging circuit, and a dynamic unit matching module. The dynamic unit matching module is used to determine the charging current level or the discharging current level according to preset parameters. The charging circuit is used to generate the charging current at the charging current level. The discharging circuit is used to generate the charging current at the discharging current level. When the charge pump is applied to a phase-locked loop (PLL) circuit, the preset parameters can be the frequency division coefficient of the PLL.

[0109] In one implementation, both the charging circuit and the discharging circuit described above include several current mirror units. The dynamic unit matching module is also used to determine the number of current mirror units in the charging circuit or discharging circuit that are turned on according to the charging current level or the discharging current level, and to turn on the current mirror units in the charging circuit or discharging circuit according to the number of units turned on.

[0110] In one implementation, the current mirror unit in the charging circuit includes a first P-type field-effect transistor and a first switch. One end of the first switch is connected to a bias voltage, the other end of the first switch is connected to the gate of the first P-type field-effect transistor, the source of the first P-type field-effect transistor is connected to a power supply, and the drain of the first P-type field-effect transistor is connected to a dynamic unit matching module.

[0111] In one implementation, the current mirror unit in the discharge circuit includes a first N-type field-effect transistor and a second switch. One end of the second switch is connected to a bias voltage, and the other end of the second switch is connected to the gate of the first N-type field-effect transistor. The source of the first N-type field-effect transistor is grounded, and the drain of the first N-type field-effect transistor is connected to a dynamic unit matching module.

[0112] In one implementation, the dynamic unit matching module includes a first dynamic unit matcher and / or a second dynamic unit matcher; the first dynamic unit matcher is used to determine the charging current level according to the preset parameters mentioned above, determine the number of current mirror units in the charging circuit to be turned on according to the charging current level, and turn on the current mirror units in the charging circuit according to the number of units turned on; the second dynamic unit matcher is used to determine the discharging current level according to the preset parameters mentioned above, determine the number of current mirror units in the discharging circuit to be turned on according to the discharging current level, and turn on the current mirror units in the discharging circuit according to the number of units turned on.

[0113] In one implementation, the dynamic unit matching module includes a first dynamic unit matcher and / or a second dynamic unit matcher; the first dynamic unit matcher is used to determine the charging current level according to the preset parameters mentioned above, determine the number of current mirror units in the charging circuit to be turned on according to the charging current level, and randomly turn on the current mirror units in the charging circuit according to the number of turns on; the second dynamic unit matcher is used to determine the discharging current level according to the preset parameters mentioned above, determine the number of current mirror units in the discharging circuit to be turned on according to the discharging current level, and randomly turn on the current mirror units in the discharging circuit according to the number of turns on.

[0114] The charge pump provided in this embodiment of the invention determines charging or discharging based on a charge / discharge control signal, determines the current level for charging or discharging, and generates a corresponding charging current or discharging current based on the determined charging or discharging and the current level for charging or discharging. This can eliminate the mismatch between the charging current and the discharging current in the charge pump, thereby effectively suppressing stray current.

[0115] The fourth embodiment of the present invention provides a chip including the phase-locked loop circuit or charge pump described in any of the above embodiments.

[0116] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0117] The above embodiments merely illustrate preferred implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention should be determined by the appended claims.

Claims

1. A phase-locked loop circuit, characterized in that, Includes a frequency and phase detector, a charge pump module, a loop filter, a voltage-controlled oscillator, and a frequency divider. The frequency and phase detector is used to receive a reference clock signal and the output signal of the frequency divider, and to generate a charge and discharge control signal based on the reference clock signal and the output signal of the frequency divider. The charge pump module is used to receive the charge / discharge control signal, determine charging or discharging according to the charge / discharge control signal, determine the current level of charging or discharging, and generate a corresponding charging current or discharging current according to the determined charging or discharging and the current level of charging or discharging. The charge pump module includes a charging circuit, a discharging circuit, and a dynamic unit matching module; the dynamic unit matching module is used to determine the charging current level or the discharging current level according to a preset frequency division coefficient. Both the charging circuit and the discharging circuit include several current mirror units. The dynamic unit matching module is also used to determine the number of current mirror units in the charging circuit or discharging circuit that are turned on according to the charging current level or discharging current level, and to turn on the current mirror units in the charging circuit or discharging circuit according to the number of units turned on. The loop filter is used to filter the charging current or discharging current to obtain a control voltage signal; The voltage-controlled oscillator is used to generate a phase-locked loop output signal of a preset frequency according to the control voltage signal; The frequency divider is used to divide the output signal of the phase-locked loop, and the divided signal is used as the output signal and input to the frequency and phase detector.

2. The phase-locked loop circuit according to claim 1, characterized in that, The charging circuit is used to generate the charging current at the specified charging current level; the discharging circuit is used to generate the charging current at the specified discharging current level.

3. The phase-locked loop circuit according to claim 1, characterized in that, The current mirror unit in the charging circuit includes a first P-type field-effect transistor and a first switch. One end of the first switch is connected to a bias voltage, and the other end of the first switch is connected to the gate of the first P-type field-effect transistor. The source of the first P-type field-effect transistor is connected to a power supply, and the drain of the first P-type field-effect transistor is connected to the dynamic unit matching module.

4. The phase-locked loop circuit according to claim 3, characterized in that, The current mirror unit in the discharge circuit includes a first N-type field-effect transistor and a second switch. One end of the second switch is connected to a bias voltage, and the other end of the second switch is connected to the gate of the first N-type field-effect transistor. The source of the first N-type field-effect transistor is grounded, and the drain of the first N-type field-effect transistor is connected to the dynamic unit matching module.

5. The phase-locked loop circuit according to claim 1, characterized in that, The dynamic unit matching module includes a first dynamic unit matcher and / or a second dynamic unit matcher; The first dynamic unit matcher is used to determine the charging current level according to a preset frequency division coefficient, determine the number of current mirror units in the charging circuit to be turned on according to the charging current level, and turn on the current mirror units in the charging circuit according to the number of units turned on. The second dynamic unit matching unit is used to determine the discharge current level according to a preset frequency division coefficient, determine the number of current mirror units in the discharge circuit to be turned on according to the discharge current level, and turn on the current mirror units in the discharge circuit according to the number of units turned on.

6. The phase-locked loop circuit according to claim 1, characterized in that, The dynamic unit matching module includes a first dynamic unit matcher and / or a second dynamic unit matcher; The first dynamic unit matcher is used to determine the charging current level according to a preset frequency division coefficient, determine the number of current mirror units in the charging circuit to be turned on according to the charging current level, and randomly turn on the current mirror units in the charging circuit according to the number of turns on. The second dynamic unit matching unit is used to determine the discharge current level according to a preset frequency division coefficient, determine the number of current mirror units in the discharge circuit to be turned on according to the discharge current level, and randomly turn on the current mirror units in the discharge circuit according to the number of units turned on.

7. The phase-locked loop circuit according to any one of claims 1-6, characterized in that, The charge pump module further includes a third switch and a fourth switch. One end of the third switch is connected to the charging circuit, and the other end of the third switch is connected to the loop filter. One end of the fourth switch is connected to the discharging circuit, and the other end of the fourth switch is connected to the loop filter.

8. The phase-locked loop circuit according to claim 4, characterized in that, It also includes a bias voltage generation circuit, which includes a second P-type field-effect transistor, a second N-type field-effect transistor, a third N-type field-effect transistor, and a reference current source; One end of the reference current source is connected to the source of the second P-type field-effect transistor, the drain of the second P-type field-effect transistor is connected to the gate, and the gate of the second P-type field-effect transistor is also connected to one end of the gate of the first switch in the charging circuit. The drain of the second N-type field-effect transistor is connected to the other end of the reference current source. The gate of the second N-type field-effect transistor is connected to the gate of the third N-type field-effect transistor. The source of the second N-type field-effect transistor is grounded to the source of the third N-type field-effect transistor. The gates of the second N-type field-effect transistor and the gate of the third N-type field-effect transistor are connected to one end of the discharge circuit where the second switch is connected to the bias voltage.

9. A phase-locked loop control method, characterized in that, Includes the following steps: Obtain the reference clock signal and the frequency divider signal, and generate the charge / discharge control signal based on the reference clock signal and the output signal of the frequency divider; The charging or discharging is determined according to the charging or discharging control signal, the charging current level or discharging current level is determined according to the preset frequency division coefficient, and the corresponding charging current or discharging current is generated according to the determined charging or discharging and the charging or discharging current level. Based on the charging current level or discharging current level, determine the number of current mirror units in the charging circuit or discharging circuit that are turned on, and turn on the current mirror units in the charging circuit or discharging circuit according to the number of units turned on. The charging current or discharging current is filtered to obtain a control voltage signal; A phase-locked loop output signal of a preset frequency is generated based on the control voltage signal; The frequency-divided signal is obtained by dividing the output signal of the phase-locked loop.

10. A charge pump, characterized in that, The charge pump is used to receive charge / discharge control signals, determine charging or discharging based on the charge / discharge control signals, determine the charging current level or discharging current level based on a preset frequency division coefficient, and generate a corresponding charging current or discharging current based on the determined charging or discharging and the charging or discharging current level; it is also used to determine the number of current mirror units in the charging circuit or discharging circuit that are turned on based on the charging current level or discharging current level, and turn on the current mirror units in the charging circuit or discharging circuit based on the number of units turned on.

11. A chip, characterized in that, Includes the phase-locked loop circuit as described in any one of claims 1-8 or the charge pump as described in claim 10.

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