Phase-locked loop circuit

Abstract

The invention relates to the technical field of integrated circuits, and discloses a phase-locked loop circuit, which comprises a time-to-digital converter for receiving a reference clock, a feedback clock and a frequency clock, the sampling module is used for counting and sampling a frequency clock according to a reference clock and a feedback clock and calculating frequency deviation information between the reference clock and the frequency clock and phase deviation information between the reference clock and the feedback clock; the digital frequency and phase detection filter is used for carrying out weighted integration on the frequency deviation information and the phase deviation information and generating a control signal; the digital control oscillator is used for generating a frequency clock according to the control signal; and the feedback frequency divider is used for carrying out frequency division on the frequency clock and generating a feedback clock. According to the invention, the frequency deviation information and the phase deviation information are jointly used as the input of the integral path in the digital phase frequency detection filter, so that the phase frequency detection function under the digital phase-locked loop system is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a phase-locked loop circuit. BACKGROUND

[0002] As an important clock and frequency control circuit, the phase-locked loop (PLL) is widely used in the fields of communication, signal processing, integrated circuit clock generation, etc. With the evolution of integrated circuit design towards full digitalization, the digital PLL (DPLL) gradually becomes one of the mainstream technologies due to its good portability, easy integration and low cost, etc. In the traditional DPLL structure, the loop mainly relies on the digital phase discriminator to extract the phase deviation signal, and adjusts the digital controlled oscillator through the digital filter to realize the phase-locked control.

[0003] Generally, the digital phase-locked loop can only simply discriminate the phase error, but cannot distinguish the frequency error like the traditional phase-locked loop based on the frequency discriminator. In particular, the linear phase discrimination range of the phase discriminator in the traditional digital phase-locked loop is generally small. When the reference clock frequency and the feedback clock frequency of the phase-locked loop deviate too much, the traditional simple phase discriminator cannot meet the needs of frequency error discrimination in the phase-locked loop, and therefore it cannot provide the correct frequency locking direction, and cannot realize the phase-locked loop locking. When the traditional digital phase-locked loop loses locking due to external disturbance, etc., it is also difficult to recover the locking, which also limits the application of the digital phase-locked loop in some scenes with strong robustness requirements.

[0004] In order to solve the problem of small frequency locking range of the full digital phase-locked loop, the traditional full digital phase-locked loop usually uses an auxiliary frequency-locked loop to help the phase-locked loop to lock in the initial state. It first uses the frequency calibration algorithm of the voltage-controlled oscillator and the auxiliary frequency-locked loop to lock the frequency of the voltage-controlled oscillator of the phase-locked loop near the target frequency, and then uses the phase-locked loop to realize the locking of the phase-locked loop. However, when the loop loses locking due to some reasons, the output frequency of the phase-locked loop may change in a large frequency range at this time, and it is difficult to lock the phase-locked loop back through the phase-locked loop. On the other hand, the switching process between the auxiliary frequency-locked loop and the normal phase-locked loop will also cause the cycle slipping of the phase-locked loop and the increase of the locking time, etc.

[0005] Therefore, the existing full digital phase-locked loop still has obvious deficiencies in the frequency capture range, system stability and robustness, and it is urgent to improve and optimize a full digital phase-locked loop system with a more simple structure, stronger frequency capture ability and self-recovery ability when losing locking. SUMMARY

[0006] The application aims to provide a phase-locked loop circuit which multiplexes frequency deviation information in a time-to-digital converter, and uses the frequency deviation information and phase deviation information as inputs of an integral path in a digital frequency and phase discriminator filter, so as to realize the frequency and phase discrimination function under a digital phase-locked loop system.

[0007] The application provides a phase-locked loop circuit, comprising:

[0008] a counter-based time-to-digital converter which receives a reference clock, a feedback clock and a frequency clock, and is configured to count and sample the frequency clock according to the reference clock and the feedback clock respectively, and calculate frequency deviation information between the reference clock and the frequency clock and phase deviation information between the reference clock and the feedback clock according to results of the count and sampling;

[0009] a digital frequency and phase discriminator filter which is configured to weight and integrate the frequency deviation information and the phase deviation information, and generate a control signal;

[0010] a digitally controlled oscillator which is configured to generate the frequency clock according to the control signal; and

[0011] a feedback frequency divider which is configured to divide the frequency clock and generate the feedback clock.

[0012] In a preferred example, the time-to-digital converter subtracts the result of the reference clock sampling count at the current time and the last time from the result of the feedback frequency divider division, to obtain the frequency deviation information.

[0013] In a preferred example, the time-to-digital converter subtracts the result of the reference clock sampling count at the current time from the result of the feedback clock sampling count at the current time, to obtain the phase deviation information.

[0014] In a preferred example, the digital frequency and phase discriminator filter multiplies the frequency deviation information by a gain coefficient of a frequency integral path, adds the result to the phase deviation information multiplied by a gain coefficient of a phase integral path, and passes through an integrator, and then adds the result to the phase deviation information multiplied by a gain coefficient of a phase proportional path, to obtain the control signal.

[0015] In a preferred example, the gain coefficient of the phase proportional path is much larger than the gain coefficient of the phase integral path.

[0016] In a preferred example, the integrator is a digital integrator.

[0017] In a preferred embodiment, the frequency integral path is enabled when the frequency deviation information is less than a first preset threshold, and the frequency integral path is disabled when the frequency deviation information is greater than or equal to a second preset threshold.

[0018] In a preferred embodiment, the digital controlled oscillator is controlled by a digital-to-analog converter, a switched-capacitor array, or a Delta-Sigma modulator noise shaper.

[0019] In a preferred embodiment, the reference clock is sampled every m reference clock cycles, where m is an integer from 1 to 5.

[0020] In the embodiments of the present application, at least the following beneficial effects are achieved:

[0021] The present application improves the robustness of the digital phase-locked loop and increases the frequency capture range of the digital phase-locked loop. Robust locking of the digital phase-locked loop can be achieved, and recovery from a large frequency deviation loss of lock state can be achieved. Moreover, the introduction of an auxiliary frequency-locked loop and the switching problem between the frequency-locked loop and the phase-locked loop can be avoided, the system design and process are simplified, and the locking time of the phase-locked loop can be reduced.

[0022] The present application introduces frequency deviation information and phase deviation information into the integral element, which not only improves the frequency capture range, but also has stronger self-recovery capability in a loss of lock state, avoids the complexity of auxiliary loop design, and is suitable for complex communication environments and high-reliability chip clock systems.

[0023] It should be understood that, within the scope of the present application, each of the above technical features of the present application and each of the technical features specifically described below (such as the embodiments) can be combined with each other to form a new or preferred technical solution. Due to the limited space, they will not be listed one by one here. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed in the embodiments or the prior art description will be briefly introduced below. It should be understood that the drawings described below are only some of the embodiments of the present application, and those skilled in the art can obtain other embodiments from these drawings without creative labor.

[0025] Figure 1 is a system block diagram of a phase-locked loop circuit according to an embodiment of the present application.

[0026] Figure 2 is a structural schematic diagram of a digital frequency-to-phase filter according to an embodiment of the present application.

[0027] Figure 3is a signal waveform diagram of a counter-based time-to-digital converter according to an embodiment of the present application. DETAILED DESCRIPTION

[0028] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application can be practiced without such specific details and that numerous implementation variations and modifications can be possible.

[0029] Explanation of some concepts:

[0030] Phase-locked loop (PLL): A closed-loop automatic control system whose basic function is to keep the phase (and even frequency) of the output signal in synchronization with the input reference signal (i.e., "locked"), widely used in frequency synthesis, clock recovery, data synchronization, wireless communication, etc.

[0031] Digital-controlled oscillator (DCO): An oscillator whose output frequency is directly adjusted by a digital control word. It is a key module in a fully digital phase-locked loop (DPLL) and is a digital version of an analog VCO.

[0032] Frequency divider: A circuit module that reduces the frequency of an input clock signal by a set ratio. It is a key component in the feedback path of a phase-locked loop (PLL / DPLL) system, used to scale the output frequency of a digital-controlled oscillator (DCO) or voltage-controlled oscillator (VCO) to the same frequency level as the reference clock, enabling closed-loop comparison and lock control.

[0033] Filter: A signal processing module that selectively passes or suppresses input signals based on frequency, time, or other characteristics, removing unwanted components and retaining target signal parts. It can be a capacitive and inductive network in an analog circuit or an algorithm module in a digital system.

[0034] Integrator: A system that integrates (or accumulates in digital systems) the input signal over time, with the output value equal to the historical cumulative sum of the input signal.

[0035] Time-to-digital converter (TDC): A circuit module that converts the time interval (delay / phase difference) between two clock signals into a digital quantity.

[0036] To make the purpose, technical solutions, and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0037] One embodiment of the present application relates to a phase-locked loop circuit, the structure of which is as shown in Figure 1As shown, the structure comprises: a counter-based time-to-digital converter (TDC), a digital loop filter (DLF), a digitally controlled oscillator (DCO), and a feedback divider (DIV). The time-to-digital converter, the digital loop filter, and the feedback divider are coupled in sequence to form a loop, and the digitally controlled oscillator is further coupled to the time-to-digital converter.

[0038] The time-to-digital converter receives a reference clock CKref, a feedback clock CKfb, and a frequency clock CKvco, and is configured to count sample the frequency clock CKvco according to the reference clock CKref, count sample the frequency clock CKvco according to the feedback clock CKfb, and calculate a frequency deviation information freqerr between the reference clock CKref and the frequency clock CKvco and a phase deviation information Pherr between the reference clock CKref and the feedback clock CKfb according to the count sample results. The digital loop filter is configured to weight integrate the frequency deviation information freqerr and the phase deviation information Pherr and generate a control signal Ctrld. The digitally controlled oscillator is configured to generate the frequency clock CKvco according to the control signal Ctrld. The feedback divider is configured to divide the frequency clock CKvco according to a division ratio and generate the feedback clock CKfb.

[0039] In one embodiment, the time-to-digital converter comprises a counter of the reference clock signal and a counter of the feedback clock signal, and is configured to count sample the frequency clock CKvco according to the reference clock signal CKref and the feedback clock signal CKfb respectively. The time-to-digital converter is configured to calculate the frequency deviation information freqerr and the phase deviation information Pherr in the following ways respectively:

[0040] (i) subtracting a count sample result of the frequency clock CKvco at a previous time instant by the reference clock CKref from a count sample result of the frequency clock CKvco at a current time instant by the reference clock CKref, and then subtracting a division ratio of the feedback divider, thereby obtaining the frequency deviation information freqerr.

[0041] (ii) subtracting a count sample result of the frequency clock CKvco at the current time instant by the feedback clock CKfb from a count sample result of the frequency clock CKvco at the current time instant by the reference clock CKref, thereby obtaining the phase deviation information Pherr.

[0042] Structure of the digital loop filter Figure 2The digital frequency and phase discriminator filter multiplies the frequency deviation information freqerr by the gain coefficient k of the frequency integration path i_freq The result is added to the result of the phase deviation information Pherr multiplied by the gain coefficient k of the phase integration path i_ph and passed through an integrator, and then added to the result of the phase deviation information Pherr multiplied by the gain coefficient k of the phase proportional path p_ph , thereby obtaining the control signal Ctrld. Among them, the gain coefficient k i_freq of the frequency integration path, the gain coefficient k i_ph of the phase integration path, and the gain coefficient k p_ph of the phase proportional path are all adjustable. Among them, the gain coefficient k p_ph of the phase proportional path is much larger than the gain coefficient k i_ph of the phase integration path.

[0043] The digital phase-locked loop in the present application multiplexes the frequency deviation information freqerr in the time-to-digital converter, and takes the frequency deviation information freqerr and the phase deviation information Pherr as inputs of the integration path in the digital filter, realizes a digital frequency and phase discriminator filter, and thereby realizes the frequency and phase discrimination function under the digital phase-locked loop system.

[0044] In order to better understand the technical solutions of the present application, a specific example will be described below, and the details listed in the example are mainly for easy understanding and do not limit the protection scope of the present application.

[0045] In the traditional all-digital proportional-integral phase-locked loop, the frequency capture of the phase-locked loop is mainly realized by the accumulation effect of the phase integration path. When there is a frequency deviation, the phase deviation between the input signals of the phase integration path, the reference clock CKref and the feedback clock CKfb, will present a periodic beat frequency, i.e. a periodic positive and negative value. The periodic beat frequency signal contains direct current information to indicate the direction of loop frequency locking, until the frequency deviation becomes smaller and the loop is finally locked. However, when the frequency deviation is large, the direct current information in the periodic beat frequency signal of the phase integration path input cannot indicate the correct loop frequency locking direction due to the influence of the nonlinearity of the loop, so the loop cannot be locked.

[0046] As shown in the figure Figure 1As shown, in the phase-locked loop system of this invention, when the reference clock CKref frequency and the feedback clock CKfb frequency differ significantly, even if the DC information in the periodic beat frequency phase deviation information can no longer lock the loop frequency in the correct direction, the input signal of the frequency integration path (frequency deviation freqerr) can be guaranteed to remain positive or negative, increasing with the frequency deviation. This can be considered as compensating for more DC deviation. Combined, the frequency integration path usually dominates, thus ensuring the phase-locked loop system can lock in the correct direction. When the frequency error of the phase-locked loop of this invention is relatively small, the input signal of the frequency integration path is very small. At this time, the loop is mainly affected by the phase integration path to achieve loop locking. Therefore, this phase-locked loop system can seamlessly transition from large frequency deviations to final loop phase locking.

[0047] like Figure 2 As shown, this digital filter contains two input signals, one of which is the frequency offset information freq. err One is the phase deviation information Ph err The frequency deviation information freq err and phase deviation information Ph err Multiply by k respectively i_ph and k i_freq The results are then added together, passed through an integrator, and finally added to the result of the phase deviation information proportional path. The frequency integration loop and the phase integration loop share the same integrator, which saves some power and area of ​​the digital integrator and avoids the outputs of the frequency integration loop and the phase integration loop being located at opposite boundaries of the phase-locked loop's linear range, thus preventing impact on system stability. Where k... p_ph k represents the gain coefficient of the phase scaling path. i_ph k represents the gain coefficient of the phase integration path. i_freq This represents the gain coefficient of the frequency integration path. Typically, k... p_ph Much greater than k i_ph To achieve a wider frequency locking range for the phase-locked loop, the gain coefficient k of the frequency integration path can be appropriately increased. i_freq Of course, the gain coefficient k of the frequency integration path... i_freq However, the gain coefficients cannot be increased indefinitely, otherwise it will lead to loop instability. It should be understood that the specific values ​​of the above-mentioned gain coefficients can be set according to the actual circuit conditions.

[0048] Figure 3 This is a schematic diagram of the signal waveform of a counter-based time-to-digital converter. Where N... CNT The output waveform of the counter is based on the DCO output clock signal CKvco, N ref (n) and N ref(n-1) are the results of the current time and the last time reference clock signal CKref sampling counter respectively, N fb (n) and N fb (n-1) are the results of the current time and the last time feedback clock signal CKfb sampling counter respectively.

[0049] In order to obtain the frequency deviation information between the reference clock CKref and the DCO output clock signal CKvco, the results of the current time and the last time reference clock signal sampling counter can be subtracted, and then subtracted by the ideal frequency division ratio, that is, the frequency deviation information freq err = N ref (n) - N ref (n-1) - N div The time-to-digital converter can output the frequency error information. Wherein N div is the ideal feedback coefficient of the loop (i.e. the frequency division ratio). Simply speaking, the frequency error is identified by counting how many DCO output clock signal CKvco cycles in a reference clock cycle.

[0050] In the embodiment, the waveform N CNT output by the counter based on the DCO output clock signal CKvco is sampled every reference clock cycle, in order to improve the accuracy of the frequency deviation information, N CNT can also be sampled every m reference clock cycles, and the value of m can be 1 to 5. For example, when m is 1, sampling is performed every cycle, and when m>1, sampling is performed every multiple cycles. M can be preferably 2 to 3.

[0051] In order to obtain the phase deviation information between the reference clock CKref and the feedback clock signal CKfb, the results of the current time reference clock and feedback clock signal sampling counter can be simply subtracted, that is, the phase deviation information Pherr = N ref (n) - N fb (n), the phase difference between the reference clock signal and the feedback clock signal can be obtained.

[0052] There are many ways to implement the DCO in the phase-locked loop of the application, including digital-to-analog converter control, switchable varactor control, switchable capacitor array control, Delta-Sigma Modulator (DSM) noise shaping control, etc. It can be understood that the implementation of the DCO can adopt any way known to those skilled in the art, and the application does not limit it.

[0053] Of course, the frequency integration loop can also be controlled with a certain threshold or have a hysteresis effect. When the frequency error is less than a certain value (a first preset threshold), the frequency integration loop is enabled, i.e. Figure 2 the frequency error information is used in the digital filter in (1). When the frequency error is greater than or equal to another certain value (a second preset threshold), the frequency integration loop is disabled, i.e. Figure 2 the frequency error information is not used in the digital filter in (1). It should be understood that the values for enabling or disabling the frequency integration loop can be set according to the actual circuit conditions.

[0054] In addition, when the frequency division ratio of the phase-locked loop is reduced, the frequency resolution of the counter-based time-to-digital converter is often small. In order to obtain higher-precision frequency deviation information, the time can be sacrificed to obtain frequency resolution accuracy. For example, the frequency deviation is discriminated once every m reference clock periods, i.e. err = N ref (n)-N ref (n-m)-m*N div On the other hand, the DCO output can also provide multiphase clock information, for example, the rising edge of the frequency clock Ckvco is sampled, and in this case, both the rising edge and the falling edge of the frequency clock Ckvco can be sampled; or the multiphase frequency clock Ckvco clock is sampled, so as to improve the sampling accuracy of the clock, and thus the frequency deviation information accuracy is improved.

[0055] It should be noted that in the application file of the present patent, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including one" does not exclude the presence of another identical element in the process, method, article or device including the element. In the application file of the present patent, if it is mentioned that a certain action is performed according to a certain element, it means that the action is performed at least according to the element, which includes two cases: the action is performed only according to the element, and the action is performed according to the element and other elements. The expressions of multiple, multiple times, multiple varieties, etc. include 2, 2 times, 2 varieties and 2 or more, 2 times or more, 2 varieties or more.

[0056] The term "coupled to" and its derivatives can be used herein. "Coupled" can mean two or more elements are in direct physical or electrical contact. However, "coupled" can also mean that two or more elements indirectly contact each other, but yet are still in cooperation or interaction with each other, and can mean that one or more other elements are coupled or connected between the elements that are said to be coupled to each other.

[0057] All documents mentioned in this specification are herein incorporated by reference in their entirety to disclose and describe the methods and / or materials in connection with which the documents are cited. The citation of any document is not to be construed as an admission that it is prior art with respect to the present description. In addition, it should be understood that the descriptions just given are illustrative of the general nature of the description described herein and are in no way to be taken as limiting the scope of the description. Any modification, equivalent replacement or improvement made during the spirit and principles of one or more embodiments described in the specification shall be included in the scope of protection of one or more embodiments described in the specification.

Claims

1. A phase-locked loop circuit, characterized by comprising: The application relates to a time-to-digital converter, a digital phase-frequency discriminator, a digital controlled oscillator and a feedback divider. The time-to-digital converter receives a reference clock, a feedback clock and a frequency clock, counts and samples the frequency clock according to the reference clock and the feedback clock respectively, and calculates frequency deviation information between the reference clock and the frequency clock and phase deviation information between the reference clock and the feedback clock according to the counting and sampling results. The digital phase-frequency discriminator weights and integrates the frequency deviation information and the phase deviation information, and generates a control signal. The digital controlled oscillator generates the frequency clock according to the control signal. The feedback divider divides the frequency clock and generates the feedback clock. The time-to-digital converter subtracts the counting and sampling result of the reference clock at a current time from the counting and sampling result of the reference clock at a previous time, and subtracts the division ratio of the feedback divider to obtain the frequency deviation information.

2. The phase-locked loop circuit of claim 1, wherein, The time-to-digital converter subtracts the counting and sampling result of the reference clock at a current time from the counting and sampling result of the feedback clock at the current time to obtain the phase deviation information.

3. The phase-locked loop circuit of claim 1, wherein, The digital phase-frequency discriminator multiplies the frequency deviation information by a gain coefficient of a frequency integration path, adds the result to the phase deviation information multiplied by a gain coefficient of a phase integration path, and passes the result through an integrator, and then adds the result to the phase deviation information multiplied by a gain coefficient of a phase proportional path, thereby obtaining the control signal.

4. The phase-locked loop circuit of claim 1, wherein, The gain coefficient of the phase proportional path is much larger than the gain coefficient of the phase integration path.

5. The phase-locked loop circuit of claim 4, wherein, The integrator is a digital integrator.

6. The phase-locked loop circuit of claim 4, wherein, When the frequency deviation information is less than a first preset threshold, the frequency integration path is enabled; when the frequency deviation information is greater than or equal to a second preset threshold, the frequency integration path is disabled.

7. The phase-locked loop circuit of claim 1, wherein, The digital controlled oscillator adopts digital-to-analog converter control, switchable varactor control, switchable capacitor array control or Delta-Sigma modulator noise shaping control.

8. The phase-locked loop circuit of claim 1, wherein, The reference clock counts and samples the frequency clock every m reference clock cycles, wherein m is 1-5.

9. The phase-locked loop circuit of claim 1, wherein, ​

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