Sigma-delta analog-to-digital converter with aliasing suppression

Abstract

This invention discloses a Sigma-Delta analog-to-digital converter (ADC) with aliasing suppression function. The Sigma-Delta ADC includes a preset loop filter module, a sampling module, a quantizer, and a preset feedback DAC module. The preset loop filter module, sampling module, and quantizer are connected in series. The preset loop filter module includes a chopper. The preset feedback DAC module is connected between the loop filter module and the quantizer to suppress aliasing introduced by the chopper and maintain the effective signal sampled by the sampling module within the corresponding frequency band. All poles of the transfer function of the preset feedback DAC module are located at the aliasing points introduced by the chopper, thus achieving the function of suppressing aliasing.

Description

Technical Field

[0001] This invention belongs to the technical field of analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), and particularly relates to a Sigma-Delta analog-to-digital converter with anti-aliasing function. Background Technology

[0002] The Sigma-Delta analog-to-digital converter (ADC), also known as a Sigma Delta analog-to-digital converter, primarily employs oversampling and noise shaping techniques for high-precision audio signal processing. The basic structure of a Sigma-Delta ADC includes a loop filter, a quantizer, and a feedback DAC, which together form a feedback loop. Generally, the Sigma-Delta ADC operates at a rate significantly higher than the bandwidth of the analog input signal to provide oversampling. The analog input is differentially compared with the feedback signal (error signal), and the resulting difference is fed into the loop filter. The Sigma-Delta ADC then uses feedback to bring this difference closer to zero, reducing the nonlinearity of the feedback DAC.

[0003] 1 / f noise, also known as flicker noise or excess noise, is characterized by its power spectral density being inversely proportional to frequency, primarily occurring in the low-frequency region below 1kHz. Existing technologies reduce 1 / f noise generated by operational amplifiers using chopping techniques. Specifically, choppers are used in Sigma-Delta analog-to-digital converters (ADCs) to frequency-shift the input signal of the operational amplifier. After modulation by the chopper (effectively chopping the operational amplifier), the 1 / f noise is shifted outside the signal band, possibly even outside the baseband, thus reducing the overall 1 / f noise of the circuit. However, in continuous-mode Sigma-Delta ADCs, the use of choppers introduces aliasing. High-frequency and low-frequency sampled signals overlap, causing spectral overlap and distortion, thus compromising the basic function of the filters built into the continuous-mode Sigma-Delta ADC. Summary of the Invention

[0004] To address the aliasing problem introduced into Sigma-Delta analog-to-digital converters (ADCs), this invention discloses a Sigma-Delta ADC with aliasing suppression functionality. By improving the feedback DAC in the feedback loop, aliasing introduced by the chopper in the associated operational amplifier structure is suppressed through time-delay, reducing the interference of aliasing on the sampling and filtering function of the Sigma-Delta ADC and ensuring its signal conversion accuracy. The specific technical solution is as follows:

[0005] A Sigma-Delta analog-to-digital converter (ADC) with aliasing suppression function is disclosed. The Sigma-Delta ADC includes a preset loop filter module, a sampling module, a quantizer, and a preset feedback DAC module. The preset loop filter module, sampling module, and quantizer are connected in series. The preset loop filter module includes a chopper. The preset feedback DAC module is connected between the loop filter module and the quantizer to suppress aliasing introduced by the chopper, allowing the sampling module to sample the valid signal, which is then quantized by the quantizer. All poles of the transfer function of the preset feedback DAC module are located at the aliasing points introduced by the chopper.

[0006] Furthermore, the preset feedback DAC module is an m-1 order feedback DAC module. The pole frequency of the transfer function of the preset feedback DAC module is an integer multiple of the ratio of the sampling frequency to m, such that the pole frequency of the transfer function of the preset feedback DAC module is equal to the aliasing frequency introduced by the chopper, or all poles of the transfer function of the preset feedback DAC module are located in the frequency aliasing interval introduced by the chopper; where m is a positive integer; and the number of taps of the filter set inside the preset feedback DAC module is m.

[0007] Furthermore, the chopper frequency is equal to the ratio of the sampling frequency to twice m; the sampling frequency is the sampling frequency belonging to the sampling module; the chopper frequency is the chopper frequency configured to be used by the chopper during the chopping process in the Sigma-Delta analog-to-digital converter, used to offset flicker noise so that the flicker noise is offset outside the signal frequency band.

[0008] Furthermore, the preset feedback DAC module includes an interpolation filter, a modulator, and a preset filter; the interpolation filter, modulator, and preset filter are connected in sequence; the preset filter is used to periodically extend the signal output by the modulator so that the denominator polynomial of the transfer function of the preset feedback DAC module forms an expansion of the order of the preset filter; wherein, the order of the interpolation filter and the order of the preset filter are both m-1; wherein, the transfer function of the preset feedback DAC module is the ratio of the output signal of the preset feedback DAC module to the input signal of the preset feedback DAC module in the frequency domain.

[0009] Further, the preset filter includes m delay units, a coefficient matching module, and an accumulator; the m delay units are connected in series to generate m digital input signals representing different delays for the aforementioned periodic extension processing; wherein, the first-stage delay unit among the m series delay units is used to input the signal output by the modulator; the coefficient matching module is used to provide a matching filter coefficient for each digital input signal, multiply each digital input signal by its matching filter coefficient, and then output the corresponding product; the accumulator is used to add each product output by the coefficient matching module to obtain a signal that has undergone digital-to-analog conversion and filtering processing, so that the output signal of the preset filter is an analog signal; wherein, the modulator outputs a digital signal.

[0010] Furthermore, the preset loop filtering module includes an N-stage integrator and a chopper; the preset loop filtering module is divided into a first chopper submodule and a loop filtering submodule; wherein, the first chopper submodule includes a first-stage integrator and a chopper connected together; the loop filtering submodule includes a second-stage integrator to an Nth-stage integrator.

[0011] Furthermore, the integrators exist in the preset loop filter module in a cascaded manner, with the input of each integrator connected to the corresponding summing node, and each integrator corresponding to a summing node; the preset feedback DAC module is connected between the input of the summing node corresponding to the first-stage integrator and the output of the quantizer. The preset feedback DAC module is used to periodically extend the quantized output signal output by the quantizer and convert it into a first feedback signal, and then transmit the first feedback signal to the input of the summing node corresponding to the first-stage integrator.

[0012] Furthermore, the Sigma-Delta analog-to-digital converter also includes a compensation feedback circuit; the compensation feedback circuit is connected between the summing node corresponding to the last stage integrator and the output terminal of the quantizer, and is used to compensate the preset loop filter module so that the noise transfer function of the preset loop filter module is restored; wherein, the compensation feedback circuit includes a feedback DAC, which is used to receive the quantized output signal output by the quantizer, convert the quantized output signal into a second feedback signal, and then transmit the second feedback signal to the summing node corresponding to the last stage integrator.

[0013] Furthermore, the first-stage integrator includes a first operational amplifier; the chopper includes an input chopper and an output chopper; the input chopper is connected to the input terminal of the first operational amplifier, and the output chopper is connected to the output terminal of the first operational amplifier, for reducing the flicker noise generated by the first operational amplifier.

[0014] Furthermore, the first-stage summing node corresponding to the first-stage integrator is provided with a first input terminal, a second input terminal, and an output terminal; the first input terminal of the first-stage summing node is used to receive an analog input signal, and the second input terminal of the first-stage summing node is used to receive a first feedback signal output by the preset feedback DAC module; the output terminal of the first-stage summing node is used to output a first-stage summing analog signal to the input chopper; wherein, the first-stage summing node is used to sum the analog signal and the first feedback signal provided by the preset feedback DAC module, and configure the sum value as the first-stage summing analog signal.

[0015] Furthermore, the first chopper submodule also includes a first branch resistor and a second branch resistor; the input terminal of the first branch resistor is configured as the first input terminal of the first-stage summing node; the output terminal of the first branch resistor is configured as the output terminal of the first-stage summing node; the input terminal of the second branch resistor is configured as the second input terminal of the first-stage summing node; and the output terminal of the second branch resistor is configured as the output terminal of the first-stage summing node.

[0016] Further, the loop filtering submodule includes N-1 stage summing nodes, N-1 stage integrators, and a final stage operational amplifier; the N-1 stage integrators include second-stage integrators to Nth-stage integrators, corresponding sequentially to the second-stage summing nodes to the Nth-stage summing nodes; wherein, the Nth-stage integrator is the last stage integrator; each stage summing node has a first input terminal, a second input terminal, and an output terminal; the output terminal of the last stage integrator is connected to the input terminal of the final stage operational amplifier, the output terminal of the final stage operational amplifier is connected to the input terminal of the sampling module, and the output terminal of the final stage operational amplifier is used to output a pre-feedback analog signal; the first input terminal of the i-th stage summing node is connected to the output terminal of the (i-1)-th stage integrator, and the first input terminal of the i-th stage summing node is used to receive the (i-1)-th stage integrated analog signal output by the (i-1)-th stage integrator; the second input terminal of the i-th stage summing node is connected to the output terminal of the final stage operational amplifier. The connection is as follows: the second input terminal of the i-th stage summing node is used to receive the pre-feedback analog signal output by the final operational amplifier; the output terminal of the i-th stage summing node is connected to the input terminal of the i-th stage integrator, and the output terminal of the i-th stage summing node is used to output the i-th stage summing analog signal to the input terminal of the i-th stage integrator, wherein the i-th stage summing analog signal is the sum of the (i-1)-th stage integrated analog signal and the pre-feedback analog signal output by the final operational amplifier; the i-th stage integrator is used to integrate the i-th stage summing analog signal and then output the i-th stage integrated analog signal; the (i-1)-th stage integrator is used to integrate the output signal of the (i-1)-th stage summing node to obtain the (i-1)-th stage integrated analog signal; wherein N is a positive integer; i is an integer greater than 1 and less than or equal to N-1; wherein each stage integrator is a continuous-time structure used to integrate the input signal through a continuous-time structure.

[0017] Furthermore, in addition to the first and second input terminals, the Nth-level summing node also has N-1 preset input terminals; in the first to N-1th level summing nodes, the signal input to the first input terminal of each level summing node is also configured to be input to the corresponding preset input terminal in the Nth-level summing node; the first input terminal of the Nth-level summing node is connected to the output terminal of the N-1th-level integrator, and the first input terminal of the Nth-level summing node is used to receive the N-1th-level integrated analog signal output by the N-1th-level integrator; the second input terminal of the i-th-level summing node... The input terminal is used to receive the feedback signal used to compensate the preset loop filter module; the output terminal of the Nth stage summing node is used to output the Nth stage summing analog signal to the Nth stage integrator; wherein, the Nth stage summing node is used to sum the N-1 stage integrated analog signal, the feedback signal used to compensate the preset loop filter module, and the signal input by each preset input terminal, and the sum value is configured as the Nth stage summing analog signal; wherein, the Nth stage integrator is used to receive the integration of the Nth stage summing analog signal to obtain the Nth stage integrated analog signal.

[0018] Furthermore, within the loop filtering submodule, each integrator stage includes a pre-configured operational amplifier. The input terminal of the pre-configured operational amplifier is configured as the input terminal of the corresponding first-stage summation node, and the output terminal of the pre-configured operational amplifier is configured as the output terminal of the corresponding first-stage summation node. The branch resistors are divided into a first preset resistor and a second preset resistor. The output terminal of the first preset resistor in the first-stage integrator is connected to the input terminal of the pre-configured operational amplifier in the first-stage integrator, and the input terminal of the second preset resistor in the first-stage integrator is configured as the second input terminal of the first-stage summation node. The output terminal of the first preset resistor in the last-stage integrator is connected to the input terminal of the pre-configured operational amplifier in the last-stage integrator, and the input terminal of the second preset resistor in the last-stage integrator is configured as the second input terminal of the last-stage summation node.

[0019] Further, N is a value of 3; when the number of quantization bits of the quantizer is set to a value of 1, the quantizer is used to quantize the analog signal sampled by the sampling module into a single-bit digital signal; the preset feedback DAC module is used to convert the 1-bit digital signal output by the quantizer into an analog signal used to suppress the aliasing introduced by the chopper.

[0020] Compared with existing technologies, when the chopper is integrated into the first-stage integrator of the Sigma-Delta analog-to-digital converter, the pole frequency generated by the transfer function of the preset feedback DAC module is fed back to the cascaded integrator. This utilizes the periodic stretching effect (i.e., time stretching effect) of the preset feedback DAC module according to the number of taps to suppress the aliasing generated by the chopper, reduce the interference caused by signal folding in the frequency band, reduce the noise aliasing problem caused by the chopping technology in the Sigma-Delta analog-to-digital converter, repair and maintain the effective signal processed by the Sigma-Delta analog-to-digital converter, and thus ensure the signal conversion accuracy of the Sigma-Delta analog-to-digital converter.

[0021] This invention delegates aliasing suppression to a feedback loop consisting of a preset loop filter module, a sampling module, a quantizer, and a preset feedback DAC module. This repairs the sampling, filtering, and conversion functions of the circuit within the corresponding signal frequency band. It not only shifts 1 / f noise outside the signal frequency band but also suppresses frequency aliasing introduced by the chopper. Furthermore, it overcomes the DAC nonlinearity problem caused by the offset associated with the reference DAC. This makes the error caused by the nonlinearity of the feedback DAC inside the continuous Sigma-Delta analog-to-digital converter negligible at the baseband, thus improving the reliability of the ADC system. Attached Figure Description

[0022] Figure 1 This is a module framework diagram of a Sigma-Delta analog-to-digital converter with anti-aliasing function disclosed in an embodiment of the present invention.

[0023] Figure 2 This is a schematic diagram of the structure of an N-order continuous Sigma-Delta analog-to-digital converter disclosed in another embodiment of the present invention.

[0024] Figure 3 This is a schematic diagram of the internal structure of the first chopper submodule with a differential structure disclosed in another embodiment of the present invention.

[0025] Figure 4 This is a schematic diagram of the internal structure of a preset feedback DAC module with an interpolation filter disclosed in another embodiment of the present invention. Detailed Implementation

[0026] The technical solutions of the present invention will now be described in detail with reference to the accompanying drawings.

[0027] In bandwidth-limited low-frequency applications, frequency shifting is used to significantly attenuate 1 / f noise after filtering. Current technology often employs choppers for this purpose, reducing 1 / f noise generated by the connected operational amplifier. Necessarily, the chopper's frequency needs to be at least an order of magnitude away from the effective sampling signal bandwidth to prevent residual flicker noise from disrupting this bandwidth. However, when choppers are used in some Sigma-Delta analog-to-digital converters (ADCs), they introduce aliasing. This includes shifting and folding high-frequency and low-frequency signal components together, causing adjacent Nyquist bands to overlap, resulting in frequency aliasing. This effectively disrupts the normal sampling and filtering function of the built-in low-pass filter in the Sigma-Delta ADC, preventing the processing of effective signals within the relevant frequency band. This leads to unstable signal sampling and conversion, decreased accuracy, and can easily cause nonlinearity in the feedback DAC output of the Sigma-Delta ADC.

[0028] As one embodiment, to reduce interference from aliasing introduced by the chopper, this invention discloses a Sigma-Delta analog-to-digital converter with aliasing suppression function, such as... Figure 1 As shown, the Sigma-Delta analog-to-digital converter includes a preset loop filter module, a sampling module, a quantizer, and a preset feedback DAC module; Figure 1 From left to right, the preset loop filter module, sampling module, and quantizer are connected in series. In this embodiment, the preset loop filter module includes a chopper. Generally, after the chopper is connected to the first-stage operational amplifier of the preset loop filter module, the chopper performs chopping at a specific chopping frequency. However, the chopper introduces aliasing into the preset loop filter module, causing noise folding and affecting the sampling module's ability to sample effective signals. The sampling module, as a sampling circuit of any type, is controlled by the clock signal of the Sigma-Delta analog-to-digital converter's internal or external components. In some embodiments, the sampling module can also be combined with an amplifier, operational amplifier, comparator, etc., and thus can be incorporated into the preset loop filter module as part of the loop filter disclosed in the prior art to realize the generation, transformation, and processing of electrical signals. Therefore, in this embodiment, the preset feedback DAC module is connected between the loop filter module and the quantizer to suppress the aliasing introduced by the chopper and allow the sampling module to sample effective signals in a predetermined frequency band, including signals to be converted with reasonable frequency or amplitude values. Figure 1As shown, the preset feedback DAC module, loop filter module, sampling module, and quantizer are connected to form a feedback loop, which serves to process the aliasing phenomenon present in the loop filter module. Specifically, all poles of the transfer function of the preset feedback DAC module are located at the aliasing points introduced by the chopper, that is, the aliasing frequency or the frequency domain near the aliasing frequency is occupied by the pole frequencies of the transfer function of the preset feedback DAC module. This repairs the filtering function of the preset loop filter module, enabling it to filter effective analog signals and have them sampled by the sampling module even in the presence of aliasing, and then quantized and encoded by the quantizer for output. In some embodiments, since all poles of the transfer function of the preset feedback DAC module are located at the aliasing points introduced by the chopper, signals on even harmonics of the chopper frequency are canceled and / or signals on odd harmonics of the chopper frequency are canceled, which can reduce flicker noise in the low-frequency region and suppress aliasing introduced by the chopper.

[0029] As one example, combined with Figure 4 It is known that the preset feedback DAC module is an m-1 order feedback DAC module. The pole frequencies of the preset feedback DAC module's transfer function are integer multiples of the ratio of the sampling frequency to m, such that the pole frequencies of the preset feedback DAC module's transfer function are equal to the aliasing frequency introduced by the chopper, or all poles of the preset feedback DAC module's transfer function are located within the frequency aliasing interval introduced by the chopper; where m is a positive integer. The number of taps of the filter set inside the preset feedback DAC module is m, that is, the order of the filter is m-1, which can also be equivalent to the order of the filtered harmonics. When the denominator term of the preset feedback DAC module's transfer function is factored, at most m roots of the denominator polynomial can be obtained, which serve as the aforementioned poles, located exactly at the corresponding aliasing frequency introduced by the chopper, or equal to the harmonic frequency; where the highest power of the denominator polynomial in the general expression of the preset feedback DAC module's transfer function represents the order of the filter. In some embodiments, when the sampling frequency is fs, the pole frequencies of the transfer function of the preset feedback DAC module include fs / m, 2*fs / m, 3*fs / m, 4*fs / m, ..., fs / 2, all of which are positive integer multiples of the ratio of the sampling frequency to m. Of course, in other embodiments, they can also be negative integer multiples of the ratio of the sampling frequency to m. The transfer function of the preset feedback DAC module designed in this embodiment reduces the circuit complexity, enabling the trigonometric integral modulator to be chopped at the "maximum" rate of fs / 2.

[0030] Based on the above embodiments, within the Sigma-Delta analog-to-digital converter, the chopper frequency is equal to the ratio of the sampling frequency to twice m, in order to suppress aliasing introduced by the chopper. It should be noted that the aforementioned sampling frequency fs belongs to the sampling frequency of the sampling module. The operational amplifier connected to the chopper within the preset loop filter module is allowed to be chopped at the "maximum" rate of fs / 2. The chopper frequency is configured as the chopper frequency used by the chopper during the chopping process within the Sigma-Delta analog-to-digital converter, used to offset flicker noise so that the flicker noise is offset outside the signal frequency band, thus the flicker noise may be canceled or attenuated in the overall circuit.

[0031] It should be noted that the operating frequency of the sampling module is not high enough to match the sampling frequency, and its application is currently mostly limited to low-frequency regions such as the audio frequency band. The switching element built into the sampling module receives the analog signal output by the loop filter module at the sampling frequency, and then samples and transmits it to the quantizer. In some embodiments, the sampling module alternately uses the transmission phase and the sampling phase to process the analog signal output by the loop filter module within one clock cycle.

[0032] As one example, such as Figure 4 As shown, the preset feedback DAC module includes an interpolation filter, a modulator, and a preset filter. The interpolation filter, modulator, and preset filter are connected sequentially to form a digital-to-analog converter with interpolation filtering function, which is an improvement over existing feedback DACs. The preset filter is used to periodically extend the signal output by the modulator, so that the denominator polynomial of the transfer function of the preset feedback DAC module forms an expansion of the order of the preset filter. It should be noted that the order of both the interpolation filter and the preset filter is m-1. The transfer function of the preset feedback DAC module is the ratio of the output signal to the input signal in the frequency domain. In this embodiment, the quantized output signal from the quantizer is filtered by the interpolation filter to output a code stream. The code stream is modulated by the modulator to output a digital code stream of a specific number of bits. Preferably, the modulator has a Sigma-Delta structure, and the output digital code stream is given to the first-stage delay unit. Then, the digital code stream of a specific number of bits is input to the preset filter to complete the digital-to-analog conversion and filtering function.

[0033] Specifically, such as Figure 4As shown, the preset filter includes m delay units, a coefficient matching module, and an accumulator; m equals the number of taps in the preset filter. The m delay units are connected in series to generate m digital input signals representing different delays for the aforementioned periodic extension processing; wherein, the first-stage delay unit in the series-connected m delay units is used as the input signal from the modulator output; the series-connected m delay units can also form an m-bit serial shift register. When the modulator outputs a 1-bit digital code stream, the 1-bit digital code stream is buffered by the series-connected m delay units to output an m-bit digital code stream, where the m-bit digital code stream represents 1-bit digital signals with different delays, such as... Figure 3 As shown, from left to right, the m 1-bit digital signals are D0, D1, D2, ..., Dm-1. These m signals are buffered in their corresponding registers. Except for the first 1-bit digital signal D0, the inputs of the remaining m-1 registers are connected to the outputs of their corresponding delay units. These m delay units can be delay units connected in series within an m-bit serial shift register. A coefficient matching module provides a matching filter coefficient for each digital input signal, multiplies each digital input signal by its matching filter coefficient, and outputs the corresponding product. An accumulator adds each product output by the coefficient matching module to obtain a signal that has undergone digital-to-analog conversion and filtering, ensuring that the output signal of the preset filter is an analog signal, a filtered quantized output signal, preferably a digital differential output signal. In summary, the preset filter disclosed in this embodiment only requires an adder and a delay, simplifying the calculation, reducing the complexity of the filter circuit implementation, improving the linearity of the digital-to-analog conversion signal, and enabling the preset feedback DAC module to obtain the pole at the aforementioned aliasing frequency.

[0034] In some embodiments, the coefficient matching module is equivalent to... Figure 4The filter coefficients a(0), a(1), a(2), ..., a(m-1) shown are multiplied by m unit current sources, and the multiplication results are then input into the accumulator for summation. The implementation structure of the preset filter is preferably a direct implementation of a finite impulse response (FIR) filter. The FIR filter mainly consists of a current source array, a coefficient matching module, and an accumulator. The filter coefficients need to be determined according to the actual filtering characteristics required. The filter coefficients involved are implemented through current sources, or the current source array can be directly connected to a node to complete the current summation function. Specifically, in the current source array, the length of the transistor is represented by L, the width by W, and the current magnitude is determined by W / L. Changing the length or width can change the current magnitude. For example, if the transistor size of a unit current source is 4 / 4, then a transistor size of 4 / 1 or 16 / 4 can obtain a current of 4 times the size of the unit current source. Therefore, in one embodiment of the present invention, different filter coefficients can be achieved by changing the length and width of the transistors, which reduces the size of the current source array compared to the conventional method of only changing the transistor width to achieve different coefficients.

[0035] As one example, combined with Figure 1 and Figure 4It is known that the input terminal of the preset filter is connected to the output terminal of the modulator, and the output terminal of the preset filter is connected to the input terminal of the summing node corresponding to the first-stage integrator. The accuracy of the output signal of the preset filter is higher than that of the quantizer output signal. Level adjustment is specifically performed by the preset filter and / or the interpolation filter. The number of taps of the preset filter determines the level adjustment stage, and the speed of level adjustment is related to the sampling frequency. The preset feedback DAC module is used to convert the filtered signal into the first feedback signal in real time, and then transmit the first feedback signal to the input terminal of the summing node corresponding to the first-stage integrator. Within the preset feedback DAC module, the preset filter performs period extension processing, the modulator performs modulation, and the interpolation filter performs filtering synchronously. It should be noted that the preset filter or interpolation filter internally has filter coefficients, which can be determined according to the actual required filtering characteristics, or in this embodiment, determined according to the degree of period extension of the signal. Accordingly, the preset filter introduces a filter transfer function into the preset feedback DAC module. In this embodiment, the filter coefficients are parameters belonging to the filter transfer function. The filter transfer function is configured to filter the digital code stream output by the modulator according to the filter transfer function, thereby performing a time-stretching operation on the digital code stream. Then, the preset filter outputs an analog signal. Optionally, the output analog signal is a current signal. The current signal is input to a buffer, which converts the current signal into a voltage signal to form the first feedback signal. The buffer can be connected in series to the output terminal of the preset filter.

[0036] As one example, such as Figure 2 As shown, the preset loop filter module includes an N-stage integrator and a chopper; the preset loop filter module is divided into... Figure 2 The first chopper submodule shown and Figure 2 The loop filtering submodule shown includes a first chopper submodule comprising a first-stage integrator and a chopper connected together, wherein one chopper can be placed at the input and one at the output of the relevant operational amplifier structure; the loop filtering submodule includes a second-stage integrator to an Nth-stage integrator, wherein the first-stage integrator and the second-stage integrator maintain a cascaded structure. Therefore, the output of the first-stage integrator is the integral result of the sum of the analog signal input to the Sigma-Delta analog-to-digital converter and the feedback signal fed back to the Sigma-Delta analog-to-digital converter from the preset feedback DAC module.

[0037] Combination Figure 2It can be seen that the integrators exist in the preset loop filter module in a cascaded manner. The input of each integrator stage is connected to a corresponding summation node, so that one integrator stage corresponds to one summation node. Therefore, the input of each integrator stage is connected to a unique summation node, and each summation node corresponds to an integrator of the same stage. Figure 2 The "+" is circled in the middle; for example, the preset loop filter module includes at least two stages of summing nodes and at least two stages of integrators, specifically... Figure 2 The first-stage integrator, second-stage integrator, third-stage integrator, ..., N-1-stage integrator, and N-stage integrator (i.e., the last stage integrator) are shown. Correspondingly, the input of the first-stage integrator is connected to the first-stage summation node, the input of the second-stage integrator is connected to the second-stage summation node, the input of the third-stage integrator is connected to the third-stage summation node, ..., the input of the N-1-stage integrator is connected to the N-1-stage summation node, and the input of the N-stage integrator is connected to the N-stage summation node.

[0038] The preset feedback DAC module is connected between the input of the summing node corresponding to the first-stage integrator and the output of the quantizer. The preset feedback DAC module performs periodic extension processing on the quantized output signal from the quantizer and converts it into a first feedback signal, which is then transmitted to the input of the summing node corresponding to the first-stage integrator. Specifically, the preset feedback DAC module extends the quantized output signal from the quantizer in the discrete-time domain, which is mathematically equivalent to processing the quantized output signal according to a relevant Z-function. This is essentially a delay processing; it can be understood that the preset feedback DAC module performs multiple delay processes for each periodic extension process, and it converts the digital signal generated by each delay process into an analog signal, i.e., the first feedback signal, in real time. When the quantization bit count of the quantizer is 1, whenever a delay process is performed on a 1-bit quantized output signal, the preset feedback DAC module feeds back an analog signal to the first-stage summing node.

[0039] It should be noted that the signal input to the preset loop filter module is an analog signal. After processing by the cascaded integrator and the feedback processing of the preset feedback DAC module, it is equivalent to filtering the analog signal at each summing node of the input. Furthermore, the quantizer quantizes the output signal of the loop filter submodule, outputting a bit stream with a value of +1 or -1, corresponding to a high or low level, converting it into a digital code stream represented using "1 / 0". Therefore, the quantized output signal is a digital signal. Quantizers can be divided into one-bit quantizers and multi-bit quantizers. Using a multi-bit quantizer can increase the signal-to-noise ratio, making the Sigma-Delta analog-to-digital converter easier to stabilize, generating fewer harmonic components, and ensuring sufficient accuracy of the preset feedback DAC module to guarantee the accuracy of the final feedback analog signal.

[0040] As one example, combined with Figure 3 It is understood that within the first chopper submodule, the first-stage integrator includes a first operational amplifier; the chopper includes an input chopper and an output chopper; in some embodiments, the input chopper and the output chopper can be incorporated into the first-stage integrator to form part of the integrator together with the first operational amplifier. The first operational amplifier supports differential input and differential output, and both the input chopper and the output chopper support differential input and differential output, meaning that the first operational amplifier, the input chopper, and the output chopper can all have dual-channel input and dual-channel output; the input chopper is connected to the input terminal of the first operational amplifier to chop the input of the first operational amplifier; the output chopper is connected to the output terminal of the first operational amplifier to chop the output of the first operational amplifier; thereby reducing the flicker noise generated by the first operational amplifier and mitigating the degree of noise degradation within the frequency band.

[0041] In the above embodiment, the first-level summing node corresponding to the first-level integrator ( Figure 2The first circled "+" on the left has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first-stage summing node is used to receive an analog input signal, and the second input terminal of the first-stage summing node is used to receive a first feedback signal output by the preset feedback DAC module. The output terminal of the first-stage summing node is used to output a first-stage summed analog signal to the input chopper. Specifically, the first-stage summing node sums the analog signal and the first feedback signal provided by the preset feedback DAC module, and configures this sum as the first-stage summed analog signal. Further, the first chopper submodule includes a first branch resistor and a second branch resistor. The input terminal of the first branch resistor is configured as the first input terminal of the first-stage summing node; the output terminal of the first branch resistor is configured as the output terminal of the first-stage summing node; the input terminal of the second branch resistor is configured as the second input terminal of the first-stage summing node; and the output terminal of the second branch resistor is configured as the output terminal of the first-stage summing node.

[0042] As one embodiment, the first operational amplifier, the input chopper, and the output chopper are all differential structures, providing differential inputs and differential outputs. Figure 3 As shown, the first branch resistor includes a first branch resistor and a first second branch resistor, and the first-stage summing node includes a first-stage summing node and a first-second-stage summing node. The two differential outputs of the input chopper are connected to the two differential inputs of the first operational amplifier, and the two differential inputs of the output chopper are connected to the two differential outputs of the first operational amplifier.

[0043] Specifically, such as Figure 3 As shown, the input terminal of the first two-branch resistor serves as the second input terminal of the first-stage summing node, used to receive the first differential feedback signal Vdac1 output by the preset feedback DAC module, wherein the aforementioned first feedback signal is a differential analog output signal; the input terminal of the first branch resistor is configured as the first input terminal of the first-stage summing node, used to receive the first analog differential input signal Vin1; the first-stage summing node is used to sum the first analog differential input signal Vin1 and the first differential feedback signal Vdac1, and configure the sum as the first-stage summing analog signal, wherein the signs of the first analog differential input signal Vin1 and the first differential feedback signal Vdac1 may be different; the output terminals of the first branch resistor and the first two-branch resistor are both configured as the output terminals of the first-stage summing node, and the output terminals of the first branch resistor and the first two-branch resistor are both connected to the positive differential input terminal of the input chopper, and the output terminal of the first-stage summing node is used to output the first-stage summing analog signal to the input chopper.

[0044] The input terminal of the second branch resistor serves as the second input terminal of the first secondary summing node, used to receive the second differential feedback signal Vdac2 output by the preset feedback DAC module. The aforementioned first feedback signal is a differential analog output signal, and the preset feedback DAC module outputs two differential feedback signals. The input terminal of the second branch resistor is configured as the first input terminal of the first secondary summing node, used to receive the second analog differential input signal Vin2. The first secondary summing node sums the second analog differential input signal Vin2 and the second differential feedback signal Vdac2, and configures this sum as the first secondary summing analog signal. The signs of the second analog differential input signal Vin2 and the second differential feedback signal Vdac2 may be different. The output terminals of both the second branch resistor and the second branch resistor are configured as output terminals of the first secondary summing node. Both the output terminals of the second branch resistor and the second branch resistor are connected to the negative differential input terminal of the input chopper. The output terminal of the first secondary summing node outputs the first secondary summing analog signal to the input chopper.

[0045] Furthermore, the input chopper is used to chop the first-stage summation analog signal and the first-stage summation analog signal to reduce flicker noise. Then, the chopped first-stage summation analog signal and the first-stage summation analog signal are fed into the first operational amplifier for integration to obtain the first-stage integrated analog signal.

[0046] Preferably, the first input terminal of the first-stage summing node and the first input terminal of the first-stage summing node are respectively connected to the two differential output terminals of an operational amplifier. Then, the first-stage summing node (i.e., the first-stage summing node and the first-stage summing node) receives analog input signals from outside the Sigma-Delta analog-to-digital converter through the operational amplifier, including the first analog differential input signal Vin1 and the second analog differential input signal Vin2, so as to improve the driving capability of analog signals.

[0047] It should be noted that during the aforementioned aliasing suppression process, the first operational amplifier operates in a closed-loop state, meaning that the first operational amplifier, input chopper, output chopper, and connected capacitors and resistors form a closed-loop structure. The first chopper submodule also includes a first integrating capacitor and a second integrating capacitor. These two integrating capacitors are connected across the two input terminals of the input chopper and the two output terminals of the output chopper. Specifically, the first integrating capacitor is connected across the positive input terminal of the input chopper and the positive output terminal of the output chopper, and the second integrating capacitor is connected across the negative input terminal of the input chopper and the negative output terminal of the output chopper. Thus, the first integrating capacitor, the second integrating capacitor, the first operational amplifier, the output chopper, and the input chopper form the aforementioned closed-loop structure. Because the proportional accuracy of the integrating capacitor can be well controlled, it can effectively compensate for the noise signal introduced by the preset feedback DAC module and the signal changes caused by the related transfer function.

[0048] As one example, combined with Figure 2It is known that the Sigma-Delta analog-to-digital converter further includes a compensation feedback circuit; the compensation feedback circuit is connected between the summing node corresponding to the last stage integrator and the output terminal of the quantizer, and is used to compensate the preset loop filter module so that the noise transfer function of the preset loop filter module is restored; wherein, the compensation feedback circuit includes a feedback DAC, which is used to receive the quantized output signal output by the quantizer, convert the quantized output signal into a second feedback signal, and then transmit the second feedback signal to the summing node corresponding to the last stage integrator. Specifically, the compensation feedback circuit can time-delay the quantized output signal from the quantizer and convert it from digital to analog to the second feedback signal. This second feedback signal is then transmitted to the summing node corresponding to the last integrator stage (i.e., the last-stage summing node). Specifically, the compensation feedback circuit extends the quantized output period of the quantizer in the discrete frequency domain, mathematically equivalent to processing the quantized output signal according to the relevant Z-function, which is equivalent to a delay processing, achieving the cancellation of the noise signal newly introduced by the aforementioned preset feedback DAC module. The node where the second feedback signal is fed back to the preset loop filter module is different from the node where the first feedback signal is fed back. Optionally, the time-delay processing performed by the compensation feedback circuit can cancel the same type of parameters at the same frequency generated by the preset feedback DAC module from the dimensions of the filter coefficients and / or the amplitude values ​​at the corresponding time nodes. This effectively makes the frequency content of the feedback signal at a specific frequency point generated by the preset feedback DAC module empty, allowing the noise transfer function of the preset loop filter module to be restored, that is, dynamically adjusting the delay state of the transfer function of the Sigma-Delta analog-to-digital converter back to the pre-set original transfer function. The compensation feedback circuit disclosed in this embodiment can assist the preset feedback DAC module in obtaining more accurate extended processing results while reducing conversion time; thereby enabling the accuracy of the digital signal converted by the Sigma-Delta analog-to-digital converter to converge faster, improving the linearity of the analog signal output by the feedback loop of the Sigma-Delta analog-to-digital converter, and achieving a balance between the component matching index and accuracy required for the DAC formed in the preset feedback DAC module.

[0049] As one example, such as Figure 2As shown, the loop filtering submodule includes N-1 stages of summing nodes, N-1 stages of integrators, and a final operational amplifier. The N-1 stages of integrators include second-stage integrators to Nth-stage integrators, corresponding sequentially to the second-stage summing nodes to the Nth-stage summing nodes. The Nth-stage integrator is the last stage integrator. Each stage of summing nodes has a first input terminal, a second input terminal, and an output terminal. The output terminal of the last stage integrator is connected to the input terminal of the final stage operational amplifier, and the output terminal of the final stage operational amplifier is connected to the input terminal of the sampling module. The output terminal of the final stage operational amplifier is used to output a pre-feedback analog signal. The pre-feedback analog signal is obtained by the N-stage integrator chopping and integrating the analog signal input to the preset loop filtering module, and receiving the first feedback signal output by the preset feedback DAC module for repair and cancellation. In this embodiment, the first input terminal of the i-th stage summing node is connected to the output terminal of the (i-1)-th stage integrator, and the first input terminal of the i-th stage summing node is used to receive the (i-1)-th stage integrated analog signal output by the (i-1)-th stage integrator; the second input terminal of the i-th stage summing node is connected to the output terminal of the final stage operational amplifier, and the second input terminal of the i-th stage summing node is used to receive the pre-feedback analog signal output by the final stage operational amplifier; the output terminal of the i-th stage summing node is connected to the input terminal of the i-th stage integrator, and the output terminal of the i-th stage summing node is used to convert the i-th stage integrator into the i-th stage integrated analog signal. The stage summation analog signal is output to the input of the i-th stage integrator, where the i-th stage summation analog signal is the sum of the (i-1)-th stage integration analog signal and the pre-feedback analog signal output from the final operational amplifier. The i-th stage integrator integrates the i-th stage summation analog signal and outputs the i-th stage integration analog signal. The (i-1)-th stage integrator integrates the output signal of the (i-1)-th stage summation node to obtain the (i-1)-th stage integration analog signal. Here, N is a positive integer; i is an integer greater than 1 and less than or equal to N-1. This makes the pre-feedback analog signal the analog feedback signal for each integrator stage except the first and last integrators, which helps overcome the offset problem within the integrator and ensures the linearity of the signal. The i-th stage integrator integrates the i-th stage summation analog signal and outputs the i-th stage integration analog signal. Here, N is a positive integer; i is an integer greater than 1 and less than or equal to N-1. Correspondingly, when i equals 2, the (i-1)-th stage integrator is... Figure 2 The first-stage integrator shown is the i-th-stage integrator. Figure 2 The second-stage integrator is shown. In summary, the analog signal output by the loop filtering submodule is compatible with the feedback loop formed inside the Sigma-Delta analog-to-digital converter, and also ensures the accuracy of the digital signal quantized by the quantizer.

[0050] It should be noted that the number of integrators in the Sigma-Delta analog-to-digital converter determines the order of the Sigma-Delta converter. Generally, a higher order results in better amplitude-frequency characteristics, more severe attenuation in the low-frequency band, better high-frequency throughput, and a larger effective number of bits. However, the delay will also be significant, reducing the swing of the input signal. In addition, excessive noise amplitude at high frequencies can reduce the stability of the entire system. Therefore, the value of N must be set considering the amplitude of the analog signal that needs to be converted into a digital signal in the preset loop filter module to meet the matching and accuracy requirements of the relevant feedback DAC.

[0051] Based on the above embodiments, the Nth-level summing node, in addition to having a first input terminal and a second input terminal, also has N-1 preset input terminals; wherein, the Nth-level summing node is Figure 2 The rightmost circled "+"; in the first to N-1 level summing nodes, the signal input to the first input terminal of each level summing node is also configured to be input to the corresponding preset input terminal in the N-th level summing node; the first input terminal of the N-th level summing node is connected to the output terminal of the N-1 level integrator, and the first input terminal of the N-th level summing node is used to receive the N-1 level integrated analog signal output by the N-1 level integrator; the second input terminal of the i-th level summing node is used to receive the feedback signal used to compensate the preset loop filter module; the N-th level summing node is used to process the N-1 level integrated analog signal, used to compensate for the feedback signal of the preset loop filter module. The Nth-stage summation node sums the feedback signal from the preset loop filter module and the signals input to each preset input terminal, and configures this sum as the Nth-stage summation analog signal. The output of the Nth-stage summation node is used to output the Nth-stage summation analog signal to the Nth-stage integrator. The Nth-stage summation node sums the (N-1)th-stage integrated analog signal, the feedback signal from the preset loop filter module, and the signals input to each preset input terminal, and configures this sum as the Nth-stage summation analog signal. The Nth-stage integrator receives and integrates the Nth-stage summation analog signal to obtain the Nth-stage integrated analog signal. This allows the sampling module to sample a relatively stable analog signal. In summary, the Nth-stage integrator in the Sigma-Delta analog-to-digital converter has lower performance requirements for the operational amplifier and can achieve a higher sampling rate.

[0052] In the above embodiments, the Sigma-Delta analog-to-digital converter is a differential circuit that supports differential input and differential output. Specifically, within the loop filtering submodule, each integrator stage includes a branch resistor and a pre-configured operational amplifier. The output of the branch resistor is connected to the input of the pre-configured operational amplifier. The input of the branch resistor is configured as the input of the corresponding first-stage summing node, and the output of the branch resistor is configured as the output of the corresponding first-stage summing node. Within the loop filtering submodule, the input of the pre-configured operational amplifier is the input of its respective integrator. The first input of each summing node is the input of one branch resistor within the corresponding first-stage integrator, and the second input of each summing node is the input of another branch resistor within the corresponding first-stage integrator. The cascade number of the corresponding first-stage integrator in the loop filtering module is equal to the cascade number of the summing node within the same loop filtering module. Furthermore, each preset input of the last summing node is the input of the corresponding branch resistor within the last-stage integrator. Therefore, the more input terminals of the pre-configured operational amplifier, the more input branches are provided for summation. This minimizes the nonlinearity introduced by the mismatch of current sources within the loop filter module.

[0053] Specifically, the branch resistance can be divided into a first preset resistor and a second preset resistor. The input terminal of the first preset resistor in the second-stage integrator is configured as the second input terminal of the second-stage summing node. The output terminal of the first preset resistor in the second-stage integrator is connected to the input terminal of a pre-configured operational amplifier in the second-stage integrator. The input terminal of the second preset resistor in the second-stage integrator is configured as the second input terminal of the second-stage summing node. The output terminal of the second preset resistor in the second-stage integrator is connected to the input terminal of a pre-configured operational amplifier in the second-stage integrator. Both the output terminals of the first and second preset resistors in the second-stage integrator are connected to the same input terminal of the pre-configured operational amplifier in the second-stage integrator, including the positive input terminal of the operational amplifier. Or a negative input terminal; similarly, the input terminal of the first preset resistor in the last stage integrator is configured as the first input terminal of the last stage summing node, the output terminal of the first preset resistor in the last stage integrator is connected to the input terminal of the pre-configured operational amplifier in the last stage integrator, the input terminal of the second preset resistor in the last stage integrator is configured as the second input terminal of the last stage summing node, and the output terminal of the second preset resistor in the last stage integrator is connected to the input terminal of the pre-configured operational amplifier in the last stage integrator, wherein the output terminals of the first preset resistor and the second preset resistor in the last stage integrator are both input terminals with the same electrode attribute as the pre-configured operational amplifier in the last stage integrator, including the positive or negative input terminal of the operational amplifier. In summary, for each stage of the summing node of each analog signal in the input analog differential signal, each input terminal of each stage of the summing node is connected to a branch resistor. The input terminal of the branch resistor is configured as an input terminal of the summing node, and the output terminal of the branch resistor is connected to the same input terminal of the pre-configured operational amplifier. The output terminal of the branch resistor is configured as the output terminal of the summing node.

[0054] In the foregoing embodiments, each integrator stage is a continuous-time structure used to integrate the input signal. Therefore, the Sigma-Delta analog-to-digital converter (ADC) is configured as a continuous-time Sigma-Delta ADC. Compared to traditional discrete Sigma-Delta ADCs, the continuous-time Sigma-Delta ADC disclosed in this embodiment has lower performance requirements for its built-in operational amplifiers due to its built-in preset loop filter module, allowing for higher sampling rates and lower sensitivity requirements for its internal capacitors. It should be noted that the continuous-time Sigma-Delta ADC places the sampling module after the cascaded integrators, unlike the discrete Sigma-Delta ADC. Furthermore, the continuous-time Sigma-Delta ADC can reduce the system's requirements for the operational amplifier speed in the integrator, offering significant advantages in power consumption and speed, making it suitable for low-frequency applications.

[0055] In summary, compared with existing technologies, when integrating a chopper into the first-stage integrator of the Sigma-Delta analog-to-digital converter, the pole frequency generated by the transfer function of the preset feedback DAC module is fed back to the cascaded integrator. This utilizes the periodic stretching effect (i.e., time stretching effect) of the preset feedback DAC module based on the number of taps to suppress aliasing generated by the chopper, reducing interference caused by signal folding in the frequency band. This also reduces noise aliasing caused by chopping technology in the Sigma-Delta analog-to-digital converter, repairs and maintains the effective signal processed by the Sigma-Delta analog-to-digital converter within the corresponding frequency band, thereby ensuring the accuracy of signal conversion in the Sigma-Delta analog-to-digital converter. This invention delegates aliasing suppression to a feedback loop consisting of a preset loop filter module, a sampling module, a quantizer, and a preset feedback DAC module. This repairs the sampling, filtering, and conversion functions of the circuit within the corresponding signal frequency band. It not only shifts 1 / f noise outside the signal frequency band but also suppresses frequency aliasing introduced by the chopper. Furthermore, it overcomes the DAC nonlinearity problem caused by the offset associated with the reference DAC. This makes the error caused by the nonlinearity of the feedback DAC inside the continuous Sigma-Delta analog-to-digital converter negligible at the baseband, thus improving the reliability of the ADC system.

[0056] As one embodiment, when N is 3, a third-order Sigma-Delta analog-to-digital converter is formed. When the quantization bit count of the quantizer is set to 1, the quantizer is used to quantize the analog signal sampled by the sampling module into a 1-bit digital signal. The preset feedback DAC module is used to convert the single-bit digital signal output by the quantizer into an analog signal used to suppress aliasing introduced by the chopper. The signal flow and effects of the preset loop filter module, sampling module, quantizer, and preset feedback DAC module are the same as in the previous embodiment and will not be repeated here.

[0057] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them; although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications can still be made to the specific implementation of the present invention or equivalent substitutions can be made to some technical features without departing from the spirit of the technical solutions of the present invention, and all such modifications and substitutions should be covered within the scope of the technical solutions claimed in the present invention.

Claims

1. A Sigma-Delta analog-to-digital converter with anti-aliasing function, characterized in that, The Sigma-Delta analog-to-digital converter includes a preset loop filter module, a sampling module, a quantizer, and a preset feedback DAC module; The preset loop filter module, sampling module, and quantizer are connected in series in sequence. The preset loop filter module includes a chopper; The preset feedback DAC module is connected between the loop filter module and the quantizer to suppress aliasing introduced by the chopper; In this case, all poles of the transfer function of the preset feedback DAC module are located at the aliasing introduced by the chopper. The preset feedback DAC module includes an interpolation filter, a modulator, and a preset filter; the interpolation filter, modulator, and preset filter are connected in sequence. The preset filter is used to periodically extend the signal output by the modulator so that the denominator polynomial of the transfer function of the preset feedback DAC module is formed as the expansion of the order of the preset filter. In this context, the order of the interpolation filter and the order of the preset filter are both m-1; The transfer function of the preset feedback DAC module is the ratio of the output signal of the preset feedback DAC module to the input signal of the preset feedback DAC module in the frequency domain. The preset loop filtering module includes an N-stage integrator and a chopper; The preset loop filtering module is divided into a first chopper submodule and a loop filtering submodule; The first chopper submodule includes a first-stage integrator and a chopper connected together; the loop filter submodule includes a second-stage integrator to an Nth-stage integrator. The integrators exist in the preset loop filter module in a cascaded manner, with the input of each integrator connected to the corresponding summing node, and each integrator corresponding to a summing node.

2. The Sigma-Delta analog-to-digital converter according to claim 1, characterized in that, The preset feedback DAC module is an m-1 order feedback DAC module. The pole frequency of the transfer function of the preset feedback DAC module is equal to an integer multiple of the ratio of the sampling frequency to m, such that the pole frequency of the transfer function of the preset feedback DAC module is equal to the aliasing frequency introduced by the chopper, or all poles of the transfer function of the preset feedback DAC module are located in the frequency aliasing interval introduced by the chopper. Where m is a positive integer; The preset feedback DAC module has a filter with m taps.

3. The Sigma-Delta analog-to-digital converter according to claim 2, characterized in that, The chopper frequency is equal to the ratio of the sampling frequency to twice the value of m. The chopper frequency is configured to be the chopper frequency used during the chopping process within the Sigma-Delta analog-to-digital converter to offset flicker noise so that the flicker noise is shifted outside the signal frequency band.

4. The Sigma-Delta analog-to-digital converter according to claim 2, characterized in that, The preset filter includes m delay units, a coefficient matching module, and an accumulator; m delay units are connected in series to generate m digital input signals representing different delays for the aforementioned periodic extension processing; wherein, the first-stage delay unit among the m series delay units is used to input the signal output by the modulator. The coefficient matching module is used to provide a matching filter coefficient for each of the digital input signals, multiply each of the digital input signals by its matching filter coefficient, and then output the corresponding product; An accumulator is used to add up each product output by the coefficient matching module to obtain a signal that has undergone digital-to-analog conversion and filtering, so that the output signal of the preset filter is an analog signal; wherein, the output of the modulator is a digital signal.

5. The Sigma-Delta analog-to-digital converter according to claim 1, characterized in that, The preset feedback DAC module is connected between the input of the summing node corresponding to the first-stage integrator and the output of the quantizer. The preset feedback DAC module is used to periodically extend the quantized output signal output by the quantizer and convert it into a first feedback signal, and then transmit the first feedback signal to the input of the summing node corresponding to the first-stage integrator.

6. The Sigma-Delta analog-to-digital converter according to claim 1, characterized in that, The Sigma-Delta analog-to-digital converter also includes a compensation feedback circuit; The compensation feedback circuit is connected between the summing node corresponding to the last stage integrator and the output of the quantizer. The compensation feedback circuit is used to compensate the preset loop filter module so that the noise transfer function of the preset loop filter module is restored. The compensation feedback circuit includes a feedback DAC, which receives the quantized output signal from the quantizer, converts the quantized output signal into a second feedback signal, and then transmits the second feedback signal to the summing node corresponding to the last stage integrator.

7. The Sigma-Delta analog-to-digital converter according to claim 5, characterized in that, The first-stage integrator includes a first operational amplifier; the chopper includes an input chopper and an output chopper; An input chopper is connected to the input terminal of the first operational amplifier, and an output chopper is connected to the output terminal of the first operational amplifier to reduce the flicker noise generated by the first operational amplifier.

8. The Sigma-Delta analog-to-digital converter according to claim 7, characterized in that, The first-stage summing node corresponding to the first-stage integrator is provided with a first input terminal, a second input terminal, and an output terminal; The first input terminal of the first-level summing node is used to receive the analog input signal, and the second input terminal of the first-level summing node is used to receive the first feedback signal output by the preset feedback DAC module; The output of the first-stage summing node is used to output the first-stage summing analog signal to the input chopper; The first-level summing node is used to sum the analog signal and the first feedback signal provided by the preset feedback DAC module, and configure the sum value as the first-level summed analog signal.

9. The Sigma-Delta analog-to-digital converter according to claim 8, characterized in that, The first chopper submodule also includes a first branch resistor and a second branch resistor; The input terminal of the first branch resistor is configured as the first input terminal of the first-stage summing node; the output terminal of the first branch resistor is configured as the output terminal of the first-stage summing node. The input terminal of the second branch resistor is configured as the second input terminal of the first-stage summing node; The output of the second branch resistor is configured as the output of the first-stage summing node.

10. The Sigma-Delta analog-to-digital converter according to claim 5, characterized in that, The loop filtering submodule includes N-1 stage summing nodes, N-1 stage integrators, and a final operational amplifier; the N-1 stage integrators include second-stage integrators to Nth-stage integrators, corresponding sequentially to second-stage summing nodes to Nth-stage summing nodes; wherein, the Nth-stage integrator is the last stage integrator; each stage summing node has a first input terminal, a second input terminal, and an output terminal; The output of the final stage integrator is connected to the input of the final stage operational amplifier, the output of the final stage operational amplifier is connected to the input of the sampling module, and the output of the final stage operational amplifier is used to output the pre-feedback analog signal. The first input of the i-th stage summing node is connected to the output of the (i-1)-th stage integrator, and is used to receive the (i-1)-th stage integrated analog signal output by the (i-1)-th stage integrator. The second input of the i-th stage summing node is connected to the output of the final stage operational amplifier, and is used to receive the pre-feedback analog signal output by the final stage operational amplifier. The output of the i-th stage summing node is connected to the input of the i-th stage integrator, and is used to output the i-th stage summing analog signal to the input of the i-th stage integrator. The i-th stage summing analog signal is the sum of the (i-1)-th stage integrated analog signal and the pre-feedback analog signal output by the final stage operational amplifier. The i-th stage integrator is used to integrate the i-th stage summation analog signal and then output the i-th stage integrated analog signal; the (i-1)-th stage integrator is used to integrate the output signal of the (i-1)-th stage summation node to obtain the (i-1)-th stage integrated analog signal. Where N is a positive integer; i is an integer greater than 1, and i is an integer less than or equal to N-1; Each integrator stage is a continuous-time structure used to integrate the input signal through a continuous-time structure.

11. The Sigma-Delta analog-to-digital converter according to claim 10, characterized in that, In addition to the first and second input terminals, the Nth level summation node also has N-1 preset input terminals; In the first-level summing node to the (N-1)th-level summing node, the signal input to the first input terminal of each level summing node is also configured to be input to the corresponding preset input terminal in the Nth-level summing node; The first input of the Nth-level summing node is connected to the output of the (N-1)th-level integrator, and the first input of the Nth-level summing node is used to receive the (N-1)th-level integrated analog signal output by the (N-1)th-level integrator; the second input of the i-th-level summing node is used to receive the feedback signal used to compensate the preset loop filter module. The output of the Nth-level summing node is used to output the Nth-level summing analog signal to the Nth-level integrator; wherein, the Nth-level summing node is used to sum the N-1th-level integrated analog signal, the feedback signal used to compensate the preset loop filter module, and the signal input to each preset input terminal, and the sum value is configured as the Nth-level summing analog signal; The Nth-stage integrator is used to receive and integrate the Nth-stage summed analog signal to obtain the Nth-stage integrated analog signal.

12. The Sigma-Delta analog-to-digital converter according to claim 11, characterized in that, Within the loop filtering submodule, each integrator includes a pre-configured operational amplifier. The input of the pre-configured operational amplifier is configured as the input of the corresponding first-level summing node, and the output of the pre-configured operational amplifier is configured as the output of the corresponding first-level summing node. The branch resistance is divided into a first preset resistance and a second preset resistance; The output of the first preset resistor in the first-stage integrator is connected to the input of the pre-configured operational amplifier in the first-stage integrator, and the input of the second preset resistor in the first-stage integrator is configured as the second input of the first-stage summing node. The output of the first preset resistor in the last stage integrator is connected to the input of the pre-configured operational amplifier in the last stage integrator, and the input of the second preset resistor in the last stage integrator is configured as the second input of the last stage summing node.

13. The Sigma-Delta analog-to-digital converter according to claim 10, characterized in that, N is the value 3; When the number of quantization bits of the quantizer is set to a value of 1, the quantizer is used to quantize the analog signal sampled by the sampling module into a single-bit digital signal. The preset feedback DAC module is used to convert the 1-bit digital signal output by the quantizer into an analog signal used to suppress aliasing introduced by the chopper.

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