Arithmetic devices and multiply-accumulate arithmetic systems

Abstract

An arithmetic device includes a plurality of arithmetic circuit units, a signal output circuit, and a common wiring unit. The common wiring unit electrically connects a plurality of signal output lines of the signal output circuit to a plurality of input lines, each of which includes the plurality of input lines. The plurality of arithmetic circuit units includes a first arithmetic circuit unit and a second arithmetic circuit unit. Electrical signals output from the plurality of signal output lines of the signal output circuit are input as electrical signals corresponding to input values ​​to the plurality of input lines, each of which includes the plurality of input lines, via the common wiring unit. The plurality of output lines of the first arithmetic circuit unit and the plurality of output lines of the second arithmetic circuit unit are arranged to extend parallel to each other.

Description

Technical Field

[0001] The present technology relates to an arithmetic device and a multiply-accumulate system applicable to multiply-accumulate operations using an analog method. Background Art

[0002] Conventionally, a technology for performing multiplication and accumulation has been developed. Multiplication and accumulation is an operation that multiplies each of multiple input values ​​by a weight and adds the multiplication results to each other, and is used, for example, in processing such as recognizing images and sounds using neural networks.

[0003] For example, Patent Document 1 describes an analog circuit in which a multiplication-accumulation process is performed in an analog manner. In this analog circuit, a weight corresponding to each of a plurality of electrical signals is set. In addition, charges according to the corresponding electrical signals and weights are output respectively, and the output charges are appropriately accumulated in the capacitor. The value to be calculated representing the result of the multiplication-accumulation is calculated based on the voltage of the capacitor to which the charges are accumulated. Therefore, unlike, for example, digital processing (paragraphs

[0003] ,

[0049] to

[0053] and

[0062] of the specification of Patent Document 1, Figure 3 Compared with other methods (such as FPGA, FPGA, etc.), it can reduce the power consumption required for multiplication and accumulation operations.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: WO 2018 / 034163 Summary of the Invention

[0007] Technical Problems to be Solved by the Invention

[0008] The use of such analog-type circuits is expected to lead to low power consumption in neural networks and the like, and it is desirable to provide a technique capable of improving the accuracy of multiplication-accumulation operations.

[0009] In view of the above circumstances, an object of the present technology is to provide an arithmetic device and a multiply-accumulate system by which the operation accuracy of an analog type circuit that performs multiply-accumulate operations can be improved.

[0010] Solution to the problem

[0011] In order to achieve the above-mentioned object, an arithmetic device according to an embodiment of the present technology includes a plurality of arithmetic circuit units, a signal output circuit, and a common wiring circuit.

[0012] The plurality of arithmetic circuit units each include a plurality of input lines and a plurality of output lines.

[0013] A plurality of input lines are arranged in parallel using a predetermined direction as an extending direction, and electric signals corresponding to input values ​​are input to the plurality of input lines, respectively.

[0014] Using a direction different from a predetermined direction as an extension direction, multiple output lines are arranged in parallel to intersect with multiple input lines, and each output of the multiple output lines represents a multiplication-accumulation signal of the sum of product values ​​obtained by multiplying an input value generated based on an electrical signal input into the multiple input lines by a weight value.

[0015] The signal output circuit includes a plurality of signal output lines capable of outputting electrical signals respectively.

[0016] The common wiring unit electrically connects a plurality of signal output lines of the signal output circuit to a plurality of input lines, each of the plurality of arithmetic circuit units including the plurality of input lines.

[0017] The plurality of arithmetic circuit units include a first arithmetic circuit unit and a second arithmetic circuit unit.

[0018] The electric signals output from the plurality of signal output lines of the signal output circuit are input as electric signals corresponding to input values ​​to the plurality of input lines each of the first arithmetic circuit unit and the second arithmetic circuit unit includes via the common wiring unit.

[0019] An extending direction of the plurality of output lines of the first arithmetic circuit unit and an extending direction of the plurality of output lines of the second arithmetic circuit unit are arranged to be parallel to each other.

[0020] The common wiring unit may be configured using, as a reference, a wiring reference plane set based on a positional relationship between the first arithmetic circuit unit and the second arithmetic circuit unit.

[0021] The common wiring unit may include a plurality of reference lines arranged in parallel so as to extend in the same direction on a wiring reference plane.

[0022] In each of the plurality of arithmetic circuit units, a plurality of input lines and a plurality of output lines may be set by using a predetermined plane as a reference plane. In this case, the wiring reference plane may be set based on a positional relationship between a first reference plane serving as a reference plane for the first arithmetic circuit unit and a second reference plane serving as a reference plane for the second arithmetic circuit unit.

[0023] The first reference plane and the second reference plane may be arranged side by side on the same plane. In this case, the wiring reference plane may be arranged parallel to the same plane where the first reference plane and the second reference plane are arranged.

[0024] The common wiring unit may include a plurality of reference lines arranged in parallel so as to extend in the same direction on the wiring reference plane. In this case, the extension direction of the plurality of reference lines may be set to be parallel to the direction in which the first reference plane and the second reference plane are arranged side by side.

[0025] The first reference plane and the second reference plane may be arranged side by side in an extending direction of the plurality of input lines of the first arithmetic circuit unit or in an extending direction of the plurality of output lines of the first arithmetic circuit unit.

[0026] The first reference plane and the second reference plane may be arranged side by side to be orthogonal to a predetermined reference direction. In this case, the wiring reference plane is set parallel to the reference direction.

[0027] The wiring reference plane may be set to be parallel to a reference direction and an extending direction of the plurality of output lines of the first arithmetic circuit unit.

[0028] The common wiring unit may include a plurality of reference lines arranged in parallel so as to extend in the same direction on the wiring reference plane. In this case, the extension directions of the plurality of reference lines may be set to be parallel to the reference direction.

[0029] The common wiring unit may include a plurality of reference lines arranged in parallel so as to extend in the same direction on a wiring reference plane. In this case, the common wiring unit may include at least one of a first wiring unit electrically connecting the plurality of signal output lines of the signal output circuit to the plurality of reference lines, a second wiring unit electrically connecting the plurality of reference lines to the plurality of input lines of the first arithmetic circuit unit, or a third wiring unit electrically connecting the plurality of reference lines to the plurality of input lines of the second arithmetic circuit unit.

[0030] The common wiring unit may include a first wiring unit, a second wiring unit, and a third wiring unit. In this case, the first wiring unit, the second wiring unit, and the third wiring unit may extend in the same direction.

[0031] The common wiring unit may include a second wiring unit and a third wiring unit. In this case, the second wiring unit and the third wiring unit may be composed of the same wiring unit.

[0032] The common wiring unit may include a plurality of reference lines arranged in parallel so as to extend in the same direction on the wiring reference plane. In this case, the plurality of reference lines may be connected to each of the output-side ends of the plurality of signal output lines of the signal output circuit, the input-side ends of the plurality of input lines of the first arithmetic circuit unit, and the input-side ends of the plurality of input lines of the second arithmetic circuit unit.

[0033] An extension direction of the plurality of input lines of the first arithmetic circuit unit and an extension direction of the plurality of input lines of the second arithmetic circuit unit may be configured to be parallel to each other.

[0034] The plurality of signal output lines of the signal output circuit may be arranged in parallel so as to extend in the same direction. In this case, the extension direction of the plurality of signal output lines of the signal output circuit may be configured to be parallel to the extension direction of the plurality of input lines of the first arithmetic circuit unit.

[0035] The plurality of output lines included in each of the plurality of arithmetic circuit units may be arranged to extend in a direction parallel to the direction of extension of the plurality of output lines of the first arithmetic circuit unit. In this case, the electrical signals output from the plurality of signal output lines of the signal output circuit may be input as electrical signals corresponding to input values ​​to the plurality of input lines included in each of the plurality of arithmetic circuit units via the common wiring unit.

[0036] The common wiring unit may include a switch unit that outputs the electrical signals output from the plurality of signal output lines of the signal output circuit to each of the plurality of arithmetic circuit units in a switchable manner.

[0037] In order to achieve the above-mentioned object, an arithmetic device according to another embodiment of the present technology includes a plurality of arithmetic circuit units, a signal input circuit, and a common wiring unit.

[0038] The plurality of multiplication-accumulation result signal output lines output multiplication-accumulation result signals representing multiplication-accumulation results generated based on the multiplication-accumulation signals output through the plurality of output lines.

[0039] The signal input circuit includes a plurality of signal input lines, and a multiplication accumulation result signal output from each of the plurality of multiplication accumulation result signal output lines is input to each of the plurality of signal input lines.

[0040] The common wiring unit electrically connects a plurality of multiplication-accumulation result signal output lines included in each of the plurality of arithmetic circuit units to a plurality of signal input lines of the signal input circuit.

[0041] The multiplication accumulation result signals output from the plurality of multiplication accumulation result signal output lines included in each of the first arithmetic circuit unit and the second arithmetic circuit unit are input into the plurality of signal input lines of the signal input circuit.

[0042] An extending direction of the plurality of output lines of the first arithmetic circuit unit and an extending direction of the plurality of output lines of the second arithmetic circuit unit are arranged to be parallel to each other.

[0043] A multiplication-accumulation system according to an embodiment of the present technology includes the above-described plurality of arithmetic circuit units, a signal output circuit, a common wiring unit, and a network circuit.

[0044] A network circuit is configured by connecting a plurality of arithmetic circuit units. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 is a schematic diagram showing a configuration example of an arithmetic device according to the embodiment (one-input one-output configuration);

[0046] Figure 2 is a schematic diagram showing a configuration example of an arithmetic device according to the embodiment (two-input two-output configuration);

[0047] Figure 3 is a schematic diagram showing an example of an electrical signal to be input (one-input one-output configuration);

[0048] Figure 4 is a schematic diagram showing an example of electrical signals to be input (dual-input dual-output configuration);

[0049] Figure 5 is a schematic diagram showing a configuration example of the arithmetic circuit unit 5 (one-input one-output configuration);

[0050] Figure 6 is a schematic diagram showing a configuration example of a neuron circuit (one-input one-output configuration);

[0051] Figure 7 is a schematic diagram showing a configuration example of the arithmetic circuit unit 5 (two-input two-output configuration);

[0052] Figure 8 is a schematic diagram showing a configuration example of a neuron circuit (two-input two-output configuration);

[0053] Figure 9 is a diagram showing a configuration example of an arithmetic circuit unit in an arithmetic device having a one-input-one-output configuration;

[0054] Figure 10 is a diagram showing a configuration example of an arithmetic circuit unit in an arithmetic device having a one-input-one-output configuration;

[0055] Figure 11 is a diagram showing a configuration example of an arithmetic circuit unit in an arithmetic device having a two-input two-output configuration;

[0056] Figure 12 is a diagram showing a configuration example of an arithmetic circuit unit in an arithmetic device having a two-input two-output configuration;

[0057] Figure 13 is a schematic diagram showing a configuration example of an inference device including an arithmetic device according to the present technology;

[0058] Figure 14 is a table describing the convolution operations performed by the inference device;

[0059] Figure 15is a diagram describing the convolution operation performed by the inference device;

[0060] Figure 16 A schematic diagram showing examples of “a plurality of input lines”, “a plurality of output lines” and a “reference plane” of an arithmetic circuit unit;

[0061] Figure 17 is a schematic diagram showing an example of an arrangement configuration according to the present technology;

[0062] Figure 18 is shown as Figure 17 A schematic diagram of an example of a common wiring unit WC configured according to the wiring configuration shown;

[0063] Figure 19 is shown as Figure 17 A schematic diagram of an example of a common wiring unit WC configured according to the wiring configuration shown;

[0064] Figure 20 is a schematic diagram showing an example of a switch mechanism provided in a common wiring unit;

[0065] Figure 21 is a schematic diagram showing another configuration example of the arrangement configuration and the common wiring unit;

[0066] Figure 22 is a schematic diagram showing another example of an arrangement configuration;

[0067] Figure 23 is shown as Figure 22 A schematic diagram of an example of a common wiring unit WC configured according to the wiring configuration shown;

[0068] Figure 24 is shown as Figure 22 A schematic diagram of an example of a common wiring unit WC configured according to the wiring configuration shown;

[0069] Figure 25 is a schematic diagram showing another configuration example of the arrangement configuration and the common wiring unit;

[0070] Figure 26 is a schematic diagram showing another configuration example of the arrangement configuration and the common wiring unit;

[0071] Figure 27 is a schematic diagram showing an example of a configuration of an arrangement configuration and a configuration of a common wiring unit arranged between a plurality of arithmetic circuit units and a signal input circuit;

[0072] Figure 28 is a schematic diagram showing an example of a configuration of an arrangement configuration and a configuration of a common wiring unit arranged between a plurality of arithmetic circuit units and a signal input circuit;

[0073] Figure 29 is a schematic diagram showing an example of a configuration of an arrangement configuration and a configuration of a common wiring unit arranged between a plurality of arithmetic circuit units and a signal input circuit;

[0074] Figure 30 is a schematic diagram showing an example of a configuration of an arrangement configuration and a configuration of a common wiring unit arranged between a plurality of arithmetic circuit units and a signal input circuit;

[0075] Figure 31 is a schematic diagram showing an example of a configuration of an arrangement configuration and a configuration of a common wiring unit arranged between a plurality of arithmetic circuit units and a signal input circuit;

[0076] Figure 32 is a schematic diagram showing another configuration example of an arithmetic device;

[0077] Figure 33 is a schematic diagram for describing a case where the number of inputs (the number of input signal lines) of each of a plurality of arithmetic circuit units is different. DETAILED DESCRIPTION

[0078] Hereinafter, embodiments according to the present technology will be described with reference to the drawings.

[0079] [Configuration of Arithmetic Devices]

[0080] Figure 1 and Figure 2 is a schematic diagram for describing a basic configuration example of an arithmetic device according to an embodiment of the present technology.

[0081] The arithmetic device is an analog type arithmetic device that performs predetermined arithmetic processing including multiplication and accumulation operations. Figure 1 and Figure 2 The illustrated arithmetic device 100 and arithmetic device 200 make it possible to perform arithmetic processing according to a mathematical model (eg, a neural network).

[0082] Figure 1 The illustrated arithmetic device 100 includes a plurality of signal lines 1, a plurality of input units 2, and a plurality of analog circuits 3. Each signal line 1 is a line that transmits a predetermined type of electric signal.

[0083] For example, an analog signal that represents a signal value by using analog quantities such as pulse time and pulse width is used as an electrical signal. The direction of electrical signal transmission is as follows: Figure 1 In this embodiment, the analog circuit 3 corresponds to a multiplication and accumulation circuit.

[0084] For example, a plurality of signal lines 1 are connected to one analog circuit 3. The signal line 1 that transmits an electric signal to the analog circuit 3 is an input signal line, and the electric signal is input to the analog circuit 3 to which the input signal line 1 is connected.

[0085] Furthermore, the signal line 1 that transmits the electrical signal output from the analog circuit 3 is an output signal line, and the electrical signal for the analog circuit 3 connected to the signal line 1 is output from the output signal line.

[0086] The plurality of input units 2 each generate a plurality of electrical signals corresponding to input data 4. The input data 4 is, for example, data to be processed using a neural network or the like implemented by the arithmetic device 100. Therefore, it can also be said that each signal value of the plurality of electrical signals corresponding to the input data 4 is an input value of the arithmetic device 100.

[0087] For example, arbitrary data such as image data, audio data, and statistical data to be processed by the arithmetic device 100 is used as the input data 4. For example, in the case where image data is used as the input data 4, an electric signal is generated using the image pixel value (RGB value, brightness value, etc.) of each pixel of the image data as a signal value. In addition, the electric signal corresponding to the input data 4 can be appropriately generated according to the type of the input data 4 and the content of the processing performed by the arithmetic device 100.

[0088] Analog circuit 3 is an analog circuit that performs a multiplication-accumulation operation based on an input electrical signal. A multiplication-accumulation operation, for example, adds together multiple product values ​​obtained by multiplying multiple input values ​​by weight values ​​corresponding to the input values. Therefore, a multiplication-accumulation operation can also be said to be a process of calculating the sum of the product values ​​(hereinafter referred to as the multiplication-accumulation result).

[0089] like Figure 1 As shown, a plurality of input signal lines are connected to a single analog circuit 3, and a plurality of electrical signals are supplied to the single analog circuit 3. According to this embodiment, the plurality of input signal lines and the plurality of analog circuits constitute the arithmetic circuit unit 5. In addition, a plurality of electrical signals are input from each input signal line, and the multiplication-accumulation method according to this embodiment is accordingly executed by the multiplication-accumulation circuit (analog circuit 3).

[0090] Hereinafter, it is assumed that the total number of electrical signals input to one analog circuit 3 is denoted by N. It should be noted that the number N of electrical signals to be input to each analog circuit 3 is set to be appropriate for each circuit according to, for example, a model of arithmetic processing, accuracy, etc.

[0091] In the simulation circuit 3, for example, w is calculated i *x i , which is an input value x represented by an electric signal input from the i-th input signal line i and corresponding to the input value x i The weight value w iHere, i represents a natural number equal to or less than N (i = 1, 2, ..., N). The operation of the product value is performed for each electrical signal (input signal line), and N product values ​​are calculated. The value obtained by adding the N product values ​​is calculated as the multiplication accumulation result (the sum of the N product values). Therefore, the multiplication accumulation result calculated by one analog circuit 3 is expressed by the following expression.

[0092] [Formula 1]

[0093]

[0094] Weight value w i is set, for example, at −α≤w i ≤+α. Here, α represents an arbitrary real value. Therefore, the weight value w i Can include positive weight value w i , negative weight value w i , zero weight value w i As mentioned above, by setting the weight value w i Setting it within a predetermined range can prevent the multiplication and accumulation results from diverging.

[0095] In addition, for example, setting the weight value w i The range of can be normalized. In this case, the weight value w i is set at -1≤w i ≤ 1. Therefore, for example, the maximum value, minimum value, etc. of the multiplication-accumulation result can be adjusted, and the multiplication-accumulation operation can be performed with desired accuracy.

[0096] In neural networks, etc., a method called binary connection can be used, which converts the weight value w i Set to +α or -α. Binary connections are used in various fields, for example, image recognition using deep neural networks (multi-layer neural networks).

[0097] The use of binary connections can simplify the weight value w i The absolute values ​​of the positive and negative weight values ​​in the binary connection are fixed to the same value.

[0098] As mentioned above, in a binary connection, the weight value w i is binarized into binary values ​​(±α). Therefore, for example, by i By changing it to positive or negative, you can easily set the desired weight value w i Alternatively, the binarized weight value w i can be normalized, and the weight value w i Can be set to ±1.

[0099] Alternatively, the weight value w i Can be multi-valued. In this case, the weight value w is selected and set from multiple discrete weight value candidates i Examples of candidate weight values ​​may include an example of (-3, -2, -1, 0, 1, 2, 3) and an example of (1, 2, 5, 10).

[0100] Alternatively, normalized weight value candidates (-1, -0.5, 0, 0.5, 1) etc. may be used. A value is selected from these candidate weight values ​​and set as the weight value w i The number of weight value candidates, the method of setting the candidate values, etc. are not limited. For example, by making the weight value w i Multi-valued, more general neural networks can be constructed, etc.

[0101] In addition, the weight value w i The setting range, setting value, etc. of are not limited and can be appropriately set so that, for example, desired processing accuracy is achieved. i Can be set randomly.

[0102] The input value x shown in the expression (Formula 1) i For example, the value of the input data 4 output from the input unit 2 and the value of the multiplication and accumulation result output from the analog circuit 3. Therefore, it can also be said that the input unit 2 and the analog circuit 3 serve to output the input value x i signal source.

[0103] exist Figure 1 In the example shown, a single electrical signal (single input value x i ) is output from one signal source (input unit 2, analog circuit 3). Therefore, the same electrical signal is input to each of the plurality of signal lines 1 connected to the output side of one signal source. In addition, one signal source and the analog circuit 3 to which the electrical signal output from the signal source is input are connected to each other via a single input signal line.

[0104] So, for example, in Figure 1 In the arithmetic device 100 shown, M input signal lines are connected to the analog circuit 3, and the analog circuit 3 is connected to M signal sources. In this case, the total number of electrical signals input to the analog circuit 3 is N=M.

[0105] like Figure 1 As shown, the arithmetic device 100 has a layered structure in which a plurality of analog circuits 3 are provided in each of a plurality of layers. That is, a plurality of arithmetic circuit units 5 are connected in cascade.

[0106] For example, a multilayer perceptron (MLP) type neural network or the like is constructed by configuring a hierarchical structure of analog circuits 3. For example, the number of analog circuits provided in each layer, the number of layers, etc. are appropriately designed so that desired processing can be performed. Hereinafter, the number of analog circuits 3 provided in the jth layer will sometimes be referred to as N. j .

[0107] For example, N electrical signals generated by N input units 2 are input to each analog circuit 3 provided in one layer (lowest layer) of the first stage. The analog circuit 3 of the first stage calculates the input value x corresponding to the input data. i The multiplication-accumulation result is correlated, and the calculated multiplication-accumulation result is output to the analog circuit 3 provided in the next layer (second stage) after nonlinear conversion processing.

[0108] N1 electrical signals representing the respective multiplication-accumulation results calculated in the first stage are input to the respective analog circuits 3 provided in the second layer (upper layer). Therefore, from the perspective of the analog circuits 3 in the second layer, the nonlinear conversion processing results of the respective multiplication-accumulation results calculated in the first layer are the input values ​​x of the electrical signals. i The analog circuit 3 of the second stage calculates the input value x output from the first stage. i The multiplication and accumulation result is output to the upper analog circuit 3.

[0109] Thus, in the arithmetic device 100, the multiplication-accumulation result of the upper layer analog circuit 3 is calculated based on the multiplication-accumulation result calculated by the lower layer analog circuit 3. Such processing is performed a plurality of times, and the processing result is obtained from the top layer ( Figure 1 Thus, for example, processing such as image recognition in which it is determined that the object is a cat based on image data (input data 4) obtained by imaging a cat can be performed.

[0110] As described above, a desired network circuit can be configured by appropriately connecting the arithmetic circuit unit 5 including a plurality of analog circuits 3. The network circuit serves as a data flow processing system that performs arithmetic processing by, for example, passing a signal therethrough. In the network circuit, various processing functions can be realized by appropriately setting, for example, weight values ​​(synaptic connections). Using this network circuit, a multiplication-accumulation system according to this embodiment is constructed.

[0111] It should be noted that the method of connecting analog circuits 3 to each other is not limited. For example, a plurality of analog circuits 3 can be connected to each other as appropriate so that desired processing can be performed. For example, even when analog circuits 3 are connected to each other to configure a structure other than a hierarchical structure, the present technology can be applied.

[0112] For example, it is also possible to configure a plurality of analog circuits 3 included in each of a plurality of arithmetic circuit units 5 in a switchable manner, in which an electrical signal corresponding to input data 4 or an electrical signal corresponding to a multiplication-accumulation result output from an analog circuit 3 in a previous layer is output from a signal source.

[0113] For example, it is assumed that the input data 4 has already been stored in the storage device as digital data. In addition, it is assumed that the multiplication and accumulation results output from the plurality of analog circuits 3 of the arithmetic circuit unit 5 in each layer are also converted into digital data and stored.

[0114] In this case, for example, input data 4 read from a storage device is converted into an analog signal (electrical signal) by a signal source and input to the corresponding analog circuit 3 in the lowest layer. Furthermore, for example, digital data of the multiplication-accumulation result of the analog circuit 3 in the Lth layer is read and converted into an analog signal (electrical signal) by the same signal source, and then input to the analog circuit 3 in the L+1th layer.

[0115] In this way, the embodiment of the arithmetic device 100 according to the present technology can also be realized with a configuration in which a common signal source is used for a plurality of arithmetic circuit units 5 .

[0116] Furthermore, the present technology is not limited to a configuration in which the multiplication-accumulation results calculated in the lower layer are input to the upper layer as they are, and, for example, conversion processing or the like may be performed on the multiplication-accumulation results. For example, in a neural network model, a process is performed in which a nonlinear conversion is performed on the multiplication-accumulation results of each analog circuit 3 by using an activation function, for example, and the conversion result is input to the upper layer.

[0117] In the arithmetic device 100, a functional circuit 6 is used, for example, to perform nonlinear conversion on an electrical signal using an activation function. The functional circuit 6 is, for example, a circuit provided between a lower layer and an upper layer, which appropriately converts the signal value of an input electrical signal and outputs an electrical signal corresponding to the conversion result. For example, a functional circuit 6 is provided for each signal line 1. The number of functional circuits 6, their arrangement, and other aspects are appropriately determined based on, for example, a mathematical model implemented in the arithmetic device 100.

[0118] For example, a ramp function (ReLU function) or the like is used as an activation function. For example, when the input value x i When x is 0 or greater, the ReLU function outputs the input value x as is. i , otherwise 0 is output. For example, a functional circuit 6 that implements a ReLU function is appropriately connected to each signal line 1. Thus, the processing of the arithmetic device 100 can be implemented.

[0119] An amplifier circuit may also be provided that amplifies the analog signal output as the multiplication-accumulation result.

[0120] exist Figure 2 In the arithmetic device 200 shown, the signal line 1 includes a positive signal line 1a and a negative signal line 1b. The positive signal line 1a and the negative signal line 1b are arranged in pairs. The positive signal line 1a and the negative signal line 1b serve as a pair of the signal line 1. Hereinafter, the pair of the signal line 1 consisting of the positive signal line 1a and the negative signal line 1b will be referred to as a signal line pair P1. It should be noted that in Figure 2 In FIG, the positive signal line 1a is the signal line 1 connected to the white circle connection point, and the negative signal line 1b is the signal line 1 connected to the black circle connection point.

[0121] Signal line pair P1 transmits a pair of signals corresponding to a single input value (or output value). A signal pair is a pair of electrical signals input to positive signal line 1a and negative signal line 1b, respectively. The signal values ​​of each pair of electrical signals represent the input value. In other words, signal line pair P1 serves as a single transmission path for the input value.

[0122] Input value x uses positive value x + and negative x - Here, the positive value x + is equal to or greater than 0(x + ≥0). In addition, negative values ​​x - is a real number equal to or less than 0 (x - ≤0). Therefore, the input value x is expressed as x=x + +x - (i.e. positive value x + and negative x - Here, for negative values ​​of x - The absolute value of the input value x is expressed as x=x + -|x - |(i.e. positive value x + and negative x - In this way, the input value x can be represented using the difference between two positive real numbers.

[0123] In this embodiment, the signal pair includes a positive signal and a negative signal. A positive signal is a signal with a positive value x + As an electrical signal with a signal value. A positive signal is input to the positive signal line 1a. A negative signal is an electrical signal with a negative value x - The absolute value of |x - |Electrical signal as a signal value. A negative signal is input to the negative signal line 1b. Therefore, both the positive signal and the negative signal included in the signal pair are electrical signals representing positive real numbers.

[0124] Therefore, in this embodiment, the input value x represented by the signal pair is the signal value of the positive signal input to the positive signal line 1a (positive value x + ) and the signal value of the negative signal input to the negative signal line 1b (negative value x- In other words, a positive signal and a negative signal (a signal pair) are generated so that a value obtained by subtracting the signal value of the negative signal from the signal value of the positive signal is the input value x.

[0125] Each of the plurality of input units 2 generates a signal pair corresponding to the value (input value x) of the input data 4. For example, arbitrary data such as image data, audio data, and statistical data to be processed by the arithmetic device 100 is used as the input data 4. In addition, the signal pair corresponding to the input data 4 can be appropriately generated according to the type of the input data 4 and the content of the processing performed by the arithmetic device 200.

[0126] The analog circuit 3 is an analog type circuit that performs multiplication and accumulation operations based on a plurality of input signal pairs.

[0127] Assuming that the total number of signal pairs (input signal line pairs) input to a single analog circuit 3 in the arithmetic device 200 is denoted by N, the total number of input signal lines connected to the analog circuit 3 is 2×N.

[0128] Furthermore, in the multiplication and accumulation operation using the signal pair, the signal value of the positive signal input to the positive signal line 1a (positive value x i + ) and the signal value of the negative signal input to the negative signal line 1b (negative value x i - ) are multiplied by the corresponding weight values ​​to calculate the two product values. Input value x i and weight value w i The product value w i *x i Use these two product values ​​to express it.

[0129] like Figure 2 As shown, in the arithmetic device 200, corresponding to the input value x i A pair of electrical signals (signal pair) is output from a single signal source (input unit 2, analog circuit 3) via a signal line pair P1. That is, the same signal pair is input to each signal line pair P1 connected to the output side of a single signal source. Furthermore, a single signal source and the analog circuit 3 that receives the electrical signal output from the signal source are connected to each other via a single line pair P1 (input signal line pair).

[0130] So, for example, in Figure 2 In the arithmetic device 200 shown, M input signal line pairs are connected to the analog circuit 3, and the analog circuit 3 is connected to M signal sources. In this case, the total number N of signal pairs input to the analog circuit 3 is N = M. It should be noted that the total number of electrical signals input to the analog circuit 3 (i.e., the total number of signal lines 1 connected to the input side) is 2 × M.

[0131] It should be noted that the embodiment of the arithmetic device 200 according to the present technology can also be implemented with a configuration in which a common signal source is used for a plurality of arithmetic circuit units 5 .

[0132] exist Figure 1 In the arithmetic device 100 shown, the input corresponds to a single input value x i A single signal is generated and a single signal is output as the multiplication-accumulation result output from the analog circuit 3. Figure 2 In the arithmetic device 200 shown, the input corresponds to a single input value x i A pair of two signals (signal pair) is obtained, and a pair of two signals (signal pair) is output as the multiplication and accumulation result output from the analog circuit 3.

[0133] Hereinafter, the arithmetic device 100 will be referred to as an arithmetic device having a single-input single-output configuration in some cases. In addition, the arithmetic device 200 will be referred to as an arithmetic device having a two-input two-output configuration in some cases.

[0134] Figure 3 is a schematic diagram showing an example of an electric signal input into the analog circuit 3 of the arithmetic device 100 having a one-input-one-output configuration.

[0135] exist Figure 3 A and Figure 3 A graph showing waveforms of a plurality of electrical signals is schematically shown in each of FIGB. The horizontal axis of the graph represents the time axis, and the vertical axis represents the voltage of the electrical signal.

[0136] An exemplary waveform of an electrical signal according to a pulse width modulation (PWM) method is shown in FIG. Figure 3 For example, the PWM method uses the pulse width of a pulse waveform to represent the input value x. i method.

[0137] That is, in the PWM method, the pulse width of the electrical signal depends on the input value x i Generally, the longer the pulse width, the greater the input value x i The higher.

[0138] Furthermore, the electric signal is input into the analog circuit 3 within a predetermined input period T. More specifically, each electric signal is input into the analog circuit 3 such that the pulse waveform of the electric signal falls within the input period T.

[0139] Therefore, the maximum value of the pulse width of the electric signal is similar to the input period T. It should be noted that the time when each pulse waveform (electric signal) or the like is input is not limited as long as the pulse waveform falls within the input period T.

[0140] In the PWM method, for example, the pulse width τ iThe duty cycle R of the input period T i (=τ i / T) can be used to normalize the input value x i That is, the normalized input value x i is represented as the input value x i =Duty cycle R i .

[0141] It should be noted that the input value x i With pulse width τ i The associated method is not limited, for example, the input value x can be appropriately set i The pulse width τ i , so that calculation processing and the like can be performed with desired accuracy.

[0142] In the case of using an electric signal according to the PWM method, a time-axis analog multiplication-accumulation operation can be performed using the analog circuit 3 according to the PWM method.

[0143] exist Figure 3 FIG. 8B shows an exemplary waveform of an electric signal of a spike timing method (hereinafter referred to as a TACT method).

[0144] The TACT method is to express the input value x by, for example, using the rise time of a pulse i For example, by using a predetermined time as a reference, a pulse is input at a time corresponding to an input value.

[0145] The electric signal is input to the analog circuit 3 within a predetermined input period T. The input value x i It is represented by the pulse input time within the input period T.

[0146] For example, the maximum input value x i Indicated by a pulse input at the same time as the start of the input period T. Minimum input value x i Indicated by a pulse input at the same time as the input period T ends.

[0147] In other words, the input value x i It is represented by the duration from the input time of the pulse to the end time of the input period T.

[0148] For example, the maximum input value x i Represented by a pulse, its duration from the input time of the pulse to the end time of the input period T is equal to the input period T. Minimum input value x i Represented by a pulse, its duration from the input time of the pulse to the end time of the input period T is 0.

[0149] It should be noted that in Figure 3In B, according to the TACT method, a continuous pulse signal that rises to a level corresponding to the input value and remains at the ON level until the multiplication-accumulation result is obtained is used as the electrical signal. The present technology is not limited thereto, and according to the TACT method, a rectangular pulse having a predetermined pulse width or the like may be used as the electrical signal.

[0150] In the case of using an electric signal according to the TACT method, a time-axis analog multiplication-accumulation operation can be performed using the analog circuit 3 according to the TACT method.

[0151] like Figure 3 A and Figure 3 As shown in FIG. 1B, a pulse signal corresponding to an input value in duration relative to the on-time of the input period T can be used as an electric signal corresponding to the input value. It should be noted that, hereinafter, it will be assumed that the input value x represented by each electric signal i It is described by a variable that is 0 or greater and 1 or less.

[0152] Figure 4 is a schematic diagram showing an example of a pair of signals input to the analog circuit 3 of the arithmetic device 200 having a two-input two-output configuration. Figure 4 A and Figure 4 B schematically shows a graph showing the waveforms of the pair of electrical signals (signal pair).

[0153] exist Figure 4 A and Figure 4 In each of B, the above diagram represents the electrical signal input to the positive signal line 1a (positive signal IN + ) waveform. In addition, the figure below shows the electric signal input to the negative signal line 1b (negative signal IN - ) waveform. The horizontal axis of the graph represents the time axis, and the vertical axis represents the voltage of the electrical signal.

[0154] Figure 4 A shows an example of an electrical signal waveform according to the PWM method. In the PWM method, the positive signal IN i + is the value corresponding to the positive value x i + The pulse width of the electrical signal is positive, and its signal value is positive. In addition, the negative signal IN i - is the value corresponding to negative x i - The absolute value of |x i - |The pulse width of the electrical signal, negative value x i - It should be noted that the positive signal IN i + and negative signal INi - Can be entered at different times.

[0155] In addition, the input value x of the signal pair i is obtained by the positive signal IN i + The pulse width is subtracted from the negative signal IN i - Therefore, in the signal pair according to the PWM method, each electric signal (positive signal IN i + and negative signal IN i - ) represents the difference in pulse width between the input values ​​x i .

[0156] Figure 4 B shows an example of the waveform of the electric signal according to the TACT method. In the TACT method, the positive signal IN i + The pulse corresponds to the positive value x i + The positive value of the electrical signal input at the time is its signal value. In addition, the negative signal IN i - The pulse corresponds to the negative value x i - The absolute value of |x i - |The time input electrical signal, the negative value is its signal value.

[0157] The input value x of the signal pair i By positive value x i + and negative x i - The absolute value of |x i - Therefore, the input value x i is obtained by the positive signal IN i + The input time of the pulse minus the negative signal IN i - In this way, in the signal pair according to the TACT method, the difference between the input times of the pulses input to the positive signal line 1a and the negative signal line 1b represents the input value x i .

[0158] It should be noted that in Figure 4In B, according to the TACT method, a continuous pulse signal is used as the electrical signal (positive and negative signals), and each continuous pulse signal rises to a time corresponding to the signal value and remains at the on level until the multiplication accumulation result is obtained. The present technology is not limited to this. According to the TACT method, a rectangular pulse with a predetermined pulse width, etc. can be used as the electrical signal.

[0159] Figure 5 1 is a diagram showing a configuration example of the arithmetic circuit unit 5 provided as one layer in the arithmetic device 100 having a one-input-one-output configuration.

[0160] The arithmetic circuit unit 5 includes a plurality of input signal lines 7 and a plurality of analog circuits 3 .

[0161] In the predetermined input period T, corresponding to the input value x i The signal is input to each of the plurality of input signal lines 7. For example, during the input period T, according to the reference Figure 3 An electric signal of the described PWM method or TACT method is input to each input signal line 7 .

[0162] Each analog circuit 3 includes a pair of output lines 8 , a plurality of synapse circuits 9 , and a neuron circuit 10 .

[0163] like Figure 5 As shown, one analog circuit 3 is configured to extend in a predetermined direction (vertical direction in the figure). A plurality of such analog circuits 3 extending in the vertical direction are arranged in parallel in the horizontal direction, so that the arithmetic circuit unit 5 is configured as a layer. Hereinafter, it is assumed that the analog circuit 3 arranged on the far left in the figure is the first analog circuit 3.

[0164] The pair of output lines 8 are spaced apart from each other. The pair of output lines 8 includes a positive charge output line 8a and a negative charge output line 8b.

[0165] Each of the positive charge output line 8 a and the negative charge output line 8 b is connected to a neuron circuit 10 via a plurality of synapse circuits 9 .

[0166] The plurality of synapse circuits 9 are arranged corresponding to the plurality of input signal lines 7, respectively. A single input signal line 7 is connected to a single synapse circuit 9. For example, the number of synapse circuits 9 provided in a single analog circuit 3 is set to be equal to or smaller than the number of input signal lines 7. That is, the synapse circuit 9 does not need to be connected to all input signal lines 7.

[0167] In this manner, the plurality of synapse circuits 9 are respectively connected to at least some of the plurality of input signal lines 7. The input signal lines 7 to which the synapse circuits 9 are connected (i.e., the arrangement of the synapse circuits 9) are appropriately selected by, for example, using a mathematical model implemented in the arithmetic device 100, simulation, or the like.

[0168] The synaptic circuit 9 calculates the input value x represented by the electrical signal i and weight value w i The product value (w i *x i Specifically, the charge (current) corresponding to the product value is output as a multiplication-accumulation signal to the positive charge output line 8a or the negative charge output line 8b.

[0169] Positive weight value w i + Or negative weight value w i - is set to the synaptic circuit 9. For example, corresponding to a positive weight value w i + The positive weight charge of the product value of is output to the positive charge output line 8a. In addition, for example, the positive weight charge corresponding to the negative weight value w i - The negative weighted charge of the product value is output to the negative charge output line 8b.

[0170] It should be noted that in the synaptic circuit 9, charges having the same sign (for example, positive charges) are output as charges corresponding to the product value regardless of the weight value w i Is it positive or negative. That is, positive and negative charges become charges of the same sign.

[0171] In this way, the synaptic circuits 9 are configured to be i The sign of φ outputs the charge corresponding to the multiplication result to different output lines 8a or 8b.

[0172] In this embodiment, the plurality of synapse circuits 9 function as a plurality of multiplication units, each of which generates an electric charge corresponding to a product value obtained by multiplying the input value by a weight value based on an electrical signal input to each of the plurality of input lines, and outputs the electric charge as a multiplication-accumulation signal to an output line.

[0173] In this embodiment, a single input signal line 7 and a pair of output lines 8 are connected to a single synaptic circuit 9. That is, a single electrical signal is input to the single synaptic circuit 9, and a charge corresponding to a product value calculated based on the input electrical signal is output to the charge output line 8a or 8b. Therefore, the synaptic circuit 9 is a single-input, dual-output circuit connected to the single input signal line 7 and the pair of output lines 8 (positive charge output line 8a and negative charge output line 8b).

[0174] In one analog circuit 3, a plurality of synaptic circuits 9 are arranged along the pair of output lines 8. Each synaptic circuit 9 is connected in parallel to the positive charge output line 8a (negative charge output line 8b). Hereinafter, it is assumed that the synaptic circuit 9 arranged on the most downstream side (the side connected to the neuron circuit 10) is the first synaptic circuit.

[0175] like Figure 5 As shown, a plurality of input signal lines 7 are arranged to intersect with a pair of output lines 8 of each of the plurality of analog circuits 3. Typically, the input signal lines 7 are provided to be orthogonal to each output line 8. That is, the arithmetic device 100 has a crossover configuration in which the input signal lines 7 and the output lines 8 intersect each other. With this crossover configuration, for example, the analog circuits 3 and the like can be integrated at a high density.

[0176] Furthermore, in the arithmetic device 100, the j-th synapse circuit 9 included in each analog circuit 3 is connected in parallel to the j-th input signal line 7. Therefore, similar electric signals are input to the synapse circuits 9 connected to the same input signal line 7. Thus, a configuration can be achieved in which one signal source included in a lower layer is connected to a plurality of analog circuits 3 included in an upper layer.

[0177] It should be noted that in Figure 5 In the example shown, the analog circuit 3 (front neuron) included in the lower layer is schematically shown as a signal source that inputs an electric signal into each input signal line 7. The present technology is not limited thereto, and for example, a crossbar configuration can also be used when the input unit 2 is used as a signal source.

[0178] As described above, in the arithmetic device 100, the plurality of analog circuits 3 are connected in parallel to each of the plurality of input signal lines 7. Therefore, for example, electrical signals can be input in parallel to the respective analog circuits 3 (each synapse circuit 9), enabling high-speed arithmetic processing. As a result, excellent operational performance can be achieved.

[0179] The neuron circuit 10 calculates the multiplication-accumulation result shown in the expression (Formula 1) based on the product value calculated by the synaptic circuit 9. Specifically, the neuron circuit 10 outputs an electric signal representing the multiplication-accumulation result as a multiplication-accumulation result signal based on the charge input via the pair of output lines 8.

[0180] Figure 6 is a schematic diagram showing a configuration example of the neuron circuit 10. The neuron circuit 10 includes an accumulating unit 11 and a signal output unit 12. Figure 6 A dual input, single output neuron circuit 10 is shown connected to a pair of output lines 8 and a single output signal line 13 .

[0181] Accumulation unit 11 accumulates the charge outputted by the plurality of synaptic circuits 9 to the pair of output lines 8. Accumulation unit 11 includes two capacitors 14a and 14b. Capacitor 14a is connected between positive charge output line 8a and ground (GND). In addition, capacitor 14b is connected between negative charge output line 8b and GND.

[0182] Therefore, the charges flowing in from the positive charge output line 8a and the negative charge output line 8b are accumulated in the capacitors 14a and 14b, respectively. It should be noted that the capacitors 14a and 14b are set to have the same capacitance.

[0183] For example, at the time when the input period T of the electric signal ends, the charge accumulated in the capacitor 14a is the sum of the positive weighted charges σ + , each positive weight charge corresponds to a positive weight value w i + The product value of .

[0184] In addition, the charge accumulated in capacitor 14b corresponds to the negative weight value w i - The sum of the negative weighted charges of the product value σ - .

[0185] For example, when positive weighted charges are accumulated in capacitor 14a, the potential of positive charge output line 8a relative to GND increases. Therefore, the potential of positive charge output line 8a depends on the total charge σ + Each charge corresponds to a positive weight value w i + It should be noted that the potential of the positive charge output line 8a corresponds to the voltage held by the capacitor 14a.

[0186] Similarly, when negative charges are accumulated in the capacitor 14b, the potential of the negative charge output line 8b relative to GND increases. Therefore, the potential of the negative charge output line 8b depends on the total charge σ - Each charge corresponds to a negative weight value w i - It should be noted that the potential of the negative charge output line 8b corresponds to the voltage held by the capacitor 14b.

[0187] The signal output unit 12 outputs a multiplication accumulation result signal based on the charge accumulated in the accumulation unit 11. The multiplication accumulation result signal represents the product value (w i + *x i The multiplication accumulation result signal is, for example, a signal representing the total multiplication accumulation result, which is the sum of all positive and negative weight values ​​w i and the input value x i For example, the multiplication accumulation result represented by the expression (Formula 1) can be written as follows.

[0188] [Formula 2]

[0189]

[0190] Here, N+ and N - They are positive weight values ​​w i + The total number and negative weight value w i - As shown in the expression (Formula 2), the total multiplication accumulation result can be calculated as the difference between the multiplication accumulation result of the positive weight charge and the multiplication accumulation result of the negative weight charge, and the multiplication accumulation result of the positive weight charge is the positive weight value w i + The product value (w i + *x i ), the multiplication and accumulation of negative weighted charges results in a negative weight value w i - The product value (|w i - |*x i )

[0191] exist Figure 6 In the example shown, the signal output unit 12 generates a signal representing the total multiplication-accumulation result, for example, as a multiplication-accumulation result signal. Specifically, by appropriately referring to the charges accumulated in the accumulation unit 11 (capacitor 14a and capacitor 14b), a positive multiplication-accumulation result and a negative multiplication-accumulation result are calculated, and the total multiplication-accumulation result is calculated based on the difference between them.

[0192] There is no limitation on the method of referring to the charge accumulated in the accumulation unit 11. As an example, a method of detecting the charge accumulated in one capacitor 14 will be described.

[0193] In use according to Figure 3 In the case of the electric signal of the PWM method shown in A, each charge corresponding to the product value is accumulated in the capacitor 14 within the input period T. That is, the accumulation of each charge corresponding to the product value does not occur before and after the input period T.

[0194] For example, the capacitor 14 is charged at a predetermined charging speed after the end of the input period T. At this time, a comparator or the like is used to detect when the potential of the output line to which the capacitor 14 is connected reaches a predetermined threshold potential.

[0195] For example, as more charge accumulates at the start of charging, the time at which the potential reaches the threshold potential becomes earlier. Therefore, the charge accumulated within the input period T (the multiplication accumulation result) can be expressed based on time. It should be noted that the charging speed can be expressed, for example, by the amount of charge per unit time, and can also be referred to as the charging rate.

[0196] It should be noted that the threshold determination corresponds to increasing the voltage held by the capacitor 14 by charging and detecting the time it takes to reach the threshold voltage.

[0197] In use according to Figure 3 In the case of the electric signal of the TACT method shown in B, charge is accumulated in the capacitor 14 because the on-level is maintained even after the end of the input period T. With this charge accumulation, the time when the potential of the output line connected to the capacitor 14 reaches a predetermined threshold potential is detected by using a comparator or the like.

[0198] For example, the time at which the potential reaches the threshold potential becomes earlier as more charges are accumulated at the end of the input period T. Therefore, the charge accumulated within the input period T (the multiplication accumulation result) can be expressed on a time basis.

[0199] It should be noted that this threshold determination corresponds to detecting the time at which the voltage held by the capacitor 14 reaches the threshold voltage.

[0200] For example, by performing such a threshold determination, the time representing the multiplication accumulation result is detected. Based on the detection result, a multiplication accumulation result signal associated with positive weight charge, a multiplication accumulation result signal associated with negative weight charge, or a total multiplication accumulation result signal is appropriately generated.

[0201] Furthermore, for example, when the input period T ends, each multiplication-accumulation result can be calculated by directly reading the potential of the capacitor 14 .

[0202] In this embodiment, the multiplication-accumulation result signal is a signal including information about time, which corresponds to the sum of product values ​​obtained by multiplying input values ​​by weight values.

[0203] It should be noted that both the voltage depending on the accumulated positive weight charge and the voltage depending on the accumulated negative weight charge can be amplified to generate the multiplication-accumulation result signal. In addition, the multiplication-accumulation result signal can be generated by amplifying the differential voltage between the voltage depending on the accumulated positive weight charge and the voltage depending on the accumulated negative weight charge. For example, a differential amplifier or the like having any configuration can be provided in the neuron circuit 10.

[0204] In this embodiment, the neuron circuit 10 accumulates charges corresponding to product values ​​generated by a plurality of multiplication units and outputs a multiplication-accumulation result signal representing the sum of the product values ​​based on the accumulated charges.

[0205] The accumulation unit 11 included in the neuron circuit 10 functions as an accumulation unit that accumulates electric charge corresponding to a product value output to an output line by each of the plurality of multiplication units.

[0206] Furthermore, the capacitor 14 a functions as a positive charge accumulation unit and the capacitor 14 b functions as a negative charge accumulation unit.

[0207] Furthermore, in this embodiment, a charging unit is configured, and after the input period T, the accumulation unit 11 (capacitor 14 ) to which the charge corresponding to the product value is accumulated is charged.

[0208] It should be noted that, in the case of using an electric signal according to the TACT method, charging according to the present technology also includes accumulating electric charge in the capacitor 14 using a pulse signal that maintains an on-level.

[0209] The signal output unit 12 serves as an output unit that performs threshold determination on the voltage having a predetermined threshold value maintained by the accumulation unit 11 after the charging unit starts charging, thereby outputting a multiplication accumulation result signal including information about time, the multiplication accumulation result signal corresponding to the sum of product values ​​obtained by multiplying the input value by the weight value.

[0210] The signal output unit 12 performs threshold determination on each of the positive charge accumulation unit and the negative charge accumulation unit, thereby outputting a multiplication accumulation result signal. The multiplication accumulation result signal is output from a single output signal line 13.

[0211] Figure 7 is a diagram showing a configuration example of the arithmetic circuit unit 5 provided as one layer in the arithmetic device 200 having a two-input two-output configuration.

[0212] The arithmetic circuit unit 5 includes a plurality of input signal line pairs P7 and a plurality of analog circuits 3 .

[0213] In the predetermined input period T, corresponding to the input value x i The signal pair is input to each of the plurality of input signal line pairs P7. For example, during the input period T, according to the reference Figure 4 A signal pair of the described PWM method or TACT method is input to each input signal line pair P7.

[0214] Each input signal line pair P7 includes a positive input signal line 7a and a negative input signal line 7b. The positive input signal line 7a is a signal line for inputting a positive signal. The negative input signal line 7b is a signal line for inputting a negative signal. In this embodiment, the positive input signal line 7a corresponds to the positive input line, and the negative input signal line 7b corresponds to the negative input line.

[0215] The synaptic circuit 9 calculates the input value x represented by the signal pair i and weight value w i The product value (w i *x iMore specifically, by dividing each corresponding signal value (positive value x i + and negative x i The absolute value of |x i - |) multiplied by the corresponding weight value to calculate the product value (w i *x i ).

[0216] Positive weight value v i + and negative weight value v i - are respectively set to a plurality of synaptic circuits 9. Here, the positive weight value v i + is a positive real number (v i + >0). In addition, negative weight values ​​v i - is a negative real number (v i - <0).

[0217] Therefore, it can be said that the synaptic circuit 9 is a weight pair, with a positive weight value v i + and negative weight value v i - is set to this weight pair.

[0218] The synaptic circuit 9 calculates the signal value of an electric signal included in the signal pair and the positive weight value v i + The product value of .

[0219] In addition, the synaptic circuit 9 calculates the signal value of another electric signal and the negative weight value v i - Specifically, the synapse circuit 9 generates each charge (current) corresponding to each product value.

[0220] To multiply by the positive weight value v i + The electric signal is set to be suitable for each synaptic circuit 9. In addition, it is not set to be multiplied by the positive weight value v i + The electrical signal of the electric signal will be multiplied by the negative weight value v i - .

[0221] In the following, positive weight values ​​v i + The product value of will be referred to as a positive weight product value, and the charge corresponding to the positive weight product value will be referred to as a positive weight charge. i+ The product value of will be referred to as a negative weight product value, and the charge corresponding to the negative weight product value will be referred to as a negative weight charge.

[0222] As described above, the synapse circuit 9 can generate the signal obtained by multiplying the signal value of one signal input to the input signal line pair P7 connected thereto by the positive weight value v. i + The positive weight charge corresponding to the positive weight product value obtained by multiplying the signal value of another signal by the negative weight value v i - The negative weight product value obtained corresponds to the negative weight charge.

[0223] It should be noted that in the synaptic circuit 9, charges with the same sign (eg, positive charge) are output as charges corresponding to each product value regardless of whether the weight value is positive or negative. That is, positive charge and negative charge are charges with the same sign.

[0224] Thus, for example, it can be considered that in a practical circuit, a negative weight value v i - The absolute value of |v i - Multiply by the negative weight value v i - Therefore, since positive weight values ​​and negative weight values ​​can be handled as values ​​having the same sign, the circuit configuration can be simplified.

[0225] In this embodiment, for each of the plurality of synaptic circuits 9, the positive weight value v i + and negative weight value v i - The absolute value of |v i - | are set equal to each other.

[0226] Specifically, a positive weight value v i + and negative weight value v i - The absolute value of |v i - | are all set equal to each other as weight values ​​w i The absolute value of |w i |. That is, each weight value satisfies |w i |=v i + =|v i - |. In the following, in some cases, the weight value w i will be referred to as the pairwise weight w i .

[0227] In the synaptic circuit 9, the pairwise weight value w is a positive value. i + or as a negative pairwise weight w i - is set to the pairwise weight w i .

[0228] Positive and negative paired weight values ​​w i + and w i - This can be set by associating a signal pair (positive and negative signals) with a weight pair (positive weight value).

[0229] In the following, the pairwise weight values ​​w are set i + The synaptic circuit 9 will be referred to as a positive synaptic circuit 9a, and the negative pairwise weight value w is set. i - The synaptic circuit 9 will be referred to as the negative synaptic circuit 9b.

[0230] The positive synaptic circuit 9a converts the signal value (x i + ) multiplied by the positive weight value v i + To generate positive weight charge, and by the signal value of the negative signal (|x i - |) multiplied by the negative weight value |v i - |) to generate negative weighted charges. Therefore, positive weighted charges and negative weighted charges correspond to positive weighted product values ​​(v i + *x i + ) and negative weight product value (|v i - |*|x i - |)'s charge.

[0231] In this case, the difference between the positive weight product value and the negative weight product value Δ + It is expressed as follows.

[0232] Δ + =v i + *x i + -|v i - |*|x i - |=|w i |(xi + +x i - )=w i + *x i

[0233] Therefore, the difference Δ + is the pairwise weight w i + and the input value x i The product value w i + *x i That is, in the positive synaptic circuit 9a, the product value w i + *x i is calculated as the difference between the positive weighted charge and the negative weighted charge.In this embodiment, the positive synapse circuit 9a corresponds to the first multiplication unit.

[0234] The negative synaptic circuit 9b converts the signal value of the negative signal (|x i - |) multiplied by the positive weight value v i + To generate positive weight charge, and by the signal value of the positive signal (x i + ) multiplied by the negative weight value |v i - |) to generate negative weighted charges. Therefore, positive weighted charges and negative weighted charges correspond to positive weighted product values ​​(|v i - |*x i + ) and the negative weight product value (v i + *|x i - |)'s charge.

[0235] In this case, the difference between the positive weight product value and the negative weight product value Δ - It is expressed as follows.

[0236] Δ - =|v i - |*x i + -v i + *|x i - |=-|w i |(x i + +x i - )=wi - *x i

[0237] Therefore, the difference Δ - is the negative pairwise weight w i - and the input value x i The product value w i - *x i That is, in the negative synaptic circuit 9b, the product value w i - *x i is calculated as the difference between the positive weight charge and the negative weight charge.In this embodiment, the negative synapse circuit 9b corresponds to the second multiplication unit.

[0238] It should be noted that positive weighted charges corresponding to positive weighted product values ​​are output to the positive charge output line 8a, and negative weighted charges corresponding to negative weighted product values ​​are output to the negative charge output line 8b.

[0239] In this embodiment, a pair of input signal lines 7 (input signal line pair P7 ) and a pair of output lines 8 are connected to a single synapse circuit 9 .

[0240] That is, the signal pair is input to the monosynaptic circuit 9, and the charge corresponding to the product value calculated based on each electric signal is calculated according to the pair weight value w. i The sign of is output to each output line 8a or 8b. Therefore, the synaptic circuit 9 is a dual-input dual-output circuit.

[0241] Figure 7 As shown, a crossover configuration in which the input signal line pair P7 intersects the output line 8 can also be implemented in the arithmetic device 200.

[0242] Furthermore, since multiple analog circuits 3 are connected in parallel to each of the multiple input signal line pairs P7, for example, a signal pair can be input in parallel to each analog circuit 3 (each synapse circuit 9), and the arithmetic processing speed can be increased. As a result, excellent arithmetic operation performance can be achieved.

[0243] Figure 8 is a schematic diagram showing a configuration example of the neuron circuit 10. In the arithmetic device 200, a two-input two-output neuron circuit 10 connected to a pair of output lines 8 and a pair of output signal lines 13 (positive output signal line 13a and negative output signal line 13b) is configured.

[0244] The positive weighted charge output from the positive charge output line 8a as a positive multiplication accumulation signal is accumulated in the capacitor 14a. In addition, the negative charge output from the negative charge output line 8b as a negative multiplication accumulation signal is accumulated in the capacitor 14b. In this way, the accumulation unit 11 can accumulate the positive weighted charge and the negative weighted charge generated by each of the plurality of synapse circuits 9.

[0245] For example, at the time when the input period T of the electric signal ends, the charge accumulated in the capacitor 14a is the sum of positive weight charges, each of which corresponds to the positive weight value v set to each synaptic circuit 9. i + The positive weight product value of .

[0246] Furthermore, the charges accumulated in the capacitor 14b are each corresponding to the negative weight value v set to each synaptic circuit 9. i - The sum of the negative weighted charges of the negative weighted product values.

[0247] The signal output unit 12 outputs a signal representing a product value (w i *x i ) is the multiplication and accumulation result signal of the sum.

[0248] In this embodiment, a positive multiplication accumulation result signal representing the sum of positive weighted product values ​​and a negative multiplication accumulation result signal representing the sum of negative weighted product values ​​are output as the sum of product values ​​(w i *x i )’s multiplication and accumulation result signal.

[0249] Here, it is assumed that the total number of synaptic circuits 9 provided in the analog circuit 3 is denoted by N. Furthermore, it is assumed that in the N synaptic circuits 9, a positive pairwise weight value w is set for each. i + The total number of synaptic circuits 9 (positive weight pairs) is denoted by N + Represents, and each sets a negative pairwise weight value w i - The total number of synaptic circuits 9 (negative weight pairs) is denoted by N - In this way, N=N + +N - Established.

[0250] In this case, as in the arithmetic device 100 having the one-input-one-output configuration, the multiplication-accumulation result represented by the expression (Formula 1) can be written according to the above-described expression (Formula 2).

[0251] Since a signal pair is used in the dual-input dual-output arithmetic device 200, the input value x i Represented as a positive value xi + and negative x i - The absolute value of |x i - |The difference -(x i =x i + -|x i - |). Therefore, the expression (Formula 2) can be converted as follows.

[0252] [Formula 3]

[0253]

[0254] As shown in the expression (Formula 3), the multiplication accumulation result is a value obtained by subtracting the second term from the first term. Here, the first term and the second term are both terms enclosed in curly braces {}.

[0255] The first term is calculated by adding all positive weight product values ​​(w i + *x i + ) and the positive weight product value (|w i - |*|x i - |) is added, where a positive pairwise weight value w is set for each positive weight product value i + , a negative pairwise weight value w is set for each negative weight product value i - .

[0256] That is, the first term is the sum σ of the positive weight product values ​​calculated in all synaptic circuits 9 + The sum of the positive weighted product values ​​is represented by the sum of the positive weighted charges accumulated in capacitor 14a.

[0257] The second term is obtained by adding all negative weight product values ​​(w i + *|x i - |) and the negative weight product value (|w i - |*x i + ) is added, wherein a positive pairwise weight value w is set for each positive weight product value i + , a negative pairwise weight value w is set for each negative weight product valuei - .

[0258] That is, the second term is the sum σ of the negative weight product values ​​calculated in all synaptic circuits 9 - The sum of the negative weight product values ​​is represented by the sum of the negative weight charges accumulated in capacitor 14b.

[0259] In this way, the total multiplication-accumulation result can be calculated as the sum of the positive weighted product values ​​σ + The sum of the product values ​​of negative weights σ - The difference between.

[0260] It should be noted that the first term in the expression (Formula 3) (the sum of the positive weight product values ​​σ + ) does not correspond to N + Positive pairwise weights w i + In addition, the second term in the expression (Formula 3) (the sum of the negative weight product values ​​σ - ) does not correspond to N - negative pairwise weights w i - The multiplication and accumulation result of .

[0261] exist Figure 8 In the example shown, the signal output unit 12 refers to the charge accumulated in the capacitor 14a to calculate a positive multiplication accumulation result signal representing the sum of the positive weighted product values, and refers to the charge accumulated in the capacitor 14b to calculate a negative multiplication accumulation result signal representing the sum of the negative weighted product values.

[0262] At the time when the input period T ends, the charge corresponding to the sum of the positive weight product values ​​(the sum of the negative weight product values) is accumulated in the capacitor 14a (14b). This is true regardless of whether the TACT method or the PWM method is used.

[0263] After the end of the input period T, the capacitor 14a and the capacitor 14b are both charged. The signal output unit 12 performs threshold determination on each of the capacitors 14a and 14b, generates each of a positive multiplication accumulation result signal and a negative multiplication accumulation result signal, and outputs the positive multiplication accumulation result signal and the negative multiplication accumulation result signal to the output signal line pair 13 (positive output signal line 13a and negative output signal line 13b).

[0264] In this manner, the analog circuit 3 generates a pair of electrical signals (signal pair) including a positive multiplication-accumulation result signal and a negative multiplication-accumulation result signal. The analog circuit 3 is a circuit that outputs the total multiplication-accumulation result as a signal pair.

[0265] Figure 9 and Figure 10is a diagram showing a configuration example of the arithmetic circuit unit 5 in the arithmetic device 100 having a one-input-one-output configuration.

[0266] Figure 9 and Figure 10 The illustrated arithmetic circuit unit 5 includes a plurality of input signal lines 7 and a plurality of analog circuits 3 connected in parallel with the plurality of input signal lines 7 .

[0267] The analog circuit 3 is provided so as to extend in a direction perpendicular to the plurality of input signal lines 7. Figure 9 and Figure 10 In the example shown, a crossbar configuration is used.

[0268] By adopting this configuration, it is possible to input electric signals in parallel to the respective analog circuits 3 and realize high-speed arithmetic processing. As a result, it is possible to exhibit excellent operational performance.

[0269] exist Figure 9 In the example shown, an analog circuit 3 according to the PWM method is provided.

[0270] The analog circuit 3 includes a pair of output lines 8 (a positive charge output line 8 a and a negative charge output line 8 b ), a plurality of synapse circuits (a plurality of multiplication units) 9 , a neuron circuit 10 , and a charging unit 15 .

[0271] All have corresponding input values ​​x i A pulse signal (PWM signal) with a pulse width of 1000 MHz is input as an input signal to the plurality of input signal lines 7. Figure 9 In the illustrated example, seven input signal lines 7 are shown, although there is no limitation on the number of input signal lines 7. An input signal is input within an input period T having a predetermined duration.

[0272] The positive charge output line 8a outputs the positive charge corresponding to the input value x i Multiply by the positive weight w i + The product value obtained (w i + *x i ) of the positive weight charge. The negative charge output line 8b outputs the positive weight charge corresponding to the input value x i Multiply by the negative charge value w i - The product value obtained (|w i - |*x i In this embodiment, the pair of output lines 8 corresponds to one or more output lines.

[0273] A plurality of synapse circuits 9 are provided so as to be respectively associated with the plurality of input signal lines 7. In this embodiment, one synapse circuit 9 is provided in one input signal line 7.

[0274] Each of the plurality of synapse circuits 9 includes a resistor 17 connected between a corresponding input signal line 7 of the plurality of input signal lines 7 and any one of the positive charge output line 8 a or the negative charge output line 8 b. The resistor 17 may have nonlinear characteristics and may have a function of preventing current from flowing back.

[0275] Corresponding to the product value (w i + *x i )(or(|w i - |*x i )) is output to the output line 8a (or 7b) to which the resistor 17 is connected.

[0276] For example, in order to convert the input value x into i Multiply by the positive weight w i + , the resistor 17 (17a) is connected between the input signal line 7 and the positive charge output line 8a, and causes the positive charge output line 8a to output positive weighted charges.

[0277] This synapse circuit 9 is a synapse circuit 9a configured as a positive weight multiplication unit that generates positive weight charge. In other words, the synapse circuit 9a is a multiplication unit that sets a positive weight.

[0278] In order to multiply the input value xi by the negative weight value w in each synaptic circuit 9 i - , the resistor 17 (17b) is connected between the input signal line 7 and the negative charge output line 8b, and causes the negative charge output line 8b to output negative charges.

[0279] This synapse circuit 9 is a synapse circuit 9b configured as a negative weight multiplication unit that generates negative weighted charges. In other words, the synapse circuit 9b is a multiplication unit with a negative weight.

[0280] has a value corresponding to the weight w to be set i A resistor having a resistance value of φ is used as the resistor 17. That is, the resistor 17 is used to define the weight value w in the arithmetic device 100 that performs the multiplication and accumulation operation at the analog circuit 3. i components.

[0281] For example, a fixed resistor element, a variable resistor element, a MOS transistor operating in a subthreshold region, or the like is used as the resistor 17. For example, power consumption can be reduced by using a MOS transistor operating in a subthreshold region as the resistor 17. Of course, another arbitrary resistor can be used.

[0282] like Figure 6 As shown, the neuron circuit 10 includes an accumulation unit 11 and a signal output unit 12 .

[0283] The accumulation unit 11 includes a capacitor 14 a that accumulates the positive weight charge generated by the synapse circuit 9 a and a capacitor 14 b that accumulates the negative weight charge generated by the synapse circuit 9 b .

[0284] The charging unit 15 charges the accumulating unit 11, and the accumulating unit 11 accumulates the value corresponding to the product value (w i *x i In this embodiment, the charging unit 15 includes a signal source (not shown) for charging, a charging line 19 and two resistors 20.

[0285] The charging line 19 is arranged in parallel with the input signal line 7 .

[0286] One resistor 20a of the two resistors 20 is connected between the charging line 19 and the positive charge output line 8a, and the other resistor 20b is connected between the charging line 19 and the negative charge output line 8b.

[0287] Therefore, the charging line 19 is connected to the capacitor 14a of the accumulating unit 11 via the resistor 20a. Furthermore, the charging line 19 is connected to the capacitor 14a via the resistor 20b.

[0288] Resistors having the same resistance value are used as resistors 20a and 20b. Although the same resistors are generally used, different types of resistors having the same resistance value may be used. The specific configuration of resistors 20a and 20b is not limited, and various types of resistors may be used as resistor 17. In addition, resistors of the same type as resistor 17 may be used as resistors 20a and 20b, or resistors of a different type from resistor 17 may be used as resistors 20a and 20b.

[0289] Charging is performed after the input period T ends. In the present embodiment, after the input period T ends, the charging signal CH is input through the charging line 19. That is, the same charging signal CH is supplied from the charging line 19 to the capacitors 14a and 14b.

[0290] Therefore, charges based on the high-level value of the charging signal and the resistance values ​​of the resistors 20 a and 20 b are accumulated in the capacitors 14 a and 14 b .

[0291] It should be noted that, in this embodiment, the charging unit 15 performs charging in the output period T following the input period T. Therefore, the output period T is equivalent to a charging cycle.

[0292] Typically, the duration of the input period T and the duration of the output period T are set equal to each other.

[0293] Since the resistance values ​​of the resistors 20a and 20b are equal to each other, the capacitors 14a and 14b are charged at the same charging speed.

[0294] The charging of the charging unit 15 increases the potential of the positive charge output line 8a (the voltage held by the capacitor 14a) V + and the potential of the negative charge output line 8b (the voltage held by the capacitor 14b) V - Each of the .

[0295] After the charging unit 15 starts charging, the signal output unit 12 of the neuron circuit 10 performs threshold determination on the voltage held by the accumulating unit 11 at a predetermined threshold, thereby outputting a value representing the sum of the product values ​​(w i *x i )’s multiplication and accumulation result signal.

[0296] In this embodiment, the multiplication-accumulation result signal is output by performing threshold determination on each of the capacitors 14 a and 14 b having a common threshold θ.

[0297] For example, a PMW signal, which is a pulse signal whose pulse width has been modulated, is output as the multiplication-accumulation result signal.

[0298] In this way, in this embodiment, based on the multiplication accumulation result of the positive weight charge accumulated in capacitor 14a and the multiplication accumulation result of the negative weight charge accumulated in capacitor 14b, a multiplication accumulation result signal representing the total multiplication accumulation result including positive and negative values ​​is calculated.

[0299] exist Figure 10 In the example shown, an analog circuit 3 according to the TACT method is provided. Figure 10 In the analog circuit 3 shown, in the case of the input value x i In this embodiment, a continuous pulse signal that rises to a time corresponding to the input value and maintains the on-level is input.

[0300] Since the ON level of the electric signal remains unchanged even after the input period T ends, electric charge is accumulated in the capacitors 14a and 14b of the neuron circuit 10. That is, the capacitor 14a and the capacitor 14b are charged in the output period T.

[0301] As a result, the potential of the positive charge output line 8a (the voltage held by the capacitor 14a) V + and the potential of the negative charge output line 8b (the voltage held by the capacitor 14b) V - Each of them increases.

[0302] The signal output unit 12 of the neuron circuit 10 performs threshold determination on each of the capacitors 14a and 14b using a common threshold value, and as a result, outputs a multiplication-accumulation result signal.

[0303] That is, based on the multiplication accumulation result of the positive weight charge based on the positive weight charge accumulated in capacitor 14a and the multiplication accumulation result of the negative weight charge based on the negative weight charge accumulated in capacitor 14b, a multiplication accumulation result signal representing the total multiplication accumulation result including positive values ​​and negative values ​​is calculated.

[0304] For example, a PMW signal, which is a pulse signal whose pulse width has been modulated, is output as the multiplication-accumulation result signal.

[0305] Figure 11 and Figure 12 is a diagram showing a configuration example of the arithmetic circuit unit 5 in the arithmetic device 200 having a two-input two-output configuration.

[0306] Figure 11 and Figure 12 The illustrated arithmetic circuit unit 5 includes a plurality of input signal line pairs P7 and a plurality of analog circuits 3 connected in parallel to the plurality of input signal line pairs P7.

[0307] exist Figure 11 In the example shown, an analog circuit 3 according to the PWM method is provided.

[0308] The analog circuit 3 includes a pair of output lines 8 (a positive charge output line 8 a and a negative charge output line 8 b ), a plurality of synapse circuits 9 , a neuron circuit 10 , and a charging unit 15 .

[0309] The signal pairs are input to a plurality of input signal line pairs P7. Those signal pairs include input values ​​x i A negative signal pair and input value x i A positive signal pair.

[0310] That is, positive and negative input values ​​x i is transmitted by each signal pair. Figure 11 In the example shown, a signal pair according to the PWM method is used.

[0311] The positive charge output line 8a is connected to each synaptic circuit 9 and outputs the positive charge generated by multiplying the signal value of the positive signal or negative signal by the positive weight value v i+ The positive weighted product value obtained corresponds to the positive weighted charge.

[0312] Similarly, the negative charge output line 8b is connected to each synaptic circuit 9 and outputs the same charge as that obtained by multiplying the signal value of the positive signal or the negative signal by the negative weight value v. i - The absolute value of |v i - |The negative weighted charge corresponding to the negative weighted product value obtained.

[0313] The plurality of synapse circuits 9 are provided corresponding to the plurality of input signal line pairs P7 , respectively.

[0314] Each synaptic circuit 9 is equipped with two resistors 17. Both of the two resistors 17 serve as weights by which the weight value is multiplied. Therefore, the synaptic circuit 9 serves as a weight pair that multiplies the signal pair by the weight value.

[0315] The plurality of synapse circuits 9 include at least one of a positive synapse circuit 9 a and a negative synapse circuit 9 b .

[0316] The positive synaptic circuit 9a is set with a positive pairwise weight value w i + The synaptic circuit 9 is used as a positive weight pair. Figure 16 As shown in FIG. 1A , the positive synaptic circuit 9 a includes a first resistor 17 a and a second resistor 17 b .

[0317] The first resistor 17a is connected between the positive input signal line 7a and the positive charge output line 8a, defining a positive weight value v i + , and outputs the positive weighted charge to the positive charge output line 8a.

[0318] The second resistor 17b is connected between the negative input signal line 7b and the negative charge output line 8b, defining the negative charge value v i - , and outputs the negative charge to the negative charge output line 8b.

[0319] Therefore, in order to convert the signal value x of the signal pair i Multiply by the pairwise weight w i + , the positive input signal line 7a and the positive charge output line 8a are connected to each other via a resistor, and the negative input signal line 7b and the negative charge output line 8b are connected to each other via a resistor.

[0320] It can also be said that, with respect to the positive synaptic circuit 9a (positive weight pair), a positive signal (positive input) corresponds to a positive weight, and a negative signal (negative input) corresponds to a negative weight.

[0321] Negative synaptic circuit 9b is a negative pairwise weight value wi - is set to the synaptic circuit 9 and used as a negative weight pair. Figure 11 As shown, the negative synaptic circuit 9b includes a third resistor 17c and a fourth resistor 17d.

[0322] The third resistor 17c is connected between the negative input signal line 7b and the positive charge output line 8a, defining a positive weight value v i + , and outputs the positive weighted charge to the positive charge output line 8a.

[0323] The fourth resistor 17d is connected between the positive input signal line 7a and the negative charge output line 8b, defining the negative charge value v i - , and outputs the negative charge to the negative charge output line 8b.

[0324] Therefore, in order to convert the signal value x of the signal pair i Multiply by the negative weight value w i - , the negative input signal line 7b and the positive charge output line 8a are connected to each other via a resistor, and the positive input signal line 7a and the negative charge output line 8b are connected to each other via a resistor.

[0325] It can also be said that, with respect to the negative synaptic circuit 9b (negative weight pair), a positive signal (positive input) corresponds to a negative weight, and a negative signal (negative input) corresponds to a positive weight.

[0326] like Figure 11 As shown, the positive weight of the positive synaptic circuit 9a (first resistor 17a) and the positive weight of the negative synaptic circuit 9b (third resistor 17c) are connected in parallel to the capacitor 14a. Those positive weights of the respective synaptic circuits 9 constitute a positive weight column.

[0327] Furthermore, the negative weight of the positive synapse circuit 9a (second resistor 17b) and the negative weight of the negative synapse circuit 9b (fourth resistor 17d) are connected in parallel to the capacitor 14b. These negative weights of the respective synapse circuits 9 constitute a negative weight column.

[0328] After the input period T ends, the charging signal is input via the charging line 19. Therefore, the potential of the positive charge output line 8a (the voltage held by the capacitor 14a) V + and the potential of the negative charge output line 8b (the voltage held by the capacitor 14b) V - Each of them increases.

[0329] The signal output unit 12 of the neuron circuit 10 performs threshold determination on each of the capacitors 14a and 14b using a common threshold value, thereby generating each of a positive multiplication accumulation result signal and a negative multiplication accumulation result signal, and outputs the positive multiplication accumulation result signal and the negative multiplication accumulation result signal as a pair of electrical signals (signal pair) to a pair of output signal lines 13 (a positive output signal line 13a and a negative output signal line 13b).

[0330] exist Figure 12 In the example shown, an analog circuit 3 according to the TACT method is provided.

[0331] exist Figure 12 In the analog circuit 3 shown, a signal pair according to the TACT method is input to a plurality of input signal line pairs P7. In this embodiment, continuous pulse signals are input, each pulse signal rising to a time corresponding to the input value and maintaining the conduction level.

[0332] Electric charge is accumulated in the capacitor 14 a and the capacitor 14 b of the neuron circuit 10 because the on-level of the electric signal is maintained also after the end of the input period T. That is, the capacitor 14 a and the capacitor 14 b are charged in the output period T.

[0333] As a result, the potential of the positive charge output line 8a (the voltage held by the capacitor 14a) V + and the potential of the negative charge output line 8b (the voltage held by the capacitor 14b) V - Each of them increases.

[0334] The signal output unit 12 of the neuron circuit 10 performs threshold determination on each of the capacitors 14a and 14b using a common threshold value, thereby generating each of a positive multiplication accumulation result signal and a negative multiplication accumulation result signal, and outputs the positive multiplication accumulation result signal and the negative multiplication accumulation result signal as a pair of electrical signals (signal pair) to a pair of output signal lines 13 (a positive output signal line 13a and a negative output signal line 13b).

[0335] exist Figures 9 to 12 In the arithmetic circuit unit 5 shown, charging is performed in a common charging mode for multiple analog circuits 3. Furthermore, threshold determination is performed using a shared threshold value in the neuron circuit 10. That is, charging is performed in the same charging mode in each analog circuit 3, and threshold determination is performed using the same threshold value.

[0336] Therefore, the efficiency and speed of arithmetic operations can be improved.Of course, multiplication and accumulation operations can also be performed when different threshold values ​​are used.

[0337] It should be noted that in the arithmetic device 200 having a dual-input dual-output configuration, the positive multiplication-accumulation result signal and the negative multiplication-accumulation result signal can be used as inputs (signal pairs) of the next layer as they are. Therefore, a differential circuit for generating a positive or negative total multiplication-accumulation result signal based on the positive and negative multiplication-accumulation result signals becomes unnecessary.

[0338] For example, it is possible to realize a configuration in which it is sufficient to arrange only one differential circuit to generate the final multiplication-accumulation result signal. As a result, the circuit configuration can be simplified, and the power consumption of the arithmetic device 200 can be greatly reduced.

[0339] For example, there are cases where the MLP method is used as an algorithm for deep learning. For example, the MLP method can provide a fully connected configuration and does not require special processing between the previous and subsequent stages of multiplication and accumulation operations.

[0340] Therefore, while the process of calculating a positive or negative total multiplication accumulation result signal (the difference between positive and negative multiplication accumulation results) after the multiplication accumulation operation can be reduced, the circuits used for the difference calculation and the like can be reduced.

[0341] In this case, the MLP network can be implemented using only a crossbar wiring structure and a comparator circuit using resistors (resistance elements) as weights without installing unnecessary circuits. Therefore, high-speed arithmetic processing can be performed with an extremely simplified circuit configuration.

[0342] Of course, the MLP method can also be implemented by using an arithmetic device with a one-input one-output configuration.

[0343] [Inference Device]

[0344] Figure 13 3 is a schematic diagram showing a configuration example of an inference device including an arithmetic device according to the present technology. The inference device 300 is an inference device using a neural network and can implement inference based on a convolutional neural network (CNN).

[0345] Figure 14 and Figure 15 are tables and diagrams for describing the convolution operations performed by the inference device 300 .

[0346] Figure 15 Each letter shown in represents the following parameters.

[0347] H: input image size

[0348] E: output image size

[0349] R: Filter size = 2 (fixed)

[0350] M: Number of filters = 256 (fixed)

[0351] C: Number of channels = 256 (fixed)

[0352] like Figure 14 As shown in FIG, the CNN constructed in this embodiment includes eight convolutional layers, two pooling layers and one fully connected layer.

[0353] In each convolutional layer, use Figure 15 The R×R×C=2×2×256 filters shown in A perform convolution operations with a stride=1. Since the number of filters M is 256, the convolution operations are performed using 256 filters.

[0354] For example, in the first convolutional layer, Figure 15 As shown in B, for H×H×C=32×32×256 input images, a convolution operation is performed with a stride of 1. The convolution operation performed by one filter generates E×E×C=31×31×1 output images. For example, the convolution operation performed by the first filter generates Figure 15 The previous output image of C.

[0355] The convolution operation is performed by 256 filters to generate E×E×M=31×31×256 output images. For example, the convolution operation performed by the Mth filter generates the Mth output image from the previous one. Of course, the present technology is not limited to this.

[0356] like Figure 14 As shown, in each of the 8 convolutional layers, a convolution operation is performed with stride = 1 through 256 filters (R×R×C=2×2×256 filters).

[0357] Furthermore, max pooling is performed in two pooling layers.

[0358] Finally, in the fully connected layer, an output result of ten classification results is obtained from the E×E×M=4×4×256 output images (4096 pixels). For example, an analogy result indicating which of the ten types of animal information included in the input image is obtained. Of course, the present technology is not limited to this.

[0359] It should be noted that the processing in the two pooling layers and the fully connected layer is done by Figure 13 The arithmetic unit not shown in the figure performs.

[0360] like Figure 13As shown, the inference device 300 includes eight arithmetic circuit units 30 (30a to 30h), a static random access memory (SRAM) 31, an SRAM controller (SRAMC) 32, a bus 33, and a D / A converter 34. In addition, the inference device 300 includes a multiplexer (MUX) 35, an A / D converter 36, a timer 38, a control unit 39, and a weight value memory 40.

[0361] The control unit 39 is capable of comprehensively controlling the overall operation of the inference device 300. The configuration of the control unit 39 is not limited, and any hardware and software can be used. For example, a programmable logic device such as a field programmable gate array (FPGA) and other devices such as an application-specific integrated circuit (ASIC) can be used.

[0362] The timer 38 provides time (timing) information to the control unit 39. The timer 38 also provides a time that is a reference to the clock in the D / A converter (DTC: Digital to Time Converter) 34 and the clock in the A / D converter (TDC: Time to Digital Converter) 36.

[0363] The specific configuration of the timer 38 is not limited.

[0364] The weight value memory 40 stores information on the weight values ​​set to the respective synapse circuits 9 of the eight arithmetic circuit units 30 a to 30 h. For example, the weight values ​​are calculated by a learning process performed by a computer or the like (not shown) and stored in the memory 40. As needed, the control unit 39 reads the information on the weight values ​​from the memory 40 and writes the information to the eight arithmetic circuit units 30 a to 30 h.

[0365] Although Figure 13 Although not shown in FIG. 1 , the eight arithmetic circuit units 30 a to 30 h are provided with a write circuit. The write circuit is generally electrically connected to each synapse circuit 9 via an input signal line 7 and a charge output line 8 .

[0366] For example, in the case where a configuration using a volatile memory such as an SRAM is used as a configuration for setting a weight value (resistance value), it is necessary to perform writing after each power-on.

[0367] In addition, when a configuration using a nonvolatile memory is used as a configuration for setting weight values ​​(resistance values), for example, a write process is performed when the weight values ​​are updated. In addition, for example, after performing a predetermined number of inferences, the weight values ​​can also be appropriately updated.

[0368] There is no limitation on the specific configuration of the memory 41. In addition, there is no limitation on the specific configuration of the writing circuit.

[0369] As the eight arithmetic circuit units 30a to 30h, the following are used: Figure 9 and Figure 10 The arithmetic circuit unit 5 having an input-output configuration as shown or Figure 11 and Figure 12 The arithmetic circuit unit 5 shown has a two-input two-output configuration. The present technology is not limited thereto, and arithmetic circuit units having other configurations may be used.

[0370] In the following, the following examples will be used to illustrate the Figure 9 and Figure 10 Description will be given of a case where the arithmetic circuit unit 5 of the illustrated one-input-one-output configuration is used as the eight arithmetic circuit units 30a to 30h.

[0371] The eight arithmetic circuit units 30a to 30h perform convolution operations in eight convolution layers. Figure 15 As shown, a convolution operation with a stride of 1 and R×R×C=2×2×256 filters corresponds to a multiplication and accumulation operation of 1024 pieces of input data.

[0372] Furthermore, the convolution operation through one filter corresponds to the output of the multiplication-accumulation result signal through one analog circuit 3. Therefore, one analog circuit 3 is arranged for one filter.

[0373] In this embodiment, the convolution operation is performed by 256 filters. Therefore, in each arithmetic circuit unit 30, 256 analog circuits 3 including the positive charge output line 8a and the negative charge output line 8b are arranged in parallel.

[0374] The total number of charge output lines 8 arranged to intersect the plurality of input signal lines 7 is 512 (256×2).

[0375] In each analog circuit 3, the neuron circuit 10 generates a convolution result as a multiplication-accumulation result signal and outputs the multiplication-accumulation result signal from the output signal line 13. Therefore, 256 multiplication-accumulation result signals are output as convolution results from each arithmetic circuit unit 30 through 256 filters. The 256 multiplication-accumulation result signals correspond to Figure 15 C shows the pixel data at the same position in the 256 output images.

[0376] SRAM 31 stores the 32×32×256 input images and output images generated in each convolution layer. Furthermore, SRAM 31 stores images generated by the pooling layer and simulation results obtained in the fully connected layer. The specific configuration of SRAM 31 is not limited. Alternatively, another storage device may be used.

[0377] For example, a method of using two areas in the SRAM for a double buffer can be conceived. For example, in the first area starting at address 00000, the input image, L2 output image (output image in layer 2), L4 output image, L6 output image, and L8 output image are stored.

[0378] In the second area starting with address 10000, an L1 output image, an L3 output image, an L5 output image, and an L7 output image are stored.

[0379] An L1 convolution operation is performed on the input image read from the first region. As a result, the output image (L1 output image) is stored in the second region. The L2 output image, which is the result of the L2 convolution operation on the L1 output image read from the second region, is stored in the first region. In this way, the first region and the second region can be used alternately. Of course, another storage method can be used.

[0380] In accordance with an instruction from the control unit 39, the SRAMC 32 reads pixel data of the input image and the output image in each layer from the SRAM 31, and outputs the pixel data of the input image and the output image in each layer to the D / A converter 34 via the bus 33. In addition, the SRAMC 32 receives pixel data of the convolution result and the like and a signal of the inference result from the A / D converter 36, and writes the pixel data of the convolution result and the like and the signal of the inference result to the SRAM 31.

[0381] The bus 33 is composed of, for example, an address bus, a data bus, a control bus, etc. (none of which are shown). The pixel data after one convolution operation of 256 filters, i.e., pixel data of 2×2×256=1024 pixels, is output to the D / A converter 34 via the bus 33.

[0382] Furthermore, pixel data of 256 pixels output from the A / D converter 36 via the bus 33 is output to the SRAM C32 .

[0383] The D / A converter 34 is composed of 1024 D / A blocks corresponding to pixel data of 1024 pixels. The 1024 D / A blocks have the same configuration. Using pixel data (pixel value) as input value x i , each D / A block generates a value corresponding to the input value x i The analog signal is used as the input signal of each arithmetic circuit unit 30.

[0384] The specific configuration of the D / A converter 34 (D / A block) is not limited and can be arbitrarily designed.

[0385] In this embodiment, the D / A converter 34 includes 1024 signal output lines and outputs 1024 input signals (analog electric signals) corresponding to pixel data of 1024 pixels. For example, each of the 1024 D / A blocks is provided with a signal output line.

[0386] As will be described in detail later, in this embodiment, a common wiring unit WC (see FIG. 1 ) is configured that electrically connects 1024 signal output lines of the D / A converter 34 to 1024 input signal lines 7 included in each of the eight arithmetic circuit units 30 a to 30 h. Figure 19 wait).

[0387] The common wiring unit WC includes a switching mechanism that switches electrical signals output from the 1024 signal output lines of the D / A converter 34 to each of the eight arithmetic circuit units 30a to 30h. This switching mechanism enables input switching (switching) to be performed so as to input pixel data of an input image into the first arithmetic circuit unit 30a and input an L3 output image into the fourth arithmetic circuit unit 30d.

[0388] For example, a buffer capable of switching the output using an enable signal (true / false) with respect to 1024 input signal lines 7 included in each of the eight arithmetic circuit units 30a to 30h is installed. Then, by controlling the buffer using the enable signal, the arithmetic circuit unit 30 can be switched, and the output from the D / A converter 34 is input to the arithmetic circuit unit.

[0389] The specific configuration of the switch mechanism is not limited and can be arbitrarily designed.

[0390] It should be noted that the present technology is not limited to the case where a switching mechanism is provided. Without installing a switching mechanism, the output from the D / A converter 34 can be input to all the arithmetic circuit units 30. In this case, it is sufficient to switch the signal to be input to the A / D converter 36 on the output side (in this example, through the multiplexer 35).

[0391] The A / D converter 36 is composed of 256 A / D blocks corresponding to pixel data of 256 pixels. The 256 A / D blocks have the same configuration.

[0392] Each multiplication accumulation result signal outputted from the 256 output signal lines 13 included in each of the eight arithmetic circuit units 30 is converted into a digital signal by each A / D block. That is, a digital signal having a value corresponding to the time information included in the multiplication accumulation result signal is generated and outputted.

[0393] The specific configuration of the A / D converter 36 (A / D block) is not limited and can be arbitrarily designed.

[0394] In this embodiment, the A / D converter 36 includes 256 signal input lines, into which 256 multiplication-accumulation result signals (analog electrical signals) corresponding to the pixel data of 256 pixels are input. For example, each of the 256 A / D blocks is provided with a signal input line.

[0395] In this embodiment, a wiring unit (not shown) is configured which electrically connects 256 output signal lines 13 included in each of the eight arithmetic circuit units 30 a to 30 h to 256 signal input lines of the A / D converter 36 .

[0396] The wiring unit includes a switching mechanism that appropriately switches the multiplication-accumulation result signals output from the 256 output signal lines 13 included in each of the eight arithmetic circuit units 30 a to 30 h and inputs the multiplication-accumulation result signals to 256 signal input lines of the A / D converter 36 .

[0397] For example, Figure 13 A multiplexer (MUX) 35 is shown as a switching mechanism for the wiring unit.

[0398] The multiplexer 35 is provided between the eight arithmetic circuit units 30 a to 30 h and the A / D converter 36 .

[0399] The multiplexer 35 is connected to 256 output signal lines 13 included in each of the eight arithmetic circuit units 30a to 30h. Therefore, 256×8=2048 output signal lines 13 are connected. In addition, the multiplexer 35 is connected to 256 signal input lines of the A / D converter 36.

[0400] The multiplexer 35 can appropriately switch the output of each of the eight arithmetic circuit units 30a to 30b and input the output to the A / D converter 36. Therefore, the output image in each layer can be appropriately acquired.

[0401] The specific configuration of the multiplexer 35 is not limited and can be arbitrarily designed. In addition, the specific configuration of the switch mechanism is not limited and can be arbitrarily designed.

[0402] It should be noted that an A / D converter may be provided corresponding to each of the eight arithmetic circuit units 30a to 30h. That is, eight analog-to-digital converters may be arranged for the respective arithmetic circuit units 30. In this case, a common output wiring unit and a switching mechanism are unnecessary.

[0403] In the case where the arithmetic circuit unit 5 having a dual-input dual-output configuration is used as the eight arithmetic circuit units 30 a to 30 h, the total number of the plurality of input signal lines 7 is 1024×2=2048. For example, 2048 D / A blocks are provided, and input signals (analog electric signals) corresponding to pixel data are input to the 2048 input signal lines 7.

[0404] In addition, a pair of electrical signals (signal pair) is output from each arithmetic circuit unit 30 through a pair of output signal lines 13 (positive output signal line 13a and negative output signal line 13b). Therefore, 512 electrical signals (analog signals) are output from 256×2=512 output signal lines 13.

[0405] For example, 512 electrical signals (analog signals) are converted into digital data by 512 A / D blocks.

[0406] The inference device 300 may be provided with an activation function, for example, a ReLU circuit, an amplification circuit, etc. Furthermore, a differential circuit may be provided while using the arithmetic circuit unit 5 having a two-input two-output configuration or the like.

[0407] Based on the difference between the positive multiplication accumulation result signal and the negative multiplication accumulation result signal, the difference circuit outputs a multiplication accumulation result signal (an analog signal including time information) representing the total multiplication accumulation result signal. Therefore, digital data of the output image can be generated in each layer through 256 A / D blocks.

[0408] Alternatively, any circuit configuration or the like may be employed.

[0409] [Operation examples during inference]

[0410] An example of operation during inference by the inference device 300 will be described.

[0411] It should be noted that it is assumed that buffers with enables have been installed for the 1024 input signal lines 7 included in each of the eight arithmetic circuit units 30 a to 30 h.

[0412] For example, by buffering an input signal once when input to the arithmetic circuit unit 30 , the arithmetic accuracy of each arithmetic circuit unit 30 can be improved, and the arithmetic accuracy can be improved.

[0413] First, the enable of the buffer connected to the first arithmetic circuit unit 30 a is set to “true”, and the enables of the other arithmetic circuit units 30 b to 30 h are set to “false”.

[0414] Pixel data having 2×2×256=1024 pixels corresponding to the upper left corner in the 32×32×256 input images is read from the SRAM 31 and transferred to the D / A converter 34 .

[0415] The control unit 39 instructs the D / A converter 34 to start operating, and an input signal corresponding to pixel data is input to the arithmetic circuit unit 30 a .

[0416] By the arithmetic circuit unit 30 a , 256 multiplication-accumulation result signals are output via the multiplexer 35 and input to the A / D converter 36 .

[0417] The A / D converter 36 generates upper-left pixel data of each of the 256 output images included in the L1 output image, and stores the upper-left pixel data in the SRAM 31 .

[0418] By repeating the above process (32-1)×(32-1)=961 times while shifting the reading position of the input image by one pixel each time, 31×31×256 L1 output images are generated, and the digital data is stored in the SRAM 31.

[0419] Next, the enable of the buffer connected to the second arithmetic circuit unit 30 b is set to “true”, and the enables of the other arithmetic circuit units 30 a and 30 c to 30 h are set to “false”.

[0420] Pixel data having 2×2×256=1024 pixels corresponding to the upper left portion in the 31×31×256 L1 output image is read out from the SRAM 31 and transferred to the D / A converter 34 .

[0421] The control unit 39 instructs the D / A converter 34 to start operating, and an input signal corresponding to pixel data is input to the arithmetic circuit unit 30 b .

[0422] The arithmetic circuit unit 30 b outputs 256 multiplication-accumulation result signals, and the 256 multiplication-accumulation result signals are input to the A / D converter 36 via the multiplexer 35 .

[0423] The A / D converter 36 generates upper-left pixel data of each of the 256 output images included in the L2 output image, and stores the upper-left pixel data in the SRAM 31 .

[0424] By repeating the above process (31-1)×(31-1)=900 times while shifting the reading position of the input image by one pixel each time, 30×30×256 L2 output images are generated, and the digital data is stored in the SRAM 31.

[0425] Similarly, the third arithmetic circuit unit 30 c performs an L3 convolution operation and acquires 29×29×256 L3 output images.

[0426] The fourth arithmetic circuit unit 30d performs an L4 convolution operation and acquires 28×28×256 L4 output images.

[0427] An arithmetic unit (not shown) performs a maximum pooling operation and obtains 14×14×256 output images (which may also be referred to as L4p output images).

[0428] The fifth arithmetic circuit unit 30e performs an L5 convolution operation and acquires 13×13×256 L5 output images.

[0429] The sixth arithmetic circuit unit 30 f performs an L6 convolution operation and acquires 12×12×256 L6 output images.

[0430] An arithmetic unit (not shown) performs a maximum pooling operation and obtains 6×6×256 output images (also referred to as L6p output images).

[0431] The seventh arithmetic circuit unit 30g performs an L7 convolution operation and acquires 5×5×256 L7 output images.

[0432] The eighth arithmetic circuit unit 30h performs an L8 convolution operation and acquires 4×4×256 L6 output images.

[0433] An arithmetic unit (not shown) performs transformation processing including, for example, affine transformation based on the 4×4×256 L6 output images and calculates probabilities for ten classes, and then outputs the class with the highest probability as an analogy result.

[0434] [Configuration of common wiring unit]

[0435] exist Figure 13 In the inference device 300 shown, eight arithmetic circuit units 30a to 30h are connected with respect to one D / A converter 34. Then, the output of the D / A converter 34 is input to each of the eight arithmetic circuit units 30a to 30h.

[0436] According to the present technology, the D / A converter 34 corresponds to an embodiment of a signal output circuit including a plurality of signal output lines capable of respectively outputting electrical signals.

[0437] Hereinafter, a new arrangement configuration in the case where a plurality of arithmetic circuit units 5 are connected to one signal output circuit and a new wiring configuration for electrically connecting one signal source to the plurality of arithmetic circuit units 5 will be described. It can also be said that these arrangement configuration and wiring configuration are new arrangement configuration and wiring configuration in the case where a common signal output circuit is used for the plurality of arithmetic circuit units 5.

[0438] Hereinafter, the new arrangement configuration according to the present technology will be referred to as an arrangement configuration PC. In addition, the new wiring configuration according to the present technology will be referred to as a common wiring unit WC.

[0439] First, refer to Figure 16 , “a plurality of input lines”, “a plurality of output lines” and “a reference plane” are defined with respect to the arithmetic circuit unit 5 (30a to 30h).

[0440] Figure 16 The two arithmetic circuit units 5 shown in A and B are a modification, and the method of defining "a plurality of input lines", "a plurality of output lines" and "a reference plane" is similar.

[0441] Hereinafter, for easy understanding of the description, the description will be given assuming that the X direction is the left-right direction, the Y direction is the depth direction, and the Z direction is the up-down direction. In addition, the description will be given assuming that the XY plane direction is the horizontal direction and the Z direction is the vertical direction.

[0442] Of course, the application of the present technology is not limited to the case where such a direction is set. For example, also in the case where the X direction in the figure is a vertical direction, the present technology can be applied in a manner similar to the following description.

[0443] The “plurality of input lines” are lines that input electrical signals corresponding to input values.

[0444] For example, in Figure 9 and Figure 10 In the arithmetic circuit unit 5 shown, a plurality of input signal lines 7 to which pulse signals corresponding to input values ​​are input correspond to “a plurality of input lines”.

[0445] exist Figure 11 and Figure 12 In the arithmetic circuit unit 5 shown, a positive input signal line 7a and a negative input signal line 7b to which a pair of signals generated according to input values ​​are input are respectively “plurality of input lines”.

[0446] That is, in the arithmetic device 200 having a two-input two-output configuration, all the positive input signal lines 7a and the negative input signal lines 7b are “input lines” regardless of whether they are positive or negative.

[0447] Therefore, for example, in the case where N input signal line pairs P7 are arranged, a total of 2N (N×2) signal lines are “a plurality of input lines”.

[0448] Hereinafter, each of the "plurality of input lines" will be denoted by a reference numeral and referred to as an input line 50. The number of the input lines 50 is not limited and can be arbitrarily designed.

[0449] The “plurality of output lines” are lines arranged in parallel so as to intersect the “plurality of input lines.” That is, the “plurality of output lines” are lines arranged to have a crossing configuration with respect to the “plurality of input lines.”

[0450] Furthermore, each of the “plurality of output lines” is a line that outputs a multiplication-accumulation signal generated based on the electrical signal input into the “plurality of input lines”.

[0451] It should be noted that the multiplication-accumulation signal includes any signal that represents the sum of product values ​​obtained by multiplying the input value by the weight value. For example, the multiplication-accumulation signal includes a signal corresponding to the sum of product values ​​obtained by multiplying the input value x by the weight value. i Multiply by the weight w i The charge of the product value obtained corresponds to the value x i Multiply by the positive weight w i + The product value (w i + *x i ) corresponds to the positive weight charge of the input value x i Multiply by the negative weight value w i - The product value (w i - *x i )'s negative weight charge, etc.

[0452] The signal lines are a plurality of signal lines arranged in parallel so as to intersect the “plurality of input lines”, and each signal line outputs a multiplication-accumulation signal, which are the “plurality of output lines”.

[0453] For example, in Figure 9 and Figure 10 In the arithmetic circuit unit 5 shown in FIG. 1 , the positive charge output line 8a and the negative charge output line 8b are respectively “a plurality of output lines”. Figure 11 and Figure 12 In the arithmetic circuit unit 5 shown, the positive charge output line 8a and the negative charge output line 8b are respectively “a plurality of output lines”.

[0454] That is, in the arithmetic device 100 having a one-input-one-output configuration and the arithmetic device 200 having a two-input-two-output configuration, all the positive charge output lines 8a and the negative charge output lines 8b are "multiple output lines" regardless of whether they are positive or negative.

[0455] Therefore, for example, in the case where M pairs of charge output lines 8 are arranged, a total of 2M (M×2) signal lines are “a plurality of output lines”.

[0456] Hereinafter, each of the "plurality of output lines" will be denoted by a reference numeral and referred to as an output line 51. The number of the output lines 51 is not limited and can be arbitrarily designed.

[0457] The plurality of input lines 50 are arranged in parallel using a predetermined direction as an extending direction. The plurality of output lines 51 are arranged in parallel so as to intersect the plurality of input lines 50, having a direction different from the extending direction of the plurality of input lines 50 as an extending direction.

[0458] exist Figure 16 In the examples shown in A and B of FIG, the plurality of input lines 50 are arranged in parallel using the X direction as the extending direction. Therefore, the extending direction of the plurality of input lines 50 is the X direction.

[0459] The plurality of output lines 51 are arranged in parallel using the Y direction different from the X direction as an extending direction. Therefore, the extending direction of the plurality of output lines 51 is the Y direction.

[0460] exist Figure 16 In the examples shown in A and B of FIG, the extending directions of the plurality of input lines 50 and the extending directions of the plurality of output lines 51 are orthogonal to each other. Of course, the present technology is not limited thereto, and the plurality of input lines 50 and the plurality of output lines 51 may be arranged to intersect each other at any angle.

[0461] In the present disclosure, the "extension direction" of a signal line is a concept including a direction as a reference of the extension direction of the signal line. For example, when the signal line extends straight in a predetermined direction, this predetermined direction is the "extension direction".

[0462] When a signal line extends using a predetermined direction as a reference and slightly deviates from the direction or slightly winds from the middle or has a small step from the middle, such a predetermined direction is also the “extension direction” of the signal line.

[0463] Furthermore, although the arithmetic circuit unit 5 ( 30 a to 30 h ) is configured by incorporating circuit elements such as wires and transistors in a silicon substrate or the like, a specific configuration is not limited and can be arbitrarily designed.

[0464] With respect to such an arithmetic circuit unit 5 , the surface defined above on which the plurality of input lines 50 and the plurality of output lines 51 are arranged is defined as a reference plane 53 .

[0465] exist Figure 16 In the example shown, a rectangular parallelepiped portion is schematically shown as a substrate 52 on which the arithmetic circuit unit 5 is arranged. A plurality of input lines 50 and a plurality of output lines 51 are then provided on its upper surface. Therefore, the upper surface of the substrate 52 corresponds to a reference plane 53.

[0466] Of course, the present technology is not limited thereto, and a case where conductive lines are provided and the plurality of input lines 50 and the plurality of output lines 51 are provided on the lower surface of the substrate 52 or inside the substrate 52 is also possible.

[0467] In any case, a surface on which the plurality of input lines 50 and the plurality of output lines 51 are arranged is defined as a reference plane 53 of the arithmetic circuit unit 5 .

[0468] The reference plane 53 can be arbitrarily set relative to the interior of the three-dimensional space.

[0469] Hereinafter, in the drawings of the present disclosure, the arithmetic circuit unit 5 is sometimes schematically shown as a rectangular parallelepiped shape. In this case, it is assumed that the surface on the upper surface side represents the reference plane 53.

[0470] It should be noted that the surface on which the plurality of input lines 50 are provided and the surface on which the plurality of output lines 51 are provided may be different surfaces in the vertical direction (Z direction). In this case, for example, by defining the surface on which the plurality of input lines 50 are provided or the surface on which the plurality of output lines are provided as the reference plane 53, the present technology can be implemented as described below.

[0471] [Configure PC]

[0472] Figure 17 : is a schematic diagram showing an example of arranging a configuration PC. Figure 17 In the illustrated example, one signal output circuit 55 and four arithmetic circuit units 5 are shown.

[0473] The signal output circuit 55 includes a plurality of signal output lines 56. The plurality of signal output lines 56 of the signal output circuit 55 are arranged in parallel so as to extend in the same direction.

[0474] The electric signals output from the plurality of signal output lines 56 of the signal output circuit 55 are input as electric signals corresponding to the input values ​​to the plurality of input lines 50 included in each of the four arithmetic circuit units 5 via the common wiring unit WC (see FIG. Figure 19 wait).

[0475] The newly designed arrangement configuration PC has a configuration in which the extending directions of the plurality of output lines 51 of at least two arithmetic circuit units 5 of the plurality of arithmetic circuit units 5 are parallel to each other.

[0476] These two arithmetic circuit units 5 correspond to embodiments of a “first arithmetic circuit unit” and a “second arithmetic circuit unit” according to the present technology.

[0477] That is, the layout configuration PC has a configuration in which the extending direction of the plurality of output lines 51 of the “first arithmetic circuit unit” and the extending direction of the plurality of output lines 51 of the “second arithmetic circuit unit” are parallel to each other.

[0478] exist Figure 17 In the example shown, the output lines 51 included in each of the four arithmetic circuit units 5 extend in directions parallel to the Y direction. That is, the output lines 51 of all the arithmetic circuit units 5 extend in directions parallel to one another.

[0479] It can also be said that this configuration is a configuration in which arbitrary two arithmetic circuit units of the four arithmetic circuit units 5 are a “first arithmetic circuit unit” and a “second arithmetic circuit unit”.

[0480] In addition, when any one of the four arithmetic circuit units 5 is used as the "first arithmetic circuit unit", it can also be said that the extension direction of the multiple output lines 51 included in each of the multiple arithmetic circuit units 5 is parallel to the extension direction of the multiple output lines 51 of the "first arithmetic circuit unit".

[0481] also, Figure 17 The arrangement configuration PC shown has the following configuration.

[0482] The input lines 50 included in each of the four arithmetic circuit units 5 extend in parallel. Alternatively, this arrangement means that the input lines 50 of the first arithmetic circuit unit and the input lines 50 of the second arithmetic circuit unit extend in parallel.

[0483] The reference planes 53 of the four arithmetic circuit units 5 are set to a configuration in which they are arranged side by side on the same plane. Figure 17 In the illustrated example, four arithmetic circuit units 5 are arranged so that the reference planes 53 are arranged side by side on a predetermined horizontal plane (XY plane).

[0484] It can also be said that this configuration is a configuration in which four arithmetic circuit units 5 are provided so as to be arranged side by side on the same plane.

[0485] Furthermore, the respective reference planes 53 of the four arithmetic circuit units 5 are arranged side by side in a predetermined direction. Figure 17In the example shown, the reference planes 53 are arranged side by side in the extending direction (X direction) of the plurality of input lines 50 included in each of the four arithmetic circuit units 5. In other words, the four arithmetic circuit units 5 are arranged side by side in the extending direction of the plurality of input lines 50 included in each of the four arithmetic circuit units 5.

[0486] It should be noted that the direction in which the reference planes 53 of the four arithmetic circuit units 5 (four arithmetic circuit units 5) are arranged side by side is not limited. For example, it is also possible that the reference planes 53 (arithmetic circuit units 5) are arranged side by side in the extending direction (Y direction) of the plurality of output lines 51 included in each of the four arithmetic circuit units 5.

[0487] Here, the reference plane of the “first arithmetic circuit unit” is set as the “first reference plane”, and the reference plane of the “second arithmetic circuit unit” is set as the “second reference plane”.

[0488] exist Figure 17 In the illustrated example, any two arithmetic circuit units 5 among the four arithmetic circuit units 5 may be a “first arithmetic circuit unit” and a “second arithmetic circuit unit”.

[0489] You can also say, Figure 17 The arrangement configuration PC shown is a configuration in which the "first reference plane" and the "second reference plane" are arranged side by side on the same plane. Furthermore, it can also be said that the arrangement configuration PC is a configuration in which the "first reference plane" and the "second reference plane" are arranged side by side in the extending direction (X direction) of the plurality of input lines 50 respectively included in the four arithmetic circuit units 5.

[0490] also, Figure 17 The illustrated arrangement configuration PC has a configuration in which the extending direction of the plurality of signal output lines 56 of the signal output circuit 55 is parallel to the extending direction (X direction) of the plurality of input lines 50 respectively included in the four arithmetic circuit units 5 .

[0491] It can also be said that this configuration is a configuration in which the extending direction of the plurality of signal output lines 56 of the signal output circuit 55 is parallel to the extending direction of the plurality of input lines 50 of the “first arithmetic circuit unit”.

[0492] In this way, Figure 17 The arrangement configuration PC shown includes various configurations. The present technology is not limited to configurations including these. For example, a configuration in which the extension direction of the plurality of output lines 51 of the "first arithmetic circuit unit" and the extension direction of the plurality of output lines 51 of the "second arithmetic circuit unit" are parallel to each other is also possible.

[0493] [Common Wiring Unit WC]

[0494] Figure 18 and Figure 19 is shown as Figure 17 The diagram shown is a schematic diagram of an example of a common wiring unit WC of a PC configuration. Figure 19 A is a schematic diagram when the common wiring unit WC is viewed from one side in the depth direction. Figure 19 B is a schematic diagram when the common wiring unit WC is viewed from above in the vertical direction (Z direction).

[0495] The common wiring unit WC electrically connects the plurality of signal output lines 56 of the signal output circuit 55 to the plurality of input lines 50 included in each of the plurality of arithmetic circuit units 5 .

[0496] In this embodiment, the common wiring unit WC is configured to use, as a reference, a wiring reference plane 57 set based on the positional relationship between the "first arithmetic circuit unit" and the "second arithmetic circuit unit." For example, the wiring reference plane 57 is set based on the positional relationship between the "first reference plane" of the "first arithmetic circuit unit" and the "second reference plane" of the "second arithmetic circuit unit."

[0497] like Figure 18 As shown, in this embodiment, the wiring reference plane 57 is set based on the positional relationship between the four arithmetic circuit units 5. That is, the wiring reference plane 57 is set based on each reference plane 53 of the positional relationship between the four arithmetic circuit units 5.

[0498] In this embodiment, the wiring reference plane 57 is set parallel to the same plane (horizontal plane) on which the four reference planes 53 are set. It can also be said that the wiring reference plane 57 is set parallel to the same plane (horizontal plane) on which the four arithmetic circuit units 5 are set. In this example, it corresponds to the case where the wiring reference plane 57 is set so that the same plane (horizontal plane) on which the "first reference plane" and the "second reference plane" are set is parallel.

[0499] like Figure 18 As shown, in this embodiment, the wiring reference plane 57 is provided on the upper side of the four arithmetic circuit units 5 .

[0500] like Figure 18 and Figure 19 As shown, in this embodiment, the common wiring unit WC includes a plurality of reference lines 60, a plurality of output-side lines 61, and a plurality of input-side lines 62. The number of each of the plurality of reference lines 60, the plurality of output-side lines 61, and the plurality of input-side lines 62 is generally equal to the number of electrical signals input to each arithmetic circuit unit 5 (the number of input signals).

[0501] That is, the number of each of the plurality of reference lines 60 , the plurality of output-side lines 61 , and the plurality of input-side lines 62 is equal to the number of the plurality of input lines 50 of each arithmetic circuit unit 5 .

[0502] The plurality of reference lines 60 are arranged in parallel so as to extend in the same direction on the wiring reference plane 57. The extending direction of the plurality of reference lines 60 is set to be parallel to the direction in which the "first reference plane" and the "second reference plane" are arranged side by side.

[0503] In this embodiment, the extension direction of the plurality of reference lines 60 is set to be parallel to the direction in which the reference planes 53 of the four arithmetic circuit units 5 are arranged side by side, that is, the extension direction (X direction) of the plurality of input lines 50 respectively included in the four arithmetic circuit units 5.

[0504] Therefore, a plurality of reference lines 60 are arranged along the horizontal direction.

[0505] like Figure 19 As shown in FIG. 8B , the plurality of output-side lines 61 electrically connect the plurality of signal output lines 56 of the signal output circuit 55 to the plurality of reference lines 60 .

[0506] exist Figure 19 A and B schematically illustrate the output terminal 65 of the signal output circuit 55 .

[0507] The output terminal 65 of the signal output circuit 55 is a circuit configuration including the output-side terminal of the plurality of signal output lines 56 of the signal output circuit 55. Figure 19 As shown in FIG. 1B , the plurality of output-side lines 61 are connected to the output terminal 65. Therefore, the plurality of output-side lines 61 are electrically connected to the plurality of signal output lines 56. The specific configuration of the output terminal 65 is not limited.

[0508] In this embodiment, a plurality of output-side wires 61 are provided upward in the vertical direction from an output end portion 65 of the signal output circuit 55 .

[0509] like Figure 19 As shown in FIG. 2B , the plurality of input side lines 62 electrically connect the plurality of reference lines 60 to the plurality of input lines 50 of each arithmetic circuit unit 5 .

[0510] exist Figure 19 A and B schematically illustrate the input terminal 66 of each arithmetic circuit unit 5.

[0511] The input terminal 66 of each arithmetic circuit unit 5 is a circuit configuration including input-side terminals of a plurality of input lines 50 of each arithmetic circuit unit 5. Figure 19 As shown in FIG. 1B , the plurality of input side wires 62 are connected to the input terminal 66. Therefore, the plurality of input side wires 62 are electrically connected to the plurality of input wires 50. The specific configuration of the input terminal 66 is not limited.

[0512] In this embodiment, a plurality of input-side wires 62 are arranged facing the input end portion 66 of each arithmetic circuit unit 5 from above in the vertical direction.

[0513] like Figure 18 and Figure 19 As shown, in this embodiment, a plurality of output-side wires 61 are provided in the vertical direction from the signal output circuit 55. Furthermore, on the upper side of the four arithmetic circuit units 5, a plurality of reference wires 60 are provided in the horizontal direction in the direction in which the four arithmetic circuit units 5 are arranged side by side. Furthermore, an input-side wire 62 is provided in the vertical direction from the reference wires 60 toward each arithmetic circuit unit 5.

[0514] Therefore, when observing the wires from the signal output circuit 55 to each of the four arithmetic circuit units 5 , the wire lengths from the signal output circuit 55 to the respective arithmetic circuit units 5 can be made equal, and the wire lengths can also be reduced.

[0515] For example, reference Figure 19 When observing the wires from the signal output circuit 55 to the leftmost arithmetic circuit unit 5, the wire lengths can be made equal, and the wire lengths can also be reduced. Furthermore, when observing the wires from the signal output circuit 55 to the rightmost arithmetic circuit unit 5, the wire lengths can be made equal, and the wire lengths can also be reduced. The same applies to the wires to the other arithmetic circuit units 5.

[0516] Equalizing the length of the wires from the signal output circuit 55 to the respective arithmetic circuit units 5 results in equalizing the parasitic capacitances generated by the wire units. Therefore, the delay times of the analog signals can be equalized, and the transmission errors of the analog signals can be reduced.

[0517] Since information is transmitted using time (time point) or pulse width (time period), especially in the time axis analog multiplication and accumulation method, the accuracy of arithmetic operations can be greatly improved by reducing the irregularity of delay time.

[0518] Furthermore, the length of the wiring from the signal output circuit 55 to each arithmetic circuit unit 5 can be shortened, and thus the time delay compensation of the external circuit can be reduced. As a result, the waiting time can be shortened.

[0519] Furthermore, setting the input of each arithmetic circuit unit 5 to have the same condition is also advantageous because the wiring length can be shortened.

[0520] It should be noted that there may be a case where the lengths of all the wires from the signal output circuit 55 to the respective arithmetic circuit units 5 are not equal. Furthermore, there may also be a case where the lengths of all the wires are not exactly equal and there are some irregularities in the lengths.

[0521] However, by adopting the newly designed arrangement configuration PC and the common wiring unit WC, it is possible to set the number of wires from the end of the output line 66a to the end of the input line 65b to be equal, or to set the number of wires from the signal output circuit 55 to the respective arithmetic circuit units 5 to be variable within a sufficiently small range, using a predetermined length as a reference. As a result, the above-mentioned effect can be fully exerted.

[0522] It can also be said that the equal-length wiring configuration according to the present technology is a technology that enables, in an arithmetic device in which multiple arithmetic circuit units 5 are configured according to an analog method of inputting an analog signal to a common signal output circuit 55 and outputting an analog signal from the common signal output circuit, the wiring between the signal output circuit 55 and each arithmetic circuit unit 5 to be set to have equal length (equal capacity, equal delay time) and shortened by imposing appropriate restrictions on the setting of multiple arithmetic circuit units 5 and appropriately constructing the common wiring unit WC.

[0523] The method for implementing the common wiring cell WC is not limited, and any technique can be used. For example, utilizing the laminated structure of the substrate, a wiring layer is configured with an insulating film or the like, and reference line 60 is formed. Then, vertical vias or the like are configured for the vertical wiring of the wiring layer, forming output-side line 61 and input-side line 62. Alternatively, any technique can be used.

[0524] It should be noted that the wiring reference plane 57 may be provided on the lower side of the four arithmetic circuit units 5 .

[0525] In this embodiment, the output-side wiring unit 61 corresponds to a “first wiring unit.” Furthermore, the input-side wiring unit 62 corresponds to a “second wiring unit” and a “third wiring unit.”

[0526] like Figure 19 As shown in FIG. 1A , in this embodiment, the output-side wiring unit 61 and the input-side wiring unit 62 extend in the same direction (Z direction). Therefore, in this embodiment, the “first wiring unit,” “second wiring unit,” and “third wiring unit” extend in the same direction.

[0527] Figure 20 is a schematic diagram illustrating an example of a switch mechanism provided in the common wiring unit WC.

[0528] like Figure 20 As shown, a buffer 69 enabled with the above-mentioned enable is provided in each input side line 62. By controlling the buffer 69 with the enable signal (en), the electrical signals output from the plurality of signal output lines 56 of the signal output circuit 55 can be output to each of the four arithmetic circuit units 5 in a switchable manner.

[0529] The switch mechanism including the buffer 69 with an enable corresponds to an embodiment of the "switch unit" according to the present technology. The specific configuration of the "switch unit" is not limited and can be designed arbitrarily. For example, the output side line 61 can be provided with a buffer with an enable, etc.

[0530] Figure 21 : is a schematic diagram showing another configuration example of the arrangement configuration PC and the common wiring unit WC.

[0531] exist Figure 21 In the examples shown in A and B of FIG. , the arrangement configuration PC includes an arrangement configuration in which input-side end portions of the plurality of input lines 50 face each other opposite to each other in the adjacent arithmetic circuit units 5 a and 5 b .

[0532] For example, regarding the arithmetic circuit unit 5a on the far left, the input side end portion is arranged on the right side, and the input signal is input from the right side to the left side. Regarding the second arithmetic circuit unit 5b adjacent to the arithmetic circuit unit 5a on the far left, the input side end portion is arranged on the left side, and the input signal is input from the left side to the right side.

[0533] By adopting this arrangement, the input terminal 66 can be commonly provided for the two arithmetic circuit units 5a and 5b disposed facing each other. In addition, the input side line 62 electrically connecting the reference line 60 to the plurality of input lines 50 respectively included in the two arithmetic circuit units 5a and 5b can be commonly provided.

[0534] That is, the number of vertical vias (vertical wirings) can be reduced, and simplification of the structure and reduction in component cost can be achieved.

[0535] It should be noted that a switch mechanism or the like capable of switching signals input to the two arithmetic circuit units 5 a and 5 b may be installed in the commonly configured input-side line 62 .

[0536] Since the two arithmetic circuit units 5a and 5b are regarded as the “first arithmetic circuit unit” and the “second arithmetic circuit unit”, the input side line 62 set facing the two arithmetic circuit units 5a and 5b corresponds to an embodiment of the “second wiring unit” and the “third wiring unit” composed of the same wiring unit.

[0537] That is, in Figure 21 In the illustrated configuration, the "second wiring unit" and the "third wiring unit" are composed of the same wiring unit.

[0538] It should be noted that in Figure 19 The configuration shown and Figure 21In the illustrated configuration, the input-side terminal portion of the rightmost arithmetic circuit unit 5 is located on the left side, i.e., on the side of the signal output circuit 55, and the input signal is input to the input-side terminal portion from the left to the right. Therefore, the length of the reference line 60 provided to the rightmost arithmetic circuit unit 5 can be reduced, and the wire length can be reduced. Consequently, component costs can be reduced.

[0539] Figure 22 : is a schematic diagram showing another example of arranging a PC. Figure 22 In the illustrated example, there are included one signal output circuit 55, three arithmetic circuit units 5, and one signal input circuit 85. The signal input circuit 85 will be described later.

[0540] Figure 22 The illustrated arrangement configuration PC also has a configuration in which the extending directions of the plurality of output lines 51 of at least two arithmetic circuit units 5 among the plurality of arithmetic circuit units 5 are parallel to each other.

[0541] exist Figure 22 In the example shown, the extension directions of the plurality of output lines 51 included in each of the three arithmetic circuit units 5 are all parallel to the X direction. That is, the extension directions of the plurality of output lines 51 of all the arithmetic circuit units 5 are parallel to each other.

[0542] Therefore, any two arithmetic circuit units of the three arithmetic circuit units 5 may be equivalent to the “first arithmetic circuit unit” and the “second arithmetic circuit unit”.

[0543] also, Figure 22 The arrangement configuration PC shown has the following configuration.

[0544] The input lines 50 included in each of the three arithmetic circuit units 5 extend in parallel. Alternatively, this arrangement means that the input lines 50 of the first arithmetic circuit unit and the input lines 50 of the second arithmetic circuit unit extend in parallel.

[0545] The reference planes 53 of the three arithmetic circuit units 5 are arranged side by side in a configuration orthogonal to a predetermined reference direction. Figure 22 In the example shown, the three arithmetic circuit units 5 are arranged so that the reference planes 53 are arranged side by side to be orthogonal to the vertical direction (Z direction). That is, the vertical direction is set as the reference direction.

[0546] It can also be said that this configuration is a configuration in which three arithmetic circuit units 5 are arranged side by side so as to be orthogonal to the reference direction (Z direction).

[0547] Furthermore, the respective reference planes 53 of the three arithmetic circuit units 5 are provided so as to be arranged side by side in the reference direction (Z direction).

[0548] You can also say, Figure 22 The arrangement configuration PC shown is a configuration in which the "first reference plane" and the "second reference plane" are arranged side by side to be orthogonal to the predetermined reference direction. In addition, it can also be said that Figure 22 The illustrated arrangement configuration PC is a configuration in which a “first reference plane” and a “second reference plane” are provided so as to be arranged side by side in a predetermined reference direction.

[0549] It should be noted that the method of arranging the plurality of arithmetic circuit units 5 side by side in the vertical direction is not limited, and any technique can be used. For example, a technique of configuring three-dimensional large-scale integration (LSI) can be used.

[0550] also, Figure 22 The illustrated arrangement configuration PC has a configuration in which the extending direction of the plurality of signal output lines 56 of the signal output circuit 55 is parallel to the extending direction (Y direction) of the plurality of input lines 50 respectively included in the three arithmetic circuit units 5 .

[0551] It can also be said that this configuration is a configuration in which the extending direction of the plurality of signal output lines 56 of the signal output circuit 55 is parallel to the extending direction of the plurality of input lines 50 of the “first arithmetic circuit unit”.

[0552] In this way, Figure 22 The arrangement configuration PC shown includes various configurations. The present technology is not limited to configurations including these. For example, a configuration in which the extension direction of the plurality of output lines 51 of the "first arithmetic circuit unit" and the extension direction of the plurality of output lines 51 of the "second arithmetic circuit unit" are parallel to each other is also possible.

[0553] Figure 23 and Figure 24 A and B are shown as Figure 22 The diagram shown is a schematic diagram of an example of a common wiring unit WC of a PC configuration. Figure 24 B is a schematic diagram when the common wiring unit WC is viewed from the left-right direction (X direction) side.

[0554] In this embodiment, regarding the common wiring unit WC, the wiring reference plane 57 is set based on the positional relationship between the three arithmetic circuit units 5. That is, the wiring reference plane 57 is set based on the positional relationship between the respective reference planes 53 of the three arithmetic circuit units 5.

[0555] The wiring reference plane 57 is set to be parallel to the reference direction (Z direction) orthogonal to the three reference planes 53. In addition, the wiring reference plane 57 is set to be parallel to the extending direction (X direction) of the plurality of output lines 51 respectively included in the three arithmetic circuit units 5. The extending direction of the plurality of output lines 51 respectively included in the three arithmetic circuit units 5 corresponds to the extending direction of the plurality of output lines 51 of the "first arithmetic circuit unit".

[0556] That is, in this embodiment, the wiring reference plane 57 is set to be parallel to the ZX plane direction. Figure 23 The wiring reference plane 57 shown is provided on one side of the input-side end portions of the three arithmetic circuit units 5 .

[0557] like Figure 23 and Figure 24 As shown, the common wiring unit WC includes a plurality of reference lines 60 , a plurality of output-side lines 61 , and a plurality of input-side lines 62 .

[0558] The plurality of reference lines 60 are arranged in parallel so as to extend in the same direction on the wiring reference plane 57. The extending direction of the plurality of reference lines 60 is set to be parallel to the reference direction (Z direction). Therefore, the plurality of reference lines 60 are arranged in the vertical direction.

[0559] A plurality of output-side wires 61 are provided between an output end portion 65 of the signal output circuit 55 and the reference wire 60 .

[0560] The plurality of input-side lines 62 are provided between the plurality of reference lines 60 and the input terminal 66 of each arithmetic circuit unit 5 .

[0561] The plurality of reference lines 60 and the plurality of input-side lines 62 include vertical lines extending in the vertical direction and horizontal lines extending in the horizontal direction. The present technology is not limited to these configurations.

[0562] The method of realizing the common wiring unit WC is not limited, and any technology may be used.

[0563] like Figure 23 and Figure 24 As shown, in this embodiment, a plurality of reference lines 60 are provided in the vertical direction in which the three arithmetic circuit units 5 are arranged side by side. Then, an output-side line 61 is provided to connect the signal output circuit 55 to the plurality of reference lines 60. In addition, an input-side line 62 is provided to connect the plurality of reference lines 60 to each arithmetic circuit unit 5.

[0564] Therefore, when observing the wires from the signal output circuit 55 to each of the three arithmetic circuit units 5, the wire lengths from the signal output circuit 55 to the respective arithmetic circuit units 5 can be made equal and the wire lengths can also be reduced. As a result, the arithmetic operation accuracy can be greatly improved.

[0565] Figure 25 : is a schematic diagram showing another configuration example of the arrangement configuration PC and the common wiring unit WC.

[0566] exist Figure 25 In the illustrated arrangement configuration PC, the output terminal 65 of the signal output circuit 55 and the input terminal 66 of the lowermost arithmetic circuit unit 5 are commonly arranged (hereinafter, referred to as a common terminal portion).

[0567] The common wiring unit WC includes a plurality of reference lines 60 arranged to connect common ends to input ends of the second and third arithmetic circuit units 5 .

[0568] That is, in this example, multiple reference lines 60 are connected to each of the output side ends of multiple signal output lines 56 of the signal output circuit 55, the input side ends of multiple input lines 50 of the "first arithmetic circuit unit", and the input side ends of multiple input lines 50 of the "second arithmetic circuit unit".

[0569] Therefore, the common wiring unit WC can be implemented using only the plurality of reference lines 60, and can omit the output-side line 61 and the input-side line 62. As a result, the configuration of the common wiring unit WC can be simplified, and component costs can be reduced.

[0570] exist Figures 17 to 21 The arrangement shown configures the PC or Figures 22 to 25 In the illustrated arrangement configuration PC, the extension directions of the plurality of output lines 51 of all arithmetic circuit units 5 are parallel to each other. Therefore, any two arithmetic circuit units of the plurality of arithmetic circuit units 5 can be the "first arithmetic circuit unit" and the "second arithmetic circuit unit".

[0571] Application of the present technology is not limited to this configuration.

[0572] For example, assume that the extension directions of the output lines 51 of only some of the plurality of arithmetic circuit units 5 are parallel to each other, and the extension directions of the output lines 51 of the other arithmetic circuit units 5 are not parallel.

[0573] In this case as well, the arithmetic circuit units 5 in which the multiple output lines 51 extend in parallel will be referred to as the "first arithmetic circuit unit" and the "second arithmetic circuit unit," and a common wiring unit WC according to the present technology will be configured. Therefore, for the arithmetic circuit units 5 serving as the "first arithmetic circuit unit" and the "second arithmetic circuit unit," equal-length wiring can be achieved, and the wire length can be shortened. As a result, arithmetic operation accuracy can be improved.

[0574] Figure 26 : is a schematic diagram showing another configuration example of the arrangement configuration PC and the common wiring unit WC.

[0575] exist Figure 26 In the illustrated arrangement configuration PC, a plurality of arithmetic circuit units 5 arranged on the same plane are stacked in the vertical direction.

[0576] Specifically, the three arithmetic circuit units 5 are arranged side by side on a horizontal plane (XY plane) along the Y direction. The three arithmetic circuit units 5 are stacked in three layers so as to be arranged side by side in the vertical direction.

[0577] It should be noted that it is assumed that in all the arithmetic circuit units 5 , the extending direction of the plurality of output lines 51 is parallel to the X direction.

[0578] With this arrangement configuration PC, a wiring reference plane 57a is provided, and a reference line 60a is provided so as to be parallel to the vertical direction in which the three arithmetic circuit units 5 are stacked. Furthermore, a wiring reference plane 57b is provided, and a reference line 60b is provided so as to be parallel to the same plane (XY plane) in which the three arithmetic circuit units 5 are provided.

[0579] The output-side line 61 is provided to connect the signal output circuit 55 to the reference lines 60a and 60b. Furthermore, the input-side line 62 is provided to connect the reference lines 60a and 60b to each arithmetic circuit unit 5.

[0580] In this manner, by configuring the common wiring unit WC, the wiring lengths from the signal output circuit 55 to the respective arithmetic circuit units 5 can be made equal and reduced. As a result, the arithmetic operation accuracy can be greatly improved.

[0581] You can also say, Figure 26 The configuration shown is a configuration in which, in addition to the extension directions of the plurality of output lines 51 being parallel to each other, focusing on the direction in which the reference plane is arranged side by side, a "first arithmetic circuit unit" and a "second arithmetic circuit unit" are selected, and a common wiring unit WC is configured relative to the selected "first arithmetic circuit unit" and "second arithmetic circuit unit".

[0582] In the arithmetic device according to this embodiment, a plurality of arithmetic circuit units 5 are provided relative to the common signal output circuit 55. By configuring the PC and the common wiring unit WC in the above-described arrangement, the wiring lengths from the signal output circuit 55 to the respective arithmetic circuit units 5 can be made equal, and the wiring length can also be reduced. As a result, arithmetic accuracy can be improved in an analog circuit that performs multiplication and accumulation operations.

[0583] It should be noted that, as in the above-mentioned Patent Document 1, there are documents showing drawings and the like for conceptually describing the transmission of input signals or multiplication-accumulation signals, etc. However, there are no documents that refer to the actual physical arrangement configuration, wiring, etc. in the design of multiple arithmetic circuit units.

[0584] For example, it is conceivable to perform multiple types of multiply-accumulate calculations by rewriting the weights of the multiply-accumulate device. When using an analog multiply-accumulate device that uses nonvolatile memory to perform such multiply-accumulate calculations, it is necessary to provide multiple multiply-accumulate devices, each with its own weights, to avoid rewriting. Efficient arrangement and wiring for this situation have not yet been studied.

[0585] In view of this, the actual circuit configuration of an arithmetic device having multiple arithmetic circuit units has been examined. Specifically, the arrangement and wiring that are efficient in terms of power, etc., when multiple analog arithmetic circuit units that input and output analog signals including time information corresponding to input values ​​are mounted on the same chip have been examined.

[0586] As a result, the focus is on a plurality of input lines and a plurality of output lines included in the arithmetic circuit unit, which are arranged to cross each other, and the arrangement configuration PC and the common wiring unit WC according to the present technology are newly designed.

[0587] Of course, the application of this technology is not limited to the case where multiple analog arithmetic circuit units are installed on a single chip. This technology can also be applied to the case where multiple analog arithmetic circuit units are installed on multiple chips (for example, stacked chips) or three-dimensional semiconductors, and the above-mentioned effects can be exerted.

[0588] Furthermore, the application of the present technology is not limited to the case of using an analog multiply-accumulate device using a nonvolatile memory.

[0589] The present technology is also effective for analog multiplication-accumulation devices utilizing volatile memory, for example, in a case where calculations of multiple weight groups are performed on the same input generated by a D / A converter, etc., and in a case where the outputs of multiple multiplication-accumulation devices are sampled by using an A / D, etc. in a time-division manner.

[0590] <Other embodiments>

[0591] The present technology is not limited to the above-described embodiments, and various other embodiments can be implemented.

[0592] In the above description, in the case where the common signal output circuit 55 is provided with respect to the plurality of arithmetic circuit units 5 , the arrangement configuration PC and the common wiring unit WC according to the present technology are configured.

[0593] The present technology is not limited to this, and the arrangement configuration PC and common wiring unit WC according to the present technology can also be configured when an A / D converter, etc. that receives the output (multiplication accumulation result signal) from each arithmetic circuit unit 5 is commonly set relative to multiple arithmetic circuit units 5.

[0594] For example, with respect to each of the plurality of arithmetic circuit units 5 , “a plurality of multiplication-accumulation result signal output lines” are defined.

[0595] The “plurality of multiplication-accumulation result signal output lines” outputs multiplication-accumulation result signals indicating multiplication-accumulation results generated based on the multiplication-accumulation signals output from the plurality of output lines 51 .

[0596] For example, in Figure 9 and Figure 10 In the arithmetic circuit unit 5 shown in FIG. 1 , the plurality of output signal lines 13 for outputting the multiplication-accumulation result signals correspond to the “plurality of multiplication-accumulation result signal output lines”. Figure 11 and Figure 12 In the arithmetic circuit unit 5 shown, each of the plurality of output signal lines 13 (positive output signal line 13a and negative output signal line 13b) corresponds to a "plurality of multiplication-accumulation result signal output lines".

[0597] That is, in the arithmetic device 200 having a two-input two-output configuration, both the positive output signal line 13a and the negative output signal line 13b are "multiplication-accumulation result signal output lines" regardless of whether they are positive or negative.

[0598] Regarding the plurality of arithmetic circuit units 5 , a “signal input circuit” including a plurality of signal input lines into which the multiplication-accumulation result signals respectively output from the “plurality of multiplication-accumulation result signal output lines” are respectively input is configured.

[0599] In this case, by arranging the PC and the common wiring unit WC according to the present technology as described above, it is possible to make the wiring length from each arithmetic circuit unit 5 to the signal input circuit equal and also reduce the wiring length. As a result, it is possible to improve arithmetic accuracy in analog circuits that perform multiplication and accumulation operations.

[0600] For example, Figure 27 As shown, it is assumed that four arithmetic circuit units 5 and one signal input circuit 85 are provided. Respective outputs of the four arithmetic circuit units 5 are input to a plurality of signal input lines 86 of the signal input circuit 85 and are switched appropriately.

[0601] In this case, the arrangement configuration PC as described above is configured.

[0602] In addition, if Figure 28 As shown, a wiring reference plane 87 is provided, and a plurality of reference lines 89 are provided so as to be parallel to the same plane (horizontal plane) in which four arithmetic circuit units 5 are arranged side by side.

[0603] In addition, if Figure 29As shown in A and B, an output side line 91 electrically connecting each arithmetic circuit unit 5 (output end 95) to a plurality of reference lines 89 and an input side line 92 electrically connecting the plurality of reference lines 89 to the signal input line 86 (input end 96) of the signal input circuit 85 are provided.

[0604] In this manner, by configuring the common wiring unit WC, the wiring length from each arithmetic circuit unit 5 to the signal input circuit 85 can be made equal, and the wiring length can also be reduced. As a result, the arithmetic operation accuracy can be improved.

[0605] In addition, Figure 22 In the illustrated configuration, the focus is on the plurality of arithmetic circuit units 5 and the signal input circuit 85. The signal input circuit 85 includes a plurality of signal input lines 86.

[0606] like Figure 30 As shown, a wiring reference plane 87 is provided, and a plurality of reference lines 89 are provided in the vertical direction (Z direction) in which the three arithmetic circuit units 5 are arranged side by side.

[0607] In addition, if Figure 31 As shown in A and B, an output side line 91 electrically connecting each arithmetic circuit unit 5 (output end 95) to a plurality of reference lines 89 and an input side line 92 electrically connecting the plurality of reference lines 89 to the signal input line 86 (input end 96) of the signal input circuit 85 are provided.

[0608] In this manner, by configuring the common wiring unit WC, the wiring length from each arithmetic circuit unit 5 to the signal input circuit 85 can be made equal, and the wiring length can also be reduced. As a result, the arithmetic operation accuracy can be improved.

[0609] Figure 32 is a schematic diagram illustrating another configuration example of the arithmetic device.

[0610] In the arithmetic device 400, the first arithmetic circuit unit 5a1 and the second arithmetic circuit unit 5a2 are arranged relative to the signal output circuit 55a and the signal input circuit 85a. According to the present technology, the arrangement configuration of the PC and the common wiring unit WC are configured to include a group of the signal output circuit 55a, the signal input circuit 85a, the first arithmetic circuit unit 5a1, and the second arithmetic circuit unit 5a2.

[0611] In addition, the first arithmetic circuit unit 5b1 and the second arithmetic circuit unit 5b2 are arranged relative to the signal output circuit 55b and the signal input circuit 85b. According to the present technology, the arrangement configuration of the PC and the common wiring unit WC are configured to include a group of the signal output circuit 55b, the signal input circuit 85b, the first arithmetic circuit unit 5b1, and the second arithmetic circuit unit 5b2.

[0612] In this manner, the arithmetic device according to the present technology can be configured to include a plurality of groups in each of which the arrangement configuration PC and the common wiring unit WC according to the present technology are constructed.

[0613] Figure 33 1 is a schematic diagram for describing a case where the number of inputs (the number of input signal lines 7 ) of each of the plurality of arithmetic circuit units 5 is different.

[0614] For example, Figure 33 As shown in A, a method of switching the wiring route by using a circuit or the like can be conceived.

[0615] For example, a multiplexer 97 is provided in each signal line of the common wiring unit WC (e.g., each of the plurality of reference lines 60). Then, by appropriately controlling the multiplexer 97, the input to the first arithmetic circuit unit 5a and the input to the second arithmetic circuit unit 5b are appropriately switched.

[0616] In the case of this method, it is possible to eliminate mainly unnecessary wires, and to exert effects of improving power efficiency and the like.

[0617] It should be noted that, instead of the multiplexer 97, a buffer with enable or the like may be provided in each signal output line of the signal output circuit 55. Then, by controlling the buffer, the signal output line that outputs the electric signal can be appropriately selected.

[0618] like Figure 33 As shown in FIG. 8B , a method of commonly configuring all paths to the input terminal 66 in wiring to each arithmetic circuit unit 5 can be conceived.

[0619] In the case of this method, mainly in the wiring to each arithmetic circuit unit 5 , there are exerted the effect that the variation in delay time can be reduced and the circuit configuration for switching can be omitted.

[0620] It should be noted that the common wiring unit may be provided with a buffer or the like with an enable for switching the input to each arithmetic circuit unit 5 .

[0621] In the above description, an arithmetic device according to the time axis analog multiplication accumulation method has been illustrated, wherein time (time point) or pulse width (time period) is used to transmit information. However, the present technology can also be applied to an arithmetic device according to the analog multiplication accumulation method, wherein voltage or current is used to transmit information. In the case where a common signal output circuit 55 is used for a plurality of arithmetic circuit units 5, or in the case where a common signal input circuit 85 is used for a plurality of arithmetic circuit units 5, an arrangement configuration PC and a common wiring unit WC according to the present technology are constructed. Therefore, the irregularity of the delay time (wiring delay) of the analog signal (current or voltage) can be reduced. Therefore, the standby time until all the input signals of the arithmetic circuit unit become stable can be reduced, and the waiting time can be shortened.

[0622] In the above description, the inference device has been exemplified as an arithmetic device including a plurality of arithmetic circuit units. The present technology is not limited thereto, and the present technology can also be applied to another arithmetic device including a plurality of arithmetic circuit units.

[0623] In the above description, the case where the multiplication accumulation result signal is output based on the time when the voltage maintained by the accumulation unit increases and exceeds the threshold value has been illustrated. However, a configuration in which the multiplication accumulation result signal is output based on the time when the voltage maintained by the accumulation unit decreases and exceeds the threshold voltage can be adopted. For example, charging is performed in advance until the voltage of the capacitor used as the accumulation unit reaches a predetermined preset value. After the total charge value corresponding to the product value of the signal value and the weight value is accumulated, the capacitor is discharged at a predetermined rate. In this case, the multiplication accumulation result signal can be output based on the time when the voltage maintained by the capacitor decreases to below the threshold value. Of course, the present technology is not limited to this configuration. It should be noted that in the present disclosure, discharging the capacitor is included in charging the capacitor with a negative charge.

[0624] In the above description, the case of using an output line pair has been described. The present technology is not limited to this, and three or more output lines can be provided. That is, the above-mentioned present technology can also be applied to the case of using one or more output lines of any number. For example, the multiplication unit includes a resistor that is connected between the associated input line and any one of the one or more output lines, and defines a weight value, and outputs a charge corresponding to the product value to the output line to which the resistor is connected. Of course, the present technology is not limited to this.

[0625] The arithmetic device, multiplication-accumulation device, analog circuit, synaptic circuit, neuron circuit, layout configuration, configuration of the common wiring unit, etc., method of generating the multiplication-accumulation result signal, method of switching the input to the arithmetic circuit unit, etc. described above with reference to the drawings are merely embodiments and can be arbitrarily modified without departing from the gist of the present technology. That is, any other configuration, method, etc. for implementing the present technology can be adopted.

[0626] In the present disclosure, concepts that define shape, size, positional relationship, state, etc., such as "center", "middle", "uniform", "equal", "same", "orthogonal", "parallel", "vertical", "symmetrical", "extended", "axial", "rectangular parallelepiped shape", "curved shape", "curved shape", "curved shape" and "lens shape" are concepts including "basic center", "basic middle", "basic uniform", "basic equal", "basic same", "basic orthogonal", "basic parallel", "basic vertical", "basic symmetrical", "basic extended", "basic axial", "basic rectangular parallelepiped shape", "basic curved surface shape", "basic curved shape", "basic curved shape" and "basic lens shape".

[0627] For example, it also includes predetermined ranges (for example, an error range of ±10% and a predetermined range) with reference to "completely centered", "completely in the middle", "completely uniform", "completely equal", "completely identical", "completely orthogonal", "completely parallel", "completely vertical", "completely symmetrical", "completely extended", "completely axial", "completely axial", "completely rectangular shape", "completely curved shape", "completely curved shape", "completely lens shape", etc.

[0628] At least two features of the present technology described above can be combined. In other words, the various features described in each embodiment can be arbitrarily combined in the embodiment. In addition, the various effects described above are not restrictive, but merely illustrative, and other effects can be provided.

[0629] It should be noted that the present technology can also take the following configurations.

[0630] (1) An arithmetic device comprising:

[0631] A plurality of arithmetic circuit units, each arithmetic circuit unit comprising

[0632] a plurality of input lines arranged in parallel using a predetermined direction as an extending direction, and each of a plurality of electrical signals corresponding to a plurality of input values ​​is input to one of the plurality of input lines, and

[0633] a plurality of output lines arranged in parallel using a direction different from the predetermined direction as an extension direction so as to intersect the plurality of input lines, and each output line outputting a multiplication-accumulation signal representing a sum of a plurality of product values ​​obtained by multiplying a plurality of input values ​​generated based on a plurality of electrical signals input to the plurality of input lines by corresponding weight values;

[0634] a signal output circuit, comprising a plurality of signal output lines capable of respectively outputting electrical signals; and

[0635] a common wiring unit electrically connecting a plurality of signal output lines of the signal output circuit to a plurality of input lines, each of the plurality of arithmetic circuit units including a plurality of input lines, wherein

[0636] The plurality of arithmetic circuit units include a first arithmetic circuit unit and a second arithmetic circuit unit,

[0637] The electric signals output from the plurality of signal output lines of the signal output circuit are input to the plurality of input lines included in each of the first arithmetic circuit unit and the second arithmetic circuit unit as electric signals corresponding to input values ​​via the common wiring unit, and

[0638] An extending direction of the plurality of output lines of the first arithmetic circuit unit and an extending direction of the plurality of output lines of the second arithmetic circuit unit are arranged to be parallel to each other.

[0639] (2) The arithmetic device according to (1), wherein

[0640] The common wiring unit is configured using, as a reference, a wiring reference plane set based on a positional relationship between the first arithmetic circuit unit and the second arithmetic circuit unit.

[0641] (3) The arithmetic device according to (2), wherein

[0642] The common wiring unit includes a plurality of reference lines arranged in parallel on a wiring reference plane and extending in the same direction.

[0643] (4) The arithmetic device according to (2) or (3), wherein

[0644] In each of the plurality of arithmetic circuit units, a plurality of input lines and a plurality of output lines are arranged by using a predetermined plane as a reference plane, and

[0645] The wiring reference plane is set based on a positional relationship between a first reference plane as a reference plane of the first arithmetic circuit unit and a second reference plane as a reference plane of the second arithmetic circuit unit.

[0646] (5) The arithmetic device according to (4), wherein

[0647] The first reference plane and the second reference plane are arranged side by side on the same plane, and

[0648] The wiring reference plane is disposed parallel to the same plane where the first reference plane and the second reference plane are disposed.

[0649] (6) The arithmetic device according to (5), wherein

[0650] The common wiring unit includes a plurality of reference lines arranged in parallel on a wiring reference plane and extending in the same direction, and

[0651] The extension directions of the plurality of reference lines are set to be parallel to a direction in which the first reference plane and the second reference plane are arranged side by side.

[0652] (7) The arithmetic device according to (6), wherein

[0653] The first reference plane and the second reference plane are arranged side by side in an extending direction of the plurality of input lines of the first arithmetic circuit unit or in an extending direction of the plurality of output lines of the first arithmetic circuit unit.

[0654] (8) The arithmetic device according to (4), wherein

[0655] The first reference plane and the second reference plane are arranged side by side to be orthogonal to a predetermined reference direction, and

[0656] The routing reference plane is set parallel to the reference direction.

[0657] (9) The arithmetic device according to (8), wherein

[0658] The wiring reference plane is disposed in parallel with the reference direction and the extending direction of the plurality of output lines of the first arithmetic circuit unit.

[0659] (10) The arithmetic device according to (9), wherein

[0660] The common wiring unit includes a plurality of reference lines arranged in parallel on a wiring reference plane and extending in the same direction, and

[0661] The extension directions of the plurality of reference lines are set to be parallel to the reference direction.

[0662] (11) The arithmetic device according to any one of (2) to (10), wherein

[0663] The common wiring unit includes a plurality of reference lines arranged in parallel on a wiring reference plane and extending in the same direction, and

[0664] The common wiring unit includes at least one of the following: a first wiring unit that electrically connects multiple signal output lines of the signal output circuit to multiple reference lines; a second wiring unit that electrically connects the multiple reference lines to multiple input lines of the first arithmetic circuit unit; and a third wiring unit that electrically connects the multiple reference lines to the multiple input lines of the second arithmetic circuit unit.

[0665] (12) The arithmetic device according to (11), wherein

[0666] The common wiring unit includes a first wiring unit, a second wiring unit, and a third wiring unit, and

[0667] The first wiring unit, the second wiring unit, and the third wiring unit extend in the same direction.

[0668] (13) The arithmetic device according to (11) or (12), wherein

[0669] The common wiring unit includes a second wiring unit and a third wiring unit, and

[0670] The second wiring unit and the third wiring unit are composed of the same wiring unit.

[0671] (14) The arithmetic device according to any one of (2) to (13), wherein

[0672] The common wiring unit includes a plurality of reference lines arranged in parallel on a wiring reference plane and extending in the same direction, and

[0673] The plurality of reference lines are connected to each of the output-side ends of the plurality of signal output lines of the signal output circuit, the input-side ends of the plurality of input lines of the first arithmetic circuit unit, and the input-side ends of the plurality of input lines of the second arithmetic circuit unit.

[0674] (15) The arithmetic device according to any one of (1) to (14), wherein

[0675] An extending direction of the plurality of input lines of the first arithmetic circuit unit and an extending direction of the plurality of input lines of the second arithmetic circuit unit are arranged to be parallel to each other.

[0676] (16) The arithmetic device according to any one of (1) to (15), wherein

[0677] The plurality of signal output lines of the signal output circuit are arranged in parallel and extend in the same direction, and

[0678] An extension direction of the plurality of signal output lines of the signal output circuit is configured to be parallel to an extension direction of the plurality of input lines of the first arithmetic circuit unit.

[0679] (17) The arithmetic device according to any one of (1) to (16), wherein

[0680] The extension direction of the plurality of output lines included in each of the plurality of arithmetic circuit units is configured to be parallel to the extension direction of the plurality of output lines of the first arithmetic circuit unit, and

[0681] The electric signals output from the plurality of signal output lines of the signal output circuit are input as electric signals corresponding to input values ​​to the plurality of input lines included in each of the plurality of arithmetic circuit units via the common wiring unit.

[0682] (18) The arithmetic device according to any one of (1) to (17), wherein

[0683] The common wiring unit includes a switch unit that outputs the electrical signals output from the plurality of signal output lines of the signal output circuit to each of the plurality of arithmetic circuit units in a switchable manner.

[0684] (19) An arithmetic device comprising:

[0685] A plurality of arithmetic circuit units, each arithmetic circuit unit comprising

[0686] a plurality of input lines arranged in parallel using a predetermined direction as an extending direction, and each of a plurality of electrical signals corresponding to a plurality of input values ​​is input to one of the plurality of input lines,

[0687] a plurality of output lines arranged in parallel using a direction different from the predetermined direction as an extension direction so as to intersect the plurality of input lines, and each output line outputting a multiplication-accumulation signal representing a sum of a plurality of product values ​​obtained by multiplying a plurality of input values ​​generated based on a plurality of electrical signals input to the plurality of input lines by corresponding weight values, and

[0688] a plurality of multiplication-accumulation result signal output lines for outputting multiplication-accumulation result signals representing multiplication-accumulation results generated based on the multiplication-accumulation signals output via the plurality of output lines;

[0689] a signal input circuit including a plurality of signal input lines to which a multiplication accumulation result signal output from each of the plurality of multiplication accumulation result signal output lines is input; and

[0690] A common wiring unit electrically connects a plurality of multiplication-accumulation result signal output lines included in each of the plurality of arithmetic circuit units to a plurality of signal input lines of the signal input circuit, wherein

[0691] The plurality of arithmetic circuit units include a first arithmetic circuit unit and a second arithmetic circuit unit,

[0692] The multiplication accumulation result signals output from the plurality of multiplication accumulation result signal output lines included in each of the first arithmetic circuit unit and the second arithmetic circuit unit are input into the plurality of signal input lines of the signal input circuit, and

[0693] An extending direction of the plurality of output lines of the first arithmetic circuit unit and an extending direction of the plurality of output lines of the second arithmetic circuit unit are arranged to be parallel to each other.

[0694] (20) A multiplication-accumulation system comprising:

[0695] A plurality of arithmetic circuit units, each arithmetic circuit unit comprising:

[0696] a plurality of input lines arranged in parallel using a predetermined direction as an extending direction, and each of a plurality of electrical signals corresponding to a plurality of input values ​​is input to one of the plurality of input lines, and

[0697] a plurality of output lines, the plurality of output lines being arranged in parallel using a direction different from the predetermined direction as an extension direction so as to intersect the plurality of input lines, and each output line outputting a multiplication-accumulation signal representing a sum of a plurality of product values ​​obtained by multiplying a plurality of input values ​​generated based on a plurality of electrical signals input to the plurality of input lines by corresponding weight values;

[0698] A signal output circuit, comprising a plurality of signal output lines capable of outputting electrical signals respectively;

[0699] a common wiring unit electrically connecting a plurality of signal output lines of the signal output circuit to a plurality of input lines, each of the plurality of arithmetic circuit units including the plurality of input lines; and

[0700] A network circuit is configured by connecting a plurality of arithmetic circuit units, wherein

[0701] The plurality of arithmetic circuit units include a first arithmetic circuit unit and a second arithmetic circuit unit,

[0702] The electric signals output from the plurality of signal output lines of the signal output circuit are input to the plurality of input lines included in each of the first arithmetic circuit unit and the second arithmetic circuit unit as electric signals corresponding to input values ​​via the common wiring unit, and

[0703] An extending direction of the plurality of output lines of the first arithmetic circuit unit and an extending direction of the plurality of output lines of the second arithmetic circuit unit are arranged to be parallel to each other.

[0704] Reference Signs List

[0705] PC layout configuration

[0706] WC Common Wiring Unit

[0707] 1 signal line

[0708] 3 Analog Circuits

[0709] 5.30 Arithmetic Circuit Unit

[0710] 7 Input signal line

[0711] 8 Charge output lines

[0712] 9 Synaptic Circuits

[0713] 10 Neuron Circuits

[0714] 13 Output signal line

[0715] 34 D / A converters

[0716] 36 A / D converters

[0717] More than 50 input lines

[0718] 51+ output lines

[0719] 53 Reference Plane

[0720] 55 signal output circuit

[0721] 56 signal output line

[0722] 57, 87 wiring reference plane

[0723] 60, 89 reference lines

[0724] 61 Output side line

[0725] 62 Input siding

[0726] 85 signal input circuit

[0727] 86 signal input line

[0728] 91 output side line

[0729] 92 Input siding

[0730] 100, 200, 400 arithmetic devices

[0731] 300 Inference Device.

Claims

1. An arithmetic device comprising: A plurality of arithmetic circuit units, each arithmetic circuit unit comprising: a plurality of input lines arranged in parallel using a predetermined direction as an extending direction, and each of a plurality of electrical signals corresponding to a plurality of input values ​​is input to one of the plurality of input lines, and a plurality of output lines arranged in parallel using a direction different from the predetermined direction as an extension direction so as to intersect the plurality of input lines, and each output line outputting a multiplication-accumulation signal representing a sum of a plurality of product values ​​obtained by multiplying a plurality of the input values ​​generated based on the plurality of the electrical signals input to the plurality of input lines by corresponding weight values; a signal output circuit, comprising a plurality of signal output lines capable of respectively outputting electrical signals; and a common wiring unit electrically connecting the plurality of signal output lines of the signal output circuit to the plurality of input lines, each of the plurality of arithmetic circuit units including the plurality of input lines, wherein The plurality of arithmetic circuit units include a first arithmetic circuit unit and a second arithmetic circuit unit, the electric signals output from the plurality of signal output lines of the signal output circuit are input to the plurality of input lines included in each of the first arithmetic circuit unit and the second arithmetic circuit unit as the electric signals corresponding to the input values ​​via the common wiring unit, and An extending direction of the plurality of output lines of the first arithmetic circuit unit and an extending direction of the plurality of output lines of the second arithmetic circuit unit are arranged to be parallel to each other, The common wiring unit is configured using, as a reference, a wiring reference plane set based on a positional relationship between the first arithmetic circuit unit and the second arithmetic circuit unit.

2. The arithmetic device according to claim 1, wherein The common wiring unit includes a plurality of reference lines arranged in parallel on the wiring reference plane and extending in the same direction.

3. The arithmetic device according to claim 1, wherein In each of the plurality of arithmetic circuit units, the plurality of input lines and the plurality of output lines are arranged by using a predetermined plane as a reference plane, and The wiring reference plane is set based on a positional relationship between a first reference plane as the reference plane of the first arithmetic circuit unit and a second reference plane as the reference plane of the second arithmetic circuit unit.

4. The arithmetic device according to claim 3, wherein The first reference plane and the second reference plane are arranged side by side on the same plane, and The wiring reference plane is disposed parallel to the same plane where the first reference plane and the second reference plane are disposed.

5. The arithmetic device according to claim 4, wherein The common wiring unit includes a plurality of reference lines arranged in parallel on the wiring reference plane and extending in the same direction, and Extension directions of the plurality of reference lines are set to be parallel to a direction in which the first reference plane and the second reference plane are arranged side by side.

6. The arithmetic device according to claim 5, wherein The first reference plane and the second reference plane are arranged side by side in an extending direction of the plurality of input lines of the first arithmetic circuit unit or in an extending direction of the plurality of output lines of the first arithmetic circuit unit.

7. The arithmetic device according to claim 3, wherein The first reference plane and the second reference plane are arranged side by side to be orthogonal to a predetermined reference direction, and The wiring reference plane is arranged parallel to the reference direction.

8. The arithmetic device according to claim 7, wherein The wiring reference plane is disposed in parallel with the reference direction and an extending direction of the plurality of output lines of the first arithmetic circuit unit.

9. The arithmetic device according to claim 7, wherein The common wiring unit includes a plurality of reference lines arranged in parallel on the wiring reference plane and extending in the same direction, and The extension directions of the plurality of reference lines are set to be parallel to the reference direction.

10. The arithmetic device according to claim 1, wherein The common wiring unit includes a plurality of reference lines arranged in parallel on the wiring reference plane and extending in the same direction, and The common wiring unit includes at least one of the following: a first wiring unit electrically connecting the plurality of signal output lines of the signal output circuit to the plurality of reference lines; a second wiring unit electrically connecting the plurality of reference lines to the plurality of input lines of the first arithmetic circuit unit; and a third wiring unit electrically connecting the plurality of reference lines to the plurality of input lines of the second arithmetic circuit unit.

11. The arithmetic device according to claim 10, wherein The common wiring unit includes the first wiring unit, the second wiring unit, and the third wiring unit, and The first wiring unit, the second wiring unit, and the third wiring unit extend in the same direction.

12. The arithmetic device according to claim 10, wherein The common wiring unit includes the second wiring unit and the third wiring unit, and The second wiring unit and the third wiring unit are composed of the same wiring unit.

13. The arithmetic device according to claim 1, wherein The common wiring unit includes a plurality of reference lines arranged in parallel on the wiring reference plane and extending in the same direction, and The multiple reference lines are connected to each of the following: the output-side ends of the multiple signal output lines of the signal output circuit, the input-side ends of the multiple input lines of the first arithmetic circuit unit, and the input-side ends of the multiple input lines of the second arithmetic circuit unit.

14. The arithmetic device according to claim 1, wherein An extending direction of the plurality of input lines of the first arithmetic circuit unit and an extending direction of the plurality of input lines of the second arithmetic circuit unit are configured to be parallel to each other.

15. The arithmetic device according to claim 1, wherein The plurality of signal output lines of the signal output circuit are arranged in parallel and extend in the same direction, and An extension direction of the plurality of signal output lines of the signal output circuit is configured to be parallel to an extension direction of the plurality of input lines of the first arithmetic circuit unit.

16. The arithmetic device according to claim 1, wherein The extension direction of the plurality of output lines included in each of the plurality of arithmetic circuit units is configured to be parallel to the extension direction of the plurality of output lines of the first arithmetic circuit unit, and The electric signals output from the plurality of signal output lines of the signal output circuit are input to the plurality of input lines included in each of the plurality of arithmetic circuit units as the electric signals corresponding to the input values ​​via the common wiring unit.

17. The arithmetic device according to claim 1, wherein The common wiring unit includes a switch unit that outputs the electrical signal output from the plurality of signal output lines of the signal output circuit to each of the plurality of arithmetic circuit units in a switchable manner.

18. An arithmetic device comprising: A plurality of arithmetic circuit units, each arithmetic circuit unit comprising: a plurality of input lines arranged in parallel using a predetermined direction as an extending direction, and each of a plurality of electrical signals corresponding to a plurality of input values ​​is input to one of the plurality of input lines, a plurality of output lines arranged in parallel using a direction different from the predetermined direction as an extension direction so as to intersect the plurality of input lines, and each output line outputting a multiplication-accumulation signal representing a sum of a plurality of product values ​​obtained by multiplying a plurality of the input values ​​generated based on the plurality of the electrical signals input to the plurality of input lines by corresponding weight values, and a plurality of multiplication-accumulation result signal output lines for outputting multiplication-accumulation result signals representing multiplication-accumulation results generated based on the multiplication-accumulation signals outputted via the plurality of output lines; a signal input circuit including a plurality of signal input lines to which the multiplication-accumulation result signal output from each of the plurality of multiplication-accumulation result signal output lines is input; and a common wiring unit electrically connecting the plurality of multiplication-accumulation result signal output lines included in each of the plurality of arithmetic circuit units to the plurality of signal input lines of the signal input circuit, wherein The plurality of arithmetic circuit units include a first arithmetic circuit unit and a second arithmetic circuit unit, The multiplication accumulation result signals output from the plurality of multiplication accumulation result signal output lines included in each of the first arithmetic circuit unit and the second arithmetic circuit unit are input into the plurality of signal input lines of the signal input circuit, and An extending direction of the plurality of output lines of the first arithmetic circuit unit and an extending direction of the plurality of output lines of the second arithmetic circuit unit are arranged to be parallel to each other, Here, the common wiring unit is configured using a wiring reference plane set based on a positional relationship between the first arithmetic circuit unit and the second arithmetic circuit unit as a reference.

19. A multiplication-accumulation system comprising: A plurality of arithmetic circuit units, each arithmetic circuit unit comprising: a plurality of input lines arranged in parallel using a predetermined direction as an extending direction, and each of a plurality of electrical signals corresponding to a plurality of input values ​​is input to one of the plurality of input lines, and a plurality of output lines arranged in parallel using a direction different from the predetermined direction as an extension direction so as to intersect the plurality of input lines, and each output line outputting a multiplication-accumulation signal representing a sum of a plurality of product values ​​obtained by multiplying a plurality of the input values ​​generated based on the plurality of the electrical signals input to the plurality of input lines by corresponding weight values; A signal output circuit, comprising a plurality of signal output lines capable of outputting electrical signals respectively; a common wiring unit that electrically connects the plurality of signal output lines of the signal output circuit to the plurality of input lines each of the plurality of arithmetic circuit units includes; and A network circuit configured by connecting the plurality of arithmetic circuit units, wherein: The plurality of arithmetic circuit units include a first arithmetic circuit unit and a second arithmetic circuit unit, the electric signals output from the plurality of signal output lines of the signal output circuit are input to the plurality of input lines included in each of the first arithmetic circuit unit and the second arithmetic circuit unit as the electric signals corresponding to the input values ​​via the common wiring unit, and An extending direction of the plurality of output lines of the first arithmetic circuit unit and an extending direction of the plurality of output lines of the second arithmetic circuit unit are arranged to be parallel to each other, Here, the common wiring unit is configured using a wiring reference plane set based on a positional relationship between the first arithmetic circuit unit and the second arithmetic circuit unit as a reference.

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