Hierarchical memory group timing

Abstract

The memory banks of the memory device are arranged and operated in groups, and the groups are further arranged and operated as clusters of these groups. Successive accesses to memory banks within different memory bank clusters can be issued at a first time interval. Successive accesses to memory banks within different memory bank groups within the same cluster can be issued no faster than a second time interval. Furthermore, successive accesses to memory banks within the same memory bank group can be issued no faster than a third time interval. Multiple rows of memory banks in the memory device can be opened simultaneously. The rows that can be opened simultaneously are determined by the rows that are already opened. These memory banks are also arranged and operated in groups with three different minimum time intervals.

Description

Attached Figure Description

[0001] Figure 1 This is a block diagram of a memory system.

[0002] Figure 2 This is a diagram illustrating the delay between multiple commands.

[0003] Figure 3 It is a conceptual diagram of the physical arrangement of memory cells and example signal paths in a memory device.

[0004] Figure 4 This is a diagram of a memory system.

[0005] Figure 5 This is a diagram illustrating the delay between multiple commands.

[0006] Figure 6A This is a diagram illustrating the first example of a signal path used for cluster access to storage groups.

[0007] Figure 6B This is a timing diagram illustrating cluster access to storage units.

[0008] Figure 7A This is a second example illustration of a signal path used for cluster access to storage groups.

[0009] Figure 7B This is a timing diagram illustrating cluster access to storage units.

[0010] Figure 8A This is a diagram illustrating a first example of a signal path used for accessing a group of memory.

[0011] Figure 8B This is a timing diagram illustrating memory bank group access.

[0012] Figure 9A This is a diagram of a second example of a signal path used for accessing a group of memory.

[0013] Figure 9B This is a timing diagram illustrating memory bank group access.

[0014] Figure 10 This is a flowchart illustrating a method for operating a memory device with hierarchical memory bank timing.

[0015] Figure 11 It is a flowchart illustrating a method for operating a memory device.

[0016] Figure 12 This is a block diagram of the processing system. Detailed Implementation

[0017] Double Data Rate (DDR) type Dynamic Random Access Memory (DRAMs) are organized into multiple memory banks that enable sequential read or write access to active rows within a specific memory bank or group of memory banks at frequencies ranging from 100 to 200 MHz. This maximum frequency of sequential access is also known as the core frequency (abbreviated as CF in this document). However, with advancements in integrated circuit manufacturing technology, the input / output interface frequencies and bandwidths of these DRAMs are increasing generation by generation to keep pace with ever-growing application performance requirements and system clock frequencies / bandwidths.

[0018] In an embodiment, the memory banks of the memory device are arranged and operated in groups (i.e., memory bank groups), and these groups are further arranged and operated as clusters of these groups (i.e., memory bank group clusters). In this arrangement, a first (i.e., minimum) time interval (e.g., t) can be used. min =[4×CF] -1 This initiates sequential accesses to storage units within different storage unit clusters. This can be no faster than a second (i.e., the median value greater than the minimum) time interval (e.g., t). intmd =[2×CF] -1 It issues consecutive accesses to different storage groups within the same cluster. Furthermore, it can be no faster than a third (i.e., the maximum value greater than the median) time interval (e.g., t). max =CF -1 It issues consecutive accesses to memory banks within the same memory bank group.

[0019] In an embodiment, the memory bank of the memory device can have multiple rows that are open simultaneously. When a row shares a sense amplifier with another row that is already open, that row may not be opened until the other row is closed. Therefore, at any given time, some rows may be "prevented" from being opened based on which rows are currently open. The memory banks are arranged and operated in groups (i.e., memory bank groups). This can be done in a first (i.e., minimum) time interval (e.g., t). min =[4×CF] -1 This issues consecutive accesses to memory banks within different memory bank groups. This can be no faster than a second (i.e., the median value greater than the minimum) time interval (e.g., t). intmd =[2×CF] -1 This allows for consecutive accesses to memory banks within the same memory bank group. Furthermore, it can be done no faster than the third (i.e., the maximum value greater than the median) time interval (e.g., t). max =CF -1 It issues consecutive accesses to rows that are opened simultaneously in the same memory bank.

[0020] Figure 1 This is a block diagram of the memory system. Figure 1In the memory system 100, a controller 110 and a memory component 120 are included. The memory component 120 includes memory banks 151a-151c, 152a-152c, 153a-153c, 154a-154c, a multiplexing / demultiplexing (MUX / DEMUX) function 122, and a data interface 124. Memory banks 151a-151c, 152a-152c, 153a-153c, and 154a-154c are arranged and coupled as members of memory bank groups 141, 142, 143, and 144, respectively. Memory bank groups 141-142 are arranged and coupled as members of memory bank group cluster 131a. Memory bank groups 143-144 are arranged and coupled as members of memory bank group cluster 131b. Additional memory banks, memory bank groups, and / or memory bank group clusters (for simplicity) are also included. Figure 1 (Not shown in the image) may be included as part of memory component 120.

[0021] Storage group 141 includes MUX / DEMUX function 145a. MUX / DEMUX function 145a is operatively coupled to MUX / DEMUX function 135a of storage groups 151a-151c and storage group cluster 131a. Storage group 142 includes MUX / DEMUX function 145b. MUX / DEMUX function 145b is operatively coupled to MUX / DEMUX function 135a of storage groups 152a-152c and storage group cluster 131a.

[0022] Storage group 143 includes MUX / DEMUX function 145c. MUX / DEMUX function 145c is operatively coupled to MUX / DEMUX function 135b of storage groups 153a-153c and storage group cluster 131b. Storage group 144 includes MUX / DEMUX function 145d. MUX / DEMUX function 145d is operatively coupled to MUX / DEMUX function 135b of storage groups 154a-154c and storage group cluster 131b.

[0023] MUX / DEMUX functions 135a-135b are operatively coupled to MUX / DEMUX function 122. MUX / DEMUX function 122 is operatively coupled to data interface 124. Data interface 124 is operatively coupled to controller 110.

[0024] Controller 110 and memory component 120 can be integrated circuit type devices, such as those commonly referred to as "chips". The memory controller (such as controller 110) manages the flow of data to and from memory devices and / or memory modules. The memory controller can be a separate, stand-alone chip, or integrated into another chip. For example, the memory controller can be included on a single die with a microprocessor, or included as part of a more complex integrated circuit system (such as a block of a system-on-a-chip (SOC)).

[0025] Controller 110 is operatively coupled to memory component 120 via at least one command address (CA) interface. Controller 110 is operatively coupled to memory component 120 to send commands to memory component 120. Memory component 120 receives commands (and addresses) via a corresponding command address interface.

[0026] It should be understood that MUX / DEMUX functions 122, 135a-135b, and 145a-145d operate to direct data to / from their respective inputs and outputs. MUX / DEMUX functions 122, 135a-135b, and 145a-145d may be or include a signal bus shared with local, intermediate, and / or global routes, transmission gates, multiplexers, demultiplexers, other logic, and / or tri-state buffers, which are operatively coupled to drive and direct data to / from memory banks 151a-151c, 152a-152c, 153a-153c, 154a-154c, and data interface 124.

[0027] The memory banks 151a-151c, 152a-152c, 153a-153c, and 154a-154c of memory component 120 are arranged and operated in memory bank groups 141-144. Memory bank groups 141-144 are further arranged and operated as memory bank group clusters 131a-131b. Therefore, memory component 120 is configured as a three-level hierarchical grouping of memory banks (first level) to memory bank groups (second level) and memory bank groups to memory bank group clusters (third level).

[0028] In this embodiment, the hierarchical grouping of memory banks determines the minimum consecutive access timing between different memory banks. Specifically, consecutive access to different memory banks within the same memory bank group requires a longer access interval than consecutive access to memory banks within different memory bank groups. Furthermore, consecutive access to different memory banks within the same memory bank group cluster requires a longer access interval than consecutive access to memory banks in different memory bank group clusters.

[0029] As described herein, it should be understood that the column-to-column minimum latency intervals presented are merely examples. Hierarchical grouping of memory also affects the minimum latency interval for command-to-command timing. Table 1 provides some example command-to-command latency interval parameters.

[0030]

[0031]

[0032] It should also be understood that a similar set of hierarchical timing constraints with different values ​​(e.g., t) can be specified for devices that have different back-to-back delay intervals for reading compared to write operations. CCD_RD_L ≠t CCD_WR_L , t CCD_RD_M ≠t CCD_WR_M (etc.). However, for the sake of brevity, this discussion is limited to the timing of read and write operations that are assumed to be equal (i.e., (e.g., t...). CCD_RD_L =t CCD_WR_L , t CCD_RD_M =t CCD_WR_M (etc.). Memory devices with internal error correction code circuitry are examples of memory devices that may have different timing sequences for read and write operations.

[0033] For example, when the sequential access is to memory bank 151a and then memory bank 151c, the data associated with the second access (i.e., to / from memory bank 151c) needs to be propagated through MUX / DEMUX functions 145a, 135a, and 122 to reach or originate from data interface 124. However, when the sequential access is to memory bank 151a (in memory bank group 141 of memory bank group cluster 131a) and memory bank 152b (in memory bank group 142 of memory bank group cluster 131a), the data associated with the second access (i.e., to / from memory bank 152b) can wait at the input / output of MUX / DEMUX function 145b, and therefore does not need to be propagated through MUX / DEMUX function 145a before being propagated through MUX / DEMUX functions 135a and 122 to reach or originate from data interface 124. Therefore, the timing between consecutive accesses to different memory banks within the same memory bank group is specified to be longer than the timing between consecutive accesses to different memory banks in different memory bank groups.

[0034] Using column-to-column operations as an example, the interval (also known as the "long" t) between back-to-back column accesses to different banks within the same bank group is shown. CCD_LThis can be specified as a longer time (in the range of 5-10 ns) than consecutive column accesses to memory banks not in the same memory bank group (e.g., t in the range of 2.5-5 ns). CCD_M In another example, the interval (also known as the "long" t) between back-to-back row accesses to different banks within the same bank group. RRD_L ) is specified as comparing consecutive row accesses of memory banks that are not in the same memory bank group (e.g., t RRD_M (A longer time)

[0035] The hierarchical grouping of storage units also determines the minimum back-to-back access timing between storage units in different storage unit clusters. In particular, consecutive accesses to storage units within the same storage unit cluster require longer access times than consecutive accesses to storage units in different storage unit clusters.

[0036] For example, when the sequential access is to storage bank 151a (in storage bank group 141 of storage bank group cluster 131a) and then to storage bank 152b (in storage bank group 142 of storage bank group cluster 131a), the data associated with the second access (i.e., to / from storage bank 152b) needs to be propagated through MUX / DEMUX function 135a and then through MUX / DEMUX function 122 to reach or originate from data interface 124. However, when the sequential access is to memory bank 151a (in memory bank group 141 of memory bank group cluster 131a) and then to memory bank 154b (in memory bank group 144 of memory bank group cluster 131b), the data associated with the second access (i.e., to / from memory bank 154b) can wait at the input / output of MUX / DEMUX function 122, and therefore does not need to be propagated through MUX / DEMUX function 135a before propagating through MUX / DEMUX function 122 to reach or originate from data interface 124. Therefore, the timing (e.g., t) between sequential accesses to different memory banks within the same memory bank group cluster is not affected. CCD_M ) is specified to compare consecutive accesses to storage units in different storage unit clusters (e.g., t CCD_S (Within the range of 1.25-2.5ns) for longer periods.

[0037] In other words, it can be done in the first (i.e., the smallest) time interval (e.g., t). min =[4×CF] -1 , such as by t CCD_S (Control) issues consecutive accesses to different storage group clusters. This can be no faster than a second (i.e., the median value greater than the minimum) time interval (e.g., by t). CCD_M Controlled t intmd =[2×CF] -1This allows for consecutive accesses to memory banks within different memory bank groups within the same cluster. Furthermore, this can be done no faster than a third (i.e., the maximum value greater than the median) time interval (e.g., by t). CCD_L Controlled t max =CF -1 These timing references issue consecutive accesses to memory banks within the same memory bank group. Figure 2 Further explanation.

[0038] Controller 110 includes scheduling logic ( Figure 1 (Not shown in the image) to issue accesses to memory banks 151a-151c, 152a-152c, 153a-153c, and 154a-154c to memory component 120. Again, using the minimum column-to-column latency as an example, the scheduling logic of controller 110 can use the first column-to-column latency (t...) CCD_S This is used for consecutive column access to storage banks 151a-151c, 152a-152c, 153a-153c, and 154a-154c, which are members of different storage bank group clusters 131a-131b. The scheduling logic of controller 110 can use the second column-to-column delay (t) CCD_M This is used for consecutive column accesses to storage units 151a-151c and 152a-152c, which are members of the same storage unit cluster (e.g., 131a) but different storage unit groups within that cluster (e.g., storage unit groups 141 and 142 of storage unit cluster 131a). The scheduling logic of controller 110 can use a third column-to-column delay (t). CCD_L This is used for consecutive column access to storage banks 151a-151c, which are members of the same storage bank group (e.g., storage bank group 141) and the same storage bank group cluster (e.g., 131a).

[0039] In another example using row-to-row operations, the scheduling logic of controller 110 can use the first row-to-row delay (t) RRD_S This is used for consecutive row accesses to storage banks 151a-151c, 152a-152c, 153a-153c, and 154a-154c, which are members of different storage bank group clusters 131a-131b. The scheduling logic of controller 110 can use the second row-to-row delay (t) RRD_M This is used for consecutive row accesses to storage units 151a-151c and 152a-152c, which are members of the same storage unit cluster (e.g., 131a) but different storage unit groups within that cluster (e.g., storage unit groups 141 and 142 of storage unit cluster 131a). The scheduling logic of controller 110 can use the third row-to-row delay (t). RRD_LThis is used for consecutive row access to storage units 151a-151c, which are members of the same storage unit group (e.g., storage unit group 141) and the same storage unit group cluster (e.g., 131a).

[0040] It should be understood that the memory component (e.g., memory component 120) can receive a clock signal used as a timing reference. Therefore, the intervals described herein can be expressed as multiple cycles of the reference clock frequency. Because the memory component can operate at different reference clock frequencies, the intervals described herein can be expressed as intervals of an integer number of clock cycles (or phases) rounded to the timing reference.

[0041] Figure 2 This is a diagram illustrating the delay between multiple commands. Figure 2 In this example, column access is used as an example command for illustration. However, other types of commands and delays (e.g., those detailed in Table 1) may follow similar or equivalent patterns. The first example read command (RD1) is issued by controller 110 and received by memory component 120. The addresses associated with the RD1 command specify the bank group cluster address as BC1 202, the bank group address as BG1 206, the bank address as BA1 210, and the column address as COL1. If a new bank group cluster address (e.g., BC2, where BC1 ≠ BC2) is provided for a subsequent command, a minimum amount of time (i.e., t) can be used longer or later than the first command. CCD_S Within this timeframe, subsequent commands are issued / received. This timing sequence is... Figure 2 The process involves t from the first read command (RD1) to the second read command (RD2). CCD_S The latency and the change in the storage group cluster address from BC1 202 to BC2 203 are used to illustrate this. Note that as long as BC1 ≠ BC2, there are no additional constraints on the subsequent storage group (BG2), storage address (BA2), and / or column (COL2) addresses, in order to minimize the time amount (i.e., t) at later times. CCD_S Send / receive continuous commands within )

[0042] If for a subsequent command (RD3) following the second command (RD2), the storage group cluster address is the same as the second command (BC2), but a new storage group address is provided (e.g., BG3 ≠ BG2), then a longer or intermediate time period (i.e., t) can be used after the second command. CCD_M Within this timeframe, subsequent (RD3) commands are sent / received. This timing sequence is... Figure 2 The process involves t from the second read command (RD2) to the third read command (RD3). CCD_MThe delay, the same memory group cluster addresses BC 2203 and 204, and the change of memory group address from BG2 207 to BG3 208 are used to illustrate this. Note that when the memory group cluster address is the same as the previous command and a new memory group address (e.g., BG3) is provided, no constraints are imposed on the memory address (BA3) and / or column (COL3) address so that the intermediate time amount (i.e., t) is later. CCD_M Send / receive continuous commands within )

[0043] If for a subsequent command (RD4) following the third command (RD3), the storage group cluster address and storage group are the same as the third command, but a new storage address is provided (e.g., BA4 ≠ BA3), then a longer or later time period (i.e., t) following the third command is allowed. CCD_L Within this timeframe, subsequent commands are issued / received. This timing sequence is... Figure 2 The process involves reading from the third read command (RD3) to the fourth read command (RD4). CCD_L This is illustrated by the following: delays, identical memory group cluster addresses BC2 204 and 204, identical memory group addresses BG3 208 and 209, and changes in memory addresses from BA3 211 to BA4 212. Note that when the memory group cluster address and memory group are the same as in the previous command and a new memory address (e.g., BA4) is provided, no constraints are imposed on the column (COL) address to ensure that the maximum time amount (i.e., t) is reached later. CCD_L Within this scope, continuous commands can be issued / received. Table 2 summarizes the references in this article. Figure 2 The described timing constraints.

[0044]

[0045] In embodiments, the scheduling logic of controller 110 and / or memory component 120 can be configured (e.g., via registers or commands) to use the longest timing for all back-to-back accesses. When in this mode, the scheduling performed by controller 110 and the internal timing of memory component 120 are simplified. However, when referenced herein... Figures 1-2 In the described tiered (i.e., storage group cluster) mode, better optimized multi-level timing can be used based on access.

[0046] Figure 3 This is a conceptual diagram illustrating the physical arrangement of memory cells and example signal paths in a memory device. Figure 3In this configuration, the memory bank array is hierarchically grouped into memory bank groups, and these memory bank groups are further grouped into memory bank group clusters. A first signal path operates between memory bank 351a and the interface and serializer 390. Data is transferred between memory bank 351a and shared data path circuitry (e.g., MUX / DEMUX functions, buffers, common signal lines, logic, etc.) within the memory bank group. This... Figure 3 This is illustrated by lines 341 (between memory bank 351a and line 343) and 342 (between memory bank 351b and line 343). The shared data path circuitry within the same memory bank group can operate at the core frequency controlled by the longest column-to-column delay timing (e.g., for a 100-200MHz cycle frequency, t...). CCD_L =5-10ns).

[0047] Data is transferred between data path circuits shared within a storage group and data path circuits shared within a storage group cluster. This is in Figure 3 The diagram is illustrated by lines 343 (between memory bank group 351a and line 345) and 344 (between memory bank group 352a and line 345). Data path circuitry shared within the same memory bank group cluster can operate at frequencies controlled by the intermediate column-to-column delay timing (e.g., for a 200-400MHz cycle core frequency, t...). CCD_M =2.5-5ns).

[0048] Data is transferred between data path circuits shared within a storage group cluster and between data path circuits shared across all storage group clusters. This is in Figure 3 The diagram is illustrated by lines 345 (between the memory bank cluster of memory bank 351a and serializer 390) and 346 (between the memory bank cluster of memory bank 354a and serializer 390). The data path circuitry shared between memory bank clusters can operate at frequencies controlled by the shortest column-to-column delay timing (e.g., for a 400-800MHz cycle frequency, t...). CCD_S =1.25-2.5ns).

[0049] Figure 4 This is a diagram of a memory system. Figure 4 In this memory system 400, a controller 410 and a memory component 420 are included. The memory component 420 includes memory banks 441-444, a multiplexing / demultiplexing (MUX / DEMUX) function 422, and a data interface 424. Memory banks 441-442 are arranged and coupled as members of memory bank group 431a. Memory banks 443-444 are arranged and coupled as members of memory bank group 431b. Additional memory banks, memory bank groups, and / or memory bank group clusters (not included for brevity) are also included. Figure 4 (As shown in the figure) can be included as part of memory component 420.

[0050] Storage bank 431a also includes a MUX / DEMUX function 435a. The MUX / DEMUX function 435a is operatively coupled to storage banks 441-442. Storage bank 441 includes the MUX / DEMUX function 445a. Storage bank 442 includes the MUX / DEMUX function 445b. The MUX / DEMUX functions 445a-445b are operatively coupled to the MUX / DEMUX function 435a.

[0051] Storage bank 431b also includes a MUX / DEMUX function 435b. The MUX / DEMUX function 435b is operatively coupled to storage banks 443-444. Storage bank 443 includes a MUX / DEMUX function 445c. Storage bank 444 includes a MUX / DEMUX function 445d. MUX / DEMUX functions 445c-445d are operatively coupled to the MUX / DEMUX function 435b.

[0052] MUX / DEMUX functions 435a-435b are operatively coupled to MUX / DEMUX function 422. MUX / DEMUX function 422 is operatively coupled to data interface 424. Data interface 424 is operatively coupled to controller 410.

[0053] Controller 410 and memory component 420 can be integrated circuit type devices, such as those commonly referred to as "chips". The memory controller (such as controller 410) manages the flow of data to and from memory devices and / or memory modules. The memory controller can be a separate, independent chip, or integrated into another chip. For example, the memory controller can be included on a single die with a microprocessor, or it can be included as part of a more complex integrated circuit system, such as a block of a system-on-a-chip (SOC).

[0054] Controller 410 is operatively coupled to memory 420 via at least one command address (CA) interface. Controller 410 is operatively coupled to memory 420 to send commands to memory 420. Memory 420 receives commands (and addresses) via corresponding command address interfaces.

[0055] It should be understood that MUX / DEMUX functions 422, 435a-435b, and 445a-445d operate to direct data to / from their respective inputs and outputs. MUX / DEMUX functions 422, 435a-435b, and 445a-445d may be or include a signal bus shared with local, intermediate, and / or global routes, transmission gates, multiplexers, demultiplexers, other logic, and / or tri-state buffers, which are operatively coupled to drive and direct data to / from the row and data interfaces 424 of memory banks 441-444.

[0056] Memory component 420 may have multiple rows in the same memory bank 441-444 open simultaneously. Controller 410 divides the address space of memory bank 441-444 into segments 451a-451b, 452a-452b, 453a-453b, and 454a-454b based on row address ranges. These row address ranges do not necessarily correspond to the row address ranges of the subarrays of memory bank 441-444 (also called memory array blocks – MATs). When a command to open a row is sent, controller 410 marks multiple segments (i.e., row address ranges) as blocked. Controller 410 thus tracks the address ranges in memory bank 441-444, where it will not open a second row unless and until the first row is closed. In an embodiment, memory component 420 may store information about which segments and how many segments should be blocked in response to opening a row. This information may be read by controller 410 during initialization.

[0057] Because more than one row in the memory can be opened simultaneously, the column access operation sent to memory 420 specifies which row is the subject of the column access. In one embodiment, the entire row address is used to specify the subject row. In another embodiment, the mapping from open rows to tag values ​​is maintained by memory 420. Controller 410 sends tag values ​​to specify the subject row. These tag values ​​can be generated, for example, using a function of the row address (e.g., a hash), a count of open rows, or a priority encoder.

[0058] In this embodiment, memory 420 is configured such that multiple rows in the same memory bank 441-444 can be opened simultaneously, provided that the opened rows do not interfere with each other in segments 451a-451b, 452a-452b, 453a-453b, and 454a-454b. Therefore, for example, when memory 420 activates a row in memory bank 441, the read amplifier bars surrounding that row are used to activate the addressed row, and the remaining read amplifier bars in memory bank 441 do not participate in the activation.

[0059] Controller 410 may include a scheduler. The scheduler selects transactions / commands to be sent to memory 420. The scheduler may maintain corresponding address tables for memory banks 441-444, indicating which address ranges (i.e., segments 451a-451b, 452a-452b, 453a-453b, 454a-454b) are blocked due to open rows. Entries in the address tables may correspond to specific address ranges (i.e., segments) and store one or more indicators indicating whether an address range is available or unavailable for opening a row within that address range. Entry in the address table may include a single bit or other value corresponding to whether an address range is available to open a row. Entry in the address table may include values ​​that track when an address range becomes available. For example, when memory 420 is configured for automatic precharge, a timer value may increment or decrement under certain conditions to track when precharge will complete and thus the address range becomes available.

[0060] Further discussion of segments 451a-451b, 452a-452b, 453a-453b, 454a-454b, memory component 420, and their operation and control by controller 410 is provided in U.S. Provisional Patent Application 62 / 835,717, filed April 18, 2019, entitled “MEMORY SYSTEM WITH MULTIPLE OPEN ROWS PERBANK”, and the entire contents thereof are incorporated herein by reference.

[0061] The memory banks 441-444 of the memory assembly 420 are arranged and operated in memory bank groups 431a-431b. Therefore, the memory assembly 420 can be viewed as a three-level hierarchical grouping of segments (first level) to memory banks (second level) and memory banks to memory bank groups (third level).

[0062] In this embodiment, the hierarchical grouping of segments, banks, and bank groups determines the minimum consecutive access timing between different segments. In particular, consecutive access to different (non-blocking) segments within the same bank requires a longer access time than consecutive access to segments in different bank groups.

[0063] As described herein, it should be understood that the column-to-column minimum latency intervals presented are merely examples. Hierarchical grouping of segments, banks, and bank groups also affects the minimum latency interval for commands with similar (or identical) command timings. Table 3 provides some example command-to-command latency interval parameters.

[0064]

[0065] It should also be understood that a similar set of hierarchical timing constraints with different values ​​(e.g., t) can be specified for devices that have different back-to-back latency intervals for reading compared to write operations. CCD_RD_L ≠t CCD_WR_L , t CCD_RD_M ≠t CCD_WR_M (etc.). However, for the sake of brevity, this discussion is limited to the timing of read and write operations that are assumed to be equal (i.e., (e.g., t...). CCD_RD_L =t CCD_WR_L , t CCD_RD_M =t CCD_WR_M wait).

[0066] Using column-to-column operations as an example, when the sequential access is to segment 451a and then segment 451b, the data associated with the second access (i.e., to / from segment 451b) needs to be propagated through MUX / DEMUX functions 445a, 435a, and 422 to reach or originate from data interface 424. However, when the sequential access is to segment 451a (in memory 441 of memory bank 431a) and then segment 452b (in memory bank 442 of memory bank 431a), the data associated with the second access (i.e., to / from segment 452b) can wait at the input / output of MUX / DEMUX function 445b, and therefore does not need to be propagated through MUX / DEMUX function 445a before being propagated through MUX / DEMUX functions 435a and 422 to reach or originate from data interface 424. Therefore, the timing between consecutive accesses to different segments within the same memory (e.g., t in the 5-10 ns range) CCD_L ) is specified as comparing consecutive accesses to segments in different memory banks (e.g., t in the range of 2.5-5ns). CCD_M (A longer time)

[0067] The hierarchical grouping of segments also determines the minimum column-to-column access timing between segments in different memory groups. In particular, consecutive accesses to segments within the same memory group require longer access times than consecutive accesses to segments in different memory groups.

[0068] Continuing with column-to-column operations as an example, when consecutive accesses are to segment 451a (in memory bank 431a) and then to segment 452a (in memory bank 431a), the second access (i.e., to / from segment 452a) needs to propagate through MUX / DEMUX function 435a, and then through MUX / DEMUX function 422, to reach or originate from data interface 424. However, when consecutive accesses are to segment 451a (in memory bank 431a) and then to segment 454b (in memory bank 431b), the data associated with the second access (i.e., to / from segment 454b) can wait at the input / output of MUX / DEMUX function 422, and therefore does not need to propagate through MUX / DEMUX function 435a before propagating through MUX / DEMUX function 422 to reach or originate from data interface 424. Therefore, the timing between consecutive accesses to different memory banks within the same memory bank group (e.g., t) CCD_M ) is specified as comparing consecutive accesses to memory banks in different memory banks (e.g., t in the range of 1.25-2.5 ns). CCD_S (A longer time)

[0069] In other words, it can be done in the first (i.e., the smallest) time interval (e.g., by t). CCD_S Controlled t min =[4×CF] -1 This issues consecutive accesses to segments in different memory bank groups. This can be no faster than a second (i.e., the median value greater than the minimum) time interval (e.g., by t). CCD_M Controlled t intmd =[2×CF] -1 This allows for consecutive accesses to segments in different memory banks within the same memory bank group. Furthermore, this can be done no faster than a third (i.e., a value greater than the median maximum) time interval (e.g., by t). CCD_L Controlled t max =CF -1 This involves issuing consecutive accesses to (non-blocking) segments within the same memory bank group. These timing references... Figure 5 Further explanation.

[0070] The scheduling logic of controller 410 issues access requests to memory component 420 for segments 451a-451b, 452a-452b, 453a-453b, and 454a-454b. Again using the column-to-column minimum latency as an example, the scheduling logic of controller 410 can use the first column-to-column latency (t... CCD_SThis is used for consecutive access to segments 451a-451b, 452a-452b, 453a-453b, and 454a-454b, which are portions of memory banks that are part of different memory bank groups 431a-431b, and uses a second column-to-column delay (t). CCD_M This is for sequential access to memory segments 451a-451b, 452a-452b, 453a-453b, and 454a-454b, which are members of a first bank group (e.g., 131a) and different banks within the first bank group (e.g., banks 441 and 442 of bank group 431a). The scheduling logic of controller 110 uses a third column-to-column delay (t). CCD_L This is used for continuous access to segments 451a-451b, which are members of the first bank (e.g., bank 441) of the first bank group (e.g., 431a).

[0071] As discussed herein, the scheduler of controller 410 can issue commands that cause multiple rows of one or more memory banks 441-444 to open simultaneously. Therefore, controller 410 may include circuitry that associates indicators with corresponding row address segments (ranges) of one or more memory banks. The circuitry of controller 410 may set a corresponding indicator to a first value associated with a corresponding row address segment of a first memory bank, which is unavailable (i.e., blocked) to opening a row in the associated corresponding row address range. In response to at least memory controller 410 processing a command to memory component 420 to open a row in the corresponding row address range of memory banks 441-444 associated with at least one of the plurality of corresponding indicators, multiple corresponding indicators may be set to a first value. In other words, opening a row in one segment (e.g., 451a) of memory bank 441 may cause other segments (e.g., 451b) to become unavailable (blocked).

[0072] Figure 5 This is a diagram illustrating the delay between multiple commands. Figure 5 In this example, column access is used as an example command for illustration. However, other types of commands and delays (e.g., those detailed in Table 3) may follow similar or equivalent patterns. The first example read command (RD1) is issued by controller 410 and received by memory component 420. The addresses associated with this command specify the bank group address as BG1 502, the bank address as BA1 506, the segment address as SEG1 510, and the column address as COL1. If a new bank group address (e.g., BG2, where BG1 ≠ BG2) is provided for a subsequent command, the shortest possible time (i.e., t) can be longer or later than the first command. CCD_S Within this timeframe, subsequent commands are issued / received. This timing sequence is... Figure 5 The process involves t from the first read command (RD1) to the second read command (RD2). CCD_S The delay and the change in bank group address from BG1 502 to BG2 503 are illustrated below. Note that as long as BG1 ≠ BG2, no additional constraints are imposed on subsequent bank (BA), segment (SEG), and / or column (COL) addresses, so that the delay can be minimized in the shortest possible time (i.e., t). CCD_S Send / receive continuous commands.

[0073] If for a subsequent command (RD3) following the second command (RD2), the memory bank address is the same as the second command, but a new memory bank address is provided (e.g., BA3 ≠ BA2), then a longer or intermediate time period (i.e., t) can be used after the first command. CCD_M Within this timeframe, subsequent (RD3) commands are sent / received. This timing sequence is... Figure 5 The process involves t from the second read command (RD2) to the third read command (RD3). CCD_M The delay is illustrated by the same memory bank group addresses BG2 503 and 504, and the change of memory bank address from BA2 507 to BA3 508. Note that when the memory bank group address is the same as the first command and a new memory bank address (e.g., BA3) is provided, no additional constraints are imposed on the segment (SEG) and / or column (COL) addresses so that the intermediate time amount (i.e., t) is later. CCD_M Send / receive continuous commands within )

[0074] If, for a subsequent command (RD4) following the third command (RD3), the bank group address and bank address are the same as the first command, but a new segment address is provided (e.g., SEG4), then the maximum time interval (i.e., t) after the first command can be longer or later. CCD_L Within this timeframe, subsequent commands are issued / received. This timing sequence is... Figure 5 The process involves reading from the third read command (RD3) to the fourth read command (RD4). CCD_L This is illustrated by the following: delays, identical bank group addresses BG2 504 and 505, identical bank addresses BA3 508 and 509, and segment addresses changing from SEG3 511 to SEG4 512. Note that when the bank group address and bank address are the same as in the previous command and a new segment address is provided (e.g., SEG4 ≠ SEG3), no constraints are imposed on the (COL) address so that the maximum time amount (i.e., t) is available later. CCD_L Within this scope, continuous commands can be issued / received. Table 4 summarizes the references in this article. Figure 5 The described timing constraints.

[0075]

[0076] It should be understood that the above description assumes t CCD_L This approach applies to subsequent accesses to different columns within the same memory bank group, the same memory bank address, and the same segment, as well as subsequent accesses to different segments within the same memory bank group and the same memory bank address. In the embodiments, different timing sequences can be applied to accesses to different columns within the same memory bank group, the same memory bank address, and the same segment, as well as subsequent accesses to different segments within the same memory bank address.

[0077] In embodiments, the scheduling logic of controller 410 and / or memory component 420 can be configured (e.g., via registers or commands) to use the longest timing for all back-to-back accesses. When in this mode, the scheduling performed by controller 410 and the internal timing of memory component 120 are simplified. However, when referenced herein... Figures 4-5 In the described hierarchical (i.e., segment / bank / bank group) model, better optimized multi-level timing can be used based on access.

[0078] Figure 6A This is a diagram illustrating a first example of a signal path used for cluster access to storage groups. Figure 6A In this memory module 600, memory bank cluster #1 (BC1) 631a and memory bank cluster #2 (BC2) 631b are included. BC1 631a includes memory bank cluster #1 (BG1) 641 and memory bank cluster #2 (BG2) 642. BC2 631b includes memory bank cluster #3 (BG3) 643 and memory bank cluster #4 (BG4) 644. BG1 includes memory bank 651a and memory bank 651b. BG2 includes memory bank 652a and memory bank 652b. BG3 includes memory bank 653a and memory bank 653b. BG4 includes memory bank 654a and memory bank 654b.

[0079] Memory banks 651a and 651b are operatively coupled to data path circuit 635a (e.g., MUX / DEMUX functionality, buffers, common signal lines, logic, etc.). Memory banks 652a and 652b are operatively coupled to data path circuit 635b. Data path circuit 635a is operatively coupled to data path circuit 635b. Memory banks 654a and 654b are operatively coupled to data path circuit 635c. Memory banks 653a and 653b are operatively coupled to data path circuit 635d. Data path circuit 635c is operatively coupled to data path circuit 635d. Data path circuits 635b and 635d are operatively coupled to data path circuit 635e. Therefore, to access rows in memory banks 651a or 651b, data flows through data path circuits 635a, 635b, and 635e. Similarly, to access rows in memory bank 654a or 654b, data flows through data path circuits 635c, 635d, and 635e. To access rows in memory bank 652a or 652b, data flows through data path circuits 635b and 635e. To access rows in memory bank 653a or 653b, data flows through data path circuits 635d and 635e.

[0080] The data path circuit 635a, shared by memory banks 651a and 651b, can operate at frequencies controlled by core column-to-column delay timing (e.g., for a 100-200MHz cycle frequency, t CCD_L =5-10ns). Similarly, the data path circuit 635c shared by memory bank 654a and memory bank 654b can operate at frequencies controlled by core column-to-column delay timing (e.g., for a 100-200MHz cycle frequency, t CCD_L =5-10ns). The data path circuit 635b shared by memory bank 652a and memory bank 652b, and the data path circuit 635a can operate at a frequency controlled by intermediate column-to-column delay timing (e.g., for a period frequency of 200-400MHz, t CCD_M =2.5-5ns). Similarly, the data path circuit 635d shared by memory banks 653a and 653b, and the data path circuit 635c, can operate at frequencies controlled by intermediate column-to-column delay timing (e.g., for a 200-400MHz cycle frequency, t CCD_M = 2.5-5ns). Finally, the data path circuit 635e carrying data for all memory banks 651a, 651b, 652a, 652b, 653a, 653b, 654a, and 654b can operate at a frequency controlled by the shortest column-to-column delay timing (e.g., for a 400-800MHz cycle frequency, t CCD_s=1.25-2.5ns).

[0081] In the example access operation, four units of data (e.g., bytes, words, etc.) are transferred to or from the corresponding address lines in the respective memory banks 651a-654a. This is in Figure 6A The diagram is illustrated by lines 661a-664a. A first data unit is transferred between rows in memory bank 651a via data paths 661a and 635a. Similarly, a second data unit is transferred between rows in memory bank 654a via data paths 664a and 635c. The first data unit is time-multiplexed on data path circuit 635b with a third data unit going to / from a row in memory bank 652a. The second data unit is time-multiplexed on data path circuit 635d with a fourth data unit going to / from a row in memory bank 653a. All four data units are time-multiplexed on data path circuit 635e. Data path circuit 635e is operatively coupled to the input / output logic of memory component 600. Figure 6B The examples further illustrate the reuse of data going to / from storage units 651a-654a.

[0082] Figure 6B This is a timing diagram illustrating cluster access to storage units. Figure 6B In this system, memory cells 651a-654a are clocked by signals CK-651 to CK-654, respectively. CK-652 is delayed by 180° compared to CK-651. CK-653 is delayed by 270° compared to CK-651. CK-654 is delayed by 90° compared to CK-651.

[0083] At the rising edge of CK-651, the first data unit is read from memory 651a via data path 661a and carried via data path circuit 635a. This is illustrated by arrow 601. Data path circuit 635a couples the first data unit to data path circuit 635b. This is illustrated by arrow 602. Data path circuit 635b couples the first data unit to data path circuit 635e. This is illustrated by arrow 603.

[0084] On the next rising edge of CK-654, the second data unit is read from memory 654a via data path 664a and carried via data path circuit 635c. This is illustrated by arrow 604. Data path circuit 635c couples the second data unit to data path circuit 635d. This is illustrated by arrow 605. Data path circuit 635d couples the second data unit to data path circuit 635e. This is illustrated by arrow 606.

[0085] On the next rising edge of CK-652, the third data unit is read from memory 652a via data path 662a. This is illustrated by arrow 607. Data path 662a couples the third data unit to data path circuit 635b. This is illustrated by arrow 608. Data path circuit 635b couples the third data unit to data path circuit 635e. This is illustrated by arrow 609.

[0086] On the next rising edge of CK-653, the fourth data unit is read from memory 653a via data path 663a. This is illustrated by arrow 610. Data path 663a couples the fourth data unit to data path circuit 635d. This is illustrated by arrow 611. Data path circuit 635d couples the fourth data unit to data path circuit 635e. This is illustrated by arrow 612.

[0087] Figure 7A This is a second example illustration of a signal path used for cluster access to storage groups. Figure 7A In this memory assembly 700, memory bank cluster #1 (BC1) 731a and memory bank cluster #2 (BC2) 731b are included. BC1 731a includes memory bank cluster #1 (BG1) 741 and memory bank cluster #2 (BG2) 742. BC2 731b includes memory bank cluster #3 (BG3) 743 and memory bank cluster #4 (BG4) 744. BG1 741 includes memory bank 751a and memory bank 751b. BG2 742 includes memory bank 752a and memory bank 752b. BG3 743 includes memory bank 753a and memory bank 753b. BG4 744 includes memory bank 754a and memory bank 754b.

[0088] Memory banks 751a and 751b are operatively coupled to data path circuit 735a (e.g., MUX / DEMUX functionality, buffers, common signal lines, logic, etc.). Memory banks 752a and 752b are operatively coupled to data path circuit 735b. Data path circuit 735a is operatively coupled to data path circuit 735b. Memory banks 754a and 754b are operatively coupled to data path circuit 735c. Memory banks 753a and 753b are operatively coupled to data path circuit 735d. Data path circuit 735c is operatively coupled to data path circuit 735d. Therefore, to access a row in memory bank 751a or 751b, data flows through data path circuits 735a and 735b. Similarly, to access a row in memory bank 754a or 754b, data flows through data path circuits 735c and 735d. To access a row in memory bank 752a or 752b, data flows through data path circuit 735b. To access a row in memory bank 753a or 753b, data flows through data path circuit 735d.

[0089] The data path circuit 735a, shared by memory banks 751a and 751b, can operate at frequencies controlled by core column-to-column delay timing (e.g., for a 100-200MHz cycle frequency, t CCD_L =5-10ns). Similarly, the data path circuit 735c shared by memory bank 754a and memory bank 754b can operate at frequencies controlled by core column-to-column delay timing (e.g., for a 100-200MHz cycle frequency, t CCD_L =5-10ns). The data path circuit 735b shared by memory bank 752a and memory bank 752b, as well as the data path circuit 735a, can operate at a frequency controlled by intermediate column-to-column delay timing (e.g., for a period frequency of 200-400MHz, t CCD_M =2.5-5ns). Similarly, the data path circuit 735 shared by memory banks d753a and 753b, and the data path circuit 735c can operate at frequencies controlled by intermediate column-to-column delay timing (e.g., for a period of 200-400MHz, t). CCD_M =2.5-5ns).

[0090] In the example access operation, four units of data (e.g., bytes, words, etc.) are transferred to or from the corresponding address lines in the respective memory banks 751a-754a. This is in Figure 7AThe diagram is illustrated by lines 761a-764a. A first data unit is transmitted between rows in memory bank 751a via data paths 761a and 735a. Similarly, a second data unit is transmitted between rows in memory bank 754a via data paths 764a and 735c. The first data unit is time-multiplexed on data path circuit 735b with a third data unit going to / from a row in memory bank 752a. The second data unit is time-multiplexed on data path circuit 735d with a fourth data unit going to / from a row in memory bank 753a. Data path circuits 735b and 735d are operatively coupled to the input / output logic of memory component 700. Figure 7B The example further illustrates the reuse of data going to / from storage units 751a-754a.

[0091] Figure 7B This is a timing diagram illustrating cluster access to storage units. Figure 7B In this system, memory cells 751a-754a are clocked by signals CK-751 to CK-754, respectively. CK-752 is delayed by 180° compared to CK-751. CK-753 is delayed by 270° compared to CK-751. CK-754 is delayed by 90° compared to CK-751.

[0092] At the rising edge of CK-751, the first data unit is read from memory 751a via data path 761a and carried via data path circuit 735a. This is illustrated by arrow 701. Data path circuit 735a couples the first data unit to data path circuit 735b. This is illustrated by arrow 702.

[0093] On the next rising edge of CK-754, the second data unit is read from memory 754a via data path 764a and carried via data path circuit 735c. This is illustrated by arrow 704. Data path circuit 735c couples the second data unit to data path circuit 735d. This is illustrated by arrow 705.

[0094] On the next rising edge of CK-752, the third data unit is read from memory 752a via data path 762a. This is illustrated by arrow 707. Data path 762a couples the third data unit to data path circuit 735b. This is illustrated by arrow 708.

[0095] On the next rising edge of CK-753, the fourth data cell is read from memory 753a via data path 763a. This is illustrated by arrow 710. Data path 763a couples the fourth data cell to data path circuit 735d. This is illustrated by arrow 711.

[0096] It should be understood that the data carried by data path circuit 735b and data path circuit 735d can be transmitted via... Figure 7A Additional circuitry (e.g., data I / O circuitry such as data interface 124) not shown in the diagram may be used for further time multiplexing. This time multiplexing may result in the time being further multiplexed by t CCD_S The column-to-column latency visible to the managed storage controller.

[0097] Figure 8A This is a diagram illustrating a first example of a signal path used for accessing a group of memory. Figure 8A In this memory assembly 800, memory bank group #1 (BG1) 831a and memory bank group #2 (BG2) 831b are included. BG1 831a includes memory bank 841 and memory bank 842. BG2 831b includes memory bank 843 and memory bank 844. Memory bank 841 includes a (non-blocking) segment 851. Memory bank 842 includes a (non-blocking) segment 852. Memory bank 843 includes a (non-blocking) segment 853. Memory bank 844 includes a (non-blocking) segment 854.

[0098] Memory banks 841 and 842 are operatively coupled to data path circuitry 835a (e.g., MUX / DEMUX functionality, buffers, common signal lines, logic, etc.). Memory banks 843 and 844 are operatively coupled to data path circuitry 835b. Data path circuitry 835a is operatively coupled to data path circuitry 835b. Therefore, to access rows in memory banks 841 or 842, data flows through data path circuitry 835a and 835b. Similarly, to access rows in memory banks 843 or 844, data flows through data path circuitry 835b.

[0099] Row access data paths 861-864 can operate at frequencies controlled by core column-to-column latency timing (e.g., for a 100-200MHz cycle frequency, t CCD_L =5-10ns). The data path circuit 835a shared by memory bank 841 and memory bank 842 can operate at a frequency controlled by intermediate column-to-column delay timing (e.g., for a 200-400MHz loop frequency, t CCD_M =2.5-5ns). The data path circuit 835b, shared by memory bank 843 and memory bank 844, and the data path circuit 835a can operate at frequencies controlled by the shortest column-to-column delay timing (e.g., for a period frequency of 400-800MHz, t CCD_S =1.25-2.5ns).

[0100] In the example access operation, four units of data (e.g., bytes, words, etc.) are transferred to or from the corresponding address lines in the corresponding memory banks 841-844. This is in Figure 8A The diagram is illustrated by lines 861-864. The first data unit is transmitted between rows in segment 851 via data paths 861 and 835a. The second data unit is transmitted between rows in segment 853 via data path circuit 835b. The first data unit is time-multiplexed with the second data unit on data path circuit 835b. The third data unit is transmitted between rows in segment 852 via data paths 862 and 835a. The third data unit is time-multiplexed with the first data unit on data path circuit 835a. The third data unit is time-multiplexed with the first and second data units on data path circuit 835b. The fourth data unit is transmitted between rows in segment 854 via data path 864. The fourth data unit is time-multiplexed with the first, second, and third data units on data path circuit 835b. Therefore, all four data units are time-multiplexed on data path circuit 835b. Data path circuit 835b is operatively coupled to the input / output logic of memory component 800. Figure 8B The example in the document further illustrates the reuse of data going to / from segments 851-854.

[0101] Figure 8B This is a timing diagram illustrating memory bank group access. Figure 8B In the memory, memory cells 841-844 are clocked by signals CK-841 to CK-844 respectively. CK-842 is delayed by 180° compared to CK-841. CK-843 is delayed by 90° compared to CK-841. CK-844 is delayed by 270° compared to CK-841.

[0102] At the rising edge of CK-841, the first data unit is read from segment 851 via data path 861 and carried via data path circuit 835a. This is illustrated by arrows 801 and 802, respectively. Data path circuit 835a couples the first data unit to data path circuit 835b. This is illustrated by arrow 803.

[0103] On the next rising edge of CK-843, the second data unit is read from segment 853 via data path 863 and carried via data path circuit 835b. This is illustrated by arrows 804 and 805, respectively.

[0104] On the next rising edge of CK-842, the third data unit is read from segment 852 via data path 862 and carried via data path circuit 835a. This is illustrated by arrows 807 and 808, respectively. Data path circuit 835a couples the third data unit to data path circuit 835b. This is illustrated by arrow 809.

[0105] On the next rising edge of CK-844, the fourth data unit is read from segment 854 via data path 864 and carried via data path circuit 835b. This is illustrated by arrows 810 and 811, respectively.

[0106] Figure 9A This is a diagram illustrating a second example of a signal path used for accessing a group of memory. Figure 9A In this memory assembly 900, memory bank group #1 (BG1) 931a and memory bank group #2 (BG2) 931b are included. BG1 931a includes memory bank 941 and memory bank 942. BG2 931b includes memory bank 943 and memory bank 944. Memory bank 941 includes a (non-blocking) segment 951. Memory bank 942 includes a (non-blocking) segment 952. Memory bank 943 includes a (non-blocking) segment 953. Memory bank 944 includes a (non-blocking) segment 954.

[0107] Memory banks 941 and 942 are operatively coupled to data path circuitry 935a (e.g., MUX / DEMUX functionality, buffers, common signal lines, logic, etc.). Memory banks 943 and 944 are operatively coupled to data path circuitry 935b. Therefore, to access rows in memory banks 941 or 942, data flows via data path circuitry 935a. Similarly, to access rows in memory banks 943 or 944, data flows via data path circuitry 935b.

[0108] Data path circuits 961-964 for accessing the corresponding rows in segments 951-954 can operate at frequencies controlled by core column-to-column delay timing (e.g., for a 100-200MHz cycle frequency, t CCD_L =5-10ns). The data path circuit 935a shared by memory bank 941 and memory bank 942 can operate at frequencies controlled by the intermediate core column-to-column delay timing (e.g., for a 200-400MHz cycle frequency, t CCD M =2.5-5ns). The data path circuit 935b, shared by the circuit memory bank 943 and the memory bank 944, and the data path circuit 935a can operate at frequencies controlled by the shortest column-to-column delay timing (e.g., for a period frequency of 400-800MHz, t CCD_S =1.25-2.5ns).

[0109] In the example access operation, four units of data (e.g., bytes, words, etc.) are transferred to or from the corresponding address lines in the corresponding memory banks 941-944. This is in Figure 9AThe diagram is illustrated by lines 961-964. A first data unit is transmitted between rows in segment 951 via data paths 961 and 935a. A second data unit is transmitted between rows in segment 953 via data path circuit 935b. A third data unit is transmitted between rows in segment 952 via data paths 962 and 935a. The third data unit is time-multiplexed with the first data unit on data path circuit 935a. A fourth data unit is transmitted between rows in segment 954 via data path 964. The fourth data unit is time-multiplexed with the second data unit on data path circuit 935b. Data path circuits 935a and 935b are operatively coupled to the input / output logic of memory component 900. Figure 9B The example in the document further illustrates the reuse of data going to / from segments 951-954.

[0110] Figure 9B This is a timing diagram illustrating memory bank group access. Figure 9B In the memory, memory cells 941-944 are clocked by signals CK-941 to CK-944 respectively. CK-942 is delayed by 180° compared to CK-941. CK-943 is delayed by 90° compared to CK-941. CK-944 is delayed by 270° compared to CK-941.

[0111] At the rising edge of CK-941, the first data unit is read from segment 951 via data path 961 and carried via data path circuit 935a. This is illustrated by arrows 901 and 902 respectively. At the next rising edge of CK-943, the second data unit is read from segment 953 via data path 963 and carried via data path circuit 935b. This is illustrated by arrows 904 and 905 respectively. At the next rising edge of CK-942, the third data unit is read from segment 952 via data path 962 and carried via data path circuit 935a. This is illustrated by arrows 907 and 908 respectively. At the next rising edge of CK-944, the fourth data unit is read from segment 954 via data path 964 and carried via data path circuit 935b. This is illustrated by arrows 910 and 911 respectively.

[0112] It should be understood that the data carried by data path circuits 935a and 935b can be transmitted through... Figure 9A Additional circuitry (e.g., data I / O circuitry such as data interface 424) not shown in the diagram may be used for further time multiplexing. This time multiplexing may result in the time being further multiplexed by t CCD_S The column-to-column latency visible to the managed storage controller.

[0113] Figure 10 This is a flowchart illustrating a method for operating a memory device using hierarchical memory bank timing. Figure 10 The steps illustrated can be performed by memory system 100 and / or its components. A first command (1002) is sent to the memory device to access a first bank of a first bank group that is a member of a first bank group cluster. For example, controller 110 can send a command to memory component 120 to access bank 151a of bank group 141, which is a member of bank group cluster 131a.

[0114] At least a first time interval after the first command is sent, a second command to access the first memory bank is sent to the memory device (1004). For example, at least t seconds after the first command to access memory bank 151a is sent... CCD_L Then, the controller 110 can send a second command to the memory component 120 to access the memory bank 151a.

[0115] A third command to access a memory bank of the first memory bank group is sent to the memory device (1006). For example, the controller 110 may send a command to the memory component 120 to access memory bank 151c of memory bank group 141, which is a member of memory bank group cluster 131a.

[0116] At least a second time interval after the third command is sent, a fourth command to access a fourth memory bank of a second memory bank group that is a member of the first memory bank group cluster is sent to the memory device (1008). For example, at least a second time interval after the third command to access memory bank 151c of the first memory bank group 141 is sent. CCD_M Subsequently, the controller 110 may send a fourth command to the memory component 120 to access the memory bank 152a of the memory bank group 142, which is the member group cluster 131a of the memory bank.

[0117] A fifth command to access a memory bank of the first memory bank group is sent to the memory device (1010). For example, the controller 110 may send a command to the memory component 120 to access memory bank 151a of memory bank group 141, which is a member of memory bank group cluster 131a. At least a third time interval after sending the fifth command, a sixth command is sent to the memory device (1012) to access the fifth memory bank of the third memory bank group, which is a member of the second memory bank group cluster. For example, at least a third time interval after sending the fifth command to access memory bank 151a of memory bank group 141 (which is a member of memory bank group cluster 131a)... CCD_S Subsequently, the controller 110 may send a sixth command to the memory component 120 to access memory bank 153a of memory bank group 143, which is a member of memory bank group cluster 131b.

[0118] Figure 11It is a flowchart illustrating a method for operating a memory device. Figure 11 The steps illustrated herein can be performed by memory system 100 and / or its components. A first command (1102) is sent to the memory device to access a first row in a first memory bank that is a member of a first memory bank group. For example, controller 410 may send a command to memory component 420 to access a row in segment 451a of memory bank 441, which is a member of memory bank group 431a.

[0119] At least a first time interval after the first command is sent, a second command to access a second row in the first memory bank is sent to the memory device (1104). For example, at least t seconds after the first command to access a row in segment 451a of memory bank 441 is sent. CCD_L Then, the controller 410 can send a second command to the memory component 420 to access a line in segment 451b of the memory bank 441.

[0120] A third command to access a row in the first memory bank is sent to the memory device (1106). For example, the controller 410 may send a command to the memory component 420 to access a row in segment 451a of memory bank 441.

[0121] At least a second time interval after the third command is sent, a fourth command to access a row of the second memory bank, which is a member of the first memory bank group, is sent to the memory device (1108). For example, at least t seconds after the third command to access a row in segment 451a of memory bank 441 is sent. CCD_M Subsequently, the controller 410 may send a fourth command to the memory component 420 to access a line in segment 452a of memory bank 442, which is a member of memory bank group 431a.

[0122] A fifth command to access a row of a memory bank in the first memory bank group is sent to the memory device (1110). For example, the controller 410 may send a command to the memory component 420 to access a row of a memory segment 451a of a memory bank 441 that is a member of memory bank group 431a. At least a third time interval after sending the fifth command, a sixth command to access a row of a memory bank in the second memory bank group is sent to the memory device (1112). For example, at least a third time interval after sending the fifth command to access a row of a memory segment 451a of a memory bank group 441 that is a member of memory bank group cluster 431a. CCD_S Subsequently, the controller 410 may send a sixth command to the memory component 420 to access a line in segment 453a of memory bank 443, which is a member of memory bank group 431b.

[0123] The methods, systems, and devices described above can be implemented or stored in a computer system. The methods described above can also be stored on a non-transitory computer-readable medium. The devices, circuits, and systems described herein can be implemented using computer-aided design tools available in the art and embodied in computer-readable documents describing software containing such circuits. This includes, but is not limited to, one or more elements of memory system 100, memory 300, memory system 400, memory component 600, memory component 700, memory component 800, memory component 900, and their components. These software descriptions can be descriptions at the behavioral, register transfer, logic component, transistor, and layout geometry levels. Furthermore, the software descriptions can be stored on a storage medium or communicated via a carrier wave.

[0124] Data formats that can implement such descriptions include, but are not limited to: formats supporting behavioral languages ​​(e.g., C), formats supporting register-transfer-level (RTL) languages ​​(e.g., Verilog and VHDL), formats supporting geometric description languages ​​(e.g., GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Furthermore, data transmission of such files on machine-readable media can be conducted electronically via various media on the Internet or, for example, via email. Note that physical files can be implemented on machine-readable media such as 4mm magnetic tape, 8mm magnetic tape, 3-1 / 2 inch floppy disk media, CDs, DVDs, etc.

[0125] Figure 12 This is a block diagram illustrating one embodiment of a processing system 1200 for including, processing, or generating circuit components 1220. The processing system 1200 includes one or more processors 1202, a memory 1204, and one or more communication devices 1206. The processors 1202, memory 1204, and communication devices 1206 communicate using wired and / or wireless connections 1208 of any suitable type, number, and / or configuration.

[0126] Processor 1202 executes instructions of one or more processes 1212 stored in memory 1204 to process and / or generate circuit components 1220 in response to user input 1214 and parameters 1216. Processes 1212 may be any suitable electronic design automation (EDA) tool or part thereof used to design, simulate, analyze, and / or verify electronic circuits and / or generate photomasks for electronic circuits. Representation 1220 includes data describing all or part of memory systems 100, 300, 400, 600, 700, 800, 900, and their components, as shown in the figures.

[0127] Representation 1220 may include one or more of behavior, register transfers, logic components, transistors, and layout geometry descriptions. Furthermore, representation 1220 may be stored on a storage medium or communicated via a carrier wave.

[0128] The data formats that can represent 1220 can include, but are not limited to: formats supporting behavioral languages ​​(such as C), formats supporting register-transfer level (RTL) languages ​​(such as Verilog and VHDL), formats supporting geometric description languages ​​(such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Furthermore, data transmission of such documents on machine-readable media can be carried out electronically via various media on the Internet or, for example, via email.

[0129] User input 1214 may include input parameters from a keyboard, mouse, voice recognition interface, microphone and speaker, graphics display, touchscreen, or other type of user interface device. The user interface may be distributed across multiple interface devices. Parameter 1216 may include specifications and / or characteristics input to help define representation 1220. For example, parameter 1216 may include information defining device type (e.g., NFET, PFET, etc.), topology (e.g., block diagram, circuit description, schematic, etc.), and / or device description (e.g., device attributes, device size, power supply voltage, simulation temperature, simulation model, etc.).

[0130] The memory 1204 includes any suitable type, quantity, and / or configuration of a non-transitory computer-readable storage medium for stored procedures 1212, user inputs 1214, parameters 1216, and circuit components 1220.

[0131] Communication device 1206 includes any suitable type, quantity, and / or configuration of wired and / or wireless devices that transmit information from processing system 1200 to another processing or storage system (not shown) and / or receive information from another processing or storage system (not shown). For example, communication device 1206 can transmit circuit component 1220 to another system. Communication device 1206 can receive process 1212, user input 1214, parameters 1216, and / or circuit component 1220 and store process 1212, user input 1214, parameters 1216, and / or circuit component 1220 in memory 1204.

[0132] The implementations discussed in this article include, but are not limited to, the following examples:

[0133] Example 1: A memory device includes: a plurality of memory bank clusters; each memory bank cluster includes a plurality of corresponding memory bank groups; each memory bank group includes a plurality of corresponding memory banks; wherein consecutive accesses to different memory banks that are members of the same memory bank group have a first command-to-command delay interval for a first type of command; consecutive accesses to memory banks that are members of different memory bank groups have a second command-to-command delay interval for a first type of command; and consecutive accesses to memory banks that are members of different memory bank clusters have a third command-to-command delay interval for a first type of command, wherein the first command-to-command delay interval, the second command-to-command delay interval, and the third command-to-command delay interval are not equal.

[0134] Example 2: The memory device of Example 1, wherein the delay interval between the first command and the command is greater than the delay interval between the second command and the command.

[0135] Example 3: The memory device of Example 1, wherein the delay interval between the second command and the command is greater than the delay interval between the third command and the command.

[0136] Example 4: The memory device of Example 1, wherein a first-level multiplexer function couples a first-level bus to a corresponding second-level bus, the first-level bus transfers data to the memory banks of a corresponding memory bank group, and the first-level bus operates at a first frequency.

[0137] Example 5: The memory device of Example 4, wherein the second-level multiplexer function is coupled with the second-level bus and the corresponding third-level bus, the second-level bus transmits data with the memory bank group of the corresponding memory bank group cluster, and the third-level bus operates at a third frequency.

[0138] Example 6: The memory device of Example 5, wherein the third frequency is greater than the first frequency.

[0139] Example 7: The memory device of Example 1, wherein multiple corresponding banks of a bank group are timed by clocks having the same frequency and different phase delays relative to each other.

[0140] Example 8: A memory controller includes: scheduling logic for issuing access to a memory device to a memory bank organized into at least a plurality of memory bank clusters, each memory bank cluster including a plurality of corresponding memory bank groups, wherein each memory bank group in each memory bank group includes a plurality of corresponding memory banks; and the scheduling logic for using a first delay interval for sequential commands of a first type addressed to a first memory bank that is a member of a different memory bank cluster, and using a second delay interval for sequential commands of the first type addressed to a memory bank that is both a member of the first memory bank cluster and a member of a different memory bank group of the first memory bank cluster.

[0141] Example 9: The memory controller of Example 8, wherein scheduling logic is used to assign a third delay interval to a first type of sequential command for addressing a second memory bank that is a member of a first memory bank group cluster.

[0142] Example 10: The memory controller of Example 8, wherein the first delay interval is less than the second delay interval.

[0143] Example 11: The memory controller of Example 10, wherein the second delay interval is less than the third delay interval.

[0144] Example 12: The memory controller of Example 8, wherein the scheduler is capable of issuing a command that causes multiple rows of the first memory bank of the first memory bank cluster to be opened simultaneously.

[0145] Example 13: The memory controller of Example 8 further includes: circuitry that associates a corresponding indicator with a corresponding row address segment of the first memory bank, the row address segment corresponding to a corresponding row address range.

[0146] Example 14: The memory controller of Example 13 further includes: circuitry for setting a corresponding indicator to a first value associated with a corresponding row address segment of a first memory bank, the corresponding row address segment being unusable to open a row in the associated corresponding row address range, wherein in response to at least the memory controller processing a command to the memory device to open a row in the corresponding row address range of the first memory bank, a plurality of corresponding indicators are set to the first value, wherein a row in the corresponding row address range of the first memory bank is associated with at least one of the plurality of corresponding indicators.

[0147] Example 15: A memory device comprising: a plurality of memory banks, each memory bank in the memory bank group including a plurality of corresponding memory banks; circuitry for receiving commands causing multiple rows of at least one memory bank to be opened simultaneously; wherein consecutive commands of a first type to memory banks that are members of different memory bank groups have a first delay interval; and consecutive commands of a first type to memory banks that are members of the same memory bank group have a second delay interval.

[0148] Example 16: The memory device of Example 15, wherein consecutive commands of a first type to the first open line of the memory bank and the second open line of the memory bank have a third delay interval.

[0149] Example 17: The memory device of Example 16, wherein the first delay interval, the second delay interval, and the third delay interval are not equal.

[0150] Example 18: The memory device of Example 17, wherein the first delay interval is less than the second delay interval.

[0151] Example 19: The memory device of Example 16, wherein the second delay interval is less than the third delay interval.

[0152] Example 20: The memory device of Example 19 further includes: circuitry for receiving a column access command, the column access command including information for selecting one of a plurality of simultaneously open rows in the memory device.

[0153] The foregoing description of the invention has been presented for illustrative and descriptive purposes. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed, and other modifications and variations are possible in accordance with the foregoing teachings. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to best utilize the invention in various embodiments and modifications suited to the particular intended use. Unless limited by the prior art, the appended claims are intended to be construed as including other alternative embodiments of the invention.

Claims

1. A memory device, comprising: Command / address interface for receiving access commands from external storage controller; Multiple storage units are clustered together; Each storage group cluster in the storage group cluster includes multiple corresponding storage groups; Each of the memory groups includes multiple corresponding memory groups; The sequential access commands of the first type of command that address different memory banks that are members of the same memory bank group have a first required command-to-command minimum delay interval for receiving the first type of command. The sequential access commands of the first type of command addressing to a memory bank that is a member of a different memory bank group have a second required command-to-command minimum delay interval for receiving the first type of command; as well as A series of access commands addressing a first type of memory bank that is a member of a different memory bank cluster have a third required command-to-command minimum latency interval for receiving the first type of command, wherein the first required command-to-command minimum latency interval, the second required command-to-command minimum latency interval, and the third required command-to-command minimum latency interval are all unequal.

2. The memory device of claim 1, wherein the first required command-to-command minimum latency interval is greater than the second required command-to-command minimum latency interval.

3. The memory device of claim 1, wherein the second required command-to-command delay interval is greater than the third required command-to-command delay interval.

4. The memory device of claim 1, wherein the first-level multiplexer function couples the first-level bus to a corresponding second-level bus, the first-level bus transmits data to the memory bank of the corresponding memory bank group, and the first-level bus operates at a first frequency.

5. The memory device of claim 4, wherein the second-level multiplexer function is coupled to the second-level bus and the corresponding third-level bus, the second-level bus transmitting data to the memory bank group of the corresponding memory bank group cluster, the third-level bus operating at a third frequency.

6. The memory device of claim 5, wherein the third frequency is greater than the first frequency.

7. The memory device of claim 1, wherein the plurality of respective memory banks of the memory bank group are timed by clocks having the same frequency and different phase delays relative to each other.

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