Method for improving read current stability in analog nonvolatile memories by screening memory cells

Abstract

The present invention discloses a memory device, which includes a plurality of non-volatile memory cells and a controller. The controller is configured to: erase the plurality of memory cells, program each of the memory cells, measure a threshold voltage corresponding to a target current passing through the memory cell applied to the memory cell in a first read operation for each of the memory cells, re-measure a threshold voltage corresponding to the target current passing through the memory cell applied to the memory cell in a second read operation, and identify the memory cell as defective if the difference between the measured threshold voltage and the re-measured threshold voltage exceeds a predetermined amount.

Description

[0001] Related patent applications

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 895,458, filed on September 3, 2019, and U.S. Patent Application No. 16 / 828,206, filed on March 24, 2020. Technical Field

[0003] The present invention relates to non-volatile memory devices, and more particularly to improving the stability of memory cell current during a read operation. Background Art

[0004] Non-volatile memory devices are well known in the art. See, for example, U.S. Pat. No. 7,868,375, which discloses a quad-gate memory cell configuration. Specifically, the present application Figure 1 A split gate memory cell 10 is shown having spaced-apart source and drain regions 14 and 16 formed in a silicon semiconductor substrate 12. The source region 14 may be referred to as a source line SL (because it is typically connected to other source regions of other memory cells in the same row or column), and the drain region 16 is typically connected to a bit line through a bit line contact 28. A channel region 18 of the substrate is defined between the source region 14 / drain region 16. A floating gate 20 is disposed over and insulated from (and controls the conductivity of) a first portion of the channel region 18 (and is partially disposed over and insulated from the source region 14). A control gate 22 is disposed over and insulated from the floating gate 20. A select gate 24 is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18. An erase gate 26 is disposed over and insulated from the source region 14 and is laterally adjacent to the floating gate 20. A plurality of such memory cells may be arranged in rows and columns to form a memory cell array.

[0005] Various combinations of voltages are applied to the control gate 22, the select gate 24, the erase gate 26, and / or the source and drain regions 14, 16 to program the memory cell (i.e., inject electrons into the floating gate), erase the memory cell (i.e., remove electrons from the floating gate), and read the memory cell (i.e., measure or detect the conductivity of the channel region 18 to determine the programmed state of the floating gate 20).

[0006] The memory cell 10 can be operated in a digital manner, where the memory cell is set to one of only two possible states (i.e., a programming state and an erased state). The memory cell is erased by placing a high positive voltage on the erase gate 26 and optionally a negative voltage on the control gate 22 to cause electrons to tunnel from the floating gate 20 to the erase gate 26 (putting the floating gate in a more positively charged state - the erased state). The memory cell 10 can be programmed by placing a positive voltage on the control gate 22, the erase gate 26, the select gate 24 and the source region 14 and placing a current on the drain region 16. The electrons will then flow from the drain region 16 to the source region 14 along the channel region 18, where the electrons become accelerated and heated, whereby some of them are injected onto the floating gate 20 by hot electron injection (putting the floating gate in a more negatively charged state - the programming state). The memory cell 10 can be read by placing a positive voltage on the select gate 24 (turning on the portion of the channel region below the select gate 24) and on the drain region 16 (and optionally on the erase gate 26 and / or control gate 22) and sensing the current flowing through the channel region 18. If the floating gate 20 is positively charged (the memory cell is erased), the memory cell will be turned on and current will flow from the source region 14 to the drain region 16 (i.e., the memory cell 10 is sensed to be in its erased "1" state based on the sensed current flow). If the floating gate 20 is negatively charged (the memory cell is programmed), the channel region below the floating gate is turned off, thereby preventing any current from flowing (i.e., the memory cell 10 is sensed to be in its programmed "0" state based on the absence of current flow).

[0007] Table 1 provides non-limiting examples of erase, program, and read voltages, where Vcc is the supply voltage or another positive voltage (such as 2.5V).

[0008] Table 1

[0009] WL(SG) BL (Drain) Source EG CG Erase 0V 0V 0V 11.5V 0V programming 1V 1μA 4.5V 4.5V 10.5V Read Vcc 0.6V 0V 0V Vcc

[0010] Alternatively, the memory cell 10 may be operated in an analog manner, where the storage state of the memory cell (i.e., the amount of charge on the floating gate, such as the number of electrons) may be continuously changed anywhere from a fully erased state (least electrons on the floating gate) to a fully programmed state (most electrons on the floating gate), or only a portion of this range. This means that the cell storage is analog, which allows very precise and individual tuning of each memory cell in the memory cell array. Alternatively, the memory may be operated as an MLC (multi-level cell), where it is configured to be programmed to one of many discrete values, such as 16 or 64 different values. In the case of analog or MLC programming, the programming voltage is applied only for a limited time or as a series of pulses until the desired programming state is reached. In the case of multiple programming pulses, intermediate read operations between programming pulses may be used to determine whether the desired programming state has been achieved (in which case programming stops) or has not yet been achieved (in which case programming continues).

[0011] Memory cells 10 operated in an analog manner or as MLCs may be more sensitive to noise and read current instabilities, which may adversely affect the accuracy of the memory device. One source of read current instabilities in analog non-volatile memory devices is the capture and emission of electrons at the gate oxide-channel interface by electron traps. The gate oxide is an insulating layer that separates the floating gate 20 and the channel region 18 of the substrate 12. When electrons are trapped on interface traps, they reduce the channel conductivity during a read operation and thus increase the threshold voltage Vt of the memory cell (i.e., the minimum voltage on the control gate required to turn on the channel region of the memory cell to produce a certain current level (e.g., 1 μA)). When the control gate voltage is equal to or higher than the threshold voltage, a conductive path is formed between the source region and the drain region. When the control gate voltage is below the threshold voltage, no conductive path is formed, and any source / drain current is considered to be subthreshold or leakage current. Electrons trapped on interface traps can be emitted from the trap, thereby reducing the Vt of the memory cell and thus increasing the channel conductivity during a read operation. These single electron events of electron capture and emission by traps appear as read current noise and are referred to elsewhere as random telegraph noise (RTN). Typically, the RTN produced by a single interface trap is characterized by two states: a lower Vt state (or higher read current state) when the electron is emitted from the trap and a higher Vt state (or lower read current state) when the electron is captured by the trap. As described above, the instability of a memory cell during a read can be characterized by a threshold voltage corresponding to a target current or by the memory cell current under given read voltage conditions. The preferred way to characterize memory cell read instability is the threshold voltage used in specific embodiments of the present invention.

[0012] There is a need to reduce RTN in analog and MLC non-volatile memory devices. Summary of the invention

[0013] The foregoing problems and needs are addressed by a memory device including a plurality of nonvolatile memory cells and a controller configured to: erase the plurality of memory cells, program each of the memory cells, and for each of the memory cells, measure a threshold voltage applied to the memory cell corresponding to a target current through the memory cell in a first read operation, re-measure a threshold voltage applied to the memory cell corresponding to the target current through the memory cell in a second read operation, and identify the memory cell as defective if the difference between the measured threshold voltage and the re-measured threshold voltage exceeds a predetermined amount.

[0014] The present invention discloses a memory device, which includes a plurality of non-volatile memory cells and a controller. The controller is configured to erase the plurality of memory cells, program each of the memory cells to a programming state corresponding to a predetermined threshold voltage of the memory cell, and then, for each of the memory cells, measure the current passing through the memory cell in a first read operation using a first read voltage applied to the memory cell, the first read voltage being offset from the predetermined threshold voltage by a positive offset value or a negative offset value; and if the current measured in the first read operation is lower than a reference current value or a reference current value range, if the offset value is positive, or if the measured current is higher than the reference current value or the reference current value range, if the offset value is negative, then the memory cell is identified as defective.

[0015] Other objects and features of the present invention will become apparent by examining the specification, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a side cross-sectional view of a memory cell of the prior art.

[0017] Figure 2 is a schematic diagram illustrating components of a memory device.

[0018] Figure 3 is a flow chart showing steps for identifying defective memory cells.

[0019] Figure 4 is a flow chart showing the steps for measuring Vtcg.

[0020] Figure 5 is a flow chart showing the steps of an alternative embodiment for identifying defective memory cells.

[0021] Figure 6 is a flow chart showing the steps of an alternative embodiment for identifying defective memory cells.

[0022] Figure 7 is a flow chart showing the steps of an alternative embodiment for identifying defective memory cells. DETAILED DESCRIPTION

[0023] The present invention is a method for stabilizing Figure 1 The technology of reading the current of the memory cell array of the type to improve the accuracy of the read operation and the memory retention life. The read stability technology involves analyzing the memory cell array to detect and screen out the memory cells in the memory array that exhibit an intolerable RTN level.

[0024] Read stability techniques implemented as part of the controller configuration of a memory array can be obtained from Figure 2 The architecture of the exemplary memory device shown is better understood. The memory device includes an array 50 of non-volatile memory cells 10, which can be separated into two separate planes (Plane A 52a and Plane B 52b). The memory cells 10 can be Figure 1 Memory cells of the type shown in the figure can be formed on a single chip and can be arranged in multiple rows and columns in the semiconductor substrate 12. Adjacent to the non-volatile memory cell array are address decoders (e.g., XDEC 54), source line drivers (e.g., SLDRV 56), column decoders (e.g., YMUX 58), high voltage row decoders (e.g., HVDEC 60), and bit line controllers (e.g., BLINHCTL 62), which are used to decode addresses and supply various voltages to various memory cell gates and regions during read, program, and erase operations of the selected memory cells. The column decoder 58 includes a sense amplifier that contains circuits for measuring current on the bit line during a read operation. The controller 66 (including control circuits) controls various device elements to implement each operation (program, erase, read) on the target memory cell. The charge pump CHRGPMP 64 provides various voltages for reading, programming, and erasing memory cells under the control of the controller 66. The controller 66 is configured to operate the memory device to program, erase, and read the memory cells 10. As part of these operations, access to incoming data (which is data to be programmed into the memory cells), as well as program, erase and read commands provided on the same or different lines, may be provided to the controller 66. Data read from the memory array is provided as outgoing data.

[0025] The read stability technique involves the controller 66 analyzing the memory cell array to detect and screen memory cells that exhibit an intolerable level of read current instability. This technique involves programming the memory cells and taking multiple measurements of the memory cell threshold voltage parameter (i.e., the minimum voltage applied to the memory cell to achieve a certain source / drain current level (referred to as the target current)). The preferred threshold voltage parameter is Vtcg, which is the threshold voltage of the memory cell as viewed from the control gate 22. Specifically, the control gate threshold voltage Vtcg is the voltage on the control gate that causes the channel region to become a conductive path when a read potential of a read operation is applied to the select gate 24 and the drain region 16, and thereby causes a predetermined amount of channel region current (I target ) treats the memory cell as being on (e.g., 1 μA). The control gate threshold voltage Vtcg will vary as a function of the programming state of the memory cell, but it is expected that once the memory cell is programmed to a particular programming state, any variation in Vtcg over time will be below a predetermined amount.

[0026] The first implementation of this technology is Figure 3 , and begins by erasing the memory cell 10 (step 1). Then (step 2), a programming operation is performed on all memory cells so that Vtcg is greater than the minimum level for a read operation (e.g., 0V) used by the controller 66 for all memory cells. In step 3, Vtcg is then measured two or more times for each cell (i.e., once in a read operation and remeasured at least once again in another read operation using the same read operation parameters). One way to measure Vtcg is to place a read potential on the select gate 24 and the drain region 16 (step 3a), and ramp the voltage on the control gate 22 up in amplitude until the current through the channel region 18 reaches a certain current level, such as 1 μA (i.e., Vtcg corresponds to I in a read operation). target )(Step 3b), such as Figure 4 As shown. The detected Vtcg value for each cell is analyzed to determine whether the fluctuation of Vtcg exceeds a predetermined maximum value ΔVtcg, such as 60mV. For example, it is determined whether the difference between the measured Vtcg and the remeasured Vtcg is greater than ΔVtcg. In step 4, the memory cell that exhibits a Vtcg fluctuation Δ exceeding Vtcg is identified as defective.

[0027] Once the memory cells are identified as defective, one option is to screen them out in any appropriate manner so that they are not used to store data during normal use in the future (step 5). For example, information identifying the screened out (defective) memory cells can be stored locally in the controller 66 or elsewhere in the memory device that can be accessed by the controller 66 (e.g., a lookup table stored in the memory array), and then the information is accessed and used by the controller during normal programming and read operations so that no future attempts will be made to store or read data in any defective memory cells (i.e., they are essentially removed from service as part of normal programming and read operations for storing data to and reading data from the memory cells). Another known screening technique that can be used with any of the embodiments herein is row redundancy or column redundancy, in which the memory array includes spare rows or columns of memory cells that are used to replace any rows or columns of memory cells that are found to contain defective memory cells. Any appropriate screening technique can be used to exclude the use of defective memory cells. Another option for screening defective memory cells is that they can be deeply programmed far beyond the selected MLC or analog operating range so that they do not have an effect on any detected cell current during operation of other memory cells in the same memory array (step 6). In this option, the addresses of the defective memory cells do not need to be permanently stored in any other storage device, but these cells will be erased each time before being simulated programmed with other memory cells. The controller can apply a corresponding read operation each time before erasing to locate the deeply programmed defective memory cells, and then deeply program them again after erasing and before simulation programming. Specifically, in order to distinguish between good cells and defective memory cells that are not used to store specific analog data (programmed to a Vtcg level above the user's operating range), good cells can be programmed to a lower Vtcg level than defective cells, but deep enough to exclude their effect on the read current. All of the screening options listed above can be applied individually and / or in any combination.

[0028] Alternative implementations of read stability techniques include Figure 5, and begins by erasing the memory cell 10 (step 1). Then (step 2), each memory cell is precisely programmed to a desired programming state exhibiting (i.e., corresponding to) a target control gate threshold voltage (Vtcg_target) (i.e., any predetermined threshold voltage, which voltage will then be used in subsequent steps described below). Then (step 3), each memory cell is read one or more times using a control gate voltage Vcg equal to Vtcg_target+ΔVcg (i.e., a control gate voltage offset from Vtcg_target by a predetermined positive offset value represented as ΔVcg), and compared with a reference current value (or otherwise, a target current value) or a reference (target) current value range, and those memory cells that exhibit a read current below the reference current value or reference current value range at least once are identified as defective. In one embodiment, the reference current value is 1 μA or a small range of 1 μA included in the definition of Vtcg_target as an example herein. As described above, during a read operation, Vcg is applied to the control gate, and a positive voltage is applied to each of the select gate and the drain region. When Vcg increases by ΔVcg, a stable memory cell will provide a current higher than a reference current value or a reference (target) current value range, and therefore when Vcg = Vcg_target + ΔVcg, the memory cell is screened out when it is at least once unstable enough to produce a current lower than the reference current value.

[0029] In step 4, each memory cell is read again one or more times using a Vcg equal to Vtcg_target-ΔVcg (i.e., a control gate voltage offset from Vtcg_target by a predetermined amount in a negative direction) and compared to a reference current value or reference current value range (such as 1 μA or a small range covering 1 μA), and those memory cells that exhibit a read current higher than the reference current value or reference current value range at least once are identified as defective. As described above, during the read operation, Vcg is applied to the control gate, and a positive voltage is applied to each of the select gate and drain region. When Vcg is reduced by ΔVcg, a stable memory cell will provide a current lower than the reference current value, and thus when Vcg=Vcg_target-ΔVcg, a memory cell is screened out when it is unstable enough to produce a current higher than the reference current value or reference (target) current value range at least once. Steps 3 and 4 can be performed in reverse order. Furthermore, for some applications, only one of step 3 or step 4 may be performed instead of both, but this option may not be as efficient. Finally, defective cells may optionally be screened out (step 5) and / or deep programmed (step 6), as described above. This alternative embodiment of the read stability technique is advantageous over the previous embodiment because it is fast, does not require a test memory to store the Vtcg data for each memory cell in the array, and can be designed with the aid of a logic data read sensing schematic commonly used for flash memory devices. In other words, memory cells with excessive read current instability will be screened out by the logic pass / fail criteria in a fast and efficient manner.

[0030] Figure 6 Another embodiment for identifying defective memory cells is shown, wherein Figure 3The method of adding an additional step of applying a voltage to the gate of the memory cell. With the aid of this modified method, a voltage is applied to one or more gates (e.g., control gate, erase gate, select gate) of the memory cell after programming the memory cell to Vtcg_target and before measuring Vtcg. Specifically, a positive voltage applied to the gate of the memory cell induces an electric field stress on the gate oxide of the memory cell, thereby stimulating electron capture on traps at the gate oxide-channel interface of the memory cell. Similarly, a negative voltage applied to the gate of the memory cell induces an electric field stress on the gate oxide of the memory cell, thereby stimulating electrons to escape from the interface traps. Therefore, for a memory cell with an interface trap that produces RTN, a positive voltage will stimulate the capture of electrons, setting Vtcg to a higher state. And conversely, a negative voltage will stimulate electrons to escape from the trap, setting Vtcg to a lower state. Since RTN has an unstable behavior, a defective memory cell may only maintain one Vtcg state during all read operations. In this case, it will not be screened. Therefore, applying a positive voltage (1V to 7V) and a negative voltage (-1V to -7V) before reading will stimulate a memory cell with RTN to exhibit two Vtcg states, thereby providing screening efficiency. There are some characteristic times during which the memory cell "records" the RTN state it acquired under the applied voltage. The delay between the voltage application and the read operation should not be longer than the typical electron capture and emission time (e.g., 100 milliseconds at room temperature), otherwise applying the voltage before the read operation will not be as effective. The voltage of each polarity can be applied once, followed by the corresponding read operation, such as Figure 6 As shown. The sequence of applying voltages of each polarity and then performing the corresponding read operation may also be used multiple times to improve screening efficiency. In addition, the polarity of the voltage may be reversed (ie, steps 3c / 3d may be performed before steps 3a / 3b).

[0031] Applying a voltage to the gate of a memory cell before a read operation can also be used as another embodiment of a method for identifying a defective memory cell, such as Figure 7 shown. Figure 7 Methods and Figure 5The method in is the same as in, except that a positive voltage is applied (step 3a) before reading at Vcg equal to Vtcg_target+ΔVcg (step 3b), and a negative voltage is applied (step 4a) before reading at Vcg equal to Vtcg_target-ΔVcg (step 4b). Reading at Vtcg_target+ΔVcg (step 3b) is intended to screen out cells that remain in a higher Vtcg state (when electrons are trapped on interface traps) during reading. In order to stimulate electrons to be trapped before reading, the applied voltage should have a positive polarity. And conversely, reading at Vtcg_target-ΔVcg (step 4b) is intended to screen out cells that remain in a lower Vtcg state (when electrons are emitted from interface traps) during reading. In order to stimulate electrons to be de-trapped before reading, the applied voltage should have a negative polarity. Steps 3 and 4 can be performed in the reverse order. As mentioned in the previous embodiment, the delay between voltage application and the read operation should not be longer than the typical electron capture and emission time (e.g., 100 milliseconds at room temperature), otherwise applying the voltage before the read operation will not be as effective. The voltage of each polarity can be applied once, and then the corresponding read operation is performed, such as Figure 7 As shown. The sequence of applying voltages of each polarity and then performing the corresponding read operation may also be used multiple times to improve screening efficiency. In addition, the polarity of the voltage may be reversed (ie, step 4a / 4b may be performed before step 3a / 3b).

[0032] It should be understood that the present invention is not limited to the embodiments described above and shown herein, but encompasses any and all variations that fall within the scope of any claims. For example, references to the present invention herein are not intended to limit the scope of any claim or claim term, but only to one or more features that may be covered by one or more of these claims. The examples of materials, processes, and numerical values ​​described above are merely exemplary and should not be construed as limiting the claims. In addition, as will be apparent from the claims and description, not all method steps need to be performed in the specific order shown or required (unless otherwise stated). A single layer of material may be formed into multiple layers of such material or similar materials, and vice versa. As used herein, the terms "forming" and "formed" shall include material deposition, material growth, or any other technique for providing the disclosed or claimed material. Finally, the present invention may be used in a process having a relatively Figure 1 The invention is implemented in a memory cell array having fewer gates (eg, no erase gates).

Claims

1. A memory device, comprising: a plurality of non-volatile memory cells; A controller, the controller being configured to: erasing the plurality of memory cells, programming each of the memory cells, For each of the memory cells: measuring a threshold voltage applied to the memory cell corresponding to a target current passing through the memory cell in a first read operation, re-measuring a threshold voltage applied to the memory cell corresponding to the target current through the memory cell in a second read operation, If the difference between the measured threshold voltage and the remeasured threshold voltage exceeds a predetermined amount, identifying the memory cell as defective, and The memory cells identified as defective are screened out so that the memory cells are not used to store data.

2. The apparatus of claim 1 , wherein each of the memory cells comprises: spaced-apart source and drain regions formed in a semiconductor substrate, wherein a channel region of the substrate extends between the source and drain regions, a floating gate vertically disposed above and insulated from a first portion of the channel region, a select gate vertically disposed above and insulated from the second portion of the channel region, and A control gate is vertically disposed above the floating gate and insulated from the floating gate.

3. The device of claim 2, wherein each of the memory cells further comprises: An erase gate is disposed above the source region and insulated from the source region.

4. The device of claim 2, wherein to measure the threshold voltage in the first read operation, the controller is configured to: applying a positive voltage to the select gate and the drain region; and A voltage that is ramped up in amplitude is applied to the control gate until the target current through the memory cell is reached.

5. The device according to claim 4, wherein in order to re-measure the threshold voltage in the second read operation, the controller is configured to: applying the positive voltage to the select gate and the drain region; and A voltage that is ramped up in amplitude is applied to the control gate until the target current through the memory cell is reached.

6. The apparatus of claim 2, wherein the measured threshold voltage and the remeasured threshold voltage are applied to the control gate for each of the memory cells.

7. The device of claim 1, wherein for each of the memory cells identified as defective, the controller is further configured to store information identifying the memory cell as defective in the memory device.

8. The apparatus of claim 1, wherein the controller is further configured to deeply program the memory cells identified as defective.

9. The apparatus of claim 1, wherein the controller is further configured to apply a positive voltage or a negative voltage to a gate of the memory cell after the programming of the memory cell and before the measuring and the re-measuring of the threshold voltage.

10. The device of claim 1 , wherein the controller is further configured to apply a positive voltage to the gate of the memory cell after the programming of the memory cell and before the measuring and the re-measuring of the threshold voltage, and wherein the controller is further configured to apply a negative voltage to the gate of the memory cell after the programming of the memory cell, and then for each of the memory cells: measuring a threshold voltage applied to the memory cell corresponding to a target current passing through the memory cell in a third read operation, re-measuring a threshold voltage applied to the memory cell corresponding to the target current through the memory cell in a fourth read operation, and If a difference between a threshold voltage measured in the third read operation and a threshold voltage re-measured in the fourth read operation exceeds a predetermined amount, the memory cell is identified as defective.

11. A memory device comprising: a plurality of non-volatile memory cells; A controller, the controller being configured to: erasing the plurality of memory cells, programming each of the memory cells to a programmed state corresponding to a predetermined threshold voltage of the memory cell, For each of the memory cells: measuring a current through the memory cell in a first read operation using a first read voltage applied to the memory cell, the first read voltage being offset from the predetermined threshold voltage by a positive offset value or a negative offset value; identifying the memory cell as defective if the current measured in the first read operation is below a reference current value or a reference current value range if the offset value is positive, or if the measured current is above the reference current value or the reference current value range if the offset value is negative; as well as The memory cells identified as defective are screened out so that the memory cells are not used to store data.

12. The apparatus of claim 11, wherein the offset value is a positive offset value, and wherein for each of the memory cells, if the current measured in the first read operation is below the reference current value or the reference current value range, the memory cell is identified as defective.

13. The apparatus of claim 12, wherein the controller is further configured to, for each of the memory cells: measuring a current through the memory cell in a second read operation using a second read voltage applied to the memory cell, the second read voltage being offset from the predetermined threshold voltage by a negative offset value; and If the current measured in the second read operation is higher than the reference current value or the reference current value range, the memory cell is identified as defective.

14. The apparatus of claim 11, wherein each of the memory cells comprises: spaced-apart source and drain regions formed in a semiconductor substrate, wherein a channel region of the substrate extends between the source and drain regions, a floating gate vertically disposed above and insulated from a first portion of the channel region, a select gate vertically disposed above and insulated from the second portion of the channel region, and A control gate is vertically disposed above the floating gate and insulated from the floating gate.

15. The apparatus of claim 14, wherein each of the memory cells further comprises: An erase gate is disposed above the source region and insulated from the source region.

16. The apparatus of claim 14, wherein during the first read operation, the controller is configured to: A positive voltage is applied to the select gate and the drain region.

17. The apparatus of claim 14, wherein the first read voltage is applied to the control gate in the read operation for each of the memory cells.

18. The device of claim 11, wherein for each of the memory cells identified as defective, the controller is further configured to store information identifying the memory cell as defective in the memory device.

19. The apparatus of claim 11, wherein the controller is further configured to deeply program the memory cells identified as defective.

20. The apparatus of claim 13, wherein the controller is further configured to: applying a positive voltage to a gate of the memory cell after the programming of the memory cell and before the first reading operation, and After the programming of the memory cell and before the second reading operation, a negative voltage is applied to the gate of the memory cell.

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