Memory device with dual transistor vertical memory cell and shared channel region

Abstract

Some embodiments include apparatuses and methods of forming the same. One of the apparatuses includes a first data line in a first level of the apparatus, a second data line in a second level of the apparatus, a first memory cell in a third level of the apparatus between the first level and the second level, the first memory cell including a first transistor coupled to the first data line and a second transistor coupled between the first data line and a charge storage structure of the first transistor, and a second memory cell in a fourth level of the apparatus between the first level and the second level, the second memory cell including a third transistor coupled to the second data line and a fourth transistor coupled between the second data line and a charge storage structure of the third transistor, the first transistor and the third transistor coupled in series between the first data line and the second data line.

Description

[0001] Priority Application

[0002] This application claims the priority benefit of U.S. Provisional Application No. 62 / 893,013, filed August 28, 2019, which is incorporated by reference herein in its entirety. BACKGROUND

[0003] Memory devices are widely used in computers and many other electronic appliances to store information. Memory devices are generally classified into two types: volatile memory devices and non-volatile memory devices. A memory device typically has a number of memory cells to store information. In a volatile memory device, the information stored in the memory cells is lost if the supply power is disconnected from the memory device. In a non-volatile memory device, the information stored in the memory cells remains even if the supply power is disconnected from the memory device.

[0004] The description herein relates to volatile memory devices. Most conventional volatile memory devices store information in the form of electric charges in a capacitor structure included in a memory cell. As the demand for device storage density increases, many conventional techniques provide a way to shrink the size of a memory cell in order to increase the device storage density of a given device area. However, if the memory cell size is to be shrunk to a certain size, physical limitations and manufacturing constraints can pose a challenge to such conventional techniques. Unlike some conventional memory devices, the memory devices described herein include features that can overcome the challenges faced by conventional techniques. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1 A block diagram of an apparatus in the form of a memory device including a volatile memory cell is shown in accordance with some embodiments described herein.

[0006] Figure 2 A schematic diagram of a portion of a memory device including a memory array of dual transistor (2T) memory cells is shown in accordance with some embodiments described herein.

[0007] Figure 3 A memory device of Figure 2 including example voltages used during a read operation of the memory device in accordance with some embodiments described herein.

[0008] Figure 4 A memory device of Figure 2 including example voltages used during a write operation of the memory device in accordance with some embodiments described herein.

[0009] Figure 5 andFigure 6 different views of structures of memory devices in accordance with some embodiments described herein. Figure 2 different views of structures of memory devices in accordance with some embodiments described herein.

[0010] Figures 7 to 18 processes of forming memory devices in accordance with some embodiments described herein. DETAILED DESCRIPTION

[0011] The memory devices described herein include volatile memory cells, where each of the memory cells can include two transistors (2T). One of the two transistors has a charge storage structure, which can form a memory element of the memory cell to store information. The memory devices described herein can have a structure that allows the size of the memory devices to be relatively smaller than the size of similar conventional memory devices (e.g., 4F2cell footprint). The memory devices described herein also include multiple memory cells stacked on top of each other. This can further allow the described memory devices to have a relatively higher storage density compared to some conventional volatile memory devices (e.g., dynamic random access memory (DRAM) devices). The described memory devices can include a single access line (e.g., word line) to control the two transistors of the memory cells. This can result in reduced power dissipation and improved processing. Reference is made below to Figures 1 to 18 Other improvements and benefits of the described memory devices and variations thereof are discussed.

[0012] Figure 1 A block diagram of an apparatus in the form of a memory device 100 including volatile memory cells is shown in accordance with some embodiments described herein. The memory device 100 includes a memory array 101, which can contain memory cells 102. The memory device 100 can include a volatile memory device, such that the memory cells 102 can be volatile memory cells. Examples of the memory device 100 include a DRAM device. If the supply power (e.g., supply voltage Vcc) is disconnected from the memory device 100, the information stored in the memory cells 102 of the memory device 100 can be lost (e.g., invalidated). In the following, the supply voltage Vcc is referred to as representing some voltage level; however, it is not limited to the supply voltage (e.g., Vcc) of a memory device (e.g., the memory device 100). For example, if the memory device (e.g., the memory device 100) has an internal voltage generator (not shown in FIG. 1) that generates an internal voltage based on the supply voltage Vcc, this internal voltage can be used instead of the supply voltage Vcc. Figure 1

[0013] ​In the physical structure of memory device 100, each of memory cells 102 can include transistors (e.g., two transistors) formed vertically (e.g., stacked on different layers) in different levels above a substrate (e.g., a semiconductor substrate) of memory device 100. Memory device 100 can also include multiple levels (e.g., multiple decks) of memory cells, where one level (e.g., one deck) of memory cells can be formed (e.g., stacked) above another level (e.g., another deck) of memory cells. The structure of memory array 101 including memory cells 102 can include structures described below with reference to Figures 2 to 18 memory arrays and memory cells.

[0014] As shown in Figure 1 Memory device 100 can include access lines 104 (e.g., “word lines”) and data lines (e.g., bit lines) 105. Memory device 100 can use signals on access lines 104 (e.g., word line signals) to access memory cells 102 and use signals on data lines 105 to provide information (e.g., data) to be stored (e.g., written) in memory cells 102 or read (e.g., sensed) from memory cells 102.

[0015] Memory device 100 can include address registers 106 to receive address information ADDR (e.g., row and column address signals) on lines (e.g., address lines) 107. Memory device 100 can include row access circuitry (e.g., X decoders) 108 and column access circuitry (e.g., Y decoders) 109 operable to decode address information ADDR from address registers 106. Based on the decoded address information, memory device 100 can determine which memory cells 102 are to be accessed during a memory operation. Memory device 100 can perform write operations to store information in memory cells 102 and read operations to read (e.g., sense) information (e.g., previously stored information) in memory cells 102. Memory device 100 can also perform operations (e.g., refresh operations) to refresh values of information stored in memory cells 102 (e.g., to keep the values valid). Each of memory cells 102 can be configured to store information that can represent a single bit (e.g., with a binary 0 (“0”) or a binary 1 (“1”)) or more than one bit (e.g., with a combination of at least two binary bits).

[0016] The memory device 100 can receive supply voltages, including supply voltages Vcc and Vss on lines 130 and 132, respectively. The supply voltage Vss can operate at a ground potential (e.g., have a value of approximately zero volts). The supply voltage Vcc can include an external voltage supplied to the memory device 100 from an external power source, such as a battery or an alternating current to direct current (AC to DC) converter circuitry.

[0017] As shown in Figure 1 The memory device 100 can include a memory control unit 118 that includes circuitry (e.g., hardware components) to control memory operations (e.g., read and write operations) of the memory device 100 based on control signals on lines (e.g., control lines) 120, as shown in

[0018] As shown in Figure 1 In a read operation, the values (e.g., “0” or “1”) of the information provided to the lines 112 (read from the memory cells 102) in the form of signals DQ0 through DQN can be based on the values of the signals on the data lines 105. In a write operation, the values (e.g., “0” or “1”) of the information provided to the data lines 105 (to be stored in the memory cells 102) can be based on the values of the signals DQ0 through DQN on the lines 112.

[0019] The memory device 100 can include sensing circuitry 103, selection circuitry 115, and input / output (I / O) circuitry 116. The column access circuitry 109 can selectively enable signals on lines (e.g., select lines) based on address signals ADDR. The selection circuitry 115 can respond to signals on the lines 114 to select signals on the data lines 105. The signals on the data lines 105 can represent values of information to be stored in the memory cells 102 (e.g., during a write operation) or values of information read (e.g., sensed) from the memory cells 102 (e.g., during a read operation).

[0020] I / O circuitry 116 is operable to provide information read from memory cells 102 to lines 112 (e.g., during a read operation), and to provide information from lines 112 (e.g., provided by an external device) to data lines 105 for storage in memory cells 102 (e.g., during a write operation). Lines 112 can include nodes within memory device 100 or pins (or solder balls) on a package in which memory device 100 can reside. Other devices external to memory device 100 (e.g., a hardware memory controller or a hardware processor) can communicate with memory device 100 via lines 107, 112, and 120.

[0021] Memory device 100 can include other components that are not shown in Figure 1 to confuse the example embodiments described herein. At least a portion of memory device 100 (e.g., a portion of memory array 101) can include structures and operations similar to or the same as any of the memory devices described below with reference to Figures 2 to 18 .

[0022] Figure 2 A schematic diagram of a portion of a memory device 200 including a memory array 201 of 2T memory cells is shown in accordance with some embodiments described herein. Memory device 200 can correspond to memory device 100 of Figure 1 . For example, memory array 201 can form a portion of memory array 101 of Figure 1 . As shown in Figure 2 , memory device 200 can include memory cells 210-217, which are volatile memory cells (e.g., DRAM cells). For simplicity, similar or identical elements among memory cells 210-217 are given the same label.

[0023] Each of memory cells 210 to 217 may include two transistors (e.g., a combination of transistors T1A and T2A or a combination of transistors T1B and T2B). Therefore, each of memory cells 210 to 217 may be referred to as a 2T memory cell (e.g., a 2T gain cell). Each of transistors T1A, T2A, T1B, and T2B may include a field-effect transistor (FET). As an example, each of transistors T1A and T1B may be a p-channel FET (PFET), and each of transistors T2A and T2B may be an n-channel FET (NFET). A portion of each of transistors T1A and T1B may include a p-channel metal-oxide-semiconductor (PMOS) transistor FET (PFET) structure. Therefore, each of transistors T1A and T1B may include operations similar to those of a PMOS transistor. A portion of each of transistors T2A and T2B may include an n-channel metal-oxide-semiconductor (NMOS) structure. Therefore, transistors T2A and T2B may include operations similar to those of an NMOS transistor.

[0024] Each of transistors T1A and T1B in memory device 200 may include a charge memory-based structure (e.g., based on a floating gate). Figure 2 As shown, each of memory cells 210 to 217 may include a charge storage structure 202, which may include a floating gate of transistor T1A or T1B. The charge storage structure 202 may form a memory element of a respective memory cell among memory cells 210 to 215. The charge storage structure 202 may store charge. The value of information (e.g., "0" or "1") stored in a particular memory cell among memory cells 210 to 217 may be based on the amount of charge in the charge storage structure 202 of that particular memory cell.

[0025] like Figure 2 As shown, the transistor T2A (or T2B) (e.g., the channel region of the transistor) of a specific memory cell among memory cells 210 to 217 can be electrically coupled (e.g., directly coupled to) the charge storage structure 202 of that specific memory cell. Therefore, during operation of the memory device 200 (e.g., a write operation), a circuit path (e.g., a current path) can be directly formed between the transistor T2A (or T2B) of the specific memory cell and the charge storage structure 202 of that specific memory cell.

[0026] Memory cells 210 to 217 may be arranged in memory cell groups 2010 and 2011. For example, memory cell group 2010 may include memory cells 210, 211, 214 and 215, and memory cell group 2011 may include memory cells 212, 213, 216 and 217.Figure 2 Two groups of memory cells (e.g., 2010 and 2011) are shown as examples. However, the memory device 200 can include more than two groups of memory cells.

[0027] Within each of the groups 2010 and 2011, the memory cells can form different pairs of memory cells (multiple pairs of memory cells) between pairs of data lines (two data lines). For example, the group 2010 can include two pairs of memory cells: a pair of memory cells (pair of memory cells) 210-211 (including memory cells 210 and 211) between data lines 221 and 221’ and a pair of memory cells (pair of memory cells) 214-215 (including memory cells 214 and 215) between data lines 221 and 221’. In another example, the group 2011 can include two pairs of memory cells: a pair of memory cells 212-213 (including memory cells 212 and 213) between data lines 222 and 222’ and a pair of memory cells 216-217 (including memory cells 216 and 217) between data lines 222 and 222’. The groups of memory cells 2010 and 2011 can include the same number of pairs of memory cells (e.g., the same number of memory cells). Figure 2 Two memory cells are shown in each of the groups of memory cells 2010 and 2011 as examples. However, the number of pairs of memory cells in the groups of memory cells 2010 and 2011 can be different than two.

[0028] The memory device 200 can perform write operations to store information in the memory cells 210-217 and read operations to read (e.g., sense) information from the memory cells 210-217. The memory device 200 can be configured to operate as a DRAM device. However, unlike some conventional DRAM devices that store information in structures of containers, such as capacitors, the memory device 200 can store information in the form of electrical charges in the charge storage structure 202, which can be a floating gate structure. As mentioned above, the charge storage structure 202 can be a floating gate of the transistor T1A (or T1B). During operation of the memory device 200 (e.g., read or write operations), an access line (e.g., a single access line) and a data line (e.g., a single data line) can be used to access a selected memory cell (e.g., a target memory cell).

[0029] As Figure 2As shown in the middle, the memory device 200 can include access lines (e.g., word lines) 241 A, 241 B, 242A, and 242B that can carry respective signals (e.g., word line signals) WL1A, WL1B, WL2A, and WL2B. The access lines 241 A, 241 B, 242A, and 242B can be used to access two groups of memory cells 2010 and 2011. Each of the access lines 241 A, 241 B, 242A, and 242B can be structured as at least one wire (one wire or multiple wires that can be electrically coupled (e.g., shorted) to each other). The access lines 241 A, 241 B, 242A, and 242B can be selectively activated during an operation (e.g., a read or write operation) of the memory device 200 to access a selected memory cell (or multiple selected memory cells) among the memory cells 210-217. The selected cell can be referred to as a target cell. In a read operation, information can be read from the selected memory cell (or multiple selected memory cells). In a write operation, information can be stored in the selected memory cell (or multiple selected memory cells).

[0030] In the memory device 200, a single access line (e.g., a single word line) can be used to control (e.g., turn on or off) the transistors (e.g., T1A and T2A or T1B and T2B) of a respective memory cell during a read or write operation of the memory device 200. Some conventional memory devices can use multiple (e.g., two separate) access lines to control access to a respective memory cell during read and write operations. In comparison to such conventional memory devices (using multiple access lines for the same memory cell), the memory device 200 uses a single access line (e.g., a shared access line) in the memory device 200 to control two transistors (e.g., T1A and T2A or T1B and T2B) of a respective memory cell to access the respective memory cell. This technique can save space and simplify the operation of the memory device 200. In addition, as Figure 2 As shown in the middle, two memory cells (e.g., memory cells 210 and 211) can be coupled in series between a pair of data lines (e.g., data lines 221 and 221’).

[0031] In the memory device 200, the gate of each of the transistors T1A, T2A, T2A, and T2B can be part of a respective access line (e.g., a respective word line). As Figure 2As shown in the middle, the gate of each of the transistors TIA and T2A of the memory cell 210 can be part of the access line 241 A. The gate of each of the transistors TIB and T2B of the memory cell 211 can be part of the access line 241B. For example, in the structure of the memory device 200, different portions of the conductive material (or materials) that form the access line 241 A can form the gates (e.g., two gates) of the transistors TIA and T2A of the memory cell 210. In another example, the conductive material (or materials) that form the access line 241B can form the gates (e.g., two gates) of the transistors TIB and T2B of the memory cell 211. Similarly, the gates of the transistors to each of the other memory cells (e.g., memory cells 212-217) can be part of the respective access lines.

[0032] As described above, the memory device 200 can include data lines (e.g., bit lines) 221, 221’, 222, and 222’. The data lines 221 and 221’ can be referred to as a data line pair. The data lines 222 and 222’ can be referred to as a data line pair. The data lines 221 and 221’ can carry respective signals (e.g., bit line signals) BL1 and BL1’. The data lines 222 and 222’ can carry respective signals (e.g., bit line signals) BL2 and BL2’. During a read operation, the memory device 200 can use the data lines 221 and 221’ to obtain information read (e.g., sensed) from selected memory cells of the memory cell group 2010, and use the data lines 222 and 222’ to read information from selected memory cells of the memory cell group 2011. During a write operation, the memory device 200 can use the data lines 221 and 221’ to provide information to be stored in selected memory cells of the memory cell group 2010, and use the data lines 222 and 222’ to provide information to be stored in selected memory cells of the memory cell group 2011.

[0033] In the description herein, a memory cell pair refers to two adjacent memory cells each coupled in series between a pair of data lines (e.g., a pair of bit lines). A pair of data lines refers to two data lines of a memory cell group (e.g., group 2010 or 2011). For example, the data lines 221 and 221’ (or 222 and 222’) form a pair of data lines. For example, in the structure of the memory device 200, the data lines 221 and 221’ form a pair of data lines. In another example, in the structure of the memory device 200, the data lines 222 and 222’ form a pair of data lines. Figure 2 In the middle, the memory cells 210 and 211 form a memory cell pair.

[0034] As described above, the memory device 200 can include data lines (e.g., bit lines) 221, 221’, 222, and 222’. The data lines 221 and 221’ can be referred to as a data line pair. The data lines 222 and 222’ can be referred to as a data line pair. The data lines 221 and 221’ can carry respective signals (e.g., bit line signals) BL1 and BL1’. The data lines 222 and 222’ can carry respective signals (e.g., bit line signals) BL2 and BL2’. During a read operation, the memory device 200 can use the data lines 221 and 221’ to obtain information read (e.g., sensed) from selected memory cells of the memory cell group 2010, and use the data lines 222 and 222’ to read information from selected memory cells of the memory cell group 2011. During a write operation, the memory device 200 can use the data lines 221 and 221’ to provide information to be stored in selected memory cells of the memory cell group 2010, and use the data lines 222 and 222’ to provide information to be stored in selected memory cells of the memory cell group 2011. Figure 2As shown in the middle, the transistors T1A and T1B (e.g., the channel regions of the transistors T1A and T1B) of a pair of memory cells (e.g., memory cells 210 and 211) can be coupled in series with each other and can be electrically coupled to (e.g., directly coupled to) the pair of data lines 221 and 221’. During an operation (e.g., a read operation) performed on a selected memory cell, a circuit path (e.g., a current path) can be formed between the pair of data lines (e.g., data lines 221 and 221’) via the transistors T1A and T1B of the pair of memory cells that includes the selected memory cell. Thus, the transistors T1A and T1B of the pair of memory cells can share the circuit path between the pair of data lines (e.g., share a read channel region).

[0035] The memory device 200 can include a read path (e.g., a circuit path). Information read from a selected memory cell during a read operation can be obtained via the read path coupled to the selected memory cell. In the memory cell group 2010, the read path of a particular memory cell (e.g., memory cell 210) of a pair of memory cells (e.g., memory cells 210 and 211) can include a current path (e.g., a read current path) between the data lines (pair of data lines) 221 and 221’ via the channel region of the particular memory cell (e.g., memory cell 210) and the channel of another memory cell (e.g., memory cell 211) of the pair of memory cells. Similarly, in the memory cell group 2011, the read path of a particular memory cell (e.g., memory cell 212) of a pair of memory cells (e.g., memory cells 212 and 213) can include a current path (e.g., a read current path) between the data lines (pair of data lines) 222 and 222’ via the channel region of the particular memory cell (e.g., memory cell 212) and the channel of another memory cell (e.g., memory cell 213) of the pair of memory cells.

[0036] In instances where each of the transistors T1A and T1B is a PFET (e.g., a PMOS), the current in the read path (during a read operation) can include hole conduction (e.g., hole conduction in a direction from data line 221 to data line 221’) via the channel regions of the transistors T1A and T1B. Since each of the transistors T1A and T1B can be used in the read path to read information from the respective memory cell during a read operation, each of the transistors T1A and T1B can be referred to as a read transistor, and the channel region of each of the transistors T1A and T1B can be referred to as a read channel region.

[0037] Memory device 200 can include write paths (e.g., circuit paths). Information to be stored in a selected memory cell during a write operation can be provided to the selected memory cell via a write path coupled to the selected memory cell. In memory cell group 2010, a write path for a particular memory cell can include transistor T2A or T2B (e.g., can include a write current path through a channel region of transistor T2A or T2B) of the particular memory cell and a respective data line (e.g., data line 221 or 221’) coupled to the particular memory cell. Similarly, in memory cell group 2011, a write path for a particular memory cell can include transistor T2A or T2B (e.g., can include a write current path through a channel region of transistor T2A or T2B) of the particular memory cell and a respective data line (e.g., data line 222 or 222’).

[0038] In examples where transistors T2A and T2B are NFETs (e.g., NMOS), current in a write path through a channel region of transistor T2A of a selected memory cell (e.g., during a write operation) can include electron conduction through the channel region of transistor T2A of the selected memory cell. Current in a write path through a channel region of transistor T2B of the selected memory cell (e.g., during a write operation) can include electron conduction through the channel region of transistor T2B of the selected memory cell. The direction of electron conduction can be from a data line coupled to the selected memory cell to the charge storage structure 202 of the selected memory cell 211. Since each of transistors T2A and T2B can be used in a write path to store information in a respective memory cell during a write operation, each of transistors T2A and T2B can be referred to as a write transistor, and a channel region of each of transistors T2A and T2B can be referred to as a write channel region.

[0039] Each of the transistors T1A, T1B, T2A, and T2B can have a threshold voltage (Vt). Each of the transistors (e.g., read transistors) T1A and T1B has a threshold voltage Vti. Each of the transistors (e.g., write transistors) T2A and T2B has a threshold voltage Vt2. The values of the threshold voltages Vti and Vt2 can be different (unequal). For example, the value of the threshold voltage Vt2 can be greater than the value of the threshold voltage Vti. The difference in the values of the threshold voltages Vti and Vt2 allows information stored in the charge storage structure 202 of the read transistor (e.g., transistor T1A or T1B) of a selected memory cell T1 on the read path to be read (e.g., sensed) during a read operation without affecting (e.g., turning on) the write transistor (e.g., transistor T2A or T2B) of the selected memory cell on the write path. This can prevent leakage of charge from the charge storage structure 202 through the write transistor of the write path (e.g., during a read operation).

[0040] In a structure of the memory device 200, the read transistors (e.g., T1A and T1B) and the write transistors (e.g., T2A and T2B) can be formed (e.g., engineered) such that the threshold voltage Vti of the read transistors can be less than zero volts (e.g., Vti < 0 V) regardless of the value (e.g., “0” or “1”) of the information stored in the charge storage structure 202 of the read transistor, and Vti < Vt2. When the information having the value “0” is stored in the charge storage structure 202, the charge storage structure 202 can be in state “0”. When the information having the value “1” is stored in the charge storage structure 202, the charge storage structure 202 can be in state “1”. Thus, in this structure, the relationship between the values of the threshold voltages Vti and Vt2 can be expressed as follows: Vti for state “0” < Vti for state “1” < 0 V, and Vt2 = 0 V (or alternatively, Vt2 > 0 V).

[0041] In an alternative structure of the memory device 200, the read transistors (e.g., T1A and T1B) and the write transistors (e.g., T2A and T2B) can be formed (e.g., engineered) such that Vti for state “0” < Vti for state “1”, where Vti for state “0” < 0 V (or alternatively, Vti for state “0” = 0 V), Vti for state “1” > 0 V, and Vti < Vt2.

[0042] In another alternative structure, the read transistors (e.g., TIA and TIB) and the write transistors (e.g., T2A and T2B) can be formed (e.g., engineered) such that Vti (for state "0") < Vti (for state "1"), where Vti for state "0" = 0 V (or alternatively, Vti for state "0" > 0 V) and Vti < Vt2.

[0043] During a read operation of the memory device 200, only one memory cell of the same memory cell group can be selected at a time to read information from the selected memory cell. For example, the memory cells 210, 211, 214, and 215 of the memory cell group 2010 can be selected one at a time during a read operation to read information from a selected memory cell (e.g., one of the memory cells 210, 211, 214, and 215 in this example). In another example, the memory cells 212, 213, 216, and 217 of the memory cell group 2011 can be selected one at a time during a read operation to read information from a selected memory cell (e.g., one of the memory cells 212, 213, 216, and 217 in this example). Thus, in a read operation, only one memory of a memory cell pair of a memory cell group can be a selected memory cell at a given time.

[0044] During a read operation, memory cell pairs of different memory cell groups (e.g., memory cell groups 2010 and 2011) that share the same access line can be selected (or alternatively, can be selected sequentially) at the same time, and only one memory cell of the memory cell pair can be a selected memory cell. For example, one of the memory cells 210 and 211 (e.g., memory cell 210) and one of the memory cells 212 and 213 (e.g., memory cell 212) can be selected at the same time during a read operation to read (e.g., simultaneously read) information from the two selected memory cells (e.g., memory cells 210 and 212). In another example, one of the memory cells 214 and 215 (e.g., memory cell 215) and one of the memory cells 216 and 217 (e.g., memory cell 217) can be selected at the same time during a read operation to read (e.g., simultaneously read) information from the two selected memory cells (e.g., memory cells 215 and 217).

[0045] As described above, during a read operation of the memory device 200, only one memory cell of a memory cell pair is a selected memory cell, and the other memory cell of the memory cell pair can be an unselected memory cell. The read transistor (e.g., transistor T1A or T1B) of the unselected memory cell can be turned on to operate as a pass transistor (turn-on switch). This allows a conduction current (e.g., a read current) between the pair of data lines to be coupled to the selected memory cell.

[0046] The value of the information read from the selected memory cell of the selected memory cell pair of the memory cell group 2010 during a read operation can be determined based on the value of the current (e.g., read current) detected (e.g., sensed) from the read path (described above) that includes the read transistors (e.g., transistors T1A and T1B) of the memory cell pair and the data lines 221 and 221’. In the memory cell group 2011, the value of the information read from the selected memory cell of the selected memory cell pair during a read operation can be determined based on the value of the current (e.g., read current) detected (e.g., sensed) from the read path (described above) that includes the read transistors (e.g., transistors T1A and T1B) of the memory cell pair and the data lines 222 and 222’.

[0047] The memory device 200 can include detection circuitry (not shown) that can operate during a read operation to detect (e.g., sense) a current (e.g., current II, not shown) on the read path that includes the data lines 221 and 221’, and to detect a current (e.g., current I2, not shown) on the read path that includes the data lines 222 and 222’. The value of the detected current can be based on the value of the information stored in the selected memory cell. For example, depending on the value of the information stored in the selected memory cell of the memory cell group 2010, the value of the detected current on the data line 221 (e.g., the value of the current II) can be zero or greater than zero. Similarly, depending on the value of the information stored in the selected memory cell of the memory cell group 2011, the value of the detected current between the data lines 222 (e.g., the value of the current I2) can be zero or greater than zero. The memory device 200 can include circuitry (not shown) to translate the value of the detected current to the value of the information (e.g., “0”, “1”, or a combination of multi-bit values) stored in the selected memory cell.

[0048] During a write operation of the memory device 200, only one memory cell of the same memory cell group can be selected at a time to write information into the selected memory cell. For example, the memory cells 210, 211, 214, and 215 of the memory cell group 2010 can be selected one at a time during a write operation to store in a selected memory cell (e.g., one of the memory cells 210, 211, 214, and 215 in this example). In another example, the memory cells 212, 213, 216, and 217 of the memory cell group 2011 can be selected one at a time during a write operation to store in a selected memory cell (e.g., one of the memory cells 212, 213, 216, and 217 in this example). Thus, in a write operation, only one memory of a memory cell pair of a memory cell group can be a selected memory cell at a given time.

[0049] During a write operation, memory cell pairs of different memory cell groups (e.g., memory cell groups 2010 and 2011) that share the same access line can be selected simultaneously (or alternatively, can be selected sequentially), and only one memory cell of the selected memory cell pair can be a selected memory cell. For example, one of the memory cells 210 and 211 (e.g., memory cell 210) and one of the memory cells 212 and 213 (e.g., memory cell 212) can be selected simultaneously (e.g., to store information (e.g., memory cells 210 and 212) during a write operation. In another example, one of the memory cells 214 and 215 (e.g., memory cell 215) and one of the memory cells 216 and 217 (e.g., memory cell 217) can be selected simultaneously (e.g., to store information from two selected memory cells (e.g., memory cells 215 and 217) during a write operation.

[0050] Information to be stored in a selected memory cell of the memory cell group 2010 during a write operation can be provided via a write path (described above) that includes a data line (data line 221 or 221') and a write transistor (e.g., transistor T2A or T2B) of the selected memory cell. For example, information to be stored in the memory cell 210 (e.g., a selected memory cell) during a write operation can be provided via the data line 221 and the transistor T2A of the memory cell 210. In another example, information to be stored in the memory cell 211 (e.g., a selected memory cell) during a write operation can be provided via the data line 221' and the transistor T2B of the memory cell 211. As described above, the value (e.g., binary value) of the information stored in a particular memory cell among the memory cells 210-217 can be based on the amount of charge in the charge storage structure 202 of the particular memory cell.

[0051] In a write operation, the amount of charge in the charge storage structure 202 of a selected memory cell can be changed (to reflect the value of the information stored in the selected memory cell) by applying a voltage on a write path that includes the transistor T2A or T2B of the particular memory cell and a data line (e.g., data line 221, 221', 222, or 222') coupled to the particular memory cell. For example, if the information to be stored in a selected memory cell (e.g., memory cell 210 or 214) coupled to the data line 221 has one value (e.g., "0"), a voltage having the one value (e.g., 0 V) can be applied on the data line 221 (e.g., 0 V is provided to the signal BL1). In another example, if the information to be stored in a selected memory cell (e.g., memory cell 210 or 214) coupled to the data line 221 has another value (e.g., "1"), a voltage having the other value (e.g., a positive voltage) can be applied on the data line 221 (e.g., a positive voltage is provided to the signal BL1). Thus, information can be stored (e.g., directly stored) in the charge storage structure 202 of a particular memory cell by providing the information to be stored (e.g., in the form of a voltage) on the write path (including the transistor T2A or T2B) of the particular memory cell.

[0052] In the memory device 200 (shown in FIG. 2A), the memory cells 210-217 can be programmed (e.g., directly programmed) by providing information to be stored in the memory cells 210-217 via the write path (e.g., the data line 221 and the transistor T2A of the memory cell 210) and the read path (e.g., the data line 222 and the transistor TlA of the memory cell 210). For example, information to be stored in the memory cell 210 (e.g., a selected memory cell) can be provided via the data line 221 and the transistor T2A of the memory cell 210. In another example, information to be stored in the memory cell 211 (e.g., a selected memory cell) can be provided via the data line 221' and the transistor T2B of the memory cell 211. As described above, the value (e.g., binary value) of the information stored in a particular memory cell among the memory cells 210-217 can be based on the amount of charge in the charge storage structure 202 of the particular memory cell. Figure 5 and Figure 6In the physical structure of the memory device 200, the read transistors (e.g., transistors T1A and T1B) of each memory cell pair may have a shared read path (e.g., a shared read channel region) between the corresponding data line pairs. For example, transistors T1A and T1B of memory cells 210 and 211 may each have a shared read path (e.g., a shared read channel region) between data lines 221 and 221'. In another example, transistors T1A and T1B of memory cells 212 and 213 may each have a shared read path (e.g., a shared read channel region) between data lines 222 and 222'. This arrangement (e.g., the shared read channel region) allows the memory device 200 to include multiple memory cells directly between data line pairs. Therefore, more than one information bit (e.g., two data bits) can be stored in the memory cell region (which contains the memory cell pair) directly between the data line pairs. Therefore, compared to some conventional memory devices (e.g., DRAM devices where one bit of information is stored in a memory cell directly coupled between two data lines), memory device 200 can have a higher density for a given device area (e.g., given device area).

[0053] Figure 3 Demonstrating some embodiments according to the description herein Figure 2 The memory device 200 includes instance voltages V0, V1, V2, V3, V4 and V5 used during read operations of the memory device 200. Figure 3 The example assumes that memory cells 210 and 212 are selected memory cells (e.g., target memory cells) during a read operation to read (e.g., sense) information stored (e.g., previously stored) in memory cells 210 and 212. It is assumed that memory cells 214 to 217 are unselected memory cells. This means that in Figure 3 In this example, memory cells 214 to 217 are not accessed, and the information stored in memory cells 214 to 217 is not read, but information is read from memory cells 210 and 212.

[0054] exist Figure 3In this example, voltages V0, V1, V2, V3, V4, and V5 can represent different voltages applied to respective access lines 241A, 241B, 242A, 242B, and data lines 221, 221', 222, and 222' during a read operation of memory device 200. Voltage V0 can be 0 V (e.g., a ground potential). Voltage V5 can have a value greater than that of voltage V0. Each of voltages V3 and V4 can have a value such that transistors T1A, T1B, T2A, and T2B of each of memory cells 214-217 (unselected memory cells in this example) can be turned off (e.g., disabled). Voltage V1 can have a value to turn off (or disable) transistor T2B (e.g., a write transistor) of each of memory cells 210 and 212.

[0055] The value of voltage V1 can also be selected such that transistor T1A (e.g., a read transistor) of each of memory cells 210 and 212 (selected memory cells in this example) can be turned on. Voltage V2 can have a value such that transistor T1B (e.g., a read transistor) of each of memory cells 211 and 213 (unselected memory cells in this example) can be turned on to operate as a pass-through transistor (e.g., to conduct current). Voltage V5 can have a value greater than that of voltage V0 such that current paths can be formed between data lines 221 and 221' via transistors T1A and T1B of memory cells 210 and 211, respectively, and current paths can be formed between data lines 222 and 222' via transistors T1A and T1B of memory cells 212 and 213, respectively.

[0056] Voltage V3 can have a value such that current (e.g., a read current) can be formed on a read path between data lines 221 and 221' (via transistors T1A and T1B of memory cells 210 and 211, respectively), and another current can be formed on a read path (a separate read path) between data lines 222 and 222' (via transistors T1A and T1B of memory cells 212 and 213, respectively). This allows for detection of the current on the read paths coupled to memory cells 210 and 212, respectively. Detection circuitry (not shown) of memory device 200 can be operable to translate the value of the detected current (during reading of information from the selected memory cells) to a value of the information read from the selected memory cells (e.g., a "0," a "1," or a combination of multi-bit values). In Figure 3 In this example, the value of the detected current on the read path between data lines 221 and 221' and the read path between data lines 222 and 222' can be translated to a value of the information read from memory cells 210 and 211, respectively.

[0057] Figure 4 A memory device 200 according to some embodiments described herein is shown.Figure 2 The memory device 200 includes example voltages V6-V13 used during a write operation of the memory device 200. Figure 4 The example assumes that the memory cells 210 and 212 are selected memory cells (e.g., target memory cells) during a write operation to store information in the memory cells 210 and 212. The memory cells 211, 213, 214, 215, 216, and 217 are assumed to be unselected memory cells. This means that the memory cells 211, 213, 214, 215, 216, and 217 are not accessed and information is not stored in the memory cells 211, 213, 214, 215, 216, and 217 while information is stored in the memory cells 210 and 212. Figure 4 In the example of the memory device 200, the memory cells 211, 213, 214, 215, 216, and 217 are not accessed and information is not stored in the memory cells 211, 213, 214, 215, 216, and 217 while information is stored in the memory cells 210 and 212.

[0058] In the example of the memory device 200, the memory cells 211, 213, 214, 215, 216, and 217 are not accessed and information is not stored in the memory cells 211, 213, 214, 215, 216, and 217 while information is stored in the memory cells 210 and 212. Figure 4 In the example of the memory device 200, the memory cells 211, 213, 214, 215, 216, and 217 are not accessed and information is not stored in the memory cells 211, 213, 214, 215, 216, and 217 while information is stored in the memory cells 210 and 212. Figure 4 In the example of the memory device 200, the memory cells 211, 213, 214, 215, 216, and 217 are not accessed and information is not stored in the memory cells 211, 213, 214, 215, 216, and 217 while information is stored in the memory cells 210 and 212.

[0059] At the data lines 221, 221', 222, and 222', each of the voltages V11 and V13 can have a value of 0 V (e.g., a ground potential). Depending on the values of the information to be stored in the memory cells 210 and 212 (e.g., "0" or "1"), the voltages V10 and V12 can be the same or different. For example, if the memory cells 210 and 211 are to store information having the same value, the values of the voltages V6 and V7 can be the same (e.g., V6 = V7). In another example, if the memory cells 210 and 211 are to store information having different values, the values of the voltages V6 and V7 can be different (e.g., V6 ≠ V7).

[0060] In an example write operation, a write path can be formed between the charge storage structure 202 of the memory cell 210 and the data line 221, and a write path can be formed between the charge storage structure 202 of the memory cell 212 and the data line 222. A current (e.g., a write current) can be formed between the charge storage structure 202 of the memory cell 210 and the data line 221. This current can affect (e.g., change) the amount of charge on the charge storage structure 202 of the memory cell 210 to reflect a value of information to be stored in the memory cell 210. A current (e.g., another write current) can be formed between the charge storage structure 202 of the memory cell 212 and the data line 222. This current can affect (e.g., change) the amount of charge on the charge storage structure 202 of the memory cell 212 to reflect a value of information to be stored in the memory cell 212.

[0061] In Figure 4 an example write operation of the memory device 200, the value of the voltage V10 can cause the charge storage structure 202 of the memory cell 210 to discharge or be charged such that the resulting charge (e.g., the charge remaining after the discharging or charging action) on the charge storage structure 202 of the memory cell 210 can reflect a value of information stored in the memory cell 210. Similarly, in this example, the value of the voltage V12 can cause the charge storage structure 202 of the memory cell 212 to discharge or be charged such that the resulting charge (e.g., the charge remaining after the discharging or charging action) on the charge storage structure 202 of the memory cell 212 can reflect a value of information stored in the memory cell 211.

[0062] Figure 5 and Figure 6 different views of the structure of the memory device 200 are shown relative to the X, Y, and Z directions in accordance with some embodiments described herein. Figure 2 different views of the structure of the memory device 200 are shown relative to the X, Y, and Z directions in accordance with some embodiments described herein. Figure 5 a side view (e.g., cross-sectional view) of the memory device 200 is shown relative to the X-Z direction. Figure 6 another view (e.g., cross-sectional view) is shown taken along line 6-6 of Figure 5 another view (e.g., cross-sectional view) is shown taken along line 6-6 of

[0063] For simplicity, Figure 5 and Figure 6 the description focuses on the structure of the memory cells 210 and 211 (the pair of memory cells 210-211). Figure 2 the structure of other memory cells (e.g., the pair of memory cells 212-213 in Figure 5 the pair of memory cells 214-215 in Figure 6 the pair of memory cells 214-215 in Figure 5 the pair of memory cells 214-215 in Figure 6The structures of memory cells 210 and 211 shown in Figure 5 and Figure 6 (illustrating the physical structure of memory device 200) and Figure 2 (illustrating memory device 200 in circuit schematic form) are the same elements are given the same reference numbers.

[0064] The following description refers to Figure 5 and Figure 6 . For simplicity, detailed descriptions of the same elements are not repeated in the description of Figure 5 and Figure 6 . Also for simplicity, cross-sectional lines (e.g., hatching) are omitted from most of the elements shown in Figure 5 and Figure 6 as well as other figures in the drawings described herein (e.g., Figure 7 to 18 ). Some elements of memory device 200 (e.g., portions of structures) can be omitted from a particular figure of the drawings in order not to obscure the descriptions of elements being presented in that particular figure. The dimensions of elements in the figures described herein (e.g., Figures 5 to 16 ) are not necessarily to scale.

[0065] As shown in Figure 5 and Figure 6 , memory device 200 can include a substrate 599. Memory cells 210 and 211 can be formed over (e.g., vertically formed with respect to) different levels (e.g., tiers) of memory device 200 over substrate 599. Memory cells 212 and 213 can be formed over (e.g., vertically formed with respect to) different levels (e.g., tiers) of memory device 200 over substrate 599. Substrate 599 can be a semiconductor substrate (e.g., a silicon-based substrate) or other type of substrate. The Z-direction can be a direction perpendicular to substrate 599 (e.g., a vertical direction with respect to substrate 599). The X-direction and Y-direction are perpendicular to each other and to the Z-direction.

[0066] Memory device 200 can include a dielectric 590 formed over a portion of substrate 599. Dielectric 590 can include silicon oxide. Dielectric 590 can electrically separate bottom data lines (e.g., data lines 221' and 222') of memory device 200 from substrate 599.

[0067] As shown in Figure 5 and Figure 6 , each of data lines 221, 221', 222, and 222' (associated with signals BL1, BL1', BL2, and BL2', respectively) can have a length in the Y-direction (shown in Figure 6 ), a width in the X-direction (shown in Figure 5and a thickness in the Z direction (shown in Figure 6 The length is greater than the width, and the width can be greater than the thickness. Each of the data lines 221, 221', 222, and 222' can include a conductive material (or combination of materials) that can be structured as a wire (e.g., a conductive region). Example materials for the data lines 221, 221', 222, and 222' include a metal, conductively-doped polysilicon, or other conductive material.

[0068] As shown in Figure 5 , the data lines 221 and 221' can include respective conductive regions (portions of respective conductive materials that form the data lines 221 and 221') that are located in different levels (relative to the Z direction) of the memory device 200 and are electrically separate from one another. Similarly, the data lines 222 and 222' can include respective conductive regions (portions of respective conductive materials that form the data lines 222 and 222') that are located in different levels of the memory device 200 and are electrically separate from one another. The data lines 221 and 221' can be bottom and top data lines, respectively (relative to the substrate 599 and the Z direction). The data lines 222 and 222' can be bottom and top data lines, respectively (relative to the substrate 599 and the Z direction).

[0069] As shown in Figure 5 and Figure 6 , the access lines 241A and 241B can be located in different levels of the memory device 200. Each of the access lines 241A and 241B can be located in the same level of respective memory cells of the memory device 200. For example, the access line 241A Figure 5 may be located on the same level (relative to the Z direction) as portions of the memory cells 210 and portions of the memory cells 212. In another example, the access line 241B Figure 5 may be located on the same level (relative to the Z direction) as portions of the memory cells 211 and portions of the memory cells 213.

[0070] The access line 241A (associated with the signal WL1A) can be structured (may include) by a combination of portions 541A F and 541A B (e.g., leading and trailing conductive portions of the access line 241A relative to the Y direction). Each of the portions 541A F and 541A B may include a conductive material (or combination of materials) that can be structured as a wire (e.g., a conductive region) having a length Figure 5 that extends continuously in the X direction. In Figure 5 , the portions 541A Fand 541A B to avoid obstructing some portions of other elements of the memory device 200.

[0071] portion 541A F and 541A B Each of the portions 541A F and 541A B may have a length in the X-direction (shown in Figure 5 ), a width in the Z-direction (shown in Figure 5 ), and a thickness in the Y-direction (shown in Figure 6 ), where the length is greater than the width and the width can be greater than the thickness.

[0072] portion 541A F and 541A B may be electrically coupled to one another. For example, the memory device 200 can include a conductive material (e.g., not shown) that can contact (e.g., be electrically coupled to) the portions 541A F and 541A B such that the portions 541A F and 541A B (which are portions of a single access line 241A) can be simultaneously applied with the same signal (e.g., signal WL1A).

[0073] The access line 241B (associated with signal WL1B) can have a structure similar to that of the access line 241A. For example, as shown in Figure 5 and Figure 6 the access line 241B is structured by (may include a combination of) the portions 541B F and 541B B (e.g., leading and trailing conductive portions of the access line 241B with respect to the Y-direction). The portions 541B F and 541B B may include a conductive material (or combination of materials) that can be structured as a wire (e.g., conductive region) having a length Figure 5 that extends continuously in the X-direction. In Figure 5 , the portions 541B F and 541B B are shown in part to avoid obstructing some portions of other elements of the memory device 200.

[0074] portion 541B F and 541B BEach of these may comprise a structure (e.g., a sheet (e.g., a layer)) of a conductive material (e.g., a metal, conductive-doped polysilicon, or other conductive material). Section 541B F and 541B B Each of them may have a length in the X direction (shown in...) Figure 5 (middle), width in the Z direction (shown in) Figure 5 (in the middle) and the thickness in the Y direction (shown in Figure 6 (in the middle), wherein the length is greater than the width and the width may be greater than the thickness.

[0075] Part 541B F and 541B B They can be electrically coupled to each other. For example, memory device 200 may include a conductive material (e.g., not shown) that can contact (e.g., be electrically coupled to) portion 541B. F and 541B B This caused some 541B F and 541B B (It is a portion of a single access line 241B) The same signal (e.g., signal WL1B) can be applied simultaneously.

[0076] Figure 5 and Figure 6 Each of the access lines 241A and 241B is shown to contain a combination of two conductive portions (e.g., portion 541A). F and 541A B Combination or part of 541B F and 541B B Examples of combinations thereof. However, each of access lines 241A and 241B may contain only one conductive portion. For example, in an alternative configuration of the memory device 200, portion 541A may be omitted. F and 541B F In another example, in an alternative configuration of memory device 200, portion 541A can be omitted. B and 541B B .exist Figure 5 In the structure shown, each of the access lines 241A and 241B includes two transistors T1A that can preferably control each of the memory cells 210 and 212 during operation of the memory device 200 (e.g., read operation).

[0077] like Figure 5As shown, memory cells 210 and 211 (which form a pair of memory cells) may be located (e.g., directly) between data lines 221 and 221'. Memory cells 212 and 213 (which form a pair of memory cells) may be located (e.g., directly) between data lines 222 and 222'. The memory device 200 may include a dielectric (e.g., silicon oxide) 535 between the respective pairs of memory cells. The dielectric 535 electrically separates the charge storage structure 202 of one memory cell from the charge storage structure 202 of the other memory cell in the pair of memory cells. For example, in the pair of memory cells 210 to 211, the dielectric 535 electrically separates the charge storage structure 202 of memory cell 210 from the charge storage structure 202 of memory cell 211.

[0078] The charge storage structure 202 may comprise a structure of semiconductor material (e.g., polysilicon) (e.g., a wafer (e.g., a layer)), a metal structure (e.g., a wafer (e.g., a layer)), or a structure of a material (or multiple materials) capable of capturing charge (e.g., a wafer (e.g., a layer)). The materials used for the charge storage structure 202 and the access lines 241A and 241B may be the same or different.

[0079] Figure 5 The top edge (edge ​​data line 221) of the charge storage structure 202 of each of the memory cells 210 and 212 and a portion 541A of the access line 241A are shown. F and 541A B The edges (e.g., the bottom edge) of each element are spaced a certain distance apart (e.g., Figure 5 Examples of distances shown in the diagram. However, the top edge of the charge storage structure 202 of each of the memory cells 210 and 212 is adjacent to portion 541A. F and 541A B The distance between the edges (e.g., the bottom edge) of each element can vary.

[0080] Figure 5 The bottom edge (closer to the edge of data line 221') of the charge storage structure 202 of each of the memory cells 211 and 213 and a portion 541B of the access line 241B are shown. F and 541B B The edges (e.g., the top edge) of each of them are spaced a certain distance apart (e.g., Figure 5 Examples of distances shown in the diagram. However, the bottom edge of the charge storage structure 202 of each of the memory cells 211 and 213 is adjacent to portion 541B. F and 541B B The distance between the edges (e.g., the top edge) of each element can vary.

[0081] Figure 6 portion 541A F and 541A B overlaps (in the Z-direction) the charge storage structure 202 of each of the memory cells 210 and 212. However, portion 541A F and 541A B may not overlap with the charge storage structure 202. Figure 6 portion 541B F and 541B B overlaps (in the Z-direction) the charge storage structure 202 of each of the memory cells 211 and 213. However, portion 541A F and 541A B may not overlap with the charge storage structure 202.

[0082] As Figure 6 and Figure 6 shown in FIGS. 5A and 5B, the memory device 200 can include a material 520, which can be a portion of (e.g., can form) a write channel region of a write transistor (e.g., transistor T2A or T2B) of each of the memory cells of the memory device 200. In each of the memory cells, the material 520 can contact (e.g., can be electrically coupled to) the charge storage structure 202 of the respective memory cell and contact (e.g., can be electrically coupled to) the respective data line. For example, in the memory cell 210, the material 520 (which can form a channel region of the transistor T2A of the memory cell 210) can contact the charge storage structure 202 of the memory cell 210 as well as the data line 221. In another example, in the memory cell 211, the material 520 (which can form a channel region of the transistor T2B of the memory cell 211) can contact the charge storage structure 202 of the memory cell 211 as well as the data line 221’.

[0083] The respective material 520 can form a source (e.g., a source terminal), a drain (e.g., a drain terminal), a channel region (e.g., a write channel region) between the source and the drain of a write transistor (e.g., transistor T2A or T2B) of the respective memory cell. For example, the material 520 in the memory cell 210 can form a source, a drain, and a channel region (e.g., a write channel region) of the transistor T2A of the memory cell 210. Thus, as Figure 5As shown in the middle, the source, channel region, and drain of transistor T2A of memory cell 210 can be formed from a single structure (e.g., piece (e.g., layer)) of the same material (e.g., material 520) (or alternatively, a single structure (e.g., piece (e.g., layer)) of the same combination of materials). Thus, the source, drain, and channel region of transistor T2A of memory cell 210 can be formed from the same material (e.g., material 520) of the same conductivity type (e.g., n-type or p-type).

[0084] Similarly, material 520 in memory cell 211 can form the source, drain, and channel region (e.g., write channel region) of transistor T2B of memory cell 211. Thus, as shown in the middle, the source, channel region, and drain of transistor T2B of memory cell 211 can be formed from a single structure (e.g., piece (e.g., layer)) of the same material (e.g., material 520) (or alternatively, a single structure (e.g., piece (e.g., layer)) of the same combination of materials). Thus, the source, drain, and channel region of transistor T2B of memory cell 211 can be formed from the same material (e.g., material 520) of the same conductivity type (e.g., n-type or p-type). As with memory cells 210 and 211, other memory cells (e.g., memory cells 212 and 213 in the middle and memory cells 214 and 215 in the bottom) can have a write channel region (e.g., formed from material 520) for the write transistor (T1A or T1B). Figure 5 Figure 6 As shown in the middle, the source, channel region, and drain of transistor T2A of memory cell 211 can be formed from a single structure (e.g., piece (e.g., layer)) of the same material (e.g., material 520) (or alternatively, a single structure (e.g., piece (e.g., layer)) of the same combination of materials). Thus, the source, drain, and channel region of transistor TBA of memory cell 210 can be formed from the same material (e.g., material 520) of the same conductivity type (e.g., n-type or p-type). As with memory cells 210 and 211, other memory cells (e.g., memory cells 212 and 213 in the middle and memory cells 214 and 215 in the bottom) can have a write channel region (e.g., formed from material 520) for the write transistor (T1A or T1B). Figure 5

[0085] Material 520 can include a structure (e.g., piece (e.g., layer)) of a semiconductor material. In examples where the transistor is a PFET (as described above with reference to Figures 1 to 18 ), material 520 can include a p-type semiconductor material (e.g., p-type silicon).

[0086] In another example, the material forming material 520 can include a structure (e.g., piece (e.g., layer)) of an oxide material. Examples of oxide materials for material 520 include semiconductive oxide materials, transparent conductive oxide materials, and other oxide materials.

[0087] As an example, material 520 can include at least one of the following: zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InO x , In2O3), tin oxide (SnO2), titanium oxide (TiOx), zinc oxynitride (Zn x O y N z ), magnesium zinc oxide (Mg​​x Zn y O z ), indium zinc oxide (In x Zn y O z ), indium gallium zinc oxide (In x Ga y Zn z O a ), zirconium indium zinc oxide (Zr x In y Zn z O a ), hafnium indium zinc oxide (Hf x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum tin indium zinc oxide (Al x Sn y In z Zn a O d ), silicon indium zinc oxide (Si x In y Zn z O a ), zinc tin oxide (Zn x Sn y O z ), aluminum zinc tin oxide (Al x Zn y Sn z O a ), gallium zinc tin oxide (Ga x Zn y Sn z O a ), zirconium zinc tin oxide (Zr x Zn y Sn z O a ), indium gallium silicon oxide (InGaSiO), and gallium phosphide (GaP).

[0088] Using the materials listed above in the memory device 200 provides improvements and benefits to the memory device 200. For example, during a read operation, in order to read data from a selected memory cell (e.g., a selected memory cell 202), the selected memory cell 202 is accessed and a read voltage is applied to the selected memory cell 202. The read voltage is applied to the selected memory cell 202 to cause the selected memory cell 202 to discharge. The discharge of the selected memory cell 202 is detected by the sense amplifier 208. The selected memory cell 202 is accessed and the read voltage is applied to the selected memory cell 202 to cause the selected memory cell 202 to discharge. The discharge of the selected memory cell 202 is detected by the sense amplifier 208. Figures 7 to 18 and Figures 2 to 6from the charge storage structure 202 of the selected memory cell can leak to the write transistor (e.g., transistor T2A or T2B) of the selected memory cell. Using the above-listed materials for the channel region of the write transistor (e.g., material 520) can reduce or prevent such leakage. This improves the accuracy of reading information from the selected memory cell and improves the retention of information stored in the memory cells of the memory devices described herein (e.g., memory device 200).

[0089] The above-listed materials are examples of material 520. However, other materials (e.g., relatively higher bandgap materials) different from the above-listed materials can be used.

[0090] In Figure 7 material 520 of a respective memory cell (e.g., memory cell 210) and the charge storage structure 202 of the respective memory cell can be electrically coupled (e.g., directly coupled) to one another such that the material 520 can contact the charge storage structure 202 of the respective memory cell (e.g., memory cell 210) without an intervening material (e.g., without a conductive material) between the charge storage structure 202 and the material 520. In another example, the material 520 can be electrically coupled to the charge storage structure 202 of the respective memory cell such that the material 520 is not directly coupled to (does not contact) the charge storage structure 202, but the material 520 is coupled to (e.g., indirectly contacts) the charge storage structure 202 via an intervening material (e.g., a conductive material, Figure 7 not shown in FIG. 2A) between the charge storage structure 202 and the material 520.

[0091] As shown in Figure 7 The memory device 200 can include portions 510A and 510B that contact data lines 221 and 221’ and portions 511A and 511B that contact data lines 222 and 222’, as shown in FIG. 2A. Each of portions 510A and 510B can include a semiconductor material. Example materials for each of portions 510A and 510B include silicon, polysilicon (e.g., undoped or doped polysilicon), germanium, silicon germanium, or other semiconductor materials and semiconductive oxide materials (oxide semiconductors such as SnO or other oxide semiconductors).

[0092] Portions 510A can form shared channel regions (e.g., shared read channel regions) of transistors T1A and T1B of memory cells 210 and 211, respectively. Portions 510B can form shared channel regions (e.g., shared read channel regions) of transistors T1A and T1B of memory cells 210 and 211, respectively. As noted above with reference to Figure 5As described, each of the transistors T1A and T1B of the memory cells 210 and 211, respectively, can include a channel region (e.g., a read channel region). In Figure 5 and Figure 5 In, the channel region of the transistor T1A of the memory cell 210 can include a portion (e.g., a top portion) of each of the portions 510A and 510B. The channel region of the transistor T1B of the memory cell 211 can include a portion (e.g., a bottom portion) of each of the portions 510A and 510B. As described above with reference to Figure 8 As described, each of the memory cells 210 and 211 can include a read path (e.g., a current path between the data lines 221 and 222). In Figure 8 In, the portions 510A and 510B can be part of the read path of each of the memory cells 210 and 211, which can carry a current (e.g., a read current) during a read operation to read information from the memory cell 210 or 211. For example, during a read operation, to read information from the memory cell 210 or 211, the portions 510A and 510B can conduct a current (e.g., a read current) between the data line 221 and 221’ (through the portions 510A and 510B). The direction of the read current can be from the data line 221 to the data line 221’ (through the portions 510A and 510B).

[0093] The portion 511A can form a shared channel region (e.g., a shared read channel region) of the transistors T1A and T1B of the memory cells 212 and 213, respectively. The portion 511B can form a shared channel region (e.g., a shared read channel region) of the transistors T1A and T1B of the memory cells 212 and 213, respectively. The channel region of the transistor T1A of the memory cell 212 can include a portion (e.g., a top portion) of each of the portions 511A and 511B. The channel region of the transistor T1B of the memory cell 213 can include a portion (e.g., a bottom portion) of each of the portions 511A and 511B. During a read operation, to read information from the memory cell 212 or 213, the portions 511A and 511B can conduct a current (e.g., a read current) between the data line 222 and 222’ (through the portions 511A and 511B). The direction of the read current can be from the data line 222 to the data line 222’ (through the portions 511A and 511B).

[0094] In examples where the read transistors (e.g., transistors T1A and T1B) are PFETs and the write transistors (e.g., transistors T2A and T2B) are NFETs, the materials forming portions 510A, 510B, 511A, 511B can have a different conductivity type than material 520 (e.g., the write channel region). For example, portions 510A, 510B, 511A, and 511B can include a p-type semiconductor material (e.g., p-type silicon), and material 520 can include an n-type semiconductor material (e.g., n-type gallium phosphide (GaP)).

[0095] As shown in Figure 8 , memory cells 210 can include dielectrics (e.g., channel oxide regions) 515A, 515B, 525A, and 525B to separate the read channel regions from elements of the respective memory cell pair. For example, dielectrics 515A and 515B can electrically separate the read channel regions (e.g., portions 510A and 510B) of memory cells 210 and 211, respectively, from the write channel regions (e.g., material 520) of the memory elements (e.g., charge storage structures 202) of memory cells 210 and 211. In another example, dielectrics 525A and 525B can electrically separate the read channel regions (e.g., portions 511A and 511B) of memory cells 212 and 213, respectively, from the write channel regions (e.g., material 520) of the memory elements (e.g., charge storage structures 202) of memory cells 212 and 213. Example materials for dielectrics 515A and 515B can include silicon dioxide, hafnium oxide (e.g., Hf02), aluminum oxide (e.g., AI2O3), or other dielectric materials.

[0096] As shown in Figure 8 , portions of portion 541A F may span (e.g., overlap in the X-direction) portions of portions 510A and 510B of memory cell 210 and portions of material 520. As described above, portions 510A and 510B can form portions of the read channel region of transistor T1A, and material 520 can form a portion of the write channel region of transistor T2A of memory cell 210. Thus, as shown in Figure 2 , portions of portion 541A F may span (e.g., overlap) portions of both the read channel and the write channel of transistor T1A and T2A, respectively, of memory cell 210 (e.g., one side (e.g., the front side) in the Y-direction). Although hidden from view in the view shown in Figure 5 , portions of portion 541A BThe portion of the access line 241 A can straddle (e.g., overlap in the X-direction) portions of the memory cells 210, 510A and 510B (e.g., on the other side (e.g., back side opposite the front side) in the Y-direction) and portions of the material 520.

[0097] As shown in Figure 8 , the access line 241 A can also straddle (e.g., overlap in the X-direction) portions of the portions 511 A and 511 B (e.g., portions of the read channel region of the transistor T1 A of the memory cell 212) and portions of the material 520 (e.g., portions of the write channel region of the transistor T2A of the memory cell 212).

[0098] Similarly, the access line 241 B can straddle (e.g., overlap in the X-direction) portions of the read channel region of the transistor T1 B of the memory cell 211 and portions of the write channel region of the transistor T2B of the memory cell 211. The access line 241 B can also straddle (e.g., overlap in the X-direction) portions of the read channel region of the transistor T1 B of the memory cell 213 and portions of the write channel region of the transistor T2B of the memory cell 213.

[0099] The access line 241 A straddling (e.g., overlapping) portions of the read channel and the write channel (as described above) of each of the memory cells 210 and 212 allows the access line 241 A (a single access line) to control (e.g., turn on or off) both transistors T1 A and T2A of the memory cell 210 or the memory cell 212. Similarly, the access line 241 B straddling (e.g., overlapping) portions of the read channel and the write channel (as described above) of each of the memory cells 211 and 213 allows the access line 241 B (a single access line) to control (e.g., turn on or off) both transistors T1 B and T2B of the memory cell 211 or the memory cell 213.

[0100] As shown in Figure 9 , each of the access lines (e.g., word lines) can have portions adjacent to (e.g., on the right and left sides in the X-direction) and separate from (by a dielectric) respective sides of the material 520 and the charge storage structure 202 of the respective memory cell. For example, the portion 541 A F may be adjacent to one side (e.g., the right side in the X-direction) of a portion of each of the material 520 and the charge storage structure 202 of the memory cell 210. In another example, the portion 541 A B may be adjacent to the other side (e.g., the left side in the X-direction (opposite the right side)) of a portion of each of the material 520 and the charge storage structure 202 of the memory cell 210. Figure 8 Figure 9 may be adjacent to one side (e.g., the right side in the X-direction) of a portion of each of the material 520 and the charge storage structure 202 of the memory cell 210. In another example, the portion 541 A B may be adjacent to the other side (e.g., the left side in the X-direction (opposite the right side)) of a portion of each of the material 520 and the charge storage structure 202 of the memory cell 210.

[0101] like Figure 10 As shown, memory device 200 may include dielectrics (e.g., gate oxide regions) 518F, 518B, 519F, and 519B to electrically separate access lines (e.g., word lines) from the elements of corresponding memory cell pairs. For example, dielectrics 518F and 518B may respectively separate portions 541A of access lines 241A and 241B. F 541A B 541B F and 541B B With the read channel regions of the corresponding memory cells 210 and 211 (e.g., Figure 10 The memory cells 210 and 211 shown herein, portions 510A and 510B, write channel regions (e.g., material 520), and memory elements (e.g., charge storage structure 202) are electrically separated. In another embodiment, dielectrics 519F and 519B may respectively separate portions 542A of access lines 242A and 242B. F 542A B 542B F and 542B B With the read channel regions of the corresponding memory cells 214 and 215 (e.g., Figure 5 and Figure 11 (Not shown in the diagram) The write channel region (e.g., material 520) and memory element (e.g., charge storage structure 202) are electrically separated. Example materials for dielectrics 518F, 518B, 519F, and 519B may include silicon dioxide, hafnium oxide (e.g., HfO2), aluminum oxide (e.g., Al2O3), or other dielectric materials.

[0102] The materials (or combinations thereof) used for the dielectric (e.g., the gate oxide region) 518F, 518B, 519F, and 519B can be used with the materials used for the dielectric (e.g., the gate oxide region, as shown in...) Figure 11 The materials (or materials) of dielectrics 515A and 515B are the same (or alternatively, may be different). Additionally, the thickness of each of dielectrics 518F, 518B, 519F, and 519B may be the same (or alternatively, different) than the thickness of each of dielectrics 515A and 515B.

[0103] Please refer to the following text. Figure 10 The described technology (e.g., process) forms the memory device 200 described above.

[0104] Figure 10Different views of elements during a process to form the memory device 700 according to some embodiments described herein are shown. Some or all of the processes to form the memory device 700 can be used to form the memory device 200 described above with reference to FIGS. 1-6. Figure 5 The memory device 200 described above.

[0105] Figure 12 The memory device 700 is shown after different material levels (e.g., layers) are formed over the substrate 799 along the Z-direction of the memory device 700 in respective levels (e.g., layers). The different material levels include the dielectric material 790, the conductive material 724, the material (e.g., write channel material) 720, the material (e.g., charge storage material) 702, the dielectric material 735, the material 702 (another material level 702), and the material 720 (another material level 720). Figure 11 The material levels shown in FIG. 7B can be formed over the substrate 799 in a sequential manner with one material followed by another material. For example, the processes in FIG. 7B can include forming (e.g., depositing) the dielectric material 790 over the substrate 799; forming (e.g., depositing) the conductive material 724 over the dielectric material 790; forming (e.g., depositing) the material 720 over the conductive material 724; forming (e.g., depositing) the material 702 over the material 720; forming (e.g., depositing) the dielectric material 735 over the material 702; forming (e.g., depositing) the additional material 702 over the material 735; and forming (e.g., depositing) the additional material 720 over the additional material 702. Figure 11 The processes in FIG. 7B can include forming (e.g., depositing) the dielectric material 790 over the substrate 799; forming (e.g., depositing) the conductive material 724 over the dielectric material 790; forming (e.g., depositing) the material 720 over the conductive material 724; forming (e.g., depositing) the material 702 over the material 720; forming (e.g., depositing) the dielectric material 735 over the material 702; forming (e.g., depositing) the additional material 702 over the material 735; and forming (e.g., depositing) the additional material 720 over the additional material 702.

[0106] The substrate 799 can be similar to or the same as the substrate 599 of the memory device 200 of FIG. 1. Figure 12 The dielectric materials 790 and 735 can include the same dielectric material or different dielectric materials. Each of the dielectric materials 790 and 735 can include a nitride material (e.g., silicon nitride (e.g., Si3N4)), an oxide material (e.g., SiO2), or other dielectric material. The conductive material 724 can include the same material as the data lines 221 and 222 (e.g., metal, conductively-doped polysilicon, or other conductive material).

[0107] The material 720 can include the same material as the write channel regions (e.g., the material 520) of the transistors T2A and T2B of the memory cells (e.g., the memory cells 210-215) of the memory device 200 of FIG. 1. For example, the material 720 can include a semiconductive material. The semiconductive material can include an oxide material. Examples of the oxide material include a semiconductive oxide material, a transparent conductive oxide material, and other oxide materials. Figure 12 The material 702 can include the same material as the charge storage material (e.g., the material 520) of the memory cells (e.g., the memory cells 210-215) of the memory device 200 of FIG. 1.

[0108] Figure 13 ​The charge storage structure 202 of a memory cell (e.g., memory cells 210-215) of the memory device 200 is of the same material. For example, the material 702 can include a charge storage material (or a combination of materials) that can include a semiconductor material (e.g., polysilicon), a metal, or other material that can trap a charge.

[0109] Figure 13 The memory device 700 is shown after formation of trenches (e.g., openings) 801, 802, and 803. Formation of the trenches 801, 802, and 803 can include removing (e.g., by patterning) a portion of each of the conductive material 724, the material 720 (two levels), the material 702 (two levels), and the dielectric material 735 at the location of the trenches 801, 802, and 803. The remaining portions of the conductive material 724, the material 720 (two levels), the material 702 (two levels), and the dielectric material 735 are included in (disposed in) structures (e.g., device structures) 811 and 812, as shown in Figure 12 .

[0110] Data lines (e.g., bottom data lines) 721' and 722' (associated with signals BL1' and BL2', respectively) can be formed when the structures 811 and 812 are formed. As shown in Figure 13 , portions of the material 724 at the structures 811 and 812 can form the data lines 721' and 722', respectively. The data lines 721' and 722' are electrically separated from each other. Each of the data lines 721' and 722' can have a length in the Y direction (hidden from view in Figure 12 . The data lines 721' and 722' can be bottom data lines of the memory device 700 and can correspond to the data lines 221' and 222' of the memory device 200 Figure 13 and Figure 12 , respectively.

[0111] In Figure 12 , each of the trenches 801, 802, and 803 can have a length in the Y direction, a width (shorter than the length) in the X direction, and a bottom (not labeled) that rests on (e.g., is delimited by) a respective portion of the dielectric material 790. The structures 811 and 812 can include respective sidewalls (e.g., opposing vertical sidewalls) 861, 862, 863, and 864 that also form sidewalls of the respective trenches 801, 802, and 803. For example, the structure 811 can include the sidewalls 861 and 862, and the structure 812 can include the sidewalls 863 and 864. The sidewalls 862 and 863 can form sidewalls of the trench 802.

[0112] Figure 13The memory device 700 is shown after formation of structures 911 and 912. The structures 911 and 912 are remaining portions of the structures 811 and 812, respectively. Formation of the structures 911 and 912 can include removing portions (e.g., sidewall portions) of each of the structures 811 and 812 at the trenches 801, 802, and 803, such that the structures 911 and 912 can have narrower portions (in the X-direction) than the structures 811 and 812, respectively. For example, formation of the structures 911 and 912 can include removing (e.g., by etching) a portion (a portion at each of the sidewalls 861, 862, 863, and 864) of each of the conductive material 724, the material 720 (both levels), the material 702 (both levels). The material 724 in the formation of the data lines 721' and 722' can remain unchanged (e.g., can not be etched) during the process of Figure 13 Figure 2 such that each of the structures 911 and 912 can have a portion (e.g., a portion at the data lines 721' and 722') that is wider (in the X-direction) than a remaining portion of the respective structure (structure 911 or 912).

[0113] Figure 5 The memory device 700 is shown after formation of dielectric materials (e.g., dielectrics) 1015A, 1015B, 1025A, and 1025B on respective sidewalls (not labeled) of the respective structures 911 and 912 at sites of the trenches 801, 802, and 803. As shown in Figure 13 Figure 13

[0114] Figure 12 The memory device 700 is shown after formation of semiconductor materials 1110A, 1110B, 1111A, and 1111B adjacent to (e.g., formed on sides of) the dielectrics 1015A, 1015B, 1025A, and 1025B, respectively. The semiconductor materials 1110A, 1110B, 1111A, and 1111B are electrically separated from one another. As shown in Figure 13 Figure 17 ​​​​exposed portions of the trenches 801 and 802 in the material of the memory device 700). The semiconductor materials 1110A and 1110B can contact (e.g., be electrically coupled to) a portion of the data line 721' (at the exposed portions of the trenches 801 and 802 in the material of the memory device 700). The semiconductor materials 1111A and 1111B can contact (e.g., be electrically coupled to) a portion of the data line 722' (at the exposed portions of the trenches 801 and 802 in the material of the memory device 700). Figure 13 The semiconductor materials 1110A, 1110B, 1111A, and 1111B can be subsequently processed to form read channel regions (and shared read channel regions for respective pairs of memory cells) of respective transistors (e.g., transistors T1A or T1B) of the memory cells of the memory device 700. The semiconductor materials 1110A, 1110B, 1111A, and 1111B can have the same materials as the portions (e.g., read channel regions) 510A, 510B, 511A, and 511B of the memory device 200 ( Figure 17 ).

[0115] Figure 13 A top-down view of the memory device 700 is shown with respect to the X-Y directions of the memory device 700. For simplicity, descriptions of the same elements shown in Figure 2 Figure 5 and Figure 13 are not repeated. As shown in Figure 13 , elements of the memory device 700 can include strips (e.g., lines) of material having lengths extending in the Y direction. Subsequent processes to form the memory device 700 can include removing (e.g., cutting (e.g., etching) down) the material at the locations 1261, 1262, and 1263 until (terminate at) the data lines 721' and 722' ( Figure 12 ). In this way (terminate at the data lines 721' and 722'), each of the data lines 721' and 722' (which have lengths extending in the Y direction) can remain continuously extending in the Y direction and electrically coupled to memory cells (e.g., in columns) in the Y direction. The material of the memory device 700 at the locations 1271 and 1272 can remain (and will be structures that are part of forming respective memory cells of the memory device 700).

[0116] Figure 13 A top-down view of the memory device 700 is shown after the material at the locations 1261, 1262, and 1263 ( Figure 17 ) respectively, forms trenches (e.g., openings) 1361, 1362, and 1363. As shown in Figure 13 , structures 1371 and 1372 are formed at the locations 1271 and 1272 ( Figure 17 ) respectively. As shown in Figure 13 ​As shown, material is removed from trenches 1361, 1362, and 1363 (locations 1261, 1262, and 1263) above substrate 799, terminating (e.g., downwards to) data lines 721' and 722'. This can be achieved by removing (e.g., cutting in the X direction) the material at locations 1261, 1262, and 1263 as mentioned above. Figure 2 The material at each location is used to form grooves 1361, 1362, and 1363. Locations 1271 and 1272 ( Figure 5 The remaining material at the location forms (e.g., provides) structures 1371 and 1372. Figure 13 ).

[0117] like Figure 13 As shown, structure 1372 may include memory cells 210' (which may correspond to...) Figure 12 and Figure 13 The memory cells 210 of the memory device 200 are portions 1310A, 1310B, 1315A, and 1315B. Figure 13 ) respectively in Figure 17 In the process of removing (e.g., cutting) a portion of each of 1110A, 1110B, 1015A and 1015B, the portions 1110A, 1110B, 1015A and 1015B are... Figure 14 The remaining part of ). Parts 1310A and 1310B ( Figure 13 ) can form memory cell 210' (and such Figure 14 The read channel region of memory cell 211' (below memory cell 210') shown in the figure. Parts 1315A and 1315B ( Figure 14 A dielectric (e.g., a channel oxide region) may be formed to connect portions 1310A and 1310B to memory cell 210' (and Figure 13 Other elements of the memory cell 211' shown in the figure (e.g., write channel region and charge storage structure) are electrically separated.

[0118] like Figure 11 As shown, structure 1371 may also include a memory cell 212' (which may correspond to...) Figure 12 and Figure 14 The memory cells 212 of the memory device 200 are portions 1311A, 1311B, 1325A, and 1325B. (The remaining text appears to be a list of portions 1311A, 1311B, 1325A, and 1325B.) Figure 15 ) respectively in Figure 13In the process of removing (e.g., cutting) portions 1111A, 1111B, 1025A and 1025B ( Figure 15 The remaining portions of 1111A, 1111B, 1025A, and 1025B after each of the parts in ). Parts 1311A and 1311B ( Figure 2 ) can form memory cell 212' (and Figure 6 The read channel region of memory cell 213' (below memory cell 212') shown in the figure. Parts 1325A and 1325B ( Figure 15 A dielectric (e.g., a channel oxide region) may be formed to connect portions 1311A and 1311B to memory cell 212' (and Figure 15 Other elements of the memory cell 213' shown in the figure (e.g., write channel region and charge storage structure) are electrically separated.

[0119] like Figure 17 As shown, structure 1371 may include memory cells 214' (which may correspond to...) Figure 15 and Figure 15 The portions 1310A', 1310B', 1315A', and 1315B' of the memory cell 214 of the memory device 200. The portions 1310A', 1310B', 1315A', and 1315B' ( Figure 17 ) respectively in Figure 15 In the process of removing (e.g., cutting) portions 1110A, 1110B, 1015A and 1015B ( Figure 15 The remaining portions of 1110A, 1110B, 1015A, and 1015B after each of the parts in ) . Parts 1310A' and 1310B' ( Figure 15 This can form a read channel region for memory cell 214' (and a memory cell (not shown) located below memory cell 214'). Parts 1315A' and 1315B' ( Figure 15 A dielectric (e.g., a channel oxide region) may be formed to connect portions of 1310A' and 1310B' to memory cell 214' (and Figure 15 Other elements of the memory cell 215' shown in the figure (e.g., write channel region and charge storage structure) are electrically separated.

[0120] like Figure 15 As shown, structure 1371 may also include a memory cell 216' (which may correspond to...) Figure 16 and Figure 15The portions 1311A', 1311B', 1325A', and 1325B' of the memory cell 216 of the memory device 200. The portions 1311A', 1311B', 1325A', and 1325B' ( Figure 16 ) respectively in Figure 16 In the process of removing (e.g., cutting) portions 1110A, 1110B, 1015A and 1015B ( Figure 16 The remaining portions of 1110A, 1110B, 1015A, and 1015B after each of the parts in ) . Parts 1311A' and 1311B' ( Figure 16 This can form a read channel region for memory cell 216' (and a memory cell (not shown) located below memory cell 216'). Parts 1325A' and 1325B' ( Figure 16 A dielectric (e.g., a channel oxide region) may be formed to connect portions 1311A' and 1311B' to memory cell 216' (and Figure 17 Other elements of the memory cell 217' shown in the figure (e.g., write channel region and charge storage structure) are electrically separated. Figure 16 The middle shows along Figure 17 Another view (e.g., cross-sectional view) of the memory device 700 in the YZ direction of line 14-14.

[0121] Figure 16 A portion of each of structures 1371 and 1372 in the YZ direction is shown. Each of structures 1371 and 1372 may comprise different portions (from top to bottom), said portions comprising material (e.g., a write channel region) 1320, charge storage structure 1302, dielectric 1335, and material (e.g., another write channel region) 1320. These portions ( Figure 17 ) for in Figure 17 The corresponding material (shown in) after removing (e.g., cutting) portions of these materials in the process. Figure 16 and Figure 17 The remaining portion of (in the middle), the material comprising material 720, material 702, dielectric material 735, additional material 702, and additional material 720. For example... Figures 13 to 16 As shown, the material used for the data cable 721' is retained (e.g., not cut) during the process of forming the grooves 1361, 1362 and 1363.

[0122] Figures 13 to 17 Demonstrated in dielectrics (e.g., gate oxides) 1518F, 1518B, 1519F, and 1519B, and conductors (e.g., conductive regions) 1541A F 1541A B 1541BF , 1541B B , 1542A F , 1542A B , 1542B F and 1542B B and dielectrics 1508, 1507, and 1506 are formed in respective trenches 1361, 1362, and 1363 Figure 17 of memory device 700. Each of dielectrics 1518B, 1518F, 1519B, and 1519F and dielectrics 1506, 1507, and 1508 can include silicon dioxide or other dielectric material. Conductor 1541A F , 1541A B , 1541B F , 1541B B , 1542A F , 1542A B , 1542B F and 1542B B may include metal, conductively-doped polysilicon, or other conductive material.

[0123] Conductor 1541A F , 1541A B , 1541B F , 1541B B , 1542A F , 1542A B , 1542B F and 1542B B may form portions of respective access lines (e.g., word lines) to access memory cells (e.g., Figure 17 of memory device 700. Memory cells 210', 211', 214', and 215' can correspond to memory cells 210, 211, 214, and 215, respectively, Figure 2 and Figure 17 of memory device 200.

[0124] In Figure 15 , conductors 1541A F and 1541A B may form portions of access lines (e.g., word lines) to control transistors TIA and T2A of memory cell 210' and other memory cells (not shown in Figure 17 ) of memory device 700. Such other memory cells can be in the same row as memory cell 210' in the X-direction (e.g., memory cell 212' shown in Figure 15 ).

[0125] exist Figure 17 In the middle, conductor 1541B F and 1541B B A portion that can form access lines (e.g., word lines) to control memory cells 211' and other memory cells of memory device 700. Figure 18 Transistors T1B and T2B (not shown in the diagram). Other memory cells of this type may be located in the same row as memory cell 211' in the X direction (e.g., Figure 18 (Memory cell 213' shown in the image).

[0126] exist Figure 2 In the middle, conductor 1542A F and 1542A B Transistors T1A and T2A, which may form access lines (e.g., word lines) to control memory cells 214' and other memory cells (not shown) of memory device 700, may form transistors T1A and T2A. These other memory cells may be located in the same row as memory cell 214' in the X direction.

[0127] exist Figures 7 to 18 In the middle, conductor 1542B F and 1542B B Transistors T1B and T2B, which may form access lines (e.g., word lines) to control memory cells 215' and other memory cells (not shown) of memory device 700, may form transistors T1B and T2B. These other memory cells may be located in the same row as memory cell 215' in the X direction.

[0128] like Figure 8 As shown, wire 1541A F 1541A B 1541B F 1541B B 1542A F 1542A B 1542B F and 1542B B It may be adjacent to and separated (through a dielectric) from the corresponding side (e.g., the right or left side in the Y direction) of the material 1320 of the corresponding memory cell (e.g., the write channel region) and the corresponding side of the charge storage structure 1302. For example, wire 1541A F and 1541A B The material 1320 of the memory cell 210' and a portion of each of the charge storage structure 1302 may be adjacent to the right and left sides (in) Figure 13 In the view, in the Y direction). Similarly, as Figures 1 to 18 As shown, other conductors 1541B F 1541BB 1542A F 1542A B 1542B F and 1542B B A portion of each of the materials 1320 of the corresponding memory cell of the memory device 700 and the charge storage structure 1302 (e.g., in) Figures 1 to 18 In the view, they are adjacent and separated in the Y direction. ​ The middle shows along ​ Another view (e.g., top view) of the memory device 700 with lines 16-16.

[0129] ​ A top view is shown along line 16-16 of the memory device 700. (As shown) ​ As shown, wire 1541A F 1541A B 1542A F and 1542A B Each of them can be located in the corresponding trenches 1371 and 1372, and has a length in the X direction and a thickness in the Y direction. From ​ A top view of the memory device 700, concealing other wires 1541B F 1541B B 1542B F and 1542B B (It is located in the corresponding conductor 1541A) F 1541A B 1542A F and 1542A B (Below).

[0130] like ​ As shown, wire 1541A F 1541A B 1542A F and 1542A B Electrically separated from the components of memory cells 210', 212', 214', and 216' by corresponding dielectrics 1518B, 1518F, 1519B, and 1519F. For example, 1541A F and 1541A B It can be electrically separated from the write channel region (e.g., material 1320), charge storage structure 1302 (located below material 1320), and read channel region (e.g., portions 1310A and 1310B) of memory cell 210'. For simplicity, ​The labels of some of the elements of the memory units 212', 214', and 216', which are similar to those of the memory unit 210', are omitted. ​ Another view (e.g., cross-sectional view) of the memory device 700 along the line 17-17 of FIG. 1 1 is shown in FIG. 13. ​ Another view (e.g., cross-sectional view) of the memory device 700 along the line 17-17 of FIG. 1 1 is shown in FIG. 13.

[0131] ​ A view along the line 17-17 of FIG. 1 1 is shown in FIG. 14 relative to the X-Z direction. In ​ A view along the line 17-17 of FIG. 1 1 is shown in FIG. 14 relative to the X-Z direction. In ​ In FIG. 14, the conductive lines 1701 and 1702 are partially shown to avoid obstructing some portions of other elements of the memory device 700. As shown in ​ In FIG. 14, the conductive lines 1701 and 1702 are partially shown to avoid obstructing some portions of other elements of the memory device 700. As shown in ​ In FIG. 14, the conductive lines 1701 and 1702 are partially shown to avoid obstructing some portions of other elements of the memory device 700. As shown in

[0132] ​ Elements of the memory units 210', 21 1 ', 212', and 213' are also shown in FIG. 15. Thus, for simplicity, the description of the same elements (with the same labels) among ​ ​

[0133] ​ ​​​As shown in the middle, each of the memory cells 210', 211', 212', and 213' can have a read transistor (e.g., transistor TIA or TIB) and a write transistor (e.g., transistor T2A or T2B). Each of the portions 1310A, 1310B, 1311A, and 1311B can form a channel region (e.g., a read channel region) of a read transistor of a respective memory cell among the memory cells 210', 211', 212', and 213'. Each of the portions 1310A, 1310B, 1311A, and 1311B can also form a shared channel region (e.g., a shared read channel region) of a read transistor of a respective pair of memory cells among the memory cells 210', 211', 212', and 213'. For example, the portion 1310A can form a shared channel region (e.g., a shared read channel region) of the transistors TIA and TIB of the memory cells 210' and 211', respectively. In another example, the portion 1310B can form a shared channel region (e.g., a shared read channel region) of the transistors TIA and TIB of the memory cells 210' and 211', respectively. In another example, the portion 1311A can form a shared channel region (e.g., a shared read channel region) of the transistors TIA and TIB of the memory cells 212' and 213', respectively. In another example, the portion 1311B can form a shared channel region (e.g., a shared read channel region) of the transistors TIA and TIB of the memory cells 212' and 213', respectively.

[0134] Each of the materials 1320 can form a channel region (e.g., a write channel region) of a write transistor of a respective memory cell among the memory cells 210', 211', 212', and 213'. The dielectrics 1315A, 1315B, 1325A, and 1325B can form a channel oxide region to electrically separate a read channel region of a respective memory cell from a write channel region and a charge storage structure of the respective memory cell.

[0135] In ​ the wire 1541A F and 1541A B may be a portion of an access line (e.g., a word line) 1541A (which can receive a signal (e.g., a word line signal) WLA) to control the transistors TIA and T2A of each of the memory cells 210' and 212' during an operation (e.g., a read or a write) of the memory device 700. The wire 1541B F and 1541B BA portion of the access line (e.g., word line) 1541B, which can receive a signal (e.g., word line signal) WLB, can be to control the transistors TIB and T2B of each of the memory cells 211’ and 213’ during operation (e.g., read or write) of the memory device 700. The access lines 1541A and 1541B can correspond to the access lines 241A and 241B, respectively, of the memory device 200 of ​ FIG. 1A.

[0136] As shown in ​ FIG. 1A, each of the conductive lines 1541A F and 1541A B may span (e.g., overlap in the X-direction) a portion of the read channel region (e.g., portions 1310A and 1310B) of the transistor TIA and a portion of the write channel region (e.g., portion 1320) of the transistor T2A of the memory cell 210’. Each of the conductive lines 1541A F and 1541A B may also span (e.g., overlap in the X-direction) a portion of the read channel region (e.g., portions 1311A and 1311B) of the transistor TIA and a portion of the write channel region (e.g., portion 1320) of the transistor T2A of the memory cell 212’.

[0137] Each of the conductive lines 1541B F and 1541B B may span (e.g., overlap in the X-direction) a portion of the read channel region (e.g., portions 1310A and 1310B) of the transistor TIB and a portion of the write channel region (e.g., portion 1320) of the transistor T2B of the memory cell 211’. Each of the conductive lines 1541B F and 1541B B may also span (e.g., overlap in the X-direction) a portion of the read channel region (e.g., portions 1311A and 1311B) of the transistor TIB and a portion of the write channel region (e.g., portion 1320) of the transistor T2B of the memory cell 213’.

[0138] The process of forming the memory device 700 (e.g., in ​ may include forming the conductive connections 1541A’ as shown in ​ FIG. 1A. The conductive connections 1541A’ can include a conductive material (e.g., metal) to electrically couple the conductive lines 1541A F and 1541A B to each other. Similarly, the process of forming the memory device 700 (e.g., in ​ may include forming the conductive connections 1541B’ as shown in ​The conductive connections 1541B' can include conductive material (e.g., metal) to electrically couple the conductive lines 1541B F and 1541B B to each other.

[0139] ​ The memory device 700 is shown after the data lines 1821 and 1822 are formed (e.g., deposited) over elements of the respective memory cells 210' and 212' of the memory device 700. As shown in ​ The data line 1821 can contact (e.g., be electrically coupled to) the read channel regions (e.g., portions 1310A and 1310B) and the write channel region (e.g., material 1320) of the transistors T1A and T2A, respectively, of the memory cell 210', as shown in ​ The data lines 1821 and 1822 can have the same materials as the data lines 221 and 222 of the memory device 200. Each of the data lines 1821 and 1822 can have a length extending in the Y direction, as each of the data lines 721' and 722'. The data lines 1821 and 1822 can correspond to the data lines 221 and 222, respectively, of the memory device 200.

[0140] Referring to ​ The description of forming the memory device 700 can include other processes to form the entire memory device. These processes are omitted from the above description to avoid obscuring the subject matter described herein.

[0141] The processes of forming the memory device 700 as described above can have a relatively reduced number of masks (e.g., a reduced number of critical masks) compared to some conventional processes. For example, by forming the trenches 801, 802, and 803 in the processes associated with ​ and the material 1320 in the processes associated with ​Forming trenches 1361, 1362, and 1363 in an associated process can reduce the number of critical masks used to form memory cells of a memory device. A reduced number of masks can simplify the process of forming memory device 700, reduce cost, or both. Additionally, forming some of the elements (e.g., charge storage structures and write channel regions) using the techniques described herein can be more advantageous than using some other techniques. For example, some of the structures of the memory cells described herein (e.g., charge storage structures and write channel regions) can be formed by depositing one material over (e.g., on top of) another material rather than using other methods (e.g., atomic layer deposition). Using the techniques described herein can result in more defined structures (e.g., charge storage structures and write channel regions) of the described memory cells.

[0142] The description of the apparatuses (e.g., memory devices 100, 200, and 700) and methods (e.g., operations of memory devices 100 and 200 and methods of forming memory device 700) is intended to provide a general understanding of the structure of various embodiments, and is not intended to provide a complete description of all the elements and features of the apparatuses that can utilize the structures described herein. An apparatus refers to, for example, a device (e.g., any of memory devices 100, 200, and 700) or a system (e.g., an electronic article that can include any of memory devices 100, 200, and 700).

[0143] The above references ​ Any of the described components can be implemented in a variety of ways, including via software simulation. Accordingly, apparatuses (e.g., memory devices 100, 200, and 700) or portions of each of these memory devices described above can each be characterized herein as “a plurality of modules” (or “module”). Such modules can include hardware circuitry, single- and / or multi-processor circuitry, memory circuitry, software program modules and objects, and / or firmware, and combinations thereof, as needed and / or suitable for particular implementation of various embodiments. For example, such modules can be included in system operation simulation packages, such as software electrical signal simulation packages, power usage and range simulation packages, capacitance-inductance simulation packages, power / thermal dissipation simulation packages, signal transmission-reception simulation packages, and / or combinations of software and hardware to operate or simulate operation of various possible embodiments.

[0144] The memory devices described herein (e.g., memory devices 100, 200, and 700) can be included in a device (e.g., electronic circuitry) such as a high-speed computer, a communication and signal processing circuitry, a single- or multi-processor module, a single or multiple embedded processors, a multi-core processor, a message information exchanger, and a specialized module including multiple layers, multiple chip modules. Such a device can further include a subcomponent within a variety of other devices (e.g., electronic systems) such as a television, a cellular telephone, a personal computer (e.g., a laptop, a desktop, a handheld PC, a tablet, etc.), a workstation, a radio, a video player, an audio player (e.g., an MP3 (Motion Picture Experts Group, Audio Layer 3) player), a vehicle, a medical device (e.g., a heart monitor, a blood pressure monitor, etc.), a set-top box, and others.

[0145] The above references ​ Described embodiments include devices and methods of forming the devices. One of the devices includes a first data line in a first level of the device, a second data line in a second level of the device, a first memory cell in a third level of the device between the first level and the second level, the first memory cell including a first transistor coupled to the first data line and a second transistor coupled between the first data line and a charge storage structure of the first transistor, and a second memory cell in a fourth level of the device between the first level and the second level, the second memory cell including a third transistor coupled to the second data line and a fourth transistor coupled between the second data line and a charge storage structure of the third transistor, the first transistor and the third transistor coupled in series between the first data line and the second data line. Other embodiments include additional devices and methods are described.

[0146] In implementations and claims, the term "on" (one on another) used with respect to two or more elements (e.g., materials) means at least some contact between the elements (e.g., materials). The term "over" means close proximity of elements (e.g., materials) but possibly with one or more additional intervening elements (e.g., materials) such that contact is possible but not necessary. Neither "on" nor "over" implies any directionality as used herein unless so stated.

[0147] In the implementations and claims, a list of items joined by the term "at least one of" can mean any combination of the listed terms. For example, if A and B are listed, the phrase "at least one of A and B" means A alone, B alone, or both A and B. In another example, if A, B, and C are listed, the phrase "at least one of A, B, and C" means A alone, B alone, C alone, A and B (not C), A and C (not B), B and C (not A), or all of A, B, and C. Item A can include a single element or multiple elements. Item B can include a single element or multiple elements. Item C can include a single element or multiple elements.

[0148] In the implementations and claims, a list of items joined by the term "one of' can mean only one of the listed items. For example, if A and B are listed, the phrase "one of A and B" means A (not B) or B (not A). In another example, if A, B, and C are listed, the phrase "one of A, B, and C" means A; B; or C. Item A can include a single element or multiple elements. Item B can include a single element or multiple elements. Item C can include a single element or multiple elements.

[0149] The above description and drawings illustrate and describe several embodiments of the inventive subject matter to enable a person skilled in the art to make and use the embodiments of the inventive subject matter. Other embodiments can incorporate structural, logical, electrical, process, and other changes. Examples merely typify possible variations. Parts and features of some embodiments can be included in, or substituted for, those of other embodiments. Many of the numerous other embodiments will be apparent to those skilled in the art in view of the above description and drawings.

Claims

1. An apparatus comprising: The first data line is located in the first layer of the device; The second data line is located in the second level of the device; A first memory cell is located in a third level of the device between the first level and the second level. The first memory cell includes a first transistor coupled to the first data line and a second transistor coupled between the first data line and the charge storage structure of the first transistor. and A second memory cell is located in a fourth level of the device between the first level and the second level. The second memory cell includes a third transistor coupled to the second data line and a fourth transistor coupled between the second data line and the charge storage structure of the third transistor. The first transistor and the third transistor are coupled in series between the first data line and the second data line.

2. The device of claim 1, wherein the first transistor and the second transistor have different transistor types, and the third transistor and the fourth transistor have different transistor types.

3. The device of claim 1, wherein the first transistor and the second transistor have different threshold voltages, and the third transistor and the fourth transistor have different threshold voltages.

4. The device of claim 1, wherein each of the first charge storage structure and the second charge storage structure comprises polycrystalline silicon.

5. The device according to claim 1, wherein: The second transistor includes a first semiconducting oxide material that contacts the first data line and the first charge storage structure; and The fourth transistor includes a second semiconducting oxide material that contacts the second data line and the second charge storage structure.

6. The device according to claim 1, further comprising: A first wire, which spans a portion of each of the first transistor and the second transistor; and The second wire crosses a portion of each of the third and fourth transistors.

7. The device according to claim 6, further comprising: A first additional wire, which crosses a portion of each of the first transistor and the second transistor; and A second additional wire, which crosses a portion of each of the third and fourth transistors.

8. The device according to claim 1, further comprising: The third data line is located in the first level; The fourth data line is located in the second level; A third memory unit, located in the third level, includes components coupled to the... The fifth transistor of the third data line and the sixth transistor coupled to the fifth transistor; A fourth memory cell, located in the fourth level, the fourth memory cell comprising components coupled to the... The seventh transistor of the fourth data line and the eighth transistor coupled to the seventh transistor, wherein the seventh transistor and the fifth transistor are coupled in series between the third data line and the fourth data line; A first conductor, which spans a portion of each of the first transistor and the second transistor, and a portion of each of the fifth transistor and the sixth transistor; and The second conductor spans portions of each of the third and fourth transistors and portions of each of the seventh and eighth transistors.

9. The device according to claim 8, further comprising: A first additional conductor, which crosses a portion of each of the first transistor and the second transistor and a portion of each of the fifth transistor and the sixth transistor; and The second additional conductor crosses portions of each of the third and fourth transistors and portions of each of the seventh and eighth transistors.

10. An apparatus comprising: A first conductive region, which is located in the first layer of the device; A second conductive region, which is located in the second layer of the device; A first charge storage structure is located in a third level of the device, between the first level and the second level; A first semiconductor material is located between and in contact with the first conductive region and the first charge storage structure. The second charge storage structure is located in the fourth level of the device, which is between the second level and the third level; A second semiconductor material is located between and in contact with the second conductive region and the second charge storage structure. A third semiconductor material extends between the first layer and the second layer and contacts the first conductive region and the second conductive region; A first dielectric is located between and in contact with the first charge storage structure and the second charge storage structure; and The second dielectric separates the third semiconductor material from each of the first semiconductor material, the second semiconductor material, the first charge storage structure, and the second charge storage structure.

11. The device of claim 10, further comprising a fourth semiconductor material extending between the first layer and the second layer and contacting the first conductive region and the second conductive region.

12. The device of claim 11, further comprising a third dielectric separating the fourth semiconductor material from each of the first semiconductor material and the second semiconductor material, as well as the first charge storage structure and the second charge storage structure.

13. The device according to claim 10, wherein: The first charge storage structure forms part of the first transistor of the first memory cell; The second charge storage structure forms part of the second transistor of the second memory cell; and The third semiconductor material forms the shared channel region between the first transistor and the second transistor.

14. The device of claim 10, wherein each of the first semiconductor material and the second semiconductor material has a first conductivity type, and the third semiconductor material has a second conductivity type.

15. The device of claim 10, wherein each of the first semiconductor material and the second semiconductor material has n-type conductivity, and the third semiconductor material has p-type conductivity.

16. The device of claim 10, wherein the first semiconductor material comprises the same material as the second semiconducting material.

17. The device of claim 10, wherein each of the first semiconductor material and the second semiconductor material comprises a semiconducting oxide material.

18. The apparatus of claim 10, wherein each of the first semiconductor material and the second semiconductor material comprises at least one of the following: zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO). x Indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InO) x In₂O₃), tin oxide (SnO₂), titanium oxide (TiO₂), zinc oxide (ZnO₂) x O y N z ), magnesium zinc oxide (Mg x Zn y O z Indium zinc oxide (In) x Zn y O z Indium gallium zinc oxide (In) x Ga y Zn z O a Zirconia indium zinc (Zr) x In y Zn z O a ), Hafnium Indium Zinc Oxide (Hf x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum tin indium zinc (Al x Sn y In z Zn a O d ), silicon indium zinc (Si) x In y Zn z O a ), Zinc tin oxide (Zn) x Sn y O z ), aluminum oxide zinc tin (Al x Zn y Sn z O a Gallium zinc tin oxide (Ga) x Zn y Sn z O a Zirconia zinc tin (Zr) x Zn y Sn z O a Indium gallium silicon oxide (InGaSiO) and gallium phosphide (GaP).

19. The apparatus of claim 10, further comprising: The third conductive region spans a portion of each of the first semiconductor material and the third semiconductor material; and A fourth conductive region, which spans a portion of each of the second semiconductor material and the third semiconductor material.

20. The apparatus of claim 19, further comprising: A third additional conductive region, which spans a portion of each of the first semiconductor material and the third semiconductor material; A fourth additional conductive region, which spans a portion of each of the second semiconductor material and the third semiconductor material.

21. A method comprising: Form the first data line; A first memory cell is formed above the first data line, including a first transistor forming the first memory cell above the data line and a second transistor forming the first memory cell above at least a portion of the first transistor; A second memory cell is formed above the first memory cell, including a third transistor forming the second memory cell above at least a portion of the second transistor and a fourth transistor forming the second memory cell above at least a portion of the third transistor; and A second data line is formed above the fourth transistor.

22. The method of claim 21, wherein forming the second transistor and the third transistor comprises forming a channel region of the second transistor from a first portion of the semiconductor material and forming a channel region of the third transistor from a second portion of the semiconductor material.

23. The method of claim 22, wherein the channel region of the second transistor and the channel region of the third transistor form a circuit path between the first data line and the second data line.

24. The method of claim 21, wherein forming the first transistor and the fourth transistor comprises: Depositing different material layers above a substrate; and Removing portions of different material layers to form the channel region of the first transistor from the first material of the different material layers and the channel region of the fourth transistor from the second material of the different material layers.

25. The method of claim 24, wherein the first material and the second material comprise a semiconductive oxide material.

26. The method of claim 21, wherein forming the first data line further comprises: Multiple material layers are formed above the substrate; and Remove portions of the plurality of material layers to form the first data line from the conductive material of the plurality of material layers.

27. The method of claim 22, further comprising: A first wire is formed, which crosses a portion of each of the first transistor and the second transistor; and A second conductor is formed, which crosses a portion of each of the third and fourth transistors.

28. The method of claim 27, further comprising: A first additional wire is formed, which crosses a portion of each of the first transistor and the second transistor; and A second additional wire is formed, which crosses a portion of each of the third and fourth transistors.

29. A method comprising: Forming a material hierarchy, including: Forming conductive materials; A first semiconductor material is formed on top of the conductive material; A first charge storage material is formed on top of the first semiconductor material; A dielectric material is formed on top of the first charge storage material; A second charge storage material is formed on top of the dielectric material; and A second semiconductor material is formed on top of the second charge storage material; and A first groove is formed in the material layer by removing a portion of the material layer to provide a first remaining portion of the material layer, such that each of the first grooves contains a length in a first direction; and A second trench is formed across the first remaining portion of the material layer to form a memory cell from at least a portion of the second remaining portion of the material layer.

30. The method of claim 29, wherein the memory cell includes a first memory cell formed above a second memory cell in the memory cell, the first memory cell including a portion of the first semiconductor material, and the second memory cell including a portion of the second semiconductor material.

31. The method of claim 30, wherein the first memory cell further comprises a portion of the first charge storage material, and the second memory cell comprises a portion of the second charge storage material.

32. The method of claim 29, wherein each of the first semiconductor material and the second semiconductor material comprises a semiconducting oxide material.

33. The method of claim 29, further comprising: A first conductor is formed in the trench of the second trench, the first conductor having a length in the second direction; and A second conductor is formed in the trench of the second trench, the second conductor being located above the first conductor and including the length in the second direction.

34. The method of claim 33, further comprising: A first additional conductor is formed in the trench, the first additional conductor comprising a length in the second direction; and A second additional conductor is formed in the trench, the second additional conductor being located above the first additional conductor and including the length in the second direction.

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