Memory device with dual transistor memory cells and access line board

Abstract

Some embodiments include an apparatus and methods using a substrate, a pillar having a length perpendicular to the substrate, a first conductive plate, a second conductive plate, a memory cell located between and electrically separated from the first conductive plate and the second conductive plate, and a conductive connection. The first conductive plate is located in a first level of the apparatus and separated from the pillar by a first dielectric located in the first level. The second conductive plate is located in a second level of the apparatus and separated from the pillar by a second dielectric located in the second level. The memory cell includes a first semiconductor material located in a third level of the apparatus between the first level and the second level and in contact with the pillar and the conductive connection, and a second semiconductor material located in a fourth level of the apparatus between the first level and the second level and in contact with the pillar.

Description

[0001] Priority Application

[0002] This application claims the priority benefit of U.S. Provisional Application No. 62 / 892,995, filed August 28, 2019, which is incorporated by reference herein in its entirety. BACKGROUND

[0003] Memory devices are widely used in computers and many other electronic appliances to store information. Memory devices are generally classified into two types: volatile memory devices and non-volatile memory devices. A memory device typically has a number of memory cells to store information. In a volatile memory device, the information stored in the memory cells is lost if the supply power is disconnected from the memory device. In a non-volatile memory device, the information stored in the memory cells remains even if the supply power is disconnected from the memory device.

[0004] The description herein relates to volatile memory devices. Most conventional volatile memory devices store information in the form of electric charges in a capacitor structure included in a memory cell. As the demand for device storage density increases, many conventional techniques provide a way to shrink the size of a memory cell in order to increase the device storage density of a given device area. However, if the memory cell size is to be shrunk to a certain size, physical limitations and manufacturing constraints can pose a challenge to such conventional techniques. Unlike some conventional memory devices, the memory devices described herein include features that can overcome the challenges faced by conventional techniques. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1 A block diagram of an apparatus in the form of a memory device including a volatile memory cell is shown in accordance with some embodiments described herein.

[0006] Figure 2 A schematic diagram of a portion of a memory device including a memory array of two-transistor (2T) memory cells is shown in accordance with some embodiments described herein.

[0007] Figure 3 A memory device of Figure 2 including example voltages used during a read operation of the memory device in accordance with some embodiments described herein.

[0008] Figure 4 A memory device of Figure 2 including example voltages used during a write operation of the memory device in accordance with some embodiments described herein.

[0009] Figure 5Different views of a structure of a memory device including a plurality of stacks of memory cells and vertical common conductive connections according to some embodiments described herein are shown. Figure 2 A memory device including additional memory cells in a Y direction.

[0010] Figures 6 to 12 Different views of a structure of a memory device including a plurality of stacks of memory cells according to some embodiments described herein are shown.

[0011] Figures 13 to 18 Different views of a structure of a memory device including a plurality of stacks of memory cells and vertical common conductive connections according to some embodiments described herein are shown. DETAILED DESCRIPTION

[0012] The memory devices described herein include volatile memory cells, where each of the memory cells can include two transistors (2T). One of the two transistors has a charge storage structure, which can form a memory element of the memory cell to store information. The memory devices described herein can have a structure that allows the size of the memory device to be relatively smaller than the size of similar conventional memory devices (e.g., 4F2cell footprint). The described memory devices can include a single access line (e.g., word line) to control both transistors of the memory cell. This can result in reduced power dissipation and improved processing. Each of the memory cells of the described memory devices can include a cross-point gain cell structure (and cross-point operation), such that a single access line (e.g., word line) and a single data line (e.g., bit line) can be used to access the memory cell during operation of the memory device (e.g., read or write operation). Additionally, the described memory devices can have a plurality of stacks of memory cells, where the stacks can be commonly formed. This can reduce the cost of the memory device (e.g., cost per bit). Reference is made below to Figures 1 to 18 Other improvements and benefits of the described memory devices and variations thereof are discussed.

[0013] Figure 1This diagram illustrates a device in the form of a memory device 100 comprising volatile memory cells, according to some embodiments described herein. The memory device 100 includes a memory array 101, which may contain memory cells 102. The memory device 100 may include volatile memory devices such that memory cells 102 may be volatile memory cells. Examples of the memory device 100 include dynamic random access memory (DRAM) devices. If power supply (e.g., supply voltage Vcc) is disconnected from the memory device 100, information stored in the memory cells 102 of the memory device 100 may be lost (e.g., invalidated). Hereinafter, the supply voltage Vcc is referred to as representing some voltage level; however, these voltage levels are not limited to the supply voltage (e.g., Vcc) of the memory device (e.g., memory device 100). For example, if the memory device (e.g., memory device 100) has an internal voltage generator that generates an internal voltage based on the supply voltage Vcc... Figure 1 (not shown in the figure), then this internal voltage can be used instead of the supply voltage Vcc.

[0014] In the physical structure of the memory device 100, each of the memory cells 102 may include transistors (e.g., two transistors) vertically formed (e.g., stacked on different layers) in different layers above a substrate (e.g., a semiconductor substrate) of the memory device 100. The memory device 100 may also include multiple layers (e.g., multiple stacks) of memory cells, wherein one layer (e.g., one stack) of memory cells may be formed above (e.g., another stack) of additional memory cells (e.g., stacked on another layer). The structure of the memory array 101 including the memory cells 102 may include, as described below. Figures 2 to 18 The structure of the memory array and memory cells described.

[0015] like Figure 1 As shown, memory device 100 may include access lines 104 (e.g., "word lines") and data lines (e.g., bit lines) 105. Memory device 100 may use signals on access lines 104 (e.g., word line signals) to access memory cells 102, and use signals on data lines 105 to provide information (e.g., data) to be stored (e.g., written) to or read from memory cells 102 (e.g., sensed).

[0016] The memory device 100 can include an address register 106 to receive address information ADDR (e.g., row and column address signals) on lines (e.g., address lines) 107. The memory device 100 can include row access circuitry (e.g., X decoder) 108 and column access circuitry (e.g., Y decoder) 109 operable to decode address information ADDR from the address register 106. Based on the decoded address information, the memory device 100 can determine which memory cells 102 are to be accessed during a memory operation. The memory device 100 can perform write operations to store information in the memory cells 102 and read operations to read (e.g., sense) information (e.g., previously stored information) in the memory cells 102. The memory device 100 can also perform operations (e.g., refresh operations) to refresh (e.g., keep valid) values of information stored in the memory cells 102. Each of the memory cells 102 can be configured to store information that can represent at most one bit (e.g., a single bit having a binary 0 (“0”) or a binary 1 (“1”)), or more than one bit (e.g., a plurality of bits having a combination of at least two binary bits).

[0017] The memory device 100 can receive supply voltages, including supply voltages Vcc and Vss on lines 130 and 132, respectively. The supply voltage Vss can operate at a ground potential (e.g., having a value of approximately zero volts). The supply voltage Vcc can include an external voltage supplied to the memory device 100 from an external power source, such as a battery or alternating current to direct current (AC to DC) converter circuitry.

[0018] As shown in Figure 1 The memory device 100 can include a memory control unit 118 that includes circuitry (e.g., hardware components) to control memory operations (e.g., read and write operations) of the memory device 100 based on control signals on lines (e.g., control lines) 120. Examples of signals on the lines 120 include a row access strobe signal RAS*, a column access strobe signal CAS*, a write enable signal WE*, a chip select signal CS*, a clock signal CK, and a clock enable signal CKE. These signals can be part of the signals provided to a DRAM device.

[0019] As shown in Figure 1As shown in the middle, memory device 100 can include a line (e.g., a global data line) 112 that can carry signals DQ0 through DQN. In a read operation, the value (e.g., “0” or “1”) of the information provided to line 112 (read from memory cells 102) in the form of signals DQ0 through DQN can be based on the value of the signal on data line 105. In a write operation, the value (e.g., “0” or “1”) of the information provided to data line 105 (to be stored in memory cells 102) can be based on the value of signals DQ0 through DQN on line 112.

[0020] Memory device 100 can include sensing circuitry 103, selection circuitry 115, and input / output (I / O) circuitry 116. Column access circuitry 109 can selectively enable signals on a line (e.g., a select line) based on address signals ADDR. Selection circuitry 115 can respond to signals on line 114 to select signals on data line 105. Signals on data line 105 can represent a value of information to be stored in memory cells 102 (e.g., during a write operation) or a value of information read (e.g., sensed) from memory cells 102 (e.g., during a read operation).

[0021] I / O circuitry 116 can operate to provide information read from memory cells 102 to line 112 (e.g., during a read operation) and provide information from line 112 (e.g., provided by an external device) to data line 105 to be stored in memory cells 102 (e.g., during a write operation). Line 112 can include a node within memory device 100 or a pin (or solder ball) on a package in which memory device 100 can reside. Other devices external to memory device 100 (e.g., a hardware memory controller or a hardware processor) can communicate with memory device 100 via lines 107, 112, and 120.

[0022] Memory device 100 can include other components that are not shown in Figure 1 the middle to avoid obscuring the example embodiments described herein. At least a portion of memory device 100 (e.g., a portion of memory array 101) can include structures and operations similar to or the same as any of the memory devices described below with reference to Figures 2 to 18 .

[0023] Figure 2 A schematic diagram showing a portion of a memory device 200 including a memory array 201 of 2T memory cells is shown, in accordance with some embodiments described herein. Memory device 200 can correspond to Figure 1 memory device 100. For example, memory array 201 can form a portion of Figure 1 memory array 101. As shown in the middle, memory device 200 can include a line (e.g., a global data line) 212 that can carry signals DQ0 through DQN. In a read operation, the value (e.g., “0” or “1”) of the information provided to line 212 (read from memory cells 201) in the form of signals DQ0 through DQN can be based on the value of the signal on data line 205. In a write operation, the value (e.g., “0” or “1”) of the information provided to data line 205 (to be stored in memory cells 201) can be based on the value of signals DQ0 through DQN on line 212.Figure 2 As shown in the middle, the memory device 200 can include memory cells 210-215 that are volatile memory cells (e.g., DRAM cells). For simplicity, like or identical elements among the memory cells 210-215 are given the same label.

[0024] Figure 2 Only a portion of the memory cells in the X and Z directions are shown, which can correspond to the directions of the structure (physical structure) of the memory device 200. However, the memory device 200 also includes additional memory cells (not shown) in the Y direction. Figure 5 Some of such additional memory cells are shown below (described).

[0025] As Figure 2 As shown in the middle, each of the memory cells 210-215 can include two transistors Tl and T2. Thus, each of the memory cells 210-215 can be referred to as a 2T memory cell (e.g., a 2T gain cell). Each of the transistors Tl and T2 can include a field effect transistor (FET). As an example, the transistor Tl can be a p-channel FET (PFET), and the transistor T2 can be an n-channel FET (NFET). Portions of the transistor Tl can include the structure of a p-channel metal-oxide-semiconductor (PMOS) transistor FET (PFET). Thus, the transistor Tl can include operations similar to those of a PMOS transistor. Portions of the transistor T2 can include the structure of an n-channel metal-oxide-semiconductor (NMOS). Thus, the transistor T2 can include operations similar to those of an NMOS transistor.

[0026] The transistor Tl of the memory device 200 can include a charge-based memory structure (e.g., based on a floating gate). As Figure 2 As shown in the middle, each of the memory cells 210-215 can include a charge storage structure 202, which can include a floating gate of the transistor Tl. The charge storage structure 202 can form a memory element of a respective one of the memory cells 210-215. The charge storage structure 202 can store a charge. The value (e.g., “0” or “1”) of information stored in a particular one of the memory cells 210-215 can be based on the amount of charge in the charge storage structure 202 of that particular memory cell.

[0027] As Figure 2As shown in the middle, a transistor T2 (e.g., a channel region of the transistor T2) of a particular memory cell among the memory cells 210-215 can be electrically coupled to (e.g., directly coupled to) the charge storage structure 202 of the particular memory cell. Thus, during an operation (e.g., a write operation) of the memory device 200, a circuit path (e.g., a current path) can be directly formed between the transistor T2 of a particular memory cell and the charge storage structure 202 of the particular memory cell.

[0028] The memory cells 210-215 can be arranged in memory cell groups 2010 and 2011. Figure 2 Two memory cell groups (e.g., 2010 and 2011) are shown as examples. However, the memory device 200 can include more than two memory cell groups. The memory cell groups 2010 and 2011 can include the same number of memory cells. For example, the memory cell group 2010 can include the memory cells 210, 212, and 214, and the memory cell group 2011 can include the memory cells 211, 213, and 215. Figure 2 Three memory cells are shown in each of the memory cell groups 2010 and 2011 as examples. The number of memory cells in the memory cell groups 2010 and 2011 can be different than three.

[0029] The memory device 200 can perform write operations to store information in the memory cells 210-215 and read operations to read (e.g., sense) information from the memory cells 210-215. The memory device 200 can be configured to operate as a DRAM device. However, unlike some conventional DRAM devices that store information in structures such as a capacitor, the memory device 200 can store information in the form of a charge in the charge storage structure 202, which can be a floating gate structure. As mentioned above, the charge storage structure 202 can be a floating gate of the transistor Tl. During an operation (e.g., a read or write operation) of the memory device 200, an access line (e.g., a single access line) and a data line (e.g., a single data line) can be used to access a selected memory cell (e.g., a target memory cell).

[0030] As Figure 2As shown in the middle, memory device 200 can include access lines (e.g., word lines) 241, 242, and 243 that can carry respective signals (e.g., word line signals) WL1, WL2, and WLn. Access lines 241, 242, and 243 can be used to access two groups of memory cells 2010 and 2011. Each of access lines 241, 242, and 243 can be structured as at least one wire (one wire or multiple wires that can be electrically coupled (e.g., shorted) to each other). Access lines 241, 242, and 243 can be selectively activated (e.g., activated one at a time) during an operation (e.g., a read or write operation) of memory device 200 to access a selected memory cell (or multiple selected memory cells) among memory cells 210 through 215. The selected cell can be referred to as a target cell. In a read operation, information can be read from the selected memory cell (or multiple selected memory cells). In a write operation, information can be stored in the selected memory cell (or multiple selected memory cells).

[0031] In memory device 200, a single access line (e.g., a single word line) can be used to control (e.g., turn on or off) transistors T1 and T2 of a respective memory cell during a read or write operation of memory device 200. Some conventional memory devices can use multiple (e.g., two separate) access lines to control access to a respective memory cell during a read and write operation. In comparison to such conventional memory devices (using multiple access lines for the same memory cell), memory device 200 uses a single access line (e.g., a shared access line) in memory device 200 to control both transistors T1 and T2 of a respective memory cell to access the respective memory cell. This technique can save space and simplify the operation of memory device 200. In addition, some conventional memory devices can use multiple data lines to access a selected memory cell (e.g., during a read operation) to read information from the selected memory cell. In memory device 200, a single data line (e.g., data line 221 or 222) can be used to access a selected memory cell (e.g., during a read operation) to read information from the selected memory cell. In comparison to conventional memory devices using multiple data lines to access a selected memory cell, this can also simplify the structure, operation, or both of memory device 200.

[0032] In memory device 200, the gate of each of transistors T1 and T2 can be part of a respective access line (e.g., a respective word line). As shown in the middle, the gates of transistors T1 and T2 of memory cell 210 are part of access line 241. The gates of transistors T1 and T2 of memory cell 211 are part of access line 242. The gates of transistors T1 and T2 of memory cell 212 are part of access line 243. The gates of transistors T1 and T2 of memory cell 213 are part of access line 241. The gates of transistors T1 and T2 of memory cell 214 are part of access line 242. The gates of transistors T1 and T2 of memory cell 215 are part of access line 243. Figure 2As shown in the middle, the gate of each of the transistors T1 and T2 of the memory cell 210 can be part of the access line 241. The gate of each of the transistors T1 and T2 of the memory cell 211 can be part of the access line 241. For example, in the structure of the memory device 200, four different portions of the conductive material (or materials) that form the access line 241 can form the gates of the transistors T1 and T2 of the memory cell 210 and the gates of the transistors T1 and T2 of the memory cell 211, respectively (e.g., four gates).

[0033] The gate of each of the transistors T1 and T2 of the memory cell 212 can be part of the access line 242. The gate of each of the transistors T1 and T2 of the memory cell 213 can be part of the access line 242. For example, in the structure of the memory device 200, four different portions of the conductive material (or materials) that form the access line 242 can form the gates of the transistors T1 and T2 of the memory cell 212 and the gates of the transistors T1 and T2 of the memory cell 213, respectively (e.g., four gates).

[0034] The gate of each of the transistors T1 and T2 of the memory cell 214 can be part of the access line 243. The gate of each of the transistors T1 and T2 of the memory cell 215 can be part of the access line 243. For example, in the structure of the memory device 200, four different portions of the conductive material (or materials) that form the access line 243 can form the gates of the transistors T1 and T2 of the memory cell 214 and the gates of the transistors T1 and T2 of the memory cell 215, respectively (e.g., four gates).

[0035] The memory device 200 can include data lines (e.g., bit lines) 221 and 222 that can carry respective signals (e.g., bit line signals) BL1 and BL2. During a read operation, the memory device 200 can use the data line 221 to obtain information read (e.g., sensed) from a selected memory cell of the memory cell group 2010 and use the data line 222 to read information from a selected memory cell of the memory cell group 2011. During a write operation, the memory device 200 can use the data line 221 to provide information to be stored in a selected memory cell of the memory cell group 2010 and use the data line 222 to provide information to be stored in a selected memory cell of the memory cell group 2011.

[0036] The memory device 200 can include a ground connection (e.g., a ground plate) 297 coupled to each of the memory cells 210-215. The ground connection 297 can be structured from a conductive plate (e.g., a layer of conductive material) that can be coupled to a ground terminal of the memory device 200. As an example, the ground connection 297 can include a common conductive plate of the memory device (e.g., formed over the memory cells (e.g., memory cells 210-215)). In this example, the common conductive plate can be formed over elements (e.g., transistors Tl and T2) of each of the memory cells (e.g., memory cells 210-215) of the memory device 200.

[0037] As shown in Figure 3 The transistor Tl (e.g., the channel region of the transistor Tl) of a particular memory cell among the memory cells 210-215 can be electrically coupled to (e.g., directly coupled to) the ground connection 297 and electrically coupled to (e.g., directly coupled to) a respective data line (e.g., data line 221 or 222), as shown in

[0038] The memory device 200 can include a read path (e.g., a circuit path). Information read from a selected memory cell during a read operation can be obtained via the read path coupled to the selected memory cell. In the memory cell group 2010, the read path of a particular memory cell (e.g., memory cell 210, 212, or 214) can include a current path (e.g., a read current path) through the channel region of the transistor Tl, the data line 221, and the ground connection 297 of the particular memory cell. In the memory cell group 2011, the read path of a particular memory cell (e.g., memory cell 211, 213, or 215) can include a current path (e.g., a read current path) through the channel region of the transistor Tl, the data line 222, and the ground connection 297 of the particular memory cell. In examples where the transistor Tl is a PFET (e.g., a PMOS), the current in the read path (e.g., during a read operation) can include hole conduction (e.g., hole conduction in a direction from the data line 221 through the channel region of the transistor Tl to the ground connection 297). Since the transistor Tl can be used in the read path to read information from the respective memory cell during a read operation, the transistor Tl can be referred to as a read transistor and the channel region of the transistor Tl can be referred to as a read channel region.

[0039] Memory device 200 can include a write path (e.g., a circuit path). Information to be stored in a selected memory cell during a write operation can be provided to the selected memory cell via the write path coupled to the selected memory cell. In memory cell group 2010, the write path for a particular memory cell can include transistor T2 for the particular memory cell (e.g., can include a write current path through the channel region of transistor T2) and data line 221. In memory cell group 2011, the write path for a particular memory cell (e.g., memory cell 211, 213, or 215) can include transistor T2 for the particular memory cell (e.g., can include a write current path through the channel region of transistor T2) and data line 222. In examples where transistor T2 is an NFET (e.g., an NMOS), current in the write path (e.g., during a write operation) can include conduction of electrons (e.g., in a direction from data line 221 through the channel region of transistor T2 to charge storage structure 202). As transistor T2 can be used in the write path to store information in the respective memory cell during a write operation, transistor T2 can be referred to as a write transistor and the channel region of transistor Tl can be referred to as a write channel region.

[0040] Each of transistors Tl and T2 can include a threshold voltage (Vt). Transistor Tl has threshold voltage Vtl. Transistor T2 has threshold voltage Vt2. The values of threshold voltages Vtl and Vt2 can be different (unequal). For example, the value of threshold voltage Vt2 can be greater than the value of threshold voltage Vtl. The difference in the values of threshold voltages Vtl and Vt2 allows information stored in charge storage structure 202 in transistor Tl on the read path to be read (e.g., sensed) during a read operation without affecting (e.g., turning on) transistor T2 on the write path (e.g., the path through transistor T2). This can prevent leakage of charge from charge storage structure 202 through transistor T2 of the write path (e.g., during a read operation).

[0041] In the structure of memory device 200, transistors Tl and T2 can be formed (e.g., engineered) such that threshold voltage Vtl of transistor Tl can be less than zero volts (e.g., Vtl < 0 V) regardless of the value (e.g., "0" or "1") of information stored in charge storage structure 202 of transistor Tl, and Vtl < Vt2. When information having a value of "0" is stored in charge storage structure 202, charge storage structure 202 can be in state "0." When information having a value of "1" is stored in charge storage structure 202, charge storage structure 202 can be in state "1." Thus, in this structure, the relationship between the values of threshold voltages Vtl and Vt2 can be expressed as follows: Vtl for state "0" < Vtl for state "1" < 0 V, and Vt2 = 0 V (or alternatively, Vt2 > 0 V).

[0042] In an alternative structure of memory device 200, transistors Tl and T2 can be formed (e.g., engineered) such that Vtl for state "0" < Vtl for state "1," where Vtl for state "0" < 0 V (or alternatively, Vtl for state "0" = 0 V), Vtl for state "1" > 0 V, and Vtl < Vt2.

[0043] In another alternative structure, transistors Tl and T2 can be formed (e.g., engineered) such that Vtl for state "0" < Vtl for state "1," where Vtl for state "0" = 0 V (or alternatively, Vtl for state "0" > 0 V) and Vtl < Vt2.

[0044] During a read operation of memory device 200, only one memory cell of the same memory cell group can be selected at a time to read information from the selected memory cell. For example, memory cells 210, 212, and 214 of memory cell group 2010 can be selected one at a time during a read operation to read information from the selected memory cell (e.g., one of memory cells 210, 212, and 214 in this example). In another example, memory cells 211, 213, and 215 of memory cell group 2011 can be selected one at a time during a read operation to read information from the selected memory cell (e.g., one of memory cells 211, 213, and 215 in this example).

[0045] During a read operation, memory cells of different memory cell groups (e.g., memory cell groups 2010 and 2011) that share the same access line (e.g., access lines 241, 242, or 243) can be simultaneously selected (or alternatively, can be sequentially selected). For example, memory cells 210 and 211 can be simultaneously selected during a read operation to read (e.g., simultaneously read) information from memory cells 210 and 211. Memory cells 212 and 213 can be simultaneously selected during a read operation to read (e.g., simultaneously read) information from memory cells 212 and 213. Memory cells 214 and 215 can be simultaneously selected during a read operation to read (e.g., simultaneously read) information from memory cells 214 and 215.

[0046] The value of the information read from the selected memory cells of memory cell group 2010 during a read operation can be determined based on the value of the current detected (e.g., sensed) from the read path (described above) that includes data line 221, transistor Tl of the selected memory cell (e.g., memory cell 210, 212, or 214), and ground connection 297. The value of the information read from the selected memory cells of memory cell group 2011 during a read operation can be determined based on the value of the current detected (e.g., sensed) from the read path that includes data line 222, transistor Tl of the selected memory cell (e.g., memory cell 211, 213, or 215), and ground connection 297.

[0047] Memory device 200 can include detection circuitry (not shown) that can operate during a read operation to detect (e.g., sense) the current (e.g., current II, not shown) on the read path that includes data line 221, and to detect the current (e.g., current I2, not shown) on the read path that includes data line 222. The value of the detected current can be based on the value of the information stored in the selected memory cells. For example, depending on the value of the information stored in the selected memory cells of memory cell group 2010, the value of the detected current on data line 221 (e.g., the value of current II) can be zero or greater than zero. Similarly, depending on the value of the information stored in the selected memory cells of memory cell group 2011, the value of the detected current between data line 222 (e.g., the value of current I2) can be zero or greater than zero. Memory device 200 can include circuitry (not shown) to translate the value of the detected current to the value of the information (e.g., “0,” “1,” or a combination of multi-bit values) stored in the selected memory cells.

[0048] During a write operation of the memory device 200, only one memory cell of the same memory cell group can be selected at a time to store information in the selected memory cell. For example, the memory cells 210, 212, and 214 of the memory cell group 2010 can be selected one at a time during a write operation to store information in the selected memory cell (e.g., one of the memory cells 210, 212, and 214 in this example). In another example, the memory cells 211, 213, and 215 of the memory cell group 2011 can be selected one at a time during a write operation to store information in the selected memory cell (e.g., one of the memory cells 211, 213, and 215 in this example).

[0049] During a write operation, memory cells of different memory cell groups (e.g., the memory cell groups 2010 and 2011) that share the same access line (e.g., the access lines 241, 242, or 243) can be selected at the same time. For example, the memory cells 210 and 211 can be selected at the same time during a write operation to store (e.g., store at the same time) information in the memory cells 210 and 211. The memory cells 212 and 213 can be selected at the same time during a write operation to store (e.g., store at the same time) information in the memory cells 212 and 213. The memory cells 214 and 215 can be selected at the same time during a write operation to store (e.g., store at the same time) information in the memory cells 214 and 215.

[0050] Information to be stored in the selected memory cells of the memory cell group 2010 during a write operation can be provided via a write path (described above) that includes the data line 221 and the transistor T2 of the selected memory cell (e.g., the memory cell 210, 212, or 214). Information to be stored in the selected memory cells of the memory cell group 2011 during a write operation can be provided via a write path (described above) that includes the data line 222 and the transistor T2 of the selected memory cell (e.g., the memory cell 211, 213, or 215). As described above, the value (e.g., binary value) of the information stored in a particular memory cell among the memory cells 210-215 can be based on the amount of charge in the charge storage structure 202 of that particular memory cell.

[0051] In a write operation, the amount of charge in the charge storage structure 202 of a selected memory cell can be changed (to reflect a value of information to be stored in the selected memory cell) by applying a voltage on a write path that includes the transistor T2 of the particular memory cell and a data line (e.g., data line 221 or 222) coupled to the particular memory cell. For example, if the information to be stored in a selected memory cell among memory cells 210, 212, and 214 has one value (e.g., "0"), a voltage having one value (e.g., 0 V) can be applied on data line 221 (e.g., 0 V is provided to signal BL1). In another example, if the information to be stored in a selected memory cell among memory cells 210, 212, and 214 has another value (e.g., "1"), a voltage having the other value (e.g., a positive voltage) can be applied on data line 221 (e.g., a positive voltage is provided to signal BL1). Thus, information can be stored (e.g., directly stored) in the charge storage structure 202 of a particular memory cell by providing the information to be stored (e.g., in the form of a voltage) on the write path (including the transistor T2) of the particular memory cell.

[0052] Figure 2 A memory device 200 according to some embodiments described herein is shown. Figure 3 The memory device 200 includes example voltages VI, V2, and V3 used during a read operation of the memory device 200. Figure 3 The example assumes that memory cells 210 and 211 are selected memory cells (e.g., target memory cells) during a read operation to read (e.g., sense) information stored (e.g., previously stored) in memory cells 210 and 211. Memory cells 212 to 215 are assumed to be unselected memory cells. This means that memory cells 212 to 215 are not accessed and information stored in memory cells 212 to 215 is not read in Figure 3 The example assumes that memory cells 210 and 211 are selected memory cells (e.g., target memory cells) during a read operation to read (e.g., sense) information stored (e.g., previously stored) in memory cells 210 and 211. Memory cells 212 to 215 are assumed to be unselected memory cells. This means that memory cells 212 to 215 are not accessed and information stored in memory cells 212 to 215 is not read in

[0053] In Figure 3 In the example, voltages VI, V2, and V3 can represent different voltages applied to respective access lines 241, 242, and 243 and data lines 221 and 222 during a read operation of the memory device 200. As an example, voltages VI, V2, and V3 can have values of -1 V, 0 V, and 0.5 V, respectively. The particular values of voltages used in this description are merely example values. Different values can be used. For example, voltage VI can have a range of negative values (e.g., voltage VI can have a value from -3 V to -1 V).

[0054] In Figure 3In the read operation illustrated in the middle, voltage VI can have a value (voltage value) to turn on transistor Tl of each of memory cells 210 and 211 (selected memory cells in this example), and turn off (disable) transistor T2 of each of memory cells 210 and 211. This allows information to be read from memory cells 210 and 211. Voltage V2 can have a value such that transistors Tl and T2 of each of memory cells 212-215 (unselected memory cells in this example) are turned off (e.g., disabled). Voltage V3 can have a value such that a current (e.g., a read current) can be formed on a read path including data line 221 and transistor Tl of memory cell 210, and a read path including data line 222 and transistor Tl of memory cell 212 (separate read paths). This allows the current on the read paths coupled to memory cells 210 and 211 to be detected, respectively. Detection circuitry (not shown) of memory device 200 can be operable to translate the value of the detected current (during reading of information from a selected memory cell) to the value of the information read from the selected memory cell (e.g., a “0,” a “1,” or a combination of multi-bit values). In Figure 3 the example of FIG. 2B, the value of the detected current on data line 221 and 222, respectively, can be translated to the value of the information read from memory cells 210 and 211, respectively.

[0055] In Figure 4In the read operation shown in the middle, in addition to transistor Tl of each of memory cells 210 and 211 (selected memory cells), the voltages applied to respective access lines 241, 242, and 243 can cause transistors Tl and T2 of each of memory cells 212-215 to be turned off (or remain turned off). Depending on the value of threshold voltage Vtl of transistor Tl of memory cell 210 (selected memory cell), transistor Tl of memory cell 210 can or can not be turned on. Depending on the value of threshold voltage Vtl of transistor Tl of memory cell 211 (selected memory cell), transistor Tl of memory cell 211 can or can not be turned on. For example, if transistor Tl of each of memory cells (e.g., 210-215) of memory device 200 is configured (e.g., structured) such that the threshold voltage of transistor Tl is less than zero (e.g., Vtl < -1 V) regardless of the value (e.g., state) of information stored in respective memory cell 210, in this example, transistor Tl of memory cell 210 can be turned on and conduct current on data line 221 (via transistor Tl of memory cell 210). In this example, transistor Tl of memory cell 211 can also be turned on and conduct current on data line 222 (via transistor Tl of memory cell 211). Memory device 200 can determine the values of information stored in memory cells 210 and 211 based on the values of current on data lines 221 and 222, respectively. As described above, memory device 200 can include detection circuitry to measure the values of current on data lines 221 and 222 during the read operation.

[0056] Figure 2 A memory device 200 according to some embodiments described herein is shown Figure 4 includes example voltages V4, V5, V6, and V7 used during a write operation of memory device 200. Figure 4 The example assumes that memory cells 210 and 211 are selected memory cells (e.g., target memory cells) during the write operation to store information in memory cells 210 and 211. Memory cells 212-215 are assumed to be unselected memory cells. This means that in the example, memory cells 212-215 are not accessed and information is not stored in memory cells 212-215, while information is stored in memory cells 210 and 211. Figure 4

[0057] In the example, memory cells 212-215 are not accessed and information is not stored in memory cells 212-215, while information is stored in memory cells 210 and 211. Figure 4 ​In particular embodiments, voltages V4, V5, V6, and V7 can represent different voltages applied to respective access lines 241, 242, and 243, and data lines 221 and 222 during a write operation of memory device 200. As an example, voltages V4 and V5 can have values 3V and 0V, respectively. These values are example values. Different values can be used.

[0058] The values of voltages V6 and V7 can be the same or different depending on the values (e.g., “0” or “1”) of information to be stored in memory cells 210 and 211. For example, if memory cells 210 and 211 are to store information having the same value, the values of voltages V6 and V7 can be the same (e.g., V6 = V7). As an example, if the information to be stored in each memory cell 210 and 211 is “0”, then V6 = V7 = 0V, and if the information to be stored in each memory cell 210 and 211 is “1”, then V6 = V7 = 1V to 3V.

[0059] In another example, if memory cells 210 and 211 are to store information having different values, the values of voltages V6 and V7 can be different (e.g., V6 ≠ V7). As an example, if “0” is to be stored in memory cell 210 and “1” is to be stored in memory cell 211, then V6 = 0V and V7 = 1V to 3V. As another example, if “1” is to be stored in memory cell 210 and “0” is to be stored in memory cell 211, then V6 = 1V to 3V and V7 = 0V.

[0060] A voltage range of 1V to 3V is used here as an example. Different voltage ranges can be used. In addition, instead of applying 0V (e.g., V6 = 0V or V7 = 0V) to a particular write data line (e.g., data line 221 or 222) for storing information having a value of “0” to a memory cell (e.g., memory cell 210 or 211) coupled to that particular write data line, a positive voltage (e.g., V6 > 0V or V7 > 0V) can be applied to that particular data line.

[0061] In Figure 4In a write operation of the memory device 200, the voltage V5 can have a value such that the transistors T1 and T2 of each of the memory cells 212-215 (in this example, unselected memory cells) are turned off (e.g., disabled). The voltage V4 can have a value to turn on the transistor T2 of each of the memory cells 210 and 211 (in this example, selected memory cells) and form a write path between the charge storage structure 202 of the memory cell 210 and the data line 221 and a write path between the charge storage structure 202 of the memory cell 211 and the data line 222. A current (e.g., a write current) can be formed between the charge storage structure 202 of the memory cell 210 (selected memory cell) and the data line 221. This current can affect (e.g., change) the amount of charge on the charge storage structure 202 of the memory cell 210 to reflect a value of information to be stored in the memory cell 210. A current (e.g., another write current) can be formed between the charge storage structure 202 of the memory cell 211 (selected memory cell) and the data line 222. This current can affect (e.g., change) the amount of charge on the charge storage structure 202 of the memory cell 211 to reflect a value of information to be stored in the memory cell 211.

[0062] In Figures 2 to 4 In an example write operation, the voltage V6 can have a value to discharge or charge the charge storage structure 202 of the memory cell 210 such that the resulting charge (e.g., the charge remaining after the discharge or charge action) on the charge storage structure 202 of the memory cell 210 can reflect a value of information stored in the memory cell 210. Similarly, in this example, the voltage V7 can have a value to discharge or charge the charge storage structure 202 of the memory cell 211 such that the resulting charge (e.g., the charge remaining after the discharge or charge action) on the charge storage structure 202 of the memory cell 211 can reflect a value of information stored in the memory cell 211.

[0063] As described above with reference to Figure 5As described, the connections and structure of the memory device 200 can enable cross-point operations (which can simplify the operation of the memory device 200) in which a memory cell (e.g., memory cell 210) of the memory device 200 can be accessed using a single access line (e.g., access line 241) and a single data line (e.g., data line 221) during an operation (e.g., a read or write operation) of the memory device 200. Such cross-point operations can be enabled in part due to a terminal (e.g., a source terminal) of the transistor Tl of each of the memory cells (e.g., memory cells 210-215) being coupled to a ground connection. This ground connection allows the voltage level at the terminal (e.g., the source terminal) of the transistor Tl of a selected memory cell to remain constant (e.g., remain at 0 V without switching), thereby allowing cross-point operations. The cross-point operations and structure of the memory device 200 can provide preferred memory performance compared to some conventional volatile memory devices (e.g., DRAM devices).

[0064] Figure 5 The memory device 200 is shown including additional memory cells 208 and 209 in the Y direction relative to memory cells 210 and 211, respectively. As shown in Figure 5 The memory cells 208 and 209 can share the same access line (e.g., access line 241) with the memory cells 210 and 211, as shown in Figure 5 The memory device 200 also includes memory cells (not shown, but can be similar to memory cells 208 and 209) that share access line 242 with memory cells 212 and 213 and memory cells (not shown, but can be similar to memory cells 208 and 209) that share access line 243 with memory cells 212 and 213, although not shown in

[0065] Figure 5 The physical structure of the memory device 200 can include multiple levels (e.g., multiple decks) of memory cells in which one level (e.g., one deck) of memory cells can be formed above (e.g., stacked on) another level (e.g., another deck) of memory cells. For example, memory cells 208, 209, 210, and 211 can be included in one deck (e.g., deck one), memory cells 212 and 213 can be included in another deck (e.g., deck two (lower (underneath)) of deck one), and memory cells 214 and 215 can be included in another deck (e.g., deck three (lower) of deck two).

[0066] Figures 6 to 18The structure of the memory device 200 (e.g., a multi-stack structure) may include the following references Figure 6 The structure of the described memory device.

[0067] Figure 6 The structure of a memory device 600 comprising multiple stacks (stacks of memory cells) 6050, 6051, 6052 and 6053 according to some embodiments described herein is shown. Figure 6 The X, Y, and Z directions shown can represent the directions corresponding to the three-dimensional (3-D) structure of the memory device 600. For example... Figure 6 As shown, the memory device 600 may include a substrate 699 on which stacks 6050, 6051, 6052, and 6053 may be formed. The substrate 699 may be a semiconductor substrate (e.g., a silicon-based substrate) or other types of substrate. The Z-direction (e.g., the vertical direction) is a direction perpendicular to the substrate 699 (e.g., extending outwards from the substrate). The Z-direction is also perpendicular to the X and Y directions (e.g., extending perpendicularly from the X and Y directions). The X and Y directions are perpendicular to each other. Figure 6 A memory device 600 comprising four stacks 6050, 6051, 6052, and 6053 is shown as an example. The number of stacks in the memory device 600 may vary.

[0068] like Figure 6 As shown, the memory device 600 may include layers (e.g., different vertical layers) 650, 651, 652, and 653 relative to the Z direction. Stacks 6050, 6051, 6052, and 6053 may be located (formed) in layers 650, 651, 652, and 653, respectively.

[0069] The memory device 600 may include data lines (e.g., vertical bit lines) 621, 622, 623 and 624 that are electrically separated (isolated) from each other. Figure 5 Four data lines 621, 622, 623, and 624 are shown as an example. The number of data lines in the memory device 600 can be varied. Each of the data lines (e.g., bit lines) 621, 622, 623, and 624 can be formed of a conductive material (e.g., conductive doped polysilicon, metal, or other conductive material). The conductive material of each of the data lines 621, 622, 623, and 624 can have a pillar structure extending vertically from the substrate 699.

[0070] Each of the data lines 621, 622, 623, and 624 can have a length extending (e.g., vertically extending) along a Z direction, which is a direction perpendicular to the substrate 699 (outward from the substrate). The length of each of the data lines 621, 622, 623, and 624 can extend from one deck to another deck (e.g., extending through the decks 6050, 6051, 6052, and 6053). The data lines 621, 622, 623, and 624 can correspond to Figure 6 the data lines 221, 222, 223, and 224 of the memory device 200.

[0071] As shown in Figure 6 , the deck 6053 can include memory cells 208', 209', 210', and 211', which can respectively correspond to the memory cells 208, 209, 210, and 211. In Figure 6 , the data lines 221, 222, 223, and 224 can be electrically coupled to the memory cells 208', 209', 210', and 211', respectively. The other decks 6050, 6051, and 6052 can also include memory cells (not labeled) positioned along the lengths of the data lines 221, 222, 223, and 224 of the deck 6053 and below (underneath) the respective memory cells 208', 209', 210', and 211'. Figure 6 Four memory cells in each of the decks 6050, 6051, 6052, and 6053 (e.g., the four memory cells 208', 209', 210', and 211' in the deck 6053) are shown as examples. However, the number of memory cells in the decks 6050, 6051, 6052, and 6053 of the deck 6053 can vary.

[0072] In Figure 7 , the line X-X and the line Y-Y indicate the locations of cross-sections (e.g., cross-sectional views) of a portion of the memory device 600 shown in Figure 8 and Figure 7 , respectively. For simplicity, Figure 8 and Figure 7 the descriptions focus on the details of the elements of the deck 6053. The deck 6052 (and the other decks) of the memory device 1300 can have similar elements.

[0073] Figure 6 A view (e.g., cross-sectional view) of a portion of the memory device 600 taken along the line X-X of Figure 8 . Figure 6 A view (e.g., cross-sectional view) of a portion of the memory device 600 taken along the line Y-Y of Figure 7 . As Figure 8 and Figure 9As shown in FIG. 6A, the stack 6053 can include tiers (e.g., different material layers) 709L, 719L, 711L, and 712L. Figure 10 , Figure 11 , Figure 12 and Figures 6 to 12 show perspective (e.g., 3-D) views of the tiers 709L, 719L, 711L, and 712L, respectively. In Figures 7 to 12 , like elements are given like reference numbers.

[0074] The following description is directed to Figures 7 to 12 details of the stack 6053 and some details of the stack 6052. For simplicity, detailed descriptions of like elements are not repeated in the descriptions of Figures 7 to 12 . Also for simplicity, cross-sectional lines (e.g., section lines) are omitted from most of the elements shown in Figure 7 and other figures described herein. Some elements of the memory device 600 can be omitted from a particular figure of the drawings in order not to obscure the descriptions of the elements (or elements) being described in that particular figure. The dimensions (e.g., physical structures) of the elements shown in the figures described herein are not to scale.

[0075] Figure 6 shows cross-sectional views of the stacks 6053 and 6052 taken along the line X-X of Figure 7 . As shown in Figure 8 , each of the data lines 621 and 622 can extend along the Z direction and can be electrically coupled to some of the elements of the respective memory cells 210' and 211' of the stack 6053 and 212' and 213' of the stack 6052 (e.g., the read and write channel regions of the respective transistors T1 and T2 described below). Each of the data lines 621 and 622 can be electrically separate from the access lines (e.g., the access lines 741 and 742) of the memory device 600.

[0076] Figure 6 shows cross-sectional views of the stacks 6053 and 6052 taken along the line Y-Y of Figure 8 . Figure 7 The portion of the memory device 600 shown in Figure 7 is the same as the portion of the memory device 600 shown in Figure 8 . For example, Figure 8 the data line 621 and the memory cells 210' and 212' of Figures 7 to 12As shown in FIG. 6, data line 623 can be electrically coupled to some of the elements (e.g., read and write channel regions of respective transistors Tl and T2) of the memory cells of respective tiers 6053 and 6052 (e.g., memory cells 208' of tier 6053 and memory cells 206' of tier 6052).

[0077] Reference is made to the following descriptions which respectively describe some details of tiers 709L, 719L, 711L, and 712L of memory device 1300 shown in Figure 7 Figure 9 Figure 10 Figure 11 Figure 12 Figure 7 Figure 8 Figures 9 to 12 Figure 6 Figures 7 to 12

[0078] For simplicity, Figures 7 to 12 the description of FIG. 6 focuses on elements of tier 6053. Tier 6052 can have similar elements (which are not shown in detail in FIG. 6). Figure 7

[0079] As shown in FIGS. 6 and 7, memory device 600 can include access lines 741 (e.g., word lines), which can correspond to access lines 241 of memory device 200 of FIG. 2. Access lines 741 can receive signals (e.g., word line signals) Wl to control transistors Tl and T2 (e.g., turn on or off) of memory cells (e.g., memory cells 208', 209', 210', and 211' in FIG. 6) of tier 6053. Figure 9 Figure 5 Access lines 741 can be formed of conductive regions (e.g., conductive plates) 741T and 741B. Conductive regions 741T and 741B can be respectively referred to as top and bottom conductive regions (top and bottom portions) of access lines 741. Each of conductive regions 741T and 741B can include a conductive material (e.g., conductively-doped polysilicon, metal, or other conductive material). Memory device 600 can include a conductive connection (not shown) that electrically couples conductive region 741T to conductive region 741B. Figure 6 Figure 9

[0080]

[0081] ​​​​​​​​​​​​​​​The memory device 600 can include dielectrics 725 and 735. The conductive region 741T can be electrically separated from the data lines 621 and 622 by respective dielectrics among the dielectrics 725. The conductive region 741B is electrically separated from the data lines 621 and 622 by respective dielectrics among the dielectrics 735.

[0082] As shown in Figure 7 , the conductive region 741T can have a plate-like structure (e.g., a conductive plate structure) that includes an opening (e.g., a mesh structure). Thus, Figure 12 , the conductive region 741T shown in Figure 7 may be a portion of a conductive plate shown in Figure 9 . The level 709L of the memory device 600 can include openings (e.g., spaces) 921, 922, 923, and 924 at the conductive region 741T (e.g., a top conductive region of the access line 741 of the deck 6053) that lack material (a conductive material) of the structure (e.g., a conductive plate structure) that forms the conductive region 741T. Each of the dielectrics 725 can be located at (e.g., conform to sidewalls of) a respective opening among the openings 921, 922, 923, and 924. The data lines 621, 622, 623, and 624 can pass through the respective dielectric 725 at the location of the openings 921, 922, 923, and 924. Thus, each of the data lines 621, 622, 623, and 624 can be surrounded by (and contact) the dielectric 725 at a respective opening among the openings 921, 922, 923, and 924. Thus, the data lines 621, 622, 623, and 624 are electrically separated from the conductive region 741T (by the respective dielectric 725). The conductive region 741B (e.g., a bottom conductive region of the access line 741 of the deck 6053) and the dielectric 735 Figure 9 may have structures similar to the conductive region 741T and the dielectrics 725 of Figure 7 .

[0083] As shown in Figure 5 , the memory device 600 can include an access line 742 (e.g., a word line) that can correspond to the access line 242 of Figure 6 . The access line 742 can receive a signal (e.g., a word line signal) WL2 to control the transistors T1 and T2 (e.g., turn on or off) of the memory cells (e.g., the memory cells 208', 209', 210', and 211' in Figure 7 ) of the deck 6053. The access line 742 can be used to control the memory cells (e.g., the memory cells 212' and 213' in Figure 8 ) of the deck 6052 and Figure 9The memory cell 206' contains transistors T1 and T2 (e.g., turned on or off). Access line 742 may include conductive regions 742T and 742B, electrically separated from data lines 621 and 622 via dielectrics 745 and 755, respectively. Conductive regions 742T and dielectric 745 may have similar characteristics to... Figure 9 The conductive region 741T and the dielectric 725 have a structure. The conductive region 742B and the dielectric 755 may have a structure similar to... Figure 7 The structure of the conductive region 741T and the dielectric 725.

[0084] like Figure 7 As shown, the memory device 600 may include different dielectrics located in different layers in the Z direction to electrically separate elements within the same stack (in the Z direction) and to electrically separate one stack from another. For example, as Figure 10 As shown, memory device 600 may include dielectrics 717, 718, 719, 765, 775, and 785. Dielectrics 717, 718, and 719 electrically separate elements within stack 6052 (in the Z direction). Dielectrics 765, 775, and 785 electrically separate one stack from another stack (in the Z direction).

[0085] like Figure 7 As shown, dielectric 717 may have a plate-like structure including openings (e.g., a dielectric plate structure). Therefore, Figure 10 The dielectric 717 shown in the figure can be Figure 10 The dielectric plate portion shown in the diagram. The layers 710L of the memory device 600 may include openings (e.g., spaces) 1021, 1022, 1023, and 1024 at the dielectric 717, which lack the material (dielectric material) of the structure (e.g., dielectric plate structure) forming the dielectric 717. Data lines 621, 622, 623, and 624 are... Figure 7 The corresponding openings 1021, 1022, 1023, and 1024 allow the dielectric 717 to pass through (and contact) it. Other dielectrics 718, 719, 765, 775, and 785 (…) Figure 10 It can have similar characteristics to Figure 7 The structure of dielectric 717. Two or more dielectrics 717, 718, 719, 765, 775, and 785 may have the same thickness or different thicknesses. Dielectrics 717, 718, 719, 765, 775, and 785 may have the same dielectric material or different dielectric materials. Example materials for dielectrics 717, 718, 719, 765, 775, and 785 include silicon oxide, silicon nitride, hafnium oxide (e.g., HfO2), aluminum oxide (e.g., Al2O3), or other dielectric materials.

[0086] like Figure 11As shown in FIG. 6, each of memory cells 210' and 211' can include a transistor T2, which can include a charge storage structure 702 and a material 720 electrically coupled to charge storage structure 702. Material 720 can be between charge storage structure 702 and a respective data line (e.g., data line 621 or 622). Material 720 can form a portion of a channel region (e.g., a write channel region) of transistor T2 of a respective memory cell (e.g., memory cell 210' or 211'). Material 720 can be electrically coupled to a respective data line (e.g., data line 621 or 622). Memory device 600 can include a dielectric 715, which can include portions that electrically separate memory cells 210' and 211' from each other.

[0087] As shown in FIG. 6, dielectric 715 can have a plate-like structure (e.g., a dielectric plate structure) that includes openings. Thus, Figure 7 Figure 11 Dielectric 715 as shown in FIG. 6 can be a portion of a dielectric plate. Figure 7 Level 711L of memory device 600 can include, at dielectric 715, openings 1121, 1122, 1123, and 1124 that lack material (dielectric material) of the structure (e.g., dielectric plate structure) that forms dielectric 717. Charge storage structure 702 of each of memory cells 208', 209', 210', and 211' can be located at (e.g., conform to sidewalls of) a respective one of openings 1121, 1122, 1123, and 1124. Material 720 of each of memory cells 208', 209', 210', and 211' can be located at (e.g., conform to sidewalls of) charge storage structure 702 of a respective one of memory cells 208', 209', 210', and 211'.

[0088] Data lines 621, 622, 623, and 624 can pass through and contact (e.g., can be electrically coupled to) respective material 720 (e.g., a write channel region) at locations of openings 1121, 1122, 1123, and 1124. Thus, data lines 621, 622, 623, and 624 can be electrically coupled to channel regions of respective memory cells 208', 209', 210', and 211'.

[0089] Charge storage structure 702 Figure 11 and Figure 7 may include a charge storage material (or a combination of materials), which can include a piece (e.g., a layer) of a semiconductor material (e.g., polysilicon) that can trap charge, a piece (e.g., a layer) of a metal, or a piece of material (or multiple pieces of material). The material of charge storage structure 702 and conductive regions 741T and 741B of access line 741 can be the same or can be different. ​

[0090] Material 720 of a specific memory cell (e.g., memory cell 210') Figure 11 and Figure 7 A source (e.g., source terminal), a drain (e.g., drain terminal), or a channel region (e.g., write channel region) may be formed between the source and drain of transistor T2 in the specific memory cell (e.g., memory cell 210'). For example, such as Figure 11 and Figure 7 As shown, the source, channel region, and drain of transistor T2 in memory cell 210' can be formed from a single piece of the same material (or alternatively, a single piece of the same combination of materials), such as material 720. Therefore, the source, drain, and channel region of transistor T2 in memory cell 210' can be formed from the same material (e.g., material 720) of the same conductivity type (e.g., n-type or p-type).

[0091] The material 720 (e.g., the write channel region of transistor T2) of a specific memory cell (e.g., memory cell 210') of memory device 600 may be a portion of the write path of said specific memory cell. For example, the material 720 of memory cell 210' may be a portion of the write path of memory cell 210' that can carry current (e.g., write current) during a write operation to store information in memory cell 210'. For example, during a write operation, in order to store information in memory cell 210'... Figure 7 In the memory cell 210', the material 720 of the memory cell 210' can conduct current (e.g., write current) between the data line 621 of the memory cell 210' and the charge storage structure 702. The direction of the write current can be from the data line 621 of the memory device 210' to the charge storage structure 702. In an example where the transistor T2 is an NFET (e.g., NMOS), the current (e.g., write current) can include electronic conduction (e.g., electronic conduction in the direction from the data line 621 through the material 720 (channel region of the transistor T2) of the memory cell 210' to the charge storage structure 702).

[0092] Material 720 may comprise a semiconductor material structure (e.g., a wafer (e.g., a layer)). In an example where transistor T2 is an NFET (as described above), material 720 may comprise an n-type semiconductor material (e.g., n-type silicon).

[0093] In another example, the semiconductor material forming material 720 may comprise a sheet of oxide material. Examples of oxide materials used for material 720 include semiconductive oxide materials, transparent conductive oxide materials, and other oxide materials.

[0094] As examples, the material 720 can include at least one of zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InO x , In2O3), tin oxide (SnO2), titanium oxide (TiO x ), zinc oxynitride (Zn x O y N z ), magnesium zinc oxide (Mg x Zn y O z ), indium zinc oxide (In x Zn y O z ), indium gallium zinc oxide (In x Ga y Zn z O a ), zirconium indium zinc oxide (Zr x In y Zn z O a ), hafnium indium zinc oxide (Hf x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum tin indium zinc oxide (Al x Sn y In z Zn a O d ), silicon indium zinc oxide (Si x In y Zn z O a ), zinc tin oxide (Zn x Sn y O z ), aluminum zinc tin oxide (Al x Zn y Sn z O a ), gallium zinc tin oxide (Ga x Zn y Sn z O a ), zirconium zinc tin oxide (Zr x Zn y Sn z O a ), indium gallium silicon oxide (InGaSiO), and gallium phosphide (GaP).

[0095] The use of the materials listed above in memory device 700 provides improvements and benefits to memory device 700. For example, during a read operation, in order to read information from a selected memory cell (e.g., memory cell 210'), charge from the charge storage structure 702 of the selected memory cell may leak to the transistor T2 of the selected memory cell. Using the materials listed above in the channel region of transistor T2 (e.g., material 720) can reduce or prevent this leakage. This improves the accuracy of information read from the selected memory cell and improves the retention of information stored in the memory cells of the memory device (e.g., memory device 700) described herein.

[0096] The materials listed above are examples of material 720. However, other materials different from those listed above (e.g., materials with relatively high band gaps) may be used.

[0097] like Figure 2 As shown, each of memory cells 210' and 211' may include a transistor T1, which may include a portion 710 electrically coupled to a corresponding data line (e.g., data line 621 or 622). The portion 710 may form a portion of the channel region (e.g., read channel region) of the transistor T1 of the corresponding memory cell (e.g., memory cell 210' or 211').

[0098] Memory device 600 may include a common conductive connection 797, which may be coupled to a ground connection of memory device 600 or may be a portion of the ground connection of memory device 600. For example, during operation of memory device 600, common conductive connection 797 may receive signals that may be at a ground potential (e.g., 0V). Common conductive connection 797 may also be electrically coupled to a portion 710 of transistor T1 in each of memory cells 210' and 211'. Common conductive connection 797 may be a portion of the ground connection of memory device 600. Figure 12 The grounding connection portion of the grounding connection 297 of the memory device 200.

[0099] like Figure 7 As shown, the common conductive connection 797 may have a plate-like structure including an opening (e.g., a conductive plate structure). Therefore, Figure 12 The conductive connection 797 shown in the figure can be Figure 7The portion of the conductive plate shown in the middle. The level 712L of the memory device 600 can include openings (e.g., spaces) 1221, 1222, 1223, and 1224 at the common conductive connection 797 that lack material (conductive material) of the structure (e.g., conductive plate structure) that forms the common conductive connection 797. The portion 710 of each of the memory cells 208', 209', 210', and 211' can be located at (e.g., conform to the sidewalls of) a respective one of the openings 1221, 1222, 1223, and 1224.

[0100] The data lines 621, 622, 623, and 624 can pass through and contact (e.g., can be electrically coupled to) the respective portions 710 (e.g., read channel regions) at the locations of the openings 1221, 1222, 1223, and 1224. Thus, the data lines 621, 622, 623, and 624 can be electrically coupled to the read channel regions of the respective memory cells 208', 209', 210', and 211'.

[0101] The portion 710 Figure 12 and Figure 7 may include a semiconductor material. Example materials of the portion 710 include silicon, polysilicon (e.g., undoped or doped polysilicon), germanium, silicon-germanium, or other semiconductor materials, and semiconductive oxide materials (oxide semiconductors, such as SnO or other oxide semiconductors).

[0102] The portion 710 (e.g., the read channel region of the transistor T1) of a particular memory cell (e.g., the memory cell 210') of the memory device 600 can be part of a read path of the particular memory cell. For example, the portion 710 of the memory cell 210' can be part of a read path of the memory cell 210' that can carry current (e.g., a read current) during a read operation to read information from the memory cell 210'. For example, to read information from the memory cell 210' during a read operation, the portion 710 of the memory cell 210' can conduct current (e.g., a read current) between the data line 621 and the common conductive connection 797 (e.g., a ground connection). The direction of the read current can be from the data line 221 through the portion 710 to the common conductive connection 797. In an example where the transistor T1 is a PFET (e.g., a PMOS), the current (e.g., the read current) can include hole conduction (e.g., hole conduction in a direction from the data line 621 through the portion 720 (the channel region of the transistor T1) of the memory cell 210' to the common conductive connection 797). Figure 7

[0103] ​In the example where transistor Tl is a PFET and transistor T2 is a NFET, the material forming portion 710 can have a different conductivity type than material 720. For example, portion 710 can include a region of p-type semiconductor material (e.g., p-type silicon), and material 720 can include a region of n-type semiconductor material (e.g., n-type gallium phosphide (GaP)).

[0104] As shown in Figure 8 and Figures 7 to 12 The conductive region 741T of access line 741 can straddle (e.g., overlap in the X- and Y-directions) portions of material 720 and portions of 710 of transistors T2 and Tl, respectively, belonging to each of memory cells 208', 209', 210', and 211' of deck 6053, as shown in

[0105] The conductive region 741T of access line 741 straddling (e.g., overlapping) read and write channel regions of transistors Tl and T2 allows access line 741 (a single access line) to control (e.g., turn on or off) both transistors Tl and T2 of the memory cells of deck 6053. Similarly, the conductive region 742T of access line 742 straddling (e.g., overlapping) read and write channel regions of transistors Tl and T2 allows access line 742 (a single access line) to control (e.g., turn on or off) both transistors Tl and T2 of the memory cells of deck 6052.

[0106] As mentioned above, the description regarding Figure 7 focuses on details of elements of deck 6053. Deck 6052 (and other decks) of memory device 600 can have similar elements. For example, although the description in Figures 6 to 12The levels between which stack 6052 can have different levels are not shown, but stack 6052 can have levels similar to levels 711L between which are located levels of conductive regions 742T and 742B (e.g., which are portions of respective conductive plates). For example, stack 6052 can include a level (similar to level 711L) that can include, for each of memory cells 212' and 213', dielectric 715 (e.g., a dielectric plate structure), charge storage structure 702, and material 720 (e.g., a write channel region in contact with data line 621 or 622). In another example, stack 6052 can include a level (similar to level 712L) that can include, for each of memory cells 212' and 213', common conductive connection 797 (e.g., a common conductive plate) and portion 710 (e.g., a read channel region in contact with data line 621 or 622).

[0107] The description above with reference to Figure 13 shows that elements (e.g., memory cells, access lines (conductive plates)) can be arranged (e.g., formed) in different levels (e.g., layers) one level above another on memory device 600. This can allow multiple stacks of memory device 600 to be formed commonly. Thus, the cost of forming memory device 600 (e.g., cost per bit) can be reduced.

[0108] Figures 6 to 12 A structure of memory device 1300 including multiple stacks 6050, 6051, 6052, and 6053 and vertical common conductive connection 1397 is shown in accordance with some embodiments described herein. Memory device 1300 can include elements similar to or the same as some of the elements of memory device 600 (described above). Thus, similar or identical elements between memory device 600 and memory device 1300 are given the same labels and detailed descriptions of such elements are not repeated in the description of memory device 1300. Figures 13 to 18 ) are given the same labels and detailed descriptions of such elements are not repeated in the description of memory device 1300. Figure 7

[0109] Differences between memory device 600 and 1300 include the structure and location of common conductive connection 1397. Similar to common conductive connection 797 of memory device 600 ( Figure 8 and Figure 13 ​The common conductive connection 1397 can be electrically coupled to the read channel region of transistor T1 and the ground connection of memory device 1300. However, unlike the horizontal plate structure of the common conductive connection 797 (e.g., a conductive material layer in the XY plane), the common conductive connection 1397 of memory device 1300 can have a pillar structure (e.g., a vertical pillar of conductive material) that extends in the Z direction perpendicular to substrate 699 (e.g., vertically extending). Another difference between memory devices 600 and 1300 includes the relatively small size of each of the memory cells (e.g., memory cells 208', 209', 210', and 211'), as described in more detail below.

[0110] like Figure 2 As shown, the common conductive connection 1397 may be located in the middle (e.g., center) position relative to the position defined (e.g., around) by data lines 621, 622, 623, and 624. The common conductive connection 1300 may be coupled to a ground connection or may be corresponding to... Figure 13 The grounding connection portion of the grounding connection 297 of the memory device 200. Figure 13 In this configuration, the common conductive connection 1300 can receive a signal PLT, which can be at a ground potential (e.g., PLT = 0V). The strut structure of the common conductive connection 1397 can extend from one stack to another (e.g., extending through stacks 6050, 6051, 6052, and 6053). The common conductive connection 1397 can be formed of a conductive material (e.g., conductive doped polysilicon, metal, or other conductive material). The material of the common conductive connection 1397 can be the same as the material of each of the data lines 621, 622, 623, and 624. The common conductive connection 1397 can be formed simultaneously with the data lines 621, 622, 623, and 624 (e.g., in the same process step).

[0111] like Figure 17 As shown, the memory device 1300 may include a dielectric 1395 that may extend in the Z direction (e.g., vertically) and occupy (e.g., fill) a portion (e.g., four corners) of each of the stacks 6050, 6051, 6052, and 6053. The dielectric 1395 may comprise various oxides (e.g., low-K materials or other oxides), porous oxides and air gaps, or other dielectric materials.

[0112] As described in more detail below (for example, see references) Figure 14 The dielectric 1395 may be an isolation structure that electrically separates (isolates) some elements of the memory cells in the same stack (e.g., the write channel region of transistor T2) from each other. This electrical separation also electrically separates the data lines 621, 622, 623, and 624 from each other.

[0113] existFigure 14 In particular, line Y-Y indicates Figure 14 the location of a cross-section (e.g., a cross-sectional view) of a portion of the memory device 1300 shown in Figure 14 For simplicity, the description of

[0114] Figure 13 shows a view (e.g., a cross-sectional view) of a portion of the memory device 600 taken along line Y-Y of Figure 14 As shown in Figure 15 The deck 6053 can include tiers (e.g., different material layers) 1409L, 1410L, 1411L, and 1412L, as shown in Figure 16 , Figure 17 , Figure 18 and Figure 14 show perspective views (e.g., 3-D views) of the tiers 1409L, 1410L, 1411L, and 1412L, respectively.

[0115] As shown in Figure 14 The common conductive connection 1397 can be located between the data lines 621 and 622. The common conductive connection 1397 can be electrically coupled to (e.g., can contact) portions of the memory cells 210', 211', 212', and 213'. For example, the common conductive connection 1397 can be electrically coupled to read channel regions (e.g., portions 710) of the memory cells 208' and 210' of the deck 6053 and of the memory cells 206 and 212' of the deck 6052 (not shown).

[0116] The common conductive connection 1397 can be electrically separated from the conductive regions 741T and 741B (conductive regions of the access line 741, not labeled) by the dielectrics 725 and 735, respectively. The common conductive connection 1397 can be electrically separated from the conductive regions 742T and 742B (conductive regions of the access line 742, not labeled) by the dielectrics 745 and 755, respectively.

[0117] Figure 7 Other elements of the memory device 1300 shown in Figure 8 may be similar to or the same as those of the memory device 600 shown in Figure 14 and Figure 15As shown in FIG. 14A, tiers 1409L can include conductive region 741T, dielectric 725, and dielectric 725'. Tiers 1410L can include charge storage structure 702, material 720 (e.g., write channel region of respective memory cell (e.g., memory cell 208' or 210')), and dielectrics 715 and 715' of respective memory cell (e.g., memory cell 208' or 210'). Tiers 1412L can include portion 710 (e.g., read channel region of respective memory cell) and dielectric 1415.

[0118] Reference is made to Figure 16 , Figure 17 , Figure 18 and Figure 14 The following description of Figure 15 illustrates some details (in 3-D view) of tiers 1409L, 1410L, 1411L, and 1412L of memory device 1300 shown in Figure 16 , Figure 17 , Figure 18 and Figure 14 In each of Figures 15 to 18 illustrates the corresponding position of the cross-sectional view of tiers 1409L, 1410L, 1411L, and 1412L of memory device 1300 shown in Figure 13 In each of Figures 15 to 18 also illustrates the relative positions of memory cells 208', 209', 210', and 211' of stack 6053 of memory device 1300 of Figure 13 In each of Figure 15 also illustrates the position of dielectric 1395 of memory device 1300 of

[0119] As Figure 7As shown, the layer 1409L of the memory device 1300 may include openings (e.g., spaces) 1521, 1522, 1523, 1524, and 1597 at conductive regions 741T (e.g., the top conductive regions of the access lines of the stack 6053). Dielectrics 725 and 725' may be located at the respective openings 1521, 1522, 1523, and 1524 (e.g., adapted to the sidewalls of the respective openings). Data lines 621, 622, 623, 624, and a common conductive connection 1397 may pass through the respective dielectrics 725 and 725' at the locations of the respective openings 1521, 1522, 1523, 1524, and 1597. Therefore, each of the data lines 621, 622, 623, 624 and the common conductive connection 1397 may be surrounded (and contacted) by a dielectric (e.g., dielectric 725 or 725') at a corresponding opening in the openings 1521, 1522, 1523, 1524 and 1597. Thus, the data lines 621, 622, 623, 624 and the common conductive connection 1397 are electrically separated from the conductive region 741T (through the respective dielectrics 725 and 725'). The conductive region 741B (e.g., the bottom conductive region of the access lines of the stack 6053) and the dielectric 735 ( Figure 15 It can have similar characteristics to Figure 16 The structure of the conductive region 741T and the dielectric 725.

[0120] like Figure 16 As shown, the layer 1410L of the memory device 1300 may include openings (e.g., spaces) 1621, 1622, 1623, 1624, and 1697 at the dielectric 717, which lacks a material (dielectric material) for the structure (e.g., a plate-like structure) forming the dielectric 717. Data lines 621, 622, 623, and 624, and the common conductive connection 1397 are in... Figure 14 The corresponding openings 1621, 1622, 1623, 1624, and 1697 allow passage (and contact) with dielectric 717. Other dielectrics 717, 718, 719, 765, 775, and 785 (…) Figure 16 It can have similar characteristics to Figure 17 The structure of dielectric 717.

[0121] like Figure 17 As shown, each of the memory cells 208', 209', 210', and 211' may include a dielectric 715, a material 720 (e.g., a write channel region), and a charge storage structure 702. The material 720 and the charge storage structure 702 of the memory cells 208', 209', 210', and 211' may be electrically separated from each other by a dielectric 1395.

[0122] like Figure 17As shown in the middle, the level 1411L of the memory device 1300 can include openings (e.g., spaces) 1721, 1722, 1723, and 1724. Each of the openings 1721, 1722, 1723, and 1724 can have sidewalls (not labeled) formed by a portion of the material 720 (e.g., a write channel region) and a portion of one of the dielectrics 715 of a respective memory cell (one of the memory cells 208', 209', 210', and 211'). The data lines 621, 622, 623, and 624 can pass through and contact (e.g., can be electrically coupled to) the respective material 720 (e.g., a write channel region) at the locations of the openings 1721, 1722, 1723, and 1724. Thus, the data lines 621, 622, 623, and 624 can be electrically coupled to the channel regions of the respective memory cells 208', 209', 210', and 211'.

[0123] The level 1411L of the memory device 1300 can also include an opening (e.g., a space) 1797. The opening 1797 can have sidewalls (not labeled) formed by a portion of the charge storage structure 702 of each of the memory cells 208', 209', 210', and 211'. The dielectric 715' can be located at (e.g., conform to the sidewalls of) the opening 1797. The common conductive connection 1397 can pass through and can be surrounded by (and in contact with) the dielectric 715' at the location of the opening 1797. Thus, the common conductive connection 1397 is electrically separated from the charge storage structure 702 of each of the memory cells 208', 209', 210', and 211'.

[0124] The process of forming the level 1411L of the memory device 1300 (shown in the middle) Figure 17 ) can include forming a semiconductor material (which is later to become a write channel region), forming a charge storage material (surrounded by the semiconductor material), and forming the dielectric 715' (surrounded by the charge storage material). Then, portions of each of the semiconductor material, the charge storage material, and the dielectric 715' (at locations where the dielectric 1395 is to be later formed) can be removed (e.g., by etching). Then, the locations of the removed portions (e.g., empty spaces) of each of the semiconductor material, the charge storage material, and the dielectric 715' can be filled with a dielectric material. The dielectric 1395 can be a portion of the dielectric material.

[0125] Figure 17This demonstrates how the charge storage structure 702 of one memory cell can be electrically separated from the charge storage structure 702 of another memory cell via a corresponding dielectric 1395. However, in an alternative configuration of the memory device 1300, the charge storage structures 702 of two adjacent memory cells or all four memory cells among memory cells 208', 209', 210', and 211' can be electrically coupled to each other. For example, Figure 18 The diagram shows the extension into dielectric 715', thereby electrically separating the corners (four corners) of dielectric 1395 adjacent to opening 1797 of charge storage structure 702. However, in an alternative structure, the corners (four corners) of dielectric 1395 adjacent to opening 1797 may not extend into dielectric 715' and may partially extend into charge storage structure 702. Therefore, in this alternative structure, dielectric 1395 does not completely separate charge storage structures 702 from each other. Thus, in this alternative structure of memory device 1300, charge storage structures 702 may be electrically coupled to each other.

[0126] like Figures 6 to 12 As shown, the hierarchy 1412L of the memory device 1300 may include openings (e.g., spaces) 1821, 1822, 1823, and 1824. Each of the openings 1821, 1822, 1823, and 1824 may have a sidewall (not labeled) formed by a portion 710 of the corresponding memory cell (one of memory cells 208', 209', 210', and 211') (e.g., a read channel region) and a portion of one of the dielectrics 1415. Data lines 621, 622, 623, and 624 may pass through and contact (e.g., be electrically coupled to) the corresponding portion 710 (e.g., the read channel region) at the locations of the openings 1821, 1822, 1823, and 1824. Therefore, data lines 621, 622, 623 and 624 can be electrically coupled to the read channel regions of the corresponding memory cells 208', 209', 210' and 211'.

[0127] The level 1411L of the memory device 1300 may also include an opening (e.g., a space) 1897. The opening 1897 may have sidewalls (not labeled) formed by portions 710 of each of the memory cells 208', 209', 210', and 211'. A common conductive connection 1397 may pass through and contact (e.g., be electrically coupled to) the portion 710 at the location of the opening 1897. Therefore, the common conductive connection 1397 may be electrically coupled to the read channel regions of the respective memory cells 208', 209', 210', and 211'.

[0128] Compared to memory device 600 ( Figures 13 to 18 ), memory device 1300 ( Figure 14A relatively high number of memory cells can be achieved for a given region. This can be attributed to the relative positions of the memory cells (e.g., memory cells 208', 209', 210', and 211') and the common conductive connection 1397 of the memory device 1300.

[0129] As mentioned above, the dimensions (e.g., physical structures) of the components shown in the diagrams described herein are not scaled. Therefore, although some of the components shown in the diagrams are depicted as different sizes (e.g., different thicknesses and / or different diameters in the Z direction), such components may have the same (e.g., substantially the same) dimensions (e.g., the same thickness and / or the same diameter). For example, as... Figure 15 , Figure 17 and Figure 14 As shown, dielectric 725' ( Figure 15 and Figure 14 ) and dielectric 715' ( Figure 17 and Figure 14 Dielectrics 715' and 725' can have different diameters, with 715' having a larger diameter than 725'. However, dielectrics 715' and 725' can also have the same diameter. As an example, the diameter of dielectric 725' can be formed to be relatively large (greater than 725'). Figure 14 The diameter shown in the figure) allows the diameter of dielectric 725' to be the same as that of dielectric 715'. Similarly, dielectrics 735, 745, and 755 (which are adjacent to the common conductive connection 1395) Figures 1 to 18 The diameter of ) can be formed to be the same as the diameter of dielectric 715'.

[0130] The description of the apparatus (e.g., memory devices 100, 200, 600, and 1300) and methods (e.g., operation of memory devices 100 and 200) is intended to provide a general understanding of the structure of the various embodiments and is not intended to provide a complete description of all elements and features of an apparatus that may utilize the structure described herein. Apparatus herein refers to, for example, a device (e.g., any of memory devices 100, 200, 600, and 1300) or a system (e.g., an electronic article that may include any of memory devices 100, 200, 600, and 1300).

[0131] The above reference Figures 1 to 18Any of the described components can be implemented in a variety of ways, including via software simulation. Thus, a device (e.g., memory devices 100, 200, 600, and 1300) or portions of each of these memory devices described above can each be characterized herein as “a plurality of modules” (or “module”). Such modules can include hardware circuitry, single- and / or multi-processor circuitry, memory circuitry, software program modules and objects, and / or firmware, and combinations thereof, as needed and / or suitable for the particular implementation of various embodiments. For example, such modules can be included in system operation simulation packages, such as software electrical signal simulation packages, power usage and range simulation packages, capacitance-inductance simulation packages, power / heat dissipation simulation packages, signal transmission-reception simulation packages, and / or combinations of software and hardware for operating or simulating the operation of various possible embodiments.

[0132] The memory devices described herein (e.g., memory devices 100, 200, 600, and 1300) can be included in devices (e.g., electronic circuitry) such as high-speed computers, communications and signal processing circuitry, single- or multi-processor modules, single or multiple embedded processors, multi-core processors, message information switches, and application-specific modules including multi-layer, multi-chip modules. Such devices can further be included as subcomponents within a variety of other devices (e.g., electronic systems), such as televisions, cellular telephones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., MP3 (Motion Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (e.g., heart monitors, blood pressure monitors, etc.), set-top boxes, and others.

[0133] The above references ​ The described embodiments include devices and methods that use a substrate, a pillar having a length perpendicular to the substrate, a first conductive plate, a second conductive plate, a memory cell located between the first conductive plate and the second conductive plate and electrically separated from the first and second conductive plates, and a conductive connection. The first conductive plate is located in a first level of the device and separated from the pillar by a first dielectric located in the first level. The second conductive plate is located in a second level of the device and separated from the pillar by a second dielectric located in the second level. The memory cell includes a first semiconductor material located in a third level of the device between the first level and the second level and in contact with the pillar and the conductive connection, and a second semiconductor material located in a fourth level of the device between the first level and the second level and in contact with the pillar. Other embodiments including additional devices and methods are described.

[0134] In the implementations and claims, the term "on" as used with respect to two or more elements (e.g., materials) means at least some contact between the elements (e.g., materials). The term "over" means close proximity with one or more additional intervening elements (e.g., materials) such that contact is possible but not necessary. Neither "on" nor "over" implies any directionality as used herein unless so stated.

[0135] In the implementations and claims, a list of items joined by the term "at least one of can mean any combination of the listed items. For example, if items A and B are listed, the phrase "at least one of A and B" means A alone, B alone, or A and B. In another example, if items A, B, and C are listed, the phrase "at least one of A, B, and C" means A alone, B alone, C alone, A and B (excluding C), A and C (excluding B), B and C (excluding A), or all of A, B, and C. Item A can include a single element or multiple elements. Item B can include a single element or multiple elements. Item C can include a single element or multiple elements.

[0136] In the implementations and claims, a list of items joined by the term "one of can mean only one of the listed items. For example, if items A and B are listed, the phrase "one of A and B" means A alone (excluding B) or B alone (excluding A). In another example, if items A, B, and C are listed, the phrase "one of A, B, and C" means A alone, B alone, or C alone. Item A can include a single element or multiple elements. Item B can include a single element or multiple elements. Item C can include a single element or multiple elements.

[0137] The above description and drawings illustrate some embodiments of the inventive subject matter to enable a person skilled in the art to practice the embodiments of the inventive subject matter. Other embodiments can incorporate structural, logical, electrical, process, and other changes. Examples merely typify possible variations. Parts and features of some embodiments can be included in, or substituted for, those of other embodiments. Many other embodiments, not listed above, will be readily apparent to one of ordinary skill in the art having the benefit of this disclosure. The scope of the inventive subject matter is not intended to be limited to the described embodiments, but is intended to be accorded the widest scope consistent with the claims.

Claims

1. An apparatus comprising: a substrate: a pillar having a length perpendicular to the substrate; a first conductive plate in a first level of the apparatus, the first conductive plate separated from the pillar by a first dielectric in the first level; a second conductive plate in a second level of the apparatus, the second conductive plate separated from the pillar by a second dielectric in the second level; a memory cell between and electrically separated from the first conductive plate and the second conductive plate, the memory cell including a first semiconductor material in a third level of the apparatus between the first level and the second level and in contact with the pillar and a second semiconductor material in a fourth level of the apparatus between the first level and the second level and in contact with the pillar; and a conductive connection in contact with the first semiconductor material.

2. The apparatus of claim 1, wherein the conductive connection includes a conductive plate in the third level.

3. The apparatus of claim 2, wherein the conductive plate includes a portion surrounding and in contact with the first semiconductor material.

4. The apparatus of claim 1, wherein the conductive connection is to be coupled to a ground connection of the apparatus.

5. The apparatus of claim 1, wherein the conductive connection includes an additional pillar having a length perpendicular to the substrate, and the additional pillar includes a portion in the first level and in contact with the first semiconductor material.

6. The apparatus of claim 1, wherein the first semiconductor material and the second semiconductor material have different conductivity types.

7. The apparatus of claim 1, wherein the first semiconductor material includes polysilicon and the second semiconductor material comprises a semiconductive oxide material.

8. The apparatus of claim 1, wherein the memory cell further includes a charge storage structure in the second level and in contact with the second semiconductor material, the second semiconductor material between the pillar and the charge storage structure.

9. An apparatus comprising: a first pillar having a length perpendicular to a substrate; a second pillar having a length perpendicular to the substrate; a first memory cell including a first semiconductor material in a first level of the apparatus, the first semiconductor material in contact with the first pillar; a second memory cell including a first additional semiconductor material in the first level, the first additional semiconductor material in contact with the second pillar; and a first conductive plate in the first level of the apparatus, the conductive plate in contact with the first semiconductor material and the first additional semiconductor material; a second conductive plate in a second level of the apparatus, the second conductive plate separated from the first pillar by a first dielectric in the second level and separated from the second pillar by a second dielectric in the second level. ​ 10. The apparatus of claim 9, wherein the first conductive plate is to be coupled to a ground connection and the second conductive plate is part of an access line of the apparatus.

11. The apparatus of claim 9, further comprising a third conductive plate in a third level of the apparatus, the third conductive plate separated from the first pillar by a first additional dielectric in the third level and separated from the second pillar by a second additional dielectric in the third level, wherein the first memory cell and the second memory cell are between the second conductive plate and the third conductive plate.

12. The apparatus of claim 9, wherein: the first memory cell includes a first charge storage structure and a first additional semiconductor material in a third level of the apparatus, and the first additional semiconductor material is in contact with the first pillar and the first charge storage structure; the second memory cell includes a second charge storage structure and a second additional semiconductor material in the third level of the apparatus, and the second additional semiconductor material is in contact with the second pillar and the second charge storage structure.

13. The apparatus of claim 12, wherein each of the first additional semiconductor material and the second additional semiconductor material comprises a semiconductive oxide material.

14. An apparatus comprising: a first pillar having a length perpendicular to a substrate; a second pillar having a length perpendicular to the substrate; a third pillar having a length perpendicular to the substrate; a first memory cell including a first semiconductor material in a first level of the apparatus, the first semiconductor material in contact with the first pillar and the third pillar; a second memory cell including a first additional semiconductor material in the first level, the first additional semiconductor material in contact with the second pillar and the third pillar; and a conductive plate in a level of the apparatus, the conductive plate separated from the first pillar by a first dielectric, separated from the second pillar by a second dielectric, and separated from the third pillar by a third dielectric, the first, second, and third dielectrics in a second level.

15. The apparatus of claim 14, wherein each of the first pillar and the second pillar is part of a data line of the apparatus, the third pillar is to be coupled to a ground connection, and the conductive plate is part of a word line of the apparatus.

16. The apparatus of claim 14, wherein: the first memory cell includes a first charge storage structure and a first additional semiconductor material in an additional level of the apparatus, and the first additional semiconductor material is in contact with the first pillar and the first charge storage structure; the second memory cell includes a second charge storage structure and a second additional semiconductor material in the additional level, and the second additional semiconductor material is in contact with a second pillar and the second charge storage structure; and Each of the first and second charge storage structures is separated from the third pillar by an additional dielectric located in the additional level.

17. The apparatus of claim 14, further comprising an additional conductive plate located in a third level of the apparatus, the additional conductive plate separated from the first pillar by a first additional dielectric, separated from the second pillar by a second additional dielectric, and separated from the third pillar by a third additional dielectric, wherein the first, second, and third additional dielectrics are located in the third level.

18. The apparatus of claim 14, wherein the first and second semiconductor materials are electrically coupled to one another.

19. The apparatus of claim 14, wherein the conductive plate includes a portion that surrounds and is in contact with the third dielectric.

20. The apparatus of claim 14, wherein the third pillar is between the first and second pillars.

21. An apparatus comprising: a pillar having a length perpendicular to a substrate; a memory cell including a first transistor and a second transistor, the first transistor including a first channel region located in a first level of the apparatus, the second transistor including a second channel region located in a second level of the apparatus, each of the first and second channel regions in contact with the pillar; a first conductive plate located in a third level of the apparatus, the first conductive plate separated from the pillar by a first dielectric located in the third level; a second conductive plate located in a fourth level of the apparatus, the second conductive plate separated from the pillar by a second dielectric located in the fourth level, wherein the first and second levels are between the third and fourth levels; and a conductive connection electrically coupled to the first channel region.

22. The apparatus of claim 21, wherein the conductive connection includes a conductive plate, and the conductive plate includes a portion that surrounds the first channel region.

23. The apparatus of claim 21, wherein the conductive connection includes a pillar having a length perpendicular to a substrate, and the pillar of the conductive connection includes a portion located in the first level and in contact with the first channel region.

24. The apparatus of claim 21, wherein the first and second transistors have different transistor types.

25. The apparatus of claim 21, wherein the second channel region comprises at least one of: zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InO x , In2O3), tin oxide (SnO2), titanium oxide (TiO x ), zinc oxynitride (Zn x O y N z ), magnesium zinc oxide (Mg x Zn y O z ), indium zinc oxide (In x Zn y O z ), indium gallium zinc oxide (In x Ga y Zn z O a ), zirconium indium zinc oxide (Zr x In y Zn z O a ), hafnium indium zinc oxide (Hf x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum tin indium zinc oxide (Al x Sn y In z Zn a O d ), silicon indium zinc oxide (Si x In y Zn z O a ), zinc tin oxide (Zn x Sn y O z ), aluminum zinc tin oxide (Al x Zn y Sn z O a ), gallium zinc tin oxide (Ga x Zn y Sn z O a ), zirconium zinc tin oxide (Zr x Zn y Sn z O a ), indium gallium silicon oxide (InGaSiO), and gallium phosphide (GaP).

26. An apparatus comprising: a substrate: a first deck located over the substrate; a second deck located over the first deck; a pillar extending through the first and second decks, each of the first and second decks including a memory cell, the memory cell including: a first transistor and a second transistor, the first transistor including a first channel region located in a first level of the apparatus, the second transistor including a second channel region located in a second level of the apparatus, each of the first and second channel regions in contact with the pillar; a first conductive plate located in a third level of the apparatus, the first conductive plate separated from the pillar by a first dielectric located in the third level; a second conductive plate located in a fourth level of the apparatus, the second conductive plate separated from the pillar by a second dielectric located in the fourth level, wherein the first and second levels are between the third and fourth levels; and a conductive connection electrically coupled to the first channel region. a memory cell including a first semiconductor material in a first level of a respective stack among the first stack and the second stack and a second semiconductor material in a second level of the respective stack, each of the first semiconductor material and the second semiconductor material being in contact with the pillar; a first conductive plate in a third level of the respective stack, the first conductive plate being separated from the pillar by a first dielectric in the third level of the respective stack; and a second conductive plate in a fourth level of the respective stack, the second conductive plate being separated from the pillar by a second dielectric in the fourth level of the respective stack.

27. The apparatus of claim 26, wherein: the first stack further includes a first conductive plate, and the first conductive plate includes a portion that surrounds and is in contact with the first semiconductor material of the memory cell of the first stack; and the second stack further includes a second conductive plate, and the second conductive plate includes a portion that surrounds and is in contact with the first semiconductor material of the memory cell of the second stack.

28. The apparatus of claim 26, further comprising an additional pillar having a length that extends through the first stack and the second stack, and the additional pillar is in contact with the first semiconductor material of each of the first stack and the second stack.

29. The apparatus of claim 26, wherein the first semiconductor material includes polysilicon, and the second semiconductor material comprises a semiconductive oxide material.

30. The apparatus of claim 26, wherein the memory cell of each of the first stack and the second stack further includes a charge storage structure in the second level of the respective stack and in contact with the second semiconductor material of the respective stack. ​

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