Two-step self-test circuit for microcontroller unit and antenna

Abstract

A system (100) is disclosed. The system (100) includes an antenna (150) and a processor (105). The processor (105) has at least four ports: a first input port coupled to a first portion of a continuity component; a first output port coupled in series to a first resistor (160) coupled to a first portion of the antenna (150) and connected to ground via a second resistor (170); a second output port coupled to the first portion of the antenna (150) through a third resistor (180); and a second input port coupled to a second portion of the antenna (150) and connected to ground via a fourth resistor (190). The processor (105) is operable to activate and deactivate appropriate ports to place the processor (105) in one of three operating modes: an AC detection mode, an AC self-test mode, and a continuity test mode.

Description

[0001] This application is a divisional application of the Chinese invention patent application with the application date of August 11, 2017, application number 201780059056.6, and invention name “Two-step self-test circuit for microcontroller unit and antenna”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to U.S. Provisional Application No. 62 / 375,563, filed on August 16, 2016, the entire contents of which are incorporated herein by reference in their entirety. Background Art

[0004] Electricians often have to work on electrical wires, and they need to ensure that the lines are not hot or live. Therefore, it becomes prudent and necessary to test if the lines are hot before starting work. Electricians will use a non-contact voltage ("NCV") detector to test if the lines are hot. These non-contact voltage detectors are very useful because there is no need to touch the line to tell the voltage status of the line. However, non-contact voltage detectors are subject to faults that can produce dangerous false negative results. For example, a non-contact voltage detector may have a weak battery or a broken wire at the antenna. Conventional non-contact voltage detectors cannot detect many of these fault conditions, resulting in potentially unsafe working conditions for electricians. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate various embodiments of the present disclosure. In the drawings:

[0006] Figure 1 An embodiment of a non-contact voltage detector 100 and a self-test circuit is shown.

[0007] Figure 2 An embodiment of a non-contact voltage detector 100 and a self-test circuit operating in an AC detection mode is shown.

[0008] Figure 3 An embodiment of a non-contact voltage detector 100 and a self-test circuit operating in an AC self-test mode is shown.

[0009] Figure 4 An embodiment of a non-contact voltage detector 100 and a self-test circuit operating in a continuity test mode is shown.

[0010] Figure 5 An embodiment of a non-contact voltage detector 100 and self-test circuit is shown that is modified to increase sensitivity, reduce circuit loading, and facilitate component selection.

[0011] Figure 6A second embodiment of a non-contact voltage detector and a self-test circuit.

[0012] Figure 7 A third embodiment of a similar non-contact voltage detector and self-test circuit is provided. DETAILED DESCRIPTION

[0013] Overview

[0014] A two-step self-test apparatus and method for testing NCV detectors has been designed. Although the discussion of this embodiment will be about NCV detectors, the test equipment can be incorporated into other test facilities, including but not limited to, for example, clamp meters and multimeters. Because the technology can be incorporated into a wide range of critical circuits and components, it can provide users with an increased safety margin.

[0015] The disclosed embodiment performs AC signal path testing and antenna continuity verification in two separate stages. This allows each stage to be optimized independently to produce the most reliable results. The AC signal path test can perform more critical sensitivity testing without considering the coupling between the long parallel traces from the self-test source and the detection circuit on the printed circuit board. When injecting a simulated AC test signal into the antenna, the antenna continuity verification can use a higher test current than the test current that can be used in the prior art system. Compared with the prior art system, this higher test current is more effective in detecting critical antenna connections of the printed circuit board. The embodiment uses a microcontroller unit ("MCU") or processor in combination with a resistor and an antenna to capacitively couple to the conductor to be tested to test the presence of AC voltage. The processor has multiple ports. When the system is in AC detection mode, the first port is used as an input for AC voltage detection from the antenna. When the system is in AC self-test mode, the second port can be used to inject a signal through the resistor and into the first port. When in continuity test mode, the third port and the fourth port in combination with a pair of resistors can be used to inject a signal through the antenna. Thus, the system can operate in two different test modes: AC self-test mode and continuity test mode. The system can periodically enter these modes for short periods of time (e.g., less than 2 ms during normal AC detection operating mode), or the test mode can be triggered by the end user.

[0016] The system includes an antenna and a processor. The processor has a plurality of ports: a first input port coupled to a first portion of the antenna; a first output port coupled in series to a first resistor, the first resistor coupled to the first portion of the antenna and connected to ground via a second resistor; a second output port coupled to the first portion of the antenna via a third resistor; and a second input port coupled to the second portion of the antenna and connected to ground via a fourth resistor. The processor is operable to activate and deactivate appropriate ports to place the processor in one of three operating modes: an AC detection mode, a self-test mode, and a continuity test mode.

[0017] An alternative system includes an antenna and a processor. The processor has a plurality of ports: a first input port coupled to a first portion of the antenna; a first output port coupled in series to a first resistor and a second resistor to ground, the junction of the first resistor and the second resistor being coupled to the first portion of the antenna directly or through a fifth resistor; a second output port coupled to the first portion of the antenna through a third resistor; and a second input port coupled to the second portion of the antenna directly or through a switch and to ground through a fourth resistor. The processor is operable to activate and deactivate the appropriate ports to place the processor in one of three operating modes: an AC detection mode, a self-test mode, and a continuity test mode.

[0018] A method of testing and using an antenna by operating in a plurality of modes including an operating mode is also disclosed. The method operates in one of three modes. In a first mode, an AC signal from a first output port is injected into a circuit at a first leg of the antenna, and the presence of the AC signal is detected at a first input port. In a second mode, a voltage from a second output port is injected through the antenna, and the presence of a portion of the voltage is detected at a second input port. In a third mode, a signal from the antenna is received at the first input port.

[0019] Another system is also disclosed. The system includes an antenna having a first portion and a second portion and a processor. The processor has: a first input port coupled to the first portion of the antenna; a first output port coupled in series to a first resistor, the first resistor coupled to the first portion of the antenna and to ground via a second resistor; and a second output port coupled to the second portion of the antenna via a third resistor.

[0020] The disclosed additional system has an antenna having a first portion and a second portion, and a processor. The processor has a first input port coupled to the first portion of the antenna, a first output port coupled in series to a first resistor coupled to the first portion of the antenna and to ground via a second resistor, a second output port coupled to the second portion of the antenna via a third resistor, and a second input port coupled to the first portion of the antenna and to ground via a fourth resistor.

[0021] The foregoing overview and the following example embodiments are merely exemplary and illustrative and should not be construed as limiting the scope of the present disclosure as described and claimed. In addition, features and / or variations other than those set forth herein may also be provided. For example, embodiments of the present disclosure may relate to various feature combinations and sub-combinations described in the example embodiments.

[0022] Example Embodiments

[0023] The following detailed description refers to the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the following description to refer to the same or similar elements. Although embodiments of the present disclosure may be described, modifications, adaptations, and other implementations are possible. For example, the elements shown in the drawings may be replaced, added, or modified, and the methods described herein may be modified by replacing, reordering, or adding stages to the disclosed methods. Therefore, the following detailed description does not limit the present disclosure. On the contrary, the proper scope of the present disclosure is defined by the appended claims.

[0024] Figure 1 An embodiment of a non-contact voltage detector 100 and a self-test circuit is shown. The test system 100 includes a processor 105 having an input terminal I1, an output terminal O1, an input terminal I2, and an output terminal O2. The processor can be a microprocessor, a microcontroller, a digital signal processor, or replaced with an equivalent analog and / or digital circuit to affect the desired performance of the circuit. The input terminal I1 is coupled to a switch S1 110 in the processor 105 and a first portion of an antenna 150. The output terminal O1 is coupled to a switch S2 120 in the processor 105 and is coupled to the first portion of the antenna 150 and the input terminal I1 via a resistor R1 160. The resistor R1 160 is also grounded via a resistor R2 170 at the same node as the one coupled to the antenna 150. The output terminal O2 is coupled in series with a resistor R3 180 through the antenna 150 to the input terminal I2, and is grounded through a resistor R4 190. The output terminal O2 is further coupled to the switch S3 130 , and the input terminal I2 is further coupled to the switch S4 140 .

[0025] Input terminal I1 is used to detect AC voltage via switch S1 110. Output terminal O1 is used to output self-test voltage via switch S2 120. Output terminal O2 is used to provide continuity source voltage. And, input terminal I2 is used to detect continuity through antenna 150. Figures 2 to 4 The use of this circuit is described in more detail in .

[0026] Figure 2 An embodiment of a non-contact voltage detector 100 and self-test circuit operating in an AC detection mode is shown. When operating in the AC detection mode, switches S2 120, S3 130, and S4 140 are all open; switch S1 110 is closed. In the AC detection mode, if there is an AC voltage capacitively coupled to the antenna, the AC voltage is received by the processor 105 and the AC voltage can be indicated to the user. The indication can be in the form of a light, sound, and / or display of the detected voltage.

[0027] Figure 3 An embodiment of a non-contact voltage detector 100 and a self-test circuit operating in an AC self-test mode is shown. In the AC self-test mode, switches S1 110 and S2 120 are closed; switches S3 130 and S4 140 are open. When the AC signal path is self-tested, the second port can be configured as a digital output port. Port S2 120 is alternately coupled between the battery voltage or some other boosted or bucked battery voltage and the circuit common. This generates an analog AC signal, which is applied to port I1 via resistor R1 160. The AC signal will also flow through resistor R2 170 to reach the ground terminal. Resistors R1 160 and R2 170 are sized to provide the desired test amplitude. Unlike prior art systems, the analog AC self-test signal does not flow through the antenna. The processor 105 will check the signal received via switch S1 110 to determine whether the AC self-test is successful or failed. If the AC self-test fails, the user of the unit may be notified by lights, buzzers or some other indication. In addition, the unit may be disabled from operating in the AC detection mode and the user may be notified.

[0028] Figure 4An embodiment of a non-contact voltage detector 100 and a self-test circuit operating in a continuity test mode is shown. In the continuity test mode, switches S1 110 and S2 120 are open; switches S3 130 and S4 140 are closed. Port O2 provides a source of antenna continuity test signals. This port is coupled to a battery voltage or some boosted or reduced battery voltage inside the processor 105. Port O2 is coupled to a first portion of the antenna 150 via resistor R3 180. Based on the output voltage at port O2 and the relative size of resistors R3 180 and R4 190, the processor 105 will then detect an expected voltage value via input terminal I2 and switch S4 140. A connection failure between the first antenna portion and the printed circuit board or between the second antenna portion and the printed circuit board will result in a deviation from the expected value measured at input terminal I2. This continuity test can be performed with a test current that is several orders of magnitude larger than the normal injection signal and can produce more reliable and consistent results when looking for critical connections. This is an improvement over prior art systems which are not able to detect continuity through the antenna, so if the antenna or probe is broken in a prior art system, the prior art system can still pass the self-test.

[0029] Figure 5 is similar to Figure 1 An embodiment of a non-contact voltage detector 100 and a self-test circuit is provided which is improved to increase sensitivity, reduce circuit loading and facilitate component selection. Those skilled in the art will recognize that resistors R2 170 and R4 190 have very high values ​​to avoid reducing the sensitivity of the detection circuit. The addition of R5 200 having a high resistance value eliminates the reduction in sensitivity that may be caused by selecting convenient values ​​for R1 160 and R2 170 when establishing the amplitude of the AC self-test signal. The addition of switch S5 210 isolates resistor R4 190 in situations other than performing a continuity test. Switch S5 210 is disconnected in all modes except during a continuity test and may be an analog switch, a field effect transistor, or any other suitable low leakage discrete or integrated component. It may be activated by output O2 or other convenient means. Those skilled in the art will recognize that the addition of resistor R5 200 and switch S5 210 does not change the reference Figures 2 to 4 The basic principle of operation is disclosed.

[0030] Figure 6 is similar to Figure 5The embodiment of the non-contact voltage detector 100 and self-test circuit is shown in Figure 1, except that the antenna connection for the continuity test mode is reversed. Port O2 is coupled to the second portion of the antenna 150 via resistor R3 180 instead of the first portion. Additionally, the continuity test mode component consisting of resistor R4 190 in series with switch S5 210, together with input terminal I2, is coupled to the first portion of the antenna instead of the second portion. The operation of the continuity test mode (including the operation of all five switches) is unchanged relative to the previous description.

[0031] Figure 7 is similar to Figure 6 An embodiment of the non-contact voltage detector 100 and self-test circuit is provided, except that the input terminal I1 performs the AC voltage detection function and the continuity detection function. This has the advantage of requiring one less input terminal on the processor 105. In this embodiment, the input terminal I2 is not used, and the switch S1 110 on the input terminal I1 is closed in all operating modes and is therefore optional. Switches S2 120 and S3 130 operate as previously described: when operating in the AC self-test mode, switch S2 120 is closed and switch S3 130 is open; and when operating in the continuity test mode, switch S2 120 is open and switch S3 130 is closed.

[0032] A user of the system 100 can easily switch between the operating modes by using a mechanical switch, button, or other method. The system 100 can be converted from a first operating mode to any other operating mode. However, if the system fails the self-test mode or the continuity test mode, the system 100 may be disabled and cannot enter the AC detection mode.

[0033] When the user puts the system in AC detection mode, the system may also periodically enter either or both of the test modes for very short durations. In this way, the system may periodically (e.g., every two seconds) check its integrity even during operation. With this feature, when the user puts the system in AC detection mode, it may initially perform an AC self-test and a continuity test. It will then enter AC detection mode and periodically (e.g., every two seconds) briefly (on the order of milliseconds) enter either or both of the AC self-test mode and the continuity detection mode. In this way, the system periodically checks its integrity.

[0034] Embodiments of the present disclosure may be practiced in circuits including discrete electronic components, packaged or integrated electronic chips containing logic gates, using microprocessors, or on a single chip including electronic components or microprocessors. Embodiments of the present disclosure may also be practiced using other technologies (including but not limited to mechanical, optical, and quantum technologies) that can perform logical operations such as AND, OR, and NOT, for example. In addition, embodiments of the present disclosure may be practiced in general-purpose computers or any other circuits or systems. Throughout the above discussion, reference has been made to switches, and those skilled in the art will understand after reading this disclosure that active components such as operational amplifiers or transistors may also be used.

[0035] Although the description includes examples, the scope of the present disclosure is indicated by the following claims. In addition, although the description has been described in language specific to structural features and / or method actions, the claims are not limited to the above-mentioned features or actions. On the contrary, the specific features and actions described above are disclosed as examples for embodiments of the present disclosure.

[0036] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A system for testing an antenna, comprising: an antenna having a first portion and a second portion; as well as Processor with: a first input port coupled to the first portion of the antenna; a first output port coupled in series to a first resistor coupled to the first portion of the antenna and to ground via a second resistor; a second output port coupled to the second portion of the antenna through a third resistor, wherein when the processor is in an AC self-test mode, the first input port and the first output port are both active and the second output port is inactive, and wherein when the processor is in a continuity test mode, the first input port and the second output port are both active and the first output port is inactive, and wherein in the continuity test mode, a test signal is injected through the antenna.

2. The system according to claim 1, wherein: When the processor is in AC detection mode, the first input port is active, and the first output port and the second output port are inactive.

3. The system according to claim 1, wherein: An alternating voltage is applied to the first output port.

4. The system according to claim 3, wherein: The first input port detects the presence of the AC voltage.

5. The system according to claim 3, wherein: When the first input port fails to detect the presence of the AC voltage, a self-test failure is indicated.

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