Circuits, chips and electronic devices

Abstract

The present application provides a circuit, a chip and an electronic device, wherein the circuit includes a first processor and a first processing module connected to the first processor, the first processing module includes a second processor connected to a first memory, and the transmission delay generated by the second processor performing read and write operations on the first memory is less than the transmission delay generated by the communication between the first processor and the first processing module. Since the transmission delay generated by the second processor performing read and write operations on the first memory is less than the transmission delay generated by the communication between the first processor and the first processing module, the cost of the transmission delay of data in the bus can be reduced.

Description

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on September 30, 2020, with application number 202011060780.0 and application name “Processor Architecture, Device and Method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of chip technology, and more specifically, to circuits, chips and electronic devices. Background Art

[0003] The processors in current high-speed network chips are generally set up in a pipeline manner. When a message enters the chip, a program state (PS) is generated for the message to save the context information of the message forwarding process. The processor on the pipeline processes the message and saves the processing result in the PS before sending it to the next processor. The design between the processor and the memory that saves the PS in the current chip is unreasonable, which will lead to high latency in reading and writing the PS. Summary of the invention

[0004] The present application provides a circuit, a chip and an electronic device that can reduce transmission delay.

[0005] In a first aspect, an embodiment of the present application provides a circuit. The circuit includes a first processor and a first processing module connected to the first processor, the first processing module includes a second processor connected to a first memory, and the transmission delay generated by the second processor performing read and write operations on the first memory is less than the transmission delay generated by the communication between the first processor and the first processing module. Since the transmission delay generated by the second processor performing read and write operations on the first memory is less than the transmission delay generated by the communication between the first processor and the first processing module, the cost of the transmission delay of data in the bus can be reduced.

[0006] In combination with the first aspect, in one possible implementation, a transmission delay generated by the second processor performing read and write operations on the first memory is less than or equal to 1 / 10 of a transmission delay generated by communication between the first processor and the first processing module.

[0007] In combination with the first aspect, in one possible implementation, the second processor is a multi-core processor, and the transmission delay generated by the second processor performing read and write operations on the first memory is the transmission delay generated by any core processor of the multi-core processors included in the second processor performing read and write operations on the first memory.

[0008] In combination with the first aspect, in a possible implementation manner, the second processor is a multi-core processor,

[0009] The transmission delay generated when the second processor performs read and write operations on the first memory is the transmission delay generated when any core processor of the multi-core processor included in the second processor performs read and write operations on the first memory.

[0010] In combination with the first aspect, in a possible implementation, the first processor is connected to the first processing module via a first bus, and the second processor is connected to the first memory via a second bus, wherein the bus width of the second bus is greater than the bus width of the first bus, and / or the length of the second bus is less than the length of the first bus. Since the length of the second bus is less than the length of the first bus, the area of ​​the circuit can be reduced.

[0011] In combination with the first aspect, in a possible implementation, the length of the second bus may be less than or equal to 1 / 10 of the length of the first bus. The above technical solution can further reduce the area of ​​the circuit.

[0012] In combination with the first aspect, in one possible implementation, the first processing module also includes a third processor connected to the second memory, and the transmission delay generated by the third processor performing read and write operations on the second memory is less than the transmission delay generated by the first processor communicating with the first processing module.

[0013] In combination with the first aspect, in one possible implementation, the first processor is connected to the first processing module via a first bus, the second processor is connected to the first memory via a second bus, the third processor is connected to the second memory via a third bus, and the sum of the bus width of the second bus and the bus width of the third bus is greater than the bus width of the first bus.

[0014] In combination with the first aspect, in one possible implementation, the first processing module also includes a third processor connected to the first memory, and the transmission delay generated by the third processor performing read and write operations with the first memory is less than the transmission delay generated by the communication between the first processor and the first processing module.

[0015] In combination with the first aspect, in one possible implementation, the first processor is connected to the first processing module via a first bus, the second processor is connected to the first memory via a second bus, the third processor is connected to the first memory via a third bus, and the sum of the bus width of the second bus and the bus width of the third bus is greater than the bus width of the first bus.

[0016] In combination with the first aspect, in a possible implementation, the second processor and the third processor are pipeline processors.

[0017] In combination with the first aspect, in one possible implementation, the circuit also includes a fourth processor and a second processing module connected to the fourth processor, the second processing module includes N fifth processors connected to M memories, N and M are both integers greater than or equal to 1, and the transmission delay generated by any fifth processor performing read and write operations on the memory connected to it is less than the transmission delay generated by the fourth processor communicating with the second processing module.

[0018] In combination with the first aspect, in one possible implementation, the second processor is connected to the third processor via a fourth bus, the fourth processor is connected to the first processor via a fifth bus, and a bus width of the fourth bus is smaller than a bus width of the fifth bus.

[0019] In combination with the first aspect, in a possible implementation manner, the number of processor cores included in the fourth processor is greater than or equal to the number of processor cores included in the first processor. .

[0020] In combination with the first aspect, in a possible implementation manner, the fourth processor and the first processor are pipeline processors.

[0021] In combination with the first aspect, in a possible implementation manner, the first processing module also includes the first memory.

[0022] In a second aspect, an embodiment of the present application further provides a chip, which includes a circuit as in the first aspect or any possible implementation of the first aspect.

[0023] In a third aspect, an embodiment of the present application further provides an electronic device, which includes the chip provided in the embodiment of the present application, and the electronic device also includes a receiver and a transmitter. The receiver is used to receive a message and send the message to the chip. The chip is used to process the message. The transmitter is used to obtain the message processed by the chip and send the processed message to another electronic device. The electronic device can be a switch, a router, or any other electronic device that can be provided with the above chip.

[0024] In a fourth aspect, an embodiment of the present application also provides a processing method, which includes: a first processor receives a first message, the first message includes flow identification information; the first processor determines a first processing module based on the flow identification information, and the first processing module corresponds to the flow identification information; the first processor sends the first message to the first processing module.

[0025] In the above method, the first processor sends the message that needs to be processed by the first processing module to the first processing module according to the flow identification information carried in the message, and the processor in the first processing module performs corresponding processing. Since the first processing module is closer to the memory than the first processor, it helps to reduce transmission delay.

[0026] Optionally, the method further includes: the first processor receiving a second message from the first processing module, the second message is a message processed by the first processing module according to the flow identification information, and the second message includes the flow identification information.

[0027] Optionally, the method further includes: the first processor sending the second message to a next processor, where the next processor is the next hop of the first processor on the pipeline to which it belongs.

[0028] In the fifth aspect, an embodiment of the present application also provides a processing method, which includes: a second processor in a first processing module receives a first message from a first processor, and the first message includes flow identification information; the second processor obtains parameters for processing the first message from a memory corresponding to the second processor according to the flow identification information; the second processor processes the first message according to the parameters, and sends the processed first message to a third processor in the first processing module, and the processed first message includes the flow identification information; the third processor in the first processing module obtains parameters for processing the processed first message from a memory corresponding to the third processor according to the flow identification information; the third processor processes the processed first message according to the parameters, obtains a second message and sends it to the first processor.

[0029] In the above method, the processor in the first processing module reads the memory and performs corresponding processing according to the flow identifier in the first message. Since the first processing module is closer to the memory than the first processor, it helps to reduce the transmission delay.

[0030] Optionally, the processing may include table lookup forwarding, the parameter includes one or more of an index, a base address and a hash value of a forwarding table entry, and the parameter corresponds to the flow identifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of a chip provided according to an embodiment of the present application.

[0032] Figure 2 It is a schematic diagram of another chip provided according to an embodiment of the present application.

[0033] Figure 3A schematic diagram of a circuit is shown.

[0034] Figure 4 This is another schematic diagram of a circuit.

[0035] Figure 5 Is to use Figure 4 The circuit shown is a schematic flow chart for implementing the process of determining the next hop port.

[0036] Figure 6 Is to use Figure 3 The circuit shown is a schematic flow chart for implementing the process of determining the next hop port. DETAILED DESCRIPTION

[0037] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0038] The present application will present various aspects, embodiments or features around a system that may include multiple devices, components, modules, etc. It should be understood and appreciated that each system may include additional devices, components, modules, etc., and / or may not include all of the devices, components, modules, etc. discussed in conjunction with the figures. In addition, combinations of these schemes may also be used.

[0039] In addition, in the embodiments of the present application, words such as "exemplary" and "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the word "exemplary" is intended to present concepts in a concrete way.

[0040] In the embodiments of the present application, "corresponding (corresponding, relevant)" and "corresponding (corresponding)" can sometimes be used interchangeably. It should be pointed out that when the distinction between them is not emphasized, the meanings they intend to express are consistent.

[0041] In the embodiments of the present application, sometimes a subscript such as W1 may be mistakenly written as a non-subscript such as W1. When the difference is not emphasized, the meanings to be expressed are consistent.

[0042] The network architecture and service scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute any

[0043] As defined in the technical solution provided in the example, a person skilled in the art can appreciate that, with the evolution of network architecture and the emergence of new business scenarios, the technical solution provided in the embodiment of the present application is also applicable to similar technical problems.

[0044] References to "one embodiment" or "some embodiments" etc. described in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear at different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0045] In the present application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0046] Figure 1 Schematic diagram of a chip provided according to an embodiment of the present application. Figure 1As shown, the chip 100 includes an input-output interface 101, a processor 111, a processor 112, a processor 113 and a processor 114. The chip 100 also includes a processing module 121 and a processing module 122. The processing module 121 includes a processor 1211, a processor 1212, a memory 1221 and a memory 1222. The processing module 122 includes a processor 1213, a processor 1214, a processor 1215, a memory 1223, a memory 1224 and a memory 1225. The chip 100 also includes a memory 131 and a memory 132. The processor 111 is connected to the input-output interface 101 through a bus 61, is connected to the processor 112 through a bus 41, and is connected to the memory 131 through a bus 51. The processor 112 is connected to the processor 113 through a bus 42, and is connected to the processing module 121 through a bus 11. The processor 113 is connected to the processor 114 through a bus 43, and is connected to the memory 132 through a bus 52. The processor 114 is connected to the input / output interface 101 via the bus 62, and is connected to the processing module 122 via the bus 12. The processor 1211 is connected to the memory 1221 via the bus 31, and is connected to the processor 1212 via the bus 21. The processor 1212 is connected to the memory 1222 via the bus 32. The processor 1213 is connected to the memory 1223 via the bus 33, and is connected to the processor 1214 via the bus 22. The processor 1214 is connected to the memory 1224 via the bus 34, and is connected to the processor 1215 via the bus 23. The processor 1215 is connected to the memory 1225 via the bus 35.

[0047] The chip 100 processes the received message in a pipeline manner. Figure 1 As shown, processors 111, 112, 113 and 114 belong to the same pipeline, and processors 111, 112, 113 and 114 may also be referred to as pipeline processors. Optionally, processors 1211 and 1212 belong to the same pipeline, and processors 1213, 1214 and 1215 belong to the same pipeline. For ease of description, the pipeline may be referred to as the first pipeline. Figure 1 As shown, some processors in the first pipeline can directly access the memory through the bus. For example, processor 111 can directly access memory 131 through bus 11, and processor 113 can directly access memory 132 through bus 13. For the convenience of description, the processors in the first pipeline that can directly access the memory can be referred to as type 1 processors. Figure 1As shown, another part of the processors in the first pipeline can communicate with the processing module. For example, processor 112 communicates with processing module 121 through bus 11, and processor 114 communicates with processing module 122 through bus 12. For the convenience of description, the processors in the first pipeline that can communicate with the processing module can be referred to as type 2 processors. The multiple processors included in each processing module can also belong to one pipeline. For example, processor 1211 and processor 1212 belong to the same pipeline, and processor 1213, processor 1214 and processor 1215 belong to the same pipeline. For the convenience of description, the pipeline in the processing module can be referred to as the second pipeline. The processors in the processing module can be referred to as type 3 processors. In other words, Figure 1 The illustrated processor 1211 , processor 1212 , processor 1213 , processor 1214 , and processor 1215 may all be referred to as type 3 processors.

[0048] like Figure 1 As shown, any type 1 processor corresponds to one memory, and any type 3 processor corresponds to one memory. Any type 1 processor or any type 3 processor is connected to the corresponding memory through a bus to perform read and write operations on the memory. For example, memory 131 corresponds to processor 111, and memory 1221 corresponds to processor 1211. The one-to-one correspondence between the above memories and processors can also be replaced by a one-to-many or many-to-one correspondence, for example: any type 1 processor or any type 3 processor can correspond to multiple memories to perform read and write operations on multiple memories. Or multiple type 1 processors can correspond to one memory, and multiple type 3 processors can correspond to one memory to perform read and write operations on the memory. For example, Figure 1 The memory 131 and the memory 132 in the embodiment may be replaced by one memory, and the processor 111 and the processor 113 correspond to the same memory. Figure 1 The memory 131 in the embodiment may also be replaced by multiple memories, and the processor 111 corresponds to multiple memories. Figure 1 The memory 1221 and the memory 1222 in the embodiment may be replaced by one memory, and the processor 1211 and the processor 1212 correspond to the same memory.

[0049] Depending on the connection object, the bus in chip 100 includes a type 1 bus, a type 2 bus, a type 3 bus, a type 4 bus, a type 5 bus, and a type 6 bus. The type 1 bus is used to connect a type 2 processor and a processing module corresponding to the type 2 processor. For example, bus 11 for connecting processor 112 and processing module 121 and bus 12 for connecting processor 114 and processing module 122 are both type 1 buses. The type 2 bus is used to connect two type 3 processors. For example, bus 21 for connecting processor 1211 and processor 1212, bus 22 for connecting processor 1213 and processor 1214, and bus 23 for connecting processor 1214 and processor 1215 are both type 2 buses. The type 3 bus is used to connect a type 3 processor and a memory corresponding to the type 3 processor. For example, bus 31 for connecting processor 1211 and memory 1221, bus 33 for connecting processor 1213 and memory 1223, etc. are both type 3 buses. The type 4 bus is used to connect the two processors in the first pipeline. For example, the bus 41 used to connect the processor 111 and the processor 112, the bus 42 used to connect the processor 112 and the processor 113, and the bus 43 used to connect the processor 113 and the processor 114 all belong to the type 4 bus. The type 5 bus is used to connect the type 1 processor and the memory corresponding to the type 1 processor. For example, the bus 51 used to connect the processor 111 and the memory 131 and the bus 52 used to connect the processor 113 and the memory 132 both belong to the type 5 bus. The type 6 bus is used to connect the input-output interface 101 and the processor. For example, the bus 61 used to connect the input-output interface 101 and the processor 111 and the bus 62 used to connect the processor 114 and the input-output interface 101 both belong to the type 6 bus.

[0050] In some embodiments, each processor in the first pipeline is a multi-core processor. Each processor in the first pipeline may include multiple processor cores (also referred to as cores). In some embodiments, different processors in the first pipeline may include the same number of processor cores. In other words, any two processors in the first pipeline include the same number of processor cores. Figure 1For example, the number of processor cores included in processor 111 is equal to the number of processor cores included in processor 112, the number of processor cores included in processor 112 is equal to the number of processor cores included in processor 113, and the number of processor cores included in processor 113 is equal to processor 114. In other embodiments, the number of processor cores included in different processors in the first pipeline may be different. In other words, the number of processor cores included in any two processors in the first pipeline may be different. For example, the number of processor cores included in processor 111 is greater than the number of processor cores included in processor 112. The number of processor cores included in processor 113 is greater than the number of processor cores included in processor 114. The number of processor cores included in processor 111 is greater than the number of processor cores included in processor 113, and the number of processor cores included in processor 112 is greater than the number of processor cores included in processor 114.

[0051] In other embodiments, some processors in the first pipeline include the same number of processor cores. For example, the number of processor cores included in processor 111 is equal to the number of processor cores included in processor 113, and the number of processor cores included in processor 112 is equal to the number of processor cores included in processor core 114, but the number of processor cores included in processor 111 is different from the number of processor cores included in processor 112. As described above, according to different connected objects, the processors in the first pipeline can be divided into two categories, namely, type 1 processors (such as processor 111 and processor 113) and type 2 processors (such as processor 112 and processor 114). In some embodiments, the number of processor cores included in processors of the same type is the same, and the number of processor cores included in processors of different types may be different. In some embodiments, the number of processor cores included in the processor of type 1 may be greater than the number of processor cores included in the processor of type 2. Since the processor of type 2 communicates with the processing module, and the processor included in the processing module can perform partial processing operations, the processor of type 2 can use a single-core processor or a processor with a small number of cores, which can further reduce hardware costs. For example, the number of processor cores included in the type 2 processor may be 1 / 2, 1 / 3, 1 / 5, or 1 / 8 of the number of processor cores included in the type 1 processor.

[0052] In other embodiments, the processor of type 1 may be a multi-core processor, and the processor of type 2 may be a single-core processor. In some embodiments, the processor of type 3 may also be a multi-core processor. In other words, the processor of type 3 may also include multiple processor cores. In some embodiments, the number of processor cores included in the processor of type 3 is less than the number of processor cores included in the processor of type 1 or type 2. In other words, the number of processor cores included in the processor of type 1 and the number of processor cores included in the processor of type 2 are both greater than the number of processor cores included in the processor of type 3. For example, the number of processor cores included in processor 1211 may be less than the number of processor cores included in processor 111, and the number of processor cores included in processor 1211 may also be less than the number of processor cores included in processor 112. In other embodiments, the number of processor cores included in the processor of type 3 may be less than the number of processor cores included in the processor of type 1, and the number of processor cores included in the processor of type 3 may be equal to or greater than the number of processor cores included in the processor of type 2. For example, the number of processor cores included in processor 1213 may be less than the number of processor cores included in processor 111, and the number of processor cores included in processor 1213 may be equal to or greater than the number of processor cores included in processor 114. For example, in some embodiments, the number of processor cores included in a processor of type 3 may be less than or equal to 1 / 10 of the number of processor cores included in a processor of type 1. For another example, in other embodiments, the number of processor cores included in a processor of type 3 may be less than or equal to 1 / 2, 1 / 3, 1 / 5, or 1 / 8 of the number of processor cores included in a processor of type 1.

[0053] In other embodiments, the number of processor cores included in a processor of type 2 and the number of processor cores included in a processor of type 3 in a processing module corresponding to the processor are equal to the number of processor cores included in a processor of type 1. For example, the sum of the number of processor cores included in processor 112 and the number of processor cores included in processor 1212 is equal to the number of processor cores included in processor 111. For another example, the sum of the number of processor cores included in processor 114 and the number of processor cores included in processor 1214 is equal to the number of processor cores included in processor 113. In some embodiments, the number of processor cores included in different processors of type 3 may be the same. For example, the number of processor cores included in processor 1211 is equal to the number of processor cores included in processor 1212, and the number of processor cores included in processor 1212 is equal to the number of processor cores included in processor 1215.

[0054] In other embodiments, different type 3 processors may include different numbers of processor cores.

[0055] In other embodiments, any two processors belonging to the same processing module include the same number of processor cores, and any two processors belonging to different processing modules include different numbers of processor cores. For example, the number of processor cores included in processor 1211 is equal to the number of processor cores included in processor 1212, and the number of processor cores included in processor 1212 is not equal to the number of processor cores included in processor 1213. Figure 1 In the chip shown, each processing module includes at least two processors. In other embodiments, the processing module may also include a multi-core processor. For example, the processing module 121 may only include a processor 1211 and a memory 1221, wherein the processor 1211 is a multi-core processor.

[0056] In some embodiments, the processor of type 2 may also be a single-core processor. If the processor of type 2 is a single-core processor, the processing module including the processor may include at least two processors. In other words, if the processing module includes multiple processors, the multiple processors may include at least one single-core processor. Taking the processing module 121 as an example, the processor 1211 in the processing module 121 may be a single-core processor, and the processor 1212 may be a single-core processor or a multi-core processor.

[0057] In some embodiments, the length of the type 1 bus is greater than the length of the type 3 bus. For example, the length of the type 3 bus may be equal to 1 / 5, 1 / 8, or 1 / 10 of the length of the type 1 bus. For another example, the length of the type 3 bus may be less than 1 / 10, 1 / 15, or 1 / 20 of the length of the type 1 bus. In some embodiments, the sum of the length of the type 1 bus and the length of the type 3 bus is equal to the length of the type 5 bus.

[0058] In some embodiments, the lengths of any two type 1 buses may be the same. In some embodiments, the lengths of any two type 2 buses may be the same. In some embodiments, the lengths of any two type 3 buses may be the same. In some embodiments, the lengths of any two type 4 buses may be the same. In some embodiments, the lengths of any two type 5 buses may be the same. Due to limitations of the manufacturing process, it may be difficult to achieve that the lengths of the buses are exactly the same. Therefore, the same length in the embodiments of the present application can be understood as the lengths being exactly the same, or it can be understood as the length difference being within the allowable error range. For example, the sum of the length of the type 1 bus and the length of the type 3 bus being equal to the length of the type 5 bus can be understood as the difference between the sum of the length of the type 1 bus and the length of the type 3 bus and the length of the type 5 bus being 0 or less than or equal to a preset allowable error value. For another example, the difference between the length of bus 51 and the length of bus 52 (i.e., the lengths of the two type 5 buses) is 0 or less than or equal to a preset allowable error value.

[0059] In some embodiments, the sum of the widths of all third buses in the same processing module is greater than the width of one first bus. For example, the width of bus 31 and the width of bus 32 are greater than the width of bus 11. For another example, the sum of the width of bus 33, the width of bus 34 and the width of bus 35 is greater than the width of bus 12. The number of bits of binary data that can be transmitted simultaneously by a bus is called width (also called bit width), in bits. The larger the bus width, the better the transmission performance, and the more data that can be transmitted in the same time. The bandwidth of the bus (i.e., the total number of data that can be transmitted per unit time) is: bus bandwidth = frequency × width (Bytes / sec).

[0060] In some embodiments, the width of a type 2 bus may be less than the width of a type 4 bus. Figure 2 is a schematic diagram of another chip provided according to an embodiment of the present application. Figure 2 As shown, chip 200 includes input / output interface 201, processor 211, processor 212, processor 213 and processor 214. Chip 200 also includes processing module 221 and processing module 222. Processing module 221 includes processor 2211 and processor 2212. Processing module 222 includes processor 2213, processor 2214 and processor 2215.

[0061] The processor 211 is connected to the input-output interface 201 via a bus 2411. The processor 211 is connected to the processor 212 via a bus 2441. The processor 212 is connected to the processing module 221 via a bus 2421. The processor 212 is connected to the processor 213 via a bus 2442. The processor 213 is connected to the input-output interface 201 via a bus. The processor 213 is connected to the processor 214 via a bus 2443. The processor 214 is connected to the processing module 222 via a bus 2422. The processing module 221 is connected to the input-output interface 201 via a bus 2431. The processing module 222 is connected to the input-output interface 201 via a bus 2432. The processor 2221 is connected to the processor 2212 via a bus 2451. The processor 2213 is connected to the processor 2214 via a bus 2452. The processor 2214 is connected to the processor 2215 via a bus 2453. The memory 231 to the memory 237 are memories located outside the chip 200. The chip 200 can access the memory 231 to the memory 237 through the input and output interface 201 and the corresponding bus. Specifically, the memory 231 is connected to the chip 200 through the bus 2461; the memory 232 is connected to the chip 200 through the bus 2462; the memory 233 is connected to the chip 200 through the bus 2463; the memory 234 is connected to the chip 200 through the bus 2464; the memory 235 is connected to the chip 200 through the bus 2465; the memory 236 is connected to the chip 200 through the bus 2466; and the memory 237 is connected to the chip 200 through the bus 2467.

[0062] The chip 200 processes the received message in a pipeline manner. Figure 2 As shown, processors 211, 212, 213, and 214 in chip 200 belong to a pipeline, which can be called a first pipeline. Figure 2 As shown, some processors in the first pipeline can communicate directly with the input-output interface through the bus; another part of the processors in the first pipeline are connected to the processing module through the bus. For the convenience of description, the processors that can communicate directly with the input-output interface (i.e., the processors that are not connected to the processing module) can be called type 1 processors; the processors connected to the processing module can be called type 2 processors. For example, Figure 2 The type 1 processors may include processor 211 and processor 213 , and the type 2 processors may include processor 212 and processor 214 .

[0063] The multiple processors included in each processing module may also belong to one pipeline. For example, processor 2211 and processor 2212 belong to the same pipeline, and processor 2213, processor 2214, and processor 2215 belong to the same pipeline. For ease of description, the pipeline in the processing module may be referred to as the second pipeline. The processors in the processing module may be referred to as type 3 processors. In other words, Figure 2 The illustrated processor 2211 , processor 2212 , processor 2213 , processor 2214 , and processor 2215 may all be referred to as type 3 processors.

[0064] Each type 1 processor and each processor has a corresponding memory. The processor can read the data stored in the corresponding memory. The processor can also write data to the corresponding memory. Figure 2 , the memory corresponding to the processor 211 is the memory 231, the memory corresponding to the processor 2211 is the memory 232, the memory corresponding to the processor 2212 is the memory 233, the memory corresponding to the processor 213 is the memory 234, the memory corresponding to the processor 2213 is the memory 235, the memory corresponding to the processor 2214 is the memory 236, and the memory corresponding to the processor 2215 is the memory 237. For example, the processor 211 can read the data stored in the memory 231 and / or write the data to the memory 231. For another example, the processor 2213 can read the data stored in the memory 235 and / or write the data to the memory 235.

[0065] The processing module connected to the processor through the bus can be referred to as the processing module corresponding to the processor. For example, the processing module 121 is the processing module corresponding to the processor 112.

[0066] Depending on the connection object, the bus in chip 200 may include a type 1 bus, a type 2 bus, a type 3 bus, a type 4 bus, a type 5 bus, and a type 6 bus. The type 1 bus is used to connect a type 2 processor and a processor module corresponding to the type 2 processor. For example, the bus 2411 used to connect the processor 212 and the processing module 221 and the bus 2412 used to connect the processor 214 and the processing module 222 are both type 1 buses. The type 2 bus is used to connect two type 3 processors. For example, the bus 2421 used to connect the processor 2221 and the processor 2212, the bus 2422 used to connect the processor 2213 and the processor 2214, and the bus 2423 used to connect the processor 2214 and the processor 2215 are all type 2 buses. The type 3 bus is used to connect the processor and the input and output interface in the processing module. For example, the bus 2431, the bus 2432, the bus 2433, the bus 2434, and the bus 2435 are all type 3 buses. Bus 2431 is a type 3 bus for connecting processor 2211 and input / output interface 201. Bus 2432 is a type 3 bus for connecting processor 2212 and input / output interface 201. Bus 2433 is a type 3 bus for connecting processor 2213 and input / output interface 201. Bus 2434 is a type 3 bus for connecting processor 2214 and input / output interface 201. Bus 2435 is a type 3 bus for connecting processor 2215 and input / output interface 201. Type 4 bus is used to connect processors in two first pipelines. For example, bus 2441 for connecting processor 211 and processor 212, bus 2442 for connecting processor 212 and processor 213, and bus 2443 for connecting processor 213 and processor 214 are all type 4 buses. Type 6 bus is used to connect the first processor and the input / output interface. For example, bus 2461 and bus 2462 are both type 6 buses.

[0067] In addition to the bus in chip 200, chip 200 is also connected to the memory through the bus. Bus 2471 to bus 2477 are buses for connecting chip 200 and memory, and this bus can be called a type 7 bus. A processor of type 1 can access the corresponding memory through the corresponding bus and input-output interface. For example, processor 211 can access memory 231 through bus 2461, input-output interface 201 and bus 2471. For another example, processor 213 can access memory 234 through bus 2462, input-output interface 201 and bus 2474. A processor of type 3 can access the corresponding memory through the corresponding bus and input-output interface. For example, processor 2211 can access memory 232 through bus 2431, input-output interface 201 and bus 2472. For another example, processor 2215 can access memory 237 through bus 2435, input-output interface 201 and bus 2477.

[0068] and Figure 1 Similar to the chip shown, in some embodiments, Figure 2 The processors shown may all be multi-core processors. In other embodiments, the processors of type 1 and type 2 may be multi-core processors, and the processor of type 3 may be a single-core processor. The structure of the processor of type 3 may be simpler than that of the processor of type 1. For example, the number of processor cores included in the processor of type 3 may be less than the number of processor cores included in the processor of type 1. For another example, the number of transistors included in the processor of type 3 may be less than the number of transistors included in the processor of type 1. For details about the processor of type 1, the processor of type 2, and the processor of type 3, please refer to the following. Figure 1 For the sake of brevity, the description of the chip 100 is not repeated here.

[0069] In some embodiments, the length of the type 1 bus is greater than the length of the type 3 bus. For example, the length of the type 1 bus may be equal to 1 / 5, 1 / 8, or 1 / 10 of the length of the type 3 bus. For another example, the length of the type 3 bus may be less than 1 / 10, 1 / 15, or 1 / 20 of the length of the type 1 bus. In some embodiments, the sum of the length of the type 1 bus and the length of the type 3 bus is equal to the length of the type 6 bus. In some embodiments, the lengths of any two type 1 buses may be the same. In some embodiments, the lengths of any two type 2 buses may be the same. In some embodiments, the lengths of any two type 3 buses may be the same. In some embodiments, the lengths of any two type 4 buses may be the same. In some embodiments, the lengths of any two type 6 buses may be the same.

[0070] In some embodiments, the sum of the bus widths corresponding to the memory and chip in the same processing module is greater than the width of a first bus. For example, the width of bus 2431 and the width of bus 2432 are greater than the width of bus 2411. For another example, the sum of the width of bus 2433, the width of bus 2434 and the width of bus 2435 is greater than the width of bus 2412. In some embodiments, the width of a type 2 bus may be less than the width of a type 4 bus. Figure 1 In the illustrated embodiment, each processor (type 3 processor and type 1 processor) with a corresponding memory and the corresponding memory are located inside the chip.

[0071] like Figure 2 In the embodiment shown, the memory corresponding to the processor is located outside the chip. In other embodiments, part of the memory corresponding to the processor may be located inside the chip, and another part of the memory corresponding to the processor may be located outside the chip. This embodiment can be considered as Figure 1 The embodiments shown and Figure 2 It can be seen that, as Figure 1 or Figure 2 The chips shown include two Figure 3 The structure shown. Figure 3 FIG. 1 shows a schematic diagram of a hybrid processor circuit. Figure 3As shown, the processor 301 is connected to the processing module 310 via a bus 331. The processing module 310 includes three processors, namely, a processor 311, a processor 312 and a processor 313. The processors in the processing module 310 are connected via a bus 332. The processor 301 is a first processor, and the processors 311, 312 and 313 are processors of type 3. More specifically, the processor 311 is a processor of type 2. Each processor in the processing module 310 has a corresponding memory. The memory corresponding to the processor 311 is a memory 321, the memory corresponding to the processor 312 is a memory 322, and the memory corresponding to the processor 313 is a memory 323. Each processor in the processing module 310 is connected to the corresponding memory via a bus. The processor 311 is connected to the memory 321 via a bus 333, the processor 312 is connected to the memory 322 via a bus 334, and the processor 313 is connected to the memory 323 via a bus 335. Processor 310, processor 311, processor 312 and processor 313 are located in the same chip. Each processor in processing module 310 and the corresponding memory can be located in the same chip as processing module 310, or can be located outside the chip where processing module 310 is located. If the memory is located outside the chip where processing module 310 is located, then the bus used to connect the processor in the processing module and the corresponding memory can include a bus from the processor to the input and output interface of the chip and a bus from the chip to the corresponding memory. For example, bus 333 can include a bus from processor 311 to the input and output interface of the chip and a bus from the input and output interface of the chip to memory 321.

[0072] For ease of description, Figure 3 This structure is called a hybrid processor circuit or a hybrid processor structure. Figure 3 The processing module in the hybrid processor structure shown includes three processors. In other embodiments, the number of processors in the processing module can be a positive integer greater than or equal to 1, for example, 1, 2, 4, or 5. As described above, if the number of processors included in the processing module is 1, then the processor can be a multi-core processor. If the processing module includes at least two processors, then the at least two processors can include one or more single-core processors.

[0073] For ease of description, assume that the lengths of bus 333, bus 334, and bus 335 are the same, denoted by the letter L for the length of bus 333, and the letter R for the length of bus 331. As described in the above embodiments, in some embodiments, L is less than R. In other embodiments, L can be much less than R. For example, L can be equal to one-tenth of R, or L is less than one-tenth of R. Assume that the width of bus 333 is denoted by the letter A, the width of bus 334 is denoted by the letter B, the width of bus 335 is denoted by the letter C, and the width of bus 331 is denoted by the letter D. Then, A, B, C, and D satisfy the following relationship: D < A + B + C. Thus, as Figure 3 shown, the data transfer cost of the hybrid processor structure can be as shown in Equation 3.1:

[0074] Cost_TX = L × (A + B + C) + R × D, Equation 3.1

[0075] where Cost_TX represents the data transfer cost, L represents the length of bus 333 (the lengths of bus 333, bus 334, and bus 335 are equal), R represents the length of bus 331, A represents the width of bus 333, B represents the width of bus 334, C represents the width of bus 335, and D represents the width of bus 331.

[0076] A chip adopting a pipeline structure (such as chip 100 shown in Figure 1 or chip 200 shown in Figure 2 ) can generate a program state (PS) for this message after receiving the message. The PS is used to save the context information during the forwarding process of this message. The PS then passes through each processor in the first pipeline, and the processors in the first pipeline are responsible for processing it. For ease of description, the PS processed by the processors in the first pipeline can be called the first PS. Assume that the size of the first PS is denoted by PS_Full_Size. The processing module 310 also generates a PS during the process of processing this message. The PS then passes through each processor in the second pipeline, and the processors in the second pipeline are responsible for processing it. For ease of description, the PS processed by the processors in the second pipeline can be called the second PS. Assume that the size of the second PS is denoted by PS_Little_Size. The first PS saves the context information during the message forwarding process. The second PS only saves the information processed in the second pipeline. Therefore, the size of the first PS is greater than the size of the second PS (i.e., PS_Full_Size > PS_Little_Size). In some embodiments, the size of the second PS can be equal to or less than 1 / 5, 1 / 8, 1 / 10, 1 / 15, or 1 / 20, etc. of the size of the first PS.

[0077] Since the second PS is smaller in size than the first PS, a simpler processor can be used to process the second PS. Therefore, the structure of the processor inside the processing module (i.e., the processor of type 3) can be simpler than the structure of the processor in the first pipeline. In other words, the number of processor cores included in the type 3 processor can be less than the number of processor cores included in the first processor of type 1 and / or type 2, and / or, the number of transistors included in the type 3 processor can be less than the number of transistors included in the type 1 and / or type 2 processor. The greater the difference between the size of the first PS and the size of the second PS, the simpler the structure of the type 3 processor can be.

[0078] In some embodiments, the number of processor cores included in the type 3 processor may be less than the number of processor cores included in the type 1 processor, and / or the number of transistors included in the type 3 processor may be less than the number of transistors included in the type 1 processor. In other embodiments, the number of processor cores included in the type 3 processor may be less than the number of processor cores included in the type 2 processor, and / or the number of transistors included in the type 3 processor may be less than the number of transistors included in the type 2 processor.

[0079] Taking the number of processor cores as an example, N_Little may be used to represent the number of processor cores included in a type 3 processor, N_Big2 may be used to represent the number of processor cores included in a type 2 processor, and N_Big1 may be used to represent the number of processor cores included in a type 1 processor.

[0080] In this way, Figure 3 The processor cost of the hybrid processor structure shown can be expressed as formula 3.2:

[0081] Cost_Proc=PS_Little_Size×N_Little+PS_Full_Size×N_Big2, formula 3.2

[0082] Among them, Cost_Proc represents the processor cost, and the meanings of PS_Little_Size, N_Little, PS_Full_Size and N_Big2 are as described above, and are not repeated here for the sake of brevity.

[0083] In some embodiments, N_Little, N_Big2, and N_Big1 may satisfy the following relationship: N_Big1=N_Little+N_Big2.

[0084] If Latency_L is used to represent the input / output (I / O) delay of a bus with a length of L, and Latency_R is used to represent the I / O delay of a bus with a length of R, then Figure 3 The latency cost of the hybrid processor structure shown can be expressed as formula 3.3:

[0085] Cost_LAT=Lattency_L×3+Lattency_R×1, formula 3.3

[0086] Among them, Cost_LAT represents the latency cost, Latency_L represents the I / O latency of a bus with a length of L, and Lattency_R represents the I / O latency of a bus with a length of R.

[0087] If all are implemented as processors in a pipeline, Figure 3 The functions realized by the hybrid processing structure shown in the figure need to be Figure 4 The structure shown.

[0088] Figure 4 is another schematic diagram that includes a processor circuit. Figure 4 The circuit shown includes three processors, namely processor 401, processor 402 and processor 403. In addition, processor 401, processor 402 and processor 403 are type 1 processors (processors 401 to 403 are all processors in the same pipeline and what is connected to processor 401 to processor 403 through a bus is a memory rather than a processing module). Each of the three processors has a corresponding memory. The memory corresponding to processor 401 is memory 411, the memory corresponding to processor 402 is memory 412, and the memory corresponding to processor 403 is memory 413. Processor 401 is connected to memory 411 through bus 421, processor 402 is connected to memory 412 through bus 422, and processor 402 is connected to memory 413 through bus 423. Processor 401 is connected to processor 402 through bus 424, and processor 402 is connected to processor 403 through bus 424.

[0089] The length of bus 421, the length of bus 422 and the length of bus 423 are the same. The length of bus 421 can be equal to L+R, that is, Figure 3 The width of bus 421 may be equal to the width of bus 333, the width of bus 422 may be equal to the width of bus 334, and the width of bus 423 may be equal to the width of bus 335. In this case, the width of bus 421 may be equal to the width of bus 333, the width of bus 422 may be equal to the width of bus 334, and the width of bus 423 may be equal to the width of bus 335. Figure 4 The data transfer cost of the structure shown can be expressed as formula 4.1:

[0090] Cost_TX = (L + R) × (A + B + C), Formula 4.1

[0091] Among them, Cost_TX represents the cost of data transmission, L+R is the length of bus 421 (the length of bus 422 is equal to the length of bus 421, and the length of bus 423 is equal to the length of bus 421), A represents the width of bus 421, B represents the width of bus 422, and C represents the width of bus 423.

[0092] Comparing Formula 4.1 with Formula 3.1, we can find that when L is less than R and D is less than A+B+C, Figure 3 The data transfer cost of the structure shown is less than that of Figure 4 Data transfer cost for the structure shown.

[0093] In some embodiments, if the difference between R and L is larger, Figure 3 The structure shown has a lower data transfer cost.

[0094] As described above, since processors 401 to 403 are all type 1 processors, the PS passing through processors 401 to 403 is PS_Full, and accordingly, the size of PS_Full is PS_Full_Size, and the number of processor cores included in the type 1 processor is N_Big1. Then, using Figure 4 The processor cost of the structure shown can be expressed as formula 4.2:

[0095] Cost_Proc=PS_Full_Size×N_Big1, formula 4.2

[0096] Among them, Cost_Proc represents the processor cost, PS_Full_Size is the size of the PS passing through the processor 401, and N_Big1 is the number of processor cores included in the processor 401.

[0097] If N_Big1=N_Little+N_Big2, then Figure 4 Compared with the structure shown in Figure 3 The processor cost of the structure shown can save (PS_Full_Size-PS_Little_Size)×N_Little. If the difference between PS_Full_Size and PS_Little_Size is larger, the processor cost saved is larger (i.e., the processor cost is smaller). If the difference between N_Big1 and N_Little1 is larger, the processor cost saved is larger (i.e., the processor cost is smaller).

[0098] If Latency_L is used to represent the I / O delay of a bus with a length of L, and Lattency_R is used to represent the I / O delay of a bus with a length of R, then Figure 4 The delay cost of the structure can be expressed as formula 4.3:

[0099] Cost_LAT=(Lattency_L+Lattency_R)×3, formula 4.3

[0100] Among them, Cost_LAT represents the latency cost, Latency_L represents the I / O latency of a bus with a length of L, and Lattency_R represents the I / O latency of a bus with a length of R.

[0101] It can be seen that Figure 4 Compared with the structure shown in Figure 3 The structure shown can save I / O latency of Lattency_R × 2. The larger the difference between R and L, the more I / O latency can be saved.

[0102] In summary, the technical solution provided by the embodiment of the present application can realize the corresponding function with less cost (data transmission cost, processor cost and delay cost). In addition, since the bus length required inside the processing module is shorter and the bus width between the first processor of type 2 and the processing module is smaller, the chip using the technical solution of the present application has a smaller area than the chip realizing the same function.

[0103] The following takes equal-cost multi-path routing (ECMP) as an example. Figure 3 and Figure 4 The two structures are introduced.

[0104] The basic process of ECMP determining the next-hop port is as follows: a hash value is determined based on the flow identification information of the message (such as a five-tuple or a flow label), and then a table entry is determined based on the ECMP routing table and the hash value. The port included in the table entry is the next-hop port used to send the message.

[0105] In some cases, in order to reduce the number of entries stored in the ECMP routing table and improve the search efficiency, the ECMP routing table can be divided into multiple tables, for example, it can be divided into three tables, respectively referred to as routing entry table 1, routing table entry 2 and routing entry table 3. First, according to the flow identification information of the message, the table entry corresponding to the flow identification information is determined from routing entry table 1, and the table entry includes a base address and an index of a routing entry table. Then, according to the index of the routing entry table, routing entry table 2 is determined, and the table entry corresponding to the base address and the hash value determined according to the flow identification information of the message is queried from routing entry table 2, and the table entry includes a port index and an index of a routing entry table. Finally, according to the index of the routing entry table, routing entry table 3 is determined, and the table entry corresponding to the port index is queried from routing entry table 3, and the table entry includes the next hop port of the message.

[0106] Figure 5 It shows that the use of Figure 4 The circuit shown is a schematic flow chart for implementing the process of determining the next hop port.

[0107] 501, the processor 401 obtains an index of an entry table of routing entries from the received PS (hereinafter referred to as routing table index 1).

[0108] 502 , the processor 401 sends the routing table index 1 to the memory 411 .

[0109] 503 , the processor 401 receives the routing entry table 1 corresponding to the routing table index 1 from the memory 411 .

[0110] 504, the processor 401 determines the entry corresponding to the flow identification information of the message in the routing entry table 1. The entry includes an index of the routing entry table (hereinafter referred to as routing table index 2) and a base address, and writes the routing table index 2 and the base address into the PS.

[0111] 505 , the processor 401 sends the PS (ie, the PS after the routing table index 2 and the base address are written) to the processor 402 .

[0112] 506, the processor 402 obtains the routing table index 2, the base address and a hash value from the received PS. The hash value is determined according to the flow identification information of the message. The hash value may be determined by the upstream node of the processor 401 and written into the PS.

[0113] 507 , the processor 402 sends the routing table index 2 to the memory 412 .

[0114] 508 , the processor 402 receives the routing entry table 2 corresponding to the routing table index 2 from the memory 412 .

[0115] 509, the processor 402 searches for an entry corresponding to the base address and the hash value from the routing entry table 2, the entry including a port index and an index of a routing entry table (hereinafter referred to as routing table index 3), and writes the port index and the routing table index 3 into the PS.

[0116] 510 , the processor 402 sends the PS (that is, the PS after the port index and the routing table index 3 are written) to the processor 403 .

[0117] 511 , the processor 403 obtains the routing table index 3 and the port index from the received PS.

[0118] 512 , the processor 403 sends the routing table index 3 to the memory 413 .

[0119] 513 , the processor 403 receives the routing entry table 3 corresponding to the routing table index 3 from the memory 412 .

[0120] 514, the processor 403 searches the routing entry table 3 for an entry corresponding to the port index, and the content included in the entry is the next hop port of the message.

[0121] 515, the processor 403 writes the next hop port of the message into the PS, and sends the PS to the next node in the pipeline, and the next node continues to process the message.

[0122] Figure 6 Is to use Figure 3 The circuit shown is a schematic flow chart for implementing the process of determining the next hop port.

[0123] 601, the processor 301 obtains an index of an entry table of routing entries (hereinafter referred to as routing table index 1), flow identification information of a message, and a hash value determined according to the flow identification information of the message from the received PS.

[0124] 602 , the processor 301 sends the routing table index 1, the flow identification information of the message, and the hash value determined according to the flow identification information of the message to the processor 311 .

[0125] 603 , the processor 311 sends the routing table index 1 to the memory 321 .

[0126] 604 , the processor 311 receives the routing entry table 1 corresponding to the routing table index 1 from the memory 321 .

[0127] 605, the processor 311 determines the entry corresponding to the flow identification information of the message in the routing entry table 1. The entry includes an index of the routing entry table (hereinafter referred to as routing table index 2) and a base address, and writes the routing table index 2 and the base address into the PS. The PS may also include a hash value determined according to the flow identification information of the message.

[0128] 606 , the processor 311 sends the PS (ie, the PS after the routing table index 2 and the base address are written) to the processor 312 .

[0129] 607 , the processor 312 obtains the routing table index 2 , the base address and the hash value from the received PS.

[0130] At 608 , the processor 312 sends the routing table index 2 to the memory 322 .

[0131] 609 , the processor 312 receives the routing entry table 2 corresponding to the routing table index 2 from the memory 322 .

[0132] 610, the processor 312 searches for an entry corresponding to the base address and the hash value from the routing entry table 2, the entry including a port index and an index of a routing entry table (hereinafter referred to as routing table index 3), and writes the port index and the routing table index 3 into the PS.

[0133] 611 , the processor 312 sends the PS (ie, the PS after the port index and the routing table index 3 are written) to the processor 313 .

[0134] 612. The processor 313 obtains the routing table index 3 and the port index from the received PS.

[0135] 613 , the processor 313 sends the routing table index 3 to the memory 323 .

[0136] 614 , the processor 313 receives the routing entry table 3 corresponding to the routing table index 3 from the memory 323 .

[0137] 615, the processor 313 searches the routing entry table 3 for an entry corresponding to the port index, and the content of the entry is the next hop port of the message.

[0138] 616 : The processor 313 sends the next hop port of the message to the processor 301 .

[0139] 617, the processor 301 writes the next hop port of the message into the PS, and sends the PS to the next node in the pipeline, and the next node continues to process the message.

[0140] exist Figure 5In the process shown, processors 401 to 403 and other processors in the chip are all on the same pipeline. The PS processed by the processors in the pipeline is used to store context information during message forwarding. Therefore, in addition to the information required to query the next hop port, the PS sent by processor 401 to processor 402 and the PS sent by processor 402 to processor 403 also need to include information required by subsequent nodes. Therefore, the size of the PS will be relatively large, for example, the size of the PS may be 512 bytes. Correspondingly, the width of the bus between processors is also relatively large.

[0141] But in Figure 6 In the process shown, processors 311 to 313 only care about the routing function, and the transmitted PS only needs to include the information required for routing. Therefore, setting a smaller PS can meet the needs of processors 311 to 313. For example, a 64-byte PS can meet the routing requirements. Correspondingly, the bus width between processors can be set smaller. In addition, the information required by processors 312 and 313 all comes from the previous node, and there is no need to obtain information from processor 301. In addition, for processor 301, processor 301 only cares about what the determined next hop port is, and processor 301 does not need to obtain the routing entry table 3 used to determine the next hop port, and processor 301 does not need to send information unrelated to the determination of the next hop port to processing module 310. Therefore, the bus width between processor 301 and processing module 310 can be set smaller. For example, the width of bus 331 can be 128 bits. In contrast, the bus between the processor and the memory requires a larger width because it needs to transmit more information (such as the routing entry table). For example, the width of bus 333 to bus 335 may be 256 bits, and the width of bus 421 to bus 423 may be 256 bits.

[0142] The embodiment of the present application also provides a circuit. The circuit includes a first processor and a first processing module connected to the first processor, the first processing module includes a second processor connected to a first memory, and the transmission delay generated by the second processor performing a read and write operation on the first memory is less than the transmission delay generated by the communication between the first processor and the first processing module.

[0143] For example, suppose Figure 1The processor module 121 shown includes only a processor 1221 and a memory 1221. Then the first processor may be equivalent to the processor 112, the first processing module may be equivalent to the processing module 121, the second processor may be equivalent to the processor 1211, and the first memory may be equivalent to the memory 1221. The transmission delay generated by the processor 1211 performing read and write operations on the memory 1221 is less than the transmission delay generated by the communication between the processor 112 and the processing module 1.

[0144] For example, suppose Figure 2 The processing module 221 shown in the figure only includes the processor 2211. Then the first processor may be equivalent to the processor 212, the first processing module may be equivalent to the processing module 221, the second processor may be equivalent to the processor 2211, and the first memory may be equivalent to the memory 323.

[0145] Optionally, in some embodiments, the second processor is a multi-core processor, and the transmission delay generated by the second processor performing read and write operations on the first memory is the transmission delay generated by any core processor of the multi-core processors included in the second processor performing read and write operations on the first memory.

[0146] Optionally, in some embodiments, the first processor is connected to the first processing module via a first bus, and the second processor is connected to the first memory via a second bus, wherein the bus width of the second bus is greater than the bus width of the first bus, and / or the length of the second bus is less than the length of the first bus.

[0147] For example, still assuming that Figure 1 The processing module 121 shown includes only a processor 1221 and a memory 1221 . The first bus is equivalent to the bus 11 for connecting the processor 112 and the processing module 121 . The second bus is equivalent to the bus 31 for connecting the processor 1211 and the memory 1221 .

[0148] Again, still deepening Figure 2 The processing module 221 shown includes only the processor 221. The first bus is equivalent to the bus 2411 used to connect the processor 212 and the processing module 221, and the second bus can be equivalent to the bus used to connect the processor 2211 and the memory 232, including the bus 2431 and the bus 2472. The second bus can also be equivalent to the bus 2431 used to connect the processor 2211 and the input and output interface 201.

[0149] Optionally, in some embodiments, the first processing module also includes a third processor connected to the second memory, and a transmission delay generated by the third processor performing read and write operations on the second memory is less than a transmission delay generated by the first processor communicating with the first processing module.

[0150] by Figure 1 For example, the first processor may be equivalent to the processor 112, the first processing module may be equivalent to the processing module 121, the second processor may be equivalent to the processor 1211, the third processor may be equivalent to the processor 1212, the first memory may be equivalent to the memory 1221, and the second memory may be equivalent to the memory 1222. The transmission delay generated by the processor 1211 performing read and write operations on the memory 1221 is less than the transmission delay generated by the communication between the processor 112 and the processing module 121, and the transmission delay generated by the processor 1212 performing read and write operations on the memory 1222 is less than the transmission delay generated by the communication between the processor 1122 and the processing module 121.

[0151] by Figure 2 For example, the first processor may be equivalent to processor 212, the first processing module may be equivalent to processing module 221, the second processor may be equivalent to processor 2211, the third processor may be equivalent to processor 2212, the first memory may be equivalent to memory 232, and the second memory may be equivalent to memory 233.

[0152] Optionally, in some embodiments, the first processor is connected to the first processing module via a first bus, the second processor is connected to the first memory via a second bus, the third processor is connected to the second memory via a third bus, and the sum of the bus width of the second bus and the bus width of the third bus is greater than the bus width of the first bus.

[0153] Also Figure 1 For example, the first bus may be equivalent to bus 11, the second bus may be equivalent to bus 31, and the third bus may be equivalent to bus 32.

[0154] by Figure 2 For example, the first bus may be equivalent to the bus 2411, the second bus may be equivalent to the bus 2431 and the bus 2472, and the third bus may be equivalent to the bus 2432 and the bus 2473. The second bus may also be equivalent to the bus 2431, and the third bus may also be equivalent to the bus 2432.

[0155] Optionally, in some embodiments, the first processing module also includes a third processor connected to the first memory, and the transmission delay generated by the third processor performing read and write operations with the first memory is less than the transmission delay generated by the communication between the first processor and the first processing module.

[0156] Optionally, in some embodiments, the first processor is connected to the first processing module via a first bus, the second processor is connected to the first memory via a second bus, and the third processor is connected to the first memory via a third bus, and the sum of the bus width of the second bus and the bus width of the third bus is greater than the bus width of the first bus.

[0157] Optionally, in some embodiments, the second processor and the third processor are pipeline processors.

[0158] Optionally, in some embodiments, the circuit further includes a fourth processor and a third memory connected to the fourth processor.

[0159] Also Figure 1 For example, the processor 111 may be equivalent to the fourth processor, and the memory 113 may be equivalent to the third memory.

[0160] by Figure 2 For example, the processor 211 may be equivalent to the fourth processor, and the memory 231 may be equivalent to the third memory.

[0161] Optionally, in some embodiments, the circuit also includes a fourth processor and a second processing module connected to the fourth processor, the second processing module includes N fifth processors connected to M memories, where N and M are both integers greater than or equal to 1, and the transmission delay generated by any fifth processor performing read and write operations on the memory connected to it is less than the transmission delay generated by the fourth processor communicating with the second processing module.

[0162] Also Figure 1 For example, the processor 114 may be equivalent to the fourth processor, and the processing module 122 may be equivalent to the second processing module.

[0163] by Figure 2 For example, the processor 214 may be equivalent to the fourth processor, and the processing module 222 may be equivalent to the second processing module.

[0164] Optionally, in some embodiments, the second processor is connected to the third processor via a fourth bus, the fourth processor is connected to the first processor via a fifth bus, and a bus width of the fourth bus is smaller than a bus width of the fifth bus.

[0165] Also Figure 1 For example, bus 21 may be equivalent to the fourth bus, and bus 41 may be equivalent to the fifth bus.

[0166] by Figure 2 For example, bus 2421 may be equivalent to the fourth bus, and bus 2441 may be equivalent to the fifth bus.

[0167] Optionally, in some embodiments, the number of processor cores included in the fourth processor is greater than or equal to the number of processor cores included in the first processor.

[0168] Optionally, in some embodiments, the fourth processor and the first processor are pipeline processors.

[0169] Optionally, in some embodiments, the first processing module also includes the first memory.

[0170] The embodiment of the present application also provides an electronic device, which includes the chip provided in the embodiment of the present application, and the electronic device also includes a receiver and a transmitter. The receiver is used to receive a message and send the message to the chip. The chip is used to process the message. The transmitter is used to obtain the message processed by the chip and send the processed message to another electronic device. The electronic device can be a switch, a router or any other electronic device that can be provided with the above chip.

[0171] The chip referred to in the embodiments of the present application may be a system on chip (SoC) or a network processor (NP).

[0172] The memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0173] It should be noted that the processor in the embodiment of the present application can be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method embodiment can be completed by an integrated logic circuit of hardware in the processor or an instruction in the form of software. The processor can be a microprocessor or the processor can also be any conventional processor, etc.

[0174] In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in a processor or an instruction in the form of software. The steps of the method disclosed in conjunction with the embodiment of the present application can be directly embodied as a hardware processor for execution, or a combination of hardware and software modules in a processor for execution. The software module can be located in a storage medium mature in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in conjunction with its hardware. To avoid repetition, it is not described in detail here.

[0175] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0176] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0177] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0178] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0179] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0180] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0181] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A circuit, characterized in that: The circuit is located in a chip, and the chip is used to process received messages in a pipeline manner. The circuit includes a first processor and a first processing module connected to the first processor, and the first processing module includes a second processor connected to a first memory, and the transmission delay generated by the second processor performing a read and write operation on the first memory is less than the transmission delay generated by the communication between the first processor and the first processing module; The first processing module further includes a third processor, and the transmission delay generated by the third processor performing read and write operations on the memory connected thereto is less than the transmission delay generated by the first processor communicating with the first processing module, and the circuit further includes a fourth processor and a third memory connected to the fourth processor; wherein, The first processor and the fourth processor belong to a first pipeline, the second processor and the third processor belong to a second pipeline, and the number of processor cores included in the fourth processor is greater than or equal to the number of processor cores included in the first processor.

2. The circuit according to claim 1, characterized in that The second processor is a multi-core processor, and the transmission delay generated by the second processor performing read and write operations on the first memory is the transmission delay generated by any core processor of the multi-core processor included in the second processor performing read and write operations on the first memory.

3. The circuit according to claim 1 or 2, characterized in that: The first processor is connected to the first processing module via a first bus, and the second processor is connected to the first memory via a second bus, wherein a bus width of the second bus is greater than a bus width of the first bus, and / or a length of the second bus is less than a length of the first bus.

4. The circuit according to claim 1 or 2, characterized in that: The first processing module also includes a third processor connected to the second memory, and the transmission delay generated by the third processor performing read and write operations on the second memory is smaller than the transmission delay generated by the first processor communicating with the first processing module.

5. The circuit according to claim 4, characterized in that The first processor is connected to the first processing module via a first bus, the second processor is connected to the first memory via a second bus, the third processor is connected to the second memory via a third bus, and the sum of the bus width of the second bus and the bus width of the third bus is greater than the bus width of the first bus.

6. The circuit according to claim 1 or 2, characterized in that: The first processing module also includes a third processor connected to the first memory, and a transmission delay generated by the third processor performing read and write operations with the first memory is smaller than a transmission delay generated by the communication between the first processor and the first processing module.

7. The circuit according to claim 6, characterized in that The first processor is connected to the first processing module via a first bus, the second processor is connected to the first memory via a second bus, the third processor is connected to the first memory via a third bus, and the sum of the bus width of the second bus and the bus width of the third bus is greater than the bus width of the first bus.

8. The circuit according to claim 1 or 2, characterized in that: The second processor is connected to the third processor via a fourth bus, the fourth processor is connected to the first processor via a fifth bus, and a bus width of the fourth bus is smaller than a bus width of the fifth bus.

9. The circuit according to claim 1 or 2, characterized in that: The first processing module also includes the first memory.

10. A chip, characterized in that: The chip comprises the circuit as claimed in any one of claims 1 to 9.

11. An electronic device, characterized in that: The electronic device comprises the chip according to claim 10, and the electronic device further comprises a receiver and a transmitter, wherein the receiver is used to receive a message and send the message to the chip; The chip is used to process the message; The transmitter is used to obtain the message processed by the chip and send the processed message to another electronic device.

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