Data conversion method, device, electronic device, medium and computer program product

Abstract

The present application relates to the field of machine learning technology, and in particular to a data conversion method, device, electronic device, medium and computer program product, the method comprising: a first processor obtains a type conversion parameter of data to be converted, the type conversion parameter of the data to be converted is used to represent the range parameter of the data to be converted and the range parameter of the data conversion result corresponding to the data to be converted. The first processor determines a first coefficient and a second coefficient according to the type conversion parameter of the data to be converted. The second processor performs a convolution operation on the data to be converted based on the first coefficient and the second coefficient obtained from the first processor, using the first coefficient as the data in the convolution kernel and the second coefficient as the data in the bias term, and obtains a data conversion result corresponding to the data to be converted, thereby realizing a variety of data types that can be supported by the coprocessor, and can also improve the overall data processing efficiency of the second processor.

Description

Technical Field

[0001] The present application relates to the field of machine learning technology, and in particular to a data conversion method, device, electronic device, medium and computer program product. Background Art

[0002] At present, with the rapid application of deep learning technology in many fields, a large number of neural network models based on deep learning have emerged. For example, neural network models such as deep neural network (DNN) and convolutional neural network (CNN). However, existing neural network models all store floating-point data. A neural network model generally requires tens of megabytes to hundreds of megabytes of storage resources, which makes it difficult to port neural network models to terminal devices such as mobile phones for use. In addition, a neural network model requires a large number of multiplication and addition operations. In some application scenarios with high real-time requirements, it is difficult to meet real-time requirements by using floating-point data for calculation. For example, in the scenario of autonomous driving, multiple networks are required to perform calculations at the same time. Therefore, when the neural network model is deployed in embedded electronic devices such as mobile phones, the neural network model generally only supports integer operations.

[0003] Among them, integers include asymmetric quantized data and symmetric quantized data. For example, in actual applications, in order to further reduce the hardware cost of the neural network processor, the neural network processor running the neural network model usually only supports one of asymmetric quantized data operations or symmetric quantized data operations. Summary of the invention

[0004] The purpose of the present application is to provide a data conversion method, device, electronic device, medium and computer program product. Through the data conversion method of the present application, when the coprocessor (second processor) only supports one of asymmetric quantized data operations or symmetric quantized data operations, the coprocessor can convert asymmetric quantized data into symmetric quantized data, or symmetric quantized data into asymmetric quantized data by constructing a two-dimensional convolution operation, so that the coprocessor supports both asymmetric quantized data operations and symmetric quantized data operations. Thereby, the data type that the coprocessor can support is increased while ensuring the hardware cost of the coprocessor.

[0005] Moreover, compared with converting asymmetric quantized data into symmetric quantized data, or converting symmetric quantized data into asymmetric quantized data on the processor (first processor), and then the processor sends the symmetric quantized data or the asymmetric quantized data to the coprocessor, the coprocessor converts asymmetric quantized data into symmetric quantized data, or converts symmetric quantized data into asymmetric quantized data, by constructing a two-dimensional convolution operation, thereby avoiding additional occupation of processor resources and improving the overall data processing efficiency of the coprocessor.

[0006] A first aspect of the present application provides a data conversion method for an electronic device, the electronic device comprising a first processor and a second processor, the method comprising:

[0007] The first processor obtains a type conversion parameter of the data to be converted, where the type conversion parameter of the data to be converted is used to represent a range parameter of the data to be converted and a range parameter of a data conversion result corresponding to the data to be converted.

[0008] The first processor determines the first coefficient and the second coefficient according to a type conversion parameter of the data to be converted.

[0009] The second processor performs a convolution operation on the data to be converted based on the first coefficient and the second coefficient obtained from the first processor, using the first coefficient as the data in the convolution kernel and the second coefficient as the data in the bias item, to obtain a data conversion result corresponding to the data to be converted.

[0010] It is not difficult to understand that the data to be converted may be symmetrical quantized data, and the data corresponding to the data to be converted may be asymmetrical quantized data. The data to be converted may also be asymmetrical quantized data, and the data corresponding to the data to be converted may be symmetrical quantized data. When the data to be converted is asymmetrical quantized data, and the data conversion result corresponding to the data to be converted is symmetrical quantized data, the first coefficient is the first quantization coefficient mentioned below, and the second coefficient is the second quantization coefficient mentioned below. When the data to be converted is symmetrical quantized data, and the data conversion result corresponding to the data to be converted is asymmetrical quantized data, the first coefficient is the third quantization coefficient mentioned below, and the second coefficient is the fourth quantization coefficient mentioned below.

[0011] In a possible implementation of the first aspect above, the type conversion parameter of the data to be converted includes at least one of the following: an asymmetric quantization coefficient, a zero point value of the asymmetric quantization data, and a symmetric quantization coefficient.

[0012] In a possible implementation of the first aspect, the first processor determines the first coefficient and the second coefficient according to a type conversion parameter of the data to be converted, including:

[0013] When the data to be converted is asymmetric quantized data, and the data conversion result corresponding to the data to be converted is symmetric quantized data, the first coefficient is calculated by the following formula:

[0014] Wf=AS*S

[0015] The second coefficient is calculated by the following formula:

[0016] Bf=-ZP*AS*S

[0017] Among them, AS represents an asymmetric quantization coefficient, S represents a symmetric quantization coefficient, and ZP represents the zero point value of the asymmetric quantization data.

[0018] In a possible implementation of the first aspect, the first processor determines the first coefficient and the second coefficient according to a type conversion parameter of the data to be converted, including:

[0019] When the data to be converted is symmetrical quantized data, and the data conversion result corresponding to the data to be converted is asymmetrical quantized data, the second coefficient is the zero point value of the asymmetrical quantized data, and the first coefficient is calculated by the following formula:

[0020]

[0021] Among them, AS represents an asymmetric quantization coefficient, and S represents a symmetric quantization coefficient.

[0022] In a possible implementation of the first aspect above, a height value and a width value of the convolution kernel are respectively 1.

[0023] A second aspect of the present application provides a data conversion device, the device comprising:

[0024] The acquisition module is used for the first processor to acquire the type conversion parameters of the data to be converted, and the type conversion parameters of the data to be converted are used to represent the range parameters of the data to be converted and the range parameters of the data conversion result corresponding to the data to be converted.

[0025] The determination module is used for the first processor to determine the first coefficient and the second coefficient according to the type conversion parameter of the data to be converted.

[0026] The convolution module is used for the second processor to perform a convolution operation on the data to be converted based on the first coefficient and the second coefficient obtained from the first processor, using the first coefficient as the data in the convolution kernel and the second coefficient as the data in the bias item, to obtain a data conversion result corresponding to the data to be converted.

[0027] In a possible implementation of the second aspect, the type conversion parameter of the data to be converted includes at least one of the following: an asymmetric quantization coefficient, a zero point value of the asymmetric quantization data, and a symmetric quantization coefficient.

[0028] The first processor determines the first coefficient and the second coefficient according to the type conversion parameter of the data to be converted, including:

[0029] When the data to be converted is asymmetric quantized data, and the data conversion result corresponding to the data to be converted is symmetric quantized data, the first coefficient is calculated by the following formula:

[0030] Wf=AS*S

[0031] The second coefficient is calculated by the following formula:

[0032] Bf=-ZP*AS*S

[0033] Among them, AS represents an asymmetric quantization coefficient, S represents a symmetric quantization coefficient, and ZP represents the zero point value of the asymmetric quantization data.

[0034] In a possible implementation of the second aspect, the first processor determines the first coefficient and the second coefficient according to a type conversion parameter of the to-be-converted data, including:

[0035] When the data to be converted is symmetrical quantized data, and the data conversion result corresponding to the data to be converted is asymmetrical quantized data, the second coefficient is the zero point value of the asymmetrical quantized data, and the first coefficient is calculated by the following formula:

[0036]

[0037] Among them, AS represents an asymmetric quantization coefficient, and S represents a symmetric quantization coefficient.

[0038] In a possible implementation of the second aspect, the height and width of the convolution kernel are respectively 1.

[0039] The third aspect of the present application provides an electronic device, comprising: a memory for storing instructions executed by one or more processors of the electronic device, and multiple processors for running the instructions in the memory to execute the data conversion method of the first aspect.

[0040] The fourth aspect of the present application provides a computer-readable storage medium, including: instructions stored on the readable medium of an electronic device, which, when executed on the electronic device, enables the electronic device to execute the data conversion method of the first aspect.

[0041] A fifth aspect of the present application provides a computer program product, including instructions for implementing the data conversion method of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1According to some embodiments of the present application, a forward calculation flow chart of a convolutional neural network operation is shown;

[0043] Figure 2 According to some embodiments of the present application, a schematic diagram of the structure of a system on chip (System on Chip, SOC) for executing a data conversion method is shown;

[0044] Figure 3 According to some embodiments of the present application, a schematic diagram of asymmetric quantized data contained in an image is shown;

[0045] Figure 4 According to some embodiments of the present application, a schematic diagram of a process of converting asymmetric quantized data into symmetric quantized data by discrete components of a system on a chip is shown;

[0046] Figure 5 According to some embodiments of the present application, a schematic diagram of converting asymmetric quantized data contained in an image into corresponding symmetric quantized data is shown;

[0047] Figure 6 According to some embodiments of the present application, another schematic diagram of a process of converting asymmetric quantized data into symmetric quantized data by discrete components of a system on a chip is shown;

[0048] Figure 7 According to some embodiments of the present application, a schematic diagram of an interactive process of converting asymmetric quantized data into symmetric quantized data by discrete components of another system-on-chip is shown;

[0049] Fig. 8A According to some embodiments of the present application, a convolution layer performs a two-dimensional convolution operation on a matrix to finally obtain a schematic diagram of the matrix;

[0050] FIG. 8B to FIG. 8D According to an embodiment of the present application, an example diagram of a convolution output matrix obtained by convolving asymmetric quantized data in a matrix with a convolution kernel K1 is shown;

[0051] Fig. 9 According to some embodiments of the present application, a schematic diagram of an interactive process of converting symmetric quantized data into asymmetric quantized data by discrete components of another system-on-chip is shown;

[0052] Fig.10 According to some embodiments of the present application, a schematic diagram of a data conversion device is shown;

[0053] Fig.11 According to some embodiments of the present application, a block diagram of an electronic device including a system on a chip is shown. DETAILED DESCRIPTION

[0054] The illustrative embodiments of the present application include but are not limited to a data conversion method, device, electronic device, medium and computer program product. The embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0055] Since the present application involves the mutual conversion between asymmetric quantized data and symmetric quantized data, two-dimensional convolution operations, and the conversion of floating-point data into symmetric quantized data, in order to more clearly illustrate the scheme of the embodiments of the present application, some of the contents involved in the embodiments of the present application are explained below.

[0056] (1) Integer data

[0057] Numeric data that does not contain a decimal part. Integer data is only used to represent integers. Among them, integer data includes asymmetric quantized data and symmetric quantized data. Among them, asymmetric quantized data is a quantized integer data whose zero point (ZP) is not equal to 0. Symmetric quantized data is a quantized integer data whose zero point is equal to 0. For example, the value range of 8-bit symmetric quantized data int8 is [-128,127], and the value range of 8-bit asymmetric quantized data uint8 is [0,255].

[0058] (2) Converting asymmetric quantized data into symmetric quantized data

[0059] The data conversion formula from asymmetric quantization data to symmetric quantization data is as follows:

[0060] SD=(ASD-ZP)*AS*S

[0061] Among them, SD represents symmetric quantization data, ASD represents asymmetric quantization data, AS represents an asymmetric quantization coefficient, ZP represents the zero point value of the asymmetric quantization data, and S represents a symmetric quantization coefficient.

[0062] (3) Convolutional Neural Network (CNN)

[0063] A convolutional neural network is a multi-layer neural network, each layer consists of multiple two-dimensional planes, and each plane consists of multiple independent neurons. Multiple neurons in each plane share weights, and the number of parameters in the neural network can be reduced by weight sharing. A convolutional neural network can be composed of neural units, and a neural unit can refer to an operation unit with Fin as input. The output Fout of the operation unit can be expressed by the following formula:

[0064] Fout=CONV(Fin,Kernel) stride＝1 +B

[0065] Where Fin represents input data. Kernel represents the convolution kernel. B represents the bias term of the convolution. CONV() is the convolution operation of the convolution layer. stride=1 means that the stride is set to 1 during the convolution operation.

[0066] In some embodiments, the parameters of the convolutional neural network model may include weights and bias terms. In the convolutional neural network calculation process, the weights (i.e., convolution kernels) are used for multiplication operations (multiplied with corresponding input data), and the biases are used for addition operations. Figure 1 This is the forward calculation flow chart of the convolutional neural network operation, such as Figure 1 As shown in the figure, Fin represents the input data of the convolution layer, Kernel represents the convolution kernel, B represents the bias term, and CONV() represents the convolution operation of the convolution layer. Fout′ represents the result of convolution of the input data of the convolution layer and the data in the convolution kernel K1. Fout represents the final output result of the convolution layer. Figure 1 In FIG. 1001, 1001 indicates calculating the convolution product of the input data of the convolution layer and the data of the convolution kernel to obtain Fout′. 1002 indicates adding the corresponding data in the bias term B based on Fout′ to obtain the final output result Fout of the convolution layer.

[0067] (4) Data quantification

[0068] It may refer to converting a large data type number (e.g., a 32-bit floating point number) into a smaller data type number (e.g., 8-bit symmetrical quantized data or asymmetrical quantized data). For example, the data quantization formula for converting a floating point number into asymmetrical quantized data is as follows:

[0069] The symmetric quantization data Q can be calculated by the following formula:

[0070]

[0071]

[0072] Wherein, b represents the number of bits occupied by the symmetric quantization data Q. S_range represents the range of the floating point number F. abs() represents the absolute value function. max() represents the maximum value function. F represents a floating point number. S represents the range conversion coefficient of floating point-symmetric quantization.

[0073] (5) Converting symmetric quantized data into asymmetric quantized data

[0074] The data conversion formula from symmetric quantized data to asymmetric quantized data is as follows:

[0075]

[0076] Among them, ASD represents asymmetric quantization data, SD represents symmetric quantization data, AS represents an asymmetric quantization coefficient, ZP represents the zero point value of the asymmetric quantization data, and S represents a symmetric quantization coefficient.

[0077] Before introducing the data conversion method provided in the embodiment of the present application in detail, the hardware structure of the system on chip is first introduced.

[0078] Figure 2 The figure shows a structural schematic diagram of a system on chip (SOC) 300 that can execute a data conversion method, including a processor 310 (first processor), an interconnection unit 330, an integrated memory controller unit 350; a coprocessor 320 (second processor); a static random access memory (SRAM) unit 360 and a direct memory access (DMA) control unit 340.

[0079] Among them, the processor 310 can be used to perform specific arithmetic and / or logical operations, including one or more processing units, such as a central processing unit (CPU), a graphics processor (GPU), a digital signal processor (DSP), a microprocessor (MCU), and a programmable logic device (Field Programmable Gate Array, FPGA).

[0080] The coprocessor 320 can be used to execute the computing process of the neural network, and includes one or more processing units, for example, a processing module or processing circuit that can include an artificial intelligence processing unit (AIPU), a neural network processor (NPU), etc. It can also include multiple application-specific integrated circuits (ASICs) suitable for running neural network models, such as a convolution computing unit, a vector computing unit, etc.

[0081] The SRAM unit 360 can be used to load and cache data and / or instructions. For example, in some embodiments, the SRAM unit 360 can be used not only to load or cache the symmetric quantization coefficients, asymmetric quantization coefficients, and zero-point values ​​of asymmetric quantization data that the processor 310 needs to process, but also to load or cache the first floating-point coefficient, the second floating-point coefficient, the first quantization coefficient, the second quantization coefficient, etc. generated by the processor 310. In addition, the SRAM unit 360 can also be used to load or cache asymmetric quantization data.

[0082] In some embodiments, the processor 310 may be used to obtain the symmetric quantization coefficient, the asymmetric quantization coefficient, and the zero point value of the asymmetric quantization data from the SRAM unit 360, and determine the first floating point coefficient and the second floating point coefficient according to the symmetric quantization coefficient, the asymmetric quantization coefficient, and the zero point value of the asymmetric quantization data. The processor 310 may also be used to convert the first floating point coefficient and the second floating point coefficient into the first quantization coefficient and the second quantization coefficient, and send the first quantization coefficient and the second quantization coefficient to the coprocessor 320.

[0083] In some embodiments, the coprocessor 320 performs convolution product on the asymmetric quantized data and the first quantization coefficient in the convolution kernel according to the received first quantization coefficient and the second quantization coefficient, with the first quantization coefficient as the data in the convolution kernel of the two-dimensional convolution operation and the second quantization coefficient as the bias data of the two-dimensional convolution operation, and sums each data generated by the convolution product with each second quantization coefficient in the bias item to generate symmetric quantization data corresponding to the asymmetric quantization data.

[0084] It is understandable that if Figure 2 The exemplary structure of the SOC 300 shown does not constitute a specific limitation on the SOC 300. In other embodiments of the present application, the SOC 300 may include more or fewer components than shown in the figure, or combine some components, or split some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0085] It can be understood that the electronic device including SOC300 can be any electronic device capable of performing convolutional neural network operations, including but not limited to laptop computers, desktop computers, tablet computers, mobile phones, servers, wearable devices, head-mounted displays, mobile email devices, portable game consoles, portable music players, reader devices, and televisions in which one or more processors are embedded or coupled, and the embodiments of the present application are not limited thereto.

[0086] As mentioned above, in order to reduce hardware costs, the processor running the neural network model usually only supports one of asymmetric quantized data operations or symmetric quantized data operations. For example, the coprocessor 320 only supports the processing of symmetric quantized data.

[0087] For example, the coprocessor 320 needs to process the asymmetric quantized data contained in the image 30. Figure 3 As shown in (a) of FIG. 3 , the image 30 is a color image of 64*64 pixels. The image 30 can be represented by three matrices of 64*64 pixels. Figure 3 As shown in (b), matrix 31-1 is a matrix formed by the values ​​of each pixel point of the R (red) channel of image 30, and matrix 31-1 specifically includes 64*64 data of the R channel of image 30. Matrix 31-2 is a matrix formed by the values ​​of each pixel point of the G (green) channel of image 30, and matrix 31-2 specifically includes 64*64 pixel points of the G channel of image 30. Matrix 31-3 is a matrix formed by the values ​​of each pixel point of the B (blue) channel of image 30, and matrix 31-3 specifically includes 64*64 data of the B channel of image 30. The three matrices of RGB are called the three channels of image 30. Coprocessor 320 can run a neural network model to process the data contained in image 30 and identify that image 30 is a house. However, since the values ​​of the pixel points contained in each channel of image 30 are asymmetric quantized data, the asymmetric quantized data contained in image 30 needs to be converted into symmetric quantized data before coprocessor 320 can process image 30.

[0088] In order to ensure that the data contained in the image 30 input to the coprocessor 320 is symmetrical quantized data, the processor 310 can first convert the asymmetrical quantized data contained in the image 30 into symmetrical quantized data, and then input the converted symmetrical quantized data into the coprocessor 320. The coprocessor 320 can run a neural network model to process the symmetrical quantized data contained in the image 30 and identify that the image 30 is a house.

[0089] Specifically, the following takes the image 30 including asymmetric quantized data as an example to illustrate the process in which the discrete components of the SOC 300 cooperate to convert the asymmetric quantized data included in the image 30 into symmetric quantized data when the coprocessor 320 only supports the processing of symmetric quantized data.

[0090] based on Figure 2 The structure of the system on chip 300 shown in FIG. Figure 4 FIG. 3 shows a schematic diagram of a process of converting asymmetric quantized data into symmetric quantized data by discrete components of a system on chip 300. Specifically, Figure 4As shown, the processor 310 can obtain the asymmetric quantization data of the image 30 to be processed. The processor 310 also obtains the symmetric quantization coefficient, the asymmetric quantization coefficient, and the zero point value of the asymmetric quantization data. The processor 310 can generate symmetric quantization data corresponding to the asymmetric quantization data of the image 30 according to the symmetric quantization coefficient, the asymmetric quantization coefficient, and the zero point value of the asymmetric quantization data. Then, the processor 310 sends the symmetric quantization data of the image 30 to the coprocessor 320.

[0091] In some embodiments, according to the symmetric quantization coefficient, the asymmetric quantization coefficient and the zero point value of the asymmetric quantization data, the symmetric quantization data SD corresponding to the asymmetric quantization data in the image 30 can be expressed by formula (1):

[0092] SD=(ASD-ZP)*AS*S (1)

[0093] In formula (1), ASD represents the asymmetric quantization data in the image 30, AS represents the asymmetric quantization coefficient, ZP represents the zero point value of the asymmetric quantization data, and S represents the symmetric quantization coefficient.

[0094] For ease of explanation, it is assumed that the matrix 40 is a submatrix of the matrix 31 - 1 in the image 30 , and the process of converting the asymmetric quantized data in the image 30 into the corresponding symmetric quantized data is briefly described using the matrix 40 as an example.

[0095] like Figure 5 As shown, matrix 40 includes 3*3 asymmetric quantization data. The asymmetric quantization data of the first row of matrix 40 are 0, 1, and 2 respectively. The asymmetric quantization data of the second row of matrix 40 are 3, 4, and 1 respectively. The asymmetric quantization data of the third row of matrix 40 are 5, 2, and 5 respectively. For example, the zero point value ZP of the asymmetric quantization data is 3, the value of the asymmetric quantization coefficient AS is 0.4, and the value of the symmetric quantization coefficient S is 3.3. The symmetric quantization data corresponding to each asymmetric quantization data in matrix 40, that is, the symmetric quantization data in matrix 41, is calculated by formula (1). For example, Figure 5 As shown, the asymmetric quantized data 0 in the matrix 40 corresponds to the symmetric quantized data −3 in the matrix 41 .

[0096] Depend on Figures 4 to 5 As can be seen from the description, the processor 310 can execute the operation of formula (1) to convert the asymmetric quantized data in the image 30 into corresponding symmetric quantized data. Then, the processor 310 sends the symmetric quantized data of the image 30 to the coprocessor 320, thereby ensuring that the coprocessor 320 can successfully identify the house in the image 30.

[0097] However, in the case where the coprocessor 320 needs to process a large number of images of the video stream, each time the coprocessor 320 processes a frame of image, the processor 310 needs to obtain the asymmetric quantization data of the frame of image to be processed from the SRAM unit 360 in advance, and perform the operation of formula (1) to convert the asymmetric quantization data of the frame of image to be processed into corresponding symmetric quantization data. The processor 310 then sends the converted symmetric quantization data of the frame of image to be processed to the coprocessor 320. It can be understood that in this process, the processor 310 needs to frequently read the asymmetric quantization data of the image to be processed from the SRAM unit 360, and frequently send the symmetric quantization data of the image to be processed to the coprocessor 320, which requires the processor 310 to perform system scheduling and memory copying, which additionally occupies the resources of the processor 310.

[0098] Therefore, in order to avoid occupying additional resources of the processor 310, the present application provides another data conversion method. Figure 6 A schematic diagram of another process of converting asymmetric quantized data into symmetric quantized data by discrete component processing of a system on chip 300 is shown. By using the operation factor AS*S in formula (1) as the convolution kernel, the operation factor -ZP*AS*S as the bias term, and the asymmetric quantized data of the image 30 as the data to be convolved, a two-dimensional convolution operation is constructed on the coprocessor 320, and the result of the convolution operation data is the symmetric quantized data corresponding to the asymmetric quantized data of the image 30.

[0099] Specifically, Figure 6 As shown, since the coprocessor 320 only supports symmetric quantization data operations, the processor 310 can determine the first quantization coefficient and the second quantization coefficient according to the acquired symmetric quantization coefficient, the asymmetric quantization coefficient and the zero point value of the asymmetric quantization data. The first quantization coefficient is the operation factor AS*S in formula (1), and the second quantization coefficient is the operation factor -ZP*AS*S in formula (1). The coprocessor 320 constructs a two-dimensional convolution operation based on the first quantization coefficient, the second quantization coefficient and the asymmetric quantization data of the image 30, and generates symmetric quantization data corresponding to the asymmetric quantization data of the image 30.

[0100] Combination Figure 6 , Figure 7 FIG. 3 is a schematic diagram showing the interactive process of converting asymmetric quantized data into symmetric quantized data by discrete components of another system on chip 300. Figure 7 As shown, specifically including:

[0101] S701: The processor 310 obtains type conversion parameters of asymmetric quantized data.

[0102] In some embodiments, the type conversion parameter of the asymmetric quantized data is used to represent the range parameter of the asymmetric quantized data and the range parameter of the symmetric quantized data corresponding to the asymmetric quantized data. The type conversion parameter of the asymmetric quantized data includes at least one of the following: an asymmetric quantization coefficient, a zero point value of the asymmetric quantized data, and a symmetric quantization coefficient.

[0103] S702: The processor 310 determines a first floating-point coefficient and a second floating-point coefficient according to a type conversion parameter of the asymmetric quantized data.

[0104] In some embodiments, the processor 310 may determine the first floating-point coefficient according to the symmetric quantization coefficient and the asymmetric quantization coefficient. The first floating-point coefficient Wf may be expressed by formula (2):

[0105] Wf=AS*S (2)

[0106] In formula (2), AS represents an asymmetric quantization coefficient, and S represents a symmetric quantization coefficient.

[0107] It is not difficult to see that the first floating-point coefficient Wf in formula (2) is the product of the asymmetric quantization coefficient AS in formula (2) and the symmetric quantization coefficient S. Since the symmetric quantization coefficient S and the asymmetric quantization coefficient AS are both floating-point numbers, the first floating-point coefficient Wf is also a floating-point number.

[0108] In some embodiments, the processor 310 may determine the second floating-point coefficient according to the symmetric quantization coefficient, the asymmetric quantization coefficient, and the zero point of the asymmetric quantization data. The second floating-point coefficient Bf may be expressed by formula (3):

[0109] Bf=-ZP*AS*S (3)

[0110] In formula (3), AS represents an asymmetric quantization coefficient, S represents a symmetric quantization coefficient, and ZP represents a zero point value of the asymmetric quantization data.

[0111] It is not difficult to see that the second floating-point coefficient Bf in formula (3) is the inverse of the product of the asymmetric quantization coefficient, the symmetric quantization coefficient, and the zero value of the asymmetric quantization data in formula (1). Since the symmetric quantization coefficient S and the asymmetric quantization coefficient AS are both floating-point numbers, the second floating-point coefficient Bf is also a floating-point number.

[0112] S703: The processor 310 converts the first floating-point coefficient and the second floating-point coefficient into a first quantized coefficient and a second quantized coefficient.

[0113] Since both the first floating-point coefficient and the second floating-point coefficient are floating-point numbers, the processor 310 needs to convert the first floating-point coefficient into corresponding symmetrical quantized data (i.e., the first quantized coefficient) and the second floating-point coefficient into corresponding symmetrical quantized data (i.e., the second quantized coefficient) before inputting them into the coprocessor 320. Then, the coprocessor 320 uses the symmetrical quantized data (i.e., the first quantized coefficient) corresponding to the first floating-point coefficient as the data of the convolution kernel and the symmetrical quantized data (i.e., the second quantized coefficient) corresponding to the second floating-point coefficient as the data in the bias term. According to the data of the convolution kernel and the data in the bias term, the asymmetrical quantized data of the image 30 input to the coprocessor 320 is convolved, and the result of the convolution output is the symmetrical quantized data corresponding to the asymmetrical quantized data of the image 30.

[0114] In some embodiments, the processor 310 can convert the floating-point number of the first floating-point coefficient into a corresponding symmetric quantization number according to the floating-point-symmetric quantization range conversion coefficient of the first floating-point coefficient. The symmetric quantization number corresponding to the floating-point number of the first floating-point coefficient is also called the first quantization coefficient.

[0115] In some embodiments, the processor 310 obtains the first quantization coefficient according to the range conversion coefficient of the floating point-symmetric quantization of the first floating point coefficient and the first floating point coefficient. Specifically, the first quantization coefficient Wq can be calculated by the following formula (4):

[0116]

[0117] In formula (4), Wf represents the first floating point coefficient, and Ws represents the floating point-symmetric quantization range conversion coefficient of the first floating point coefficient.

[0118] The processor 310 may obtain the floating-point-symmetric quantization range conversion coefficient of the first floating-point coefficient according to the range of the first floating-point coefficient Wf and the number of bits occupied by the first quantization coefficient Wq. Specifically, the floating-point-symmetric quantization range conversion coefficient Ws of the first floating-point coefficient may be calculated by the following formula (5):

[0119]

[0120] In formula (5), b represents the number of bits occupied by the first quantization coefficient Wq. Wf_range represents the range of the first floating-point coefficient Wf. abs() represents the absolute value function. max() represents the maximum value function.

[0121] In some embodiments, the processor 310 can convert the floating-point number of the second floating-point coefficient into a corresponding symmetric quantization number according to the floating-point-symmetric quantization range conversion coefficient of the second floating-point coefficient. The symmetric quantization number corresponding to the floating-point number of the second floating-point coefficient is also called the second quantization coefficient.

[0122] For example, the processor 310 obtains the second quantization coefficient according to the range conversion coefficient of the floating point-symmetric quantization of the second floating point coefficient and the second floating point coefficient. Specifically, the second quantization coefficient Bq can be calculated by the following formula (6):

[0123]

[0124] In formula (6), Bf represents the second floating-point coefficient, and Bs represents the floating-point-symmetric quantization range conversion coefficient of the second floating-point coefficient.

[0125] The processor 310 can calculate the range conversion coefficient Bs of the floating-point-symmetric quantization of the second floating-point coefficient according to the range conversion coefficient Ws of the floating-point-symmetric quantization of the first floating-point coefficient and the range conversion coefficient Xs of the asymmetric quantization data of the image 30 by the following formula (7):

[0126] Bs=Ws*Xs (7)

[0127] In formula (7), Ws represents the range conversion coefficient of the floating point-symmetrical quantization of the first floating point coefficient, and Xs represents the range conversion coefficient of the asymmetrical quantized data of the image 30.

[0128] S704: The processor 310 sends the first quantization coefficient and the second quantization coefficient to the coprocessor 320.

[0129] S705 : the coprocessor 320 obtains asymmetric quantization data of the image 30 .

[0130] It can be understood that the execution order of the data conversion process described above is not limited to the execution order of steps S701 to S705. In other embodiments of the present application, the coprocessor 320 may first obtain the asymmetric quantization data of the image 30, and then the processor 310 obtains the symmetric quantization coefficient, the asymmetric quantization coefficient and the zero point value of the asymmetric quantization data, and determines the first quantization coefficient and the second quantization coefficient based on the obtained symmetric quantization coefficient, the asymmetric quantization coefficient and the zero point value of the asymmetric quantization data. For example, first execute step S705, and then execute steps S701 to S704. According to actual applications, the present application may Figure 7 The execution order of the data conversion process in is not specifically limited.

[0131] S706 : The coprocessor 320 constructs a two-dimensional convolution operation according to the first quantization coefficient, the second quantization coefficient, and the asymmetric quantization data of the image 30 , and generates symmetric quantization data corresponding to the asymmetric quantization data of the image 30 .

[0132] In some embodiments, the coprocessor 320 performs convolution product on the asymmetric quantized data in the image 30 and the first quantization coefficient in the convolution kernel according to the received first quantization coefficient and the second quantization coefficient, with the first quantization coefficient as the data in the convolution kernel of the two-dimensional convolution operation and the second quantization coefficient as the bias data of the two-dimensional convolution operation, and sums each data generated by the convolution product with each second quantization coefficient in the bias item to generate symmetric quantization data corresponding to the asymmetric quantization data in the image 30.

[0133] As mentioned above, matrix 40 is a submatrix of matrix 31-1 in image 30. The following uses matrix 40 as an example to illustrate the process of converting asymmetric quantized data in image 30 into corresponding symmetric quantized data through a two-dimensional convolution operation.

[0134] Fig. 8A FIG. 4 shows a schematic diagram of a convolution layer performing a two-dimensional convolution operation on a matrix 40 to finally obtain a matrix 41. Fig. 8A As shown, the convolution kernel K1 is a 1×1 two-dimensional matrix, and the data in the convolution kernel K1 is the first quantization coefficient. It can be understood that in order to ensure that each symmetric quantization data in the convolution output matrix output by the convolution layer corresponds one-to-one to each asymmetric quantization data in the matrix to be converted, the bias item matrix B1 has the same dimension as the matrix 40, both of which are 3×3 two-dimensional matrices, and the bias item matrix B1 includes 3×3 second quantization coefficients.

[0135] like Fig. 8A As shown, the matrix 40 includes 3×3 asymmetric quantized data, and the asymmetric quantized data in the first row of the matrix 40 are 0, 1, and 2. The asymmetric quantized data in the second row of the matrix 40 are 3, 4, and 1. The asymmetric quantized data in the third row of the matrix 40 are 5, 2, and 5.

[0136] Assume that the value of the first quantization coefficient calculated in step S703 is 1, and the value of the second quantization coefficient is -3. Fig. 8A As shown, the convolution kernel K1 includes a first quantization coefficient 1. The bias matrix B1 includes 3×3 second quantization coefficients -3.

[0137] Specifically, Fig. 8AAs shown, matrix 40 is convolved with convolution kernel K1 to generate matrix 42, and the first row of asymmetric quantized data in matrix 42 is 0, 1, and 2 respectively. The second row of asymmetric quantized data in matrix 42 is 3, 4, and 1 respectively. The third row of asymmetric quantized data in matrix 42 is 5, 2, and 5 respectively. The data in matrix 42 is added to the data in bias matrix B1 to generate symmetric quantized data in matrix 41. The first row of asymmetric quantized data in matrix 41 is -3, -2, and -1 respectively. The second row of asymmetric quantized data in matrix 41 is 0, 1, and -2 respectively. The third row of asymmetric quantized data in matrix 41 is 2, -1, and 2 respectively. It can be understood that the symmetric quantized data in matrix 41 is the symmetric quantized data corresponding to the asymmetric quantized data in matrix 40. For example, the symmetric quantization data corresponding to the asymmetric quantization data 0 in the first row and first column of matrix 40 is the symmetric quantization data -3 in the first row and first column of matrix 41, the symmetric quantization data corresponding to the asymmetric quantization data 1 in the first row and second column of matrix 40 is the symmetric quantization data -2 in the first row and second column of matrix 41, and so on. The symmetric quantization data corresponding to the asymmetric quantization data 5 in the third row and third column of matrix 40 is the symmetric quantization data 2 in the third row and third column of matrix 41.

[0138] The convolution kernel K1 performs a convolution operation on the matrix 40 to obtain the data in the matrix 42, which is specifically as follows:

[0139] like FIG. 8B to FIG. 8D As shown, for a 3×3 matrix 40, the first data 0 in the upper left corner is taken as the starting point, the step length is 1, and the filling is 0, and the 1×1 sliding window slides on the 3×3 matrix 40. For example, Figure 8B As shown, first slide from left to right in the width direction to obtain the first row of data of matrix 42, which are 0, 1, and 2 respectively. Figure 8C As shown, starting from the first asymmetric quantized data 3 in the second row of matrix 40, sliding from left to right in the width direction, the second row of data of matrix 42 is obtained in sequence, which are 3, 4, and 1 respectively. Fig.8D As shown, starting from the first asymmetric quantized data 5 in the third row of the matrix 40, slide from left to right in the width direction to obtain the second row of data of the matrix 42, which are 5, 2, and 5 respectively.

[0140] It is not difficult to see that the above two-dimensional convolution operation actually multiplies each asymmetric quantized data in the matrix 40 and the data in the two-dimensional convolution kernel K1 of size 1*1, and finally obtains a two-dimensional matrix 42 of size 3*3.

[0141] Depend on FIG. 8A to FIG. 8DIt can be seen that the coprocessor 320 constructs a two-dimensional convolution operation, uses the first quantization coefficient as the data of the convolution kernel, uses the second quantization coefficient as the data in the bias item B1, performs convolution product with the first quantization coefficient in the convolution kernel K1 and the matrix 40 (asymmetric quantization data in the image 30), and sums each data generated by the convolution product with the second quantization coefficient in the bias item B1 to generate symmetric quantization data corresponding to the asymmetric quantization data. In this way, when the hardware of the coprocessor 320 does not support asymmetric quantization data operation, the asymmetric quantization data is converted into symmetric quantization data in the coprocessor 320.

[0142] It is understood that the interactive process of data conversion in this application is not limited to Figure 7 In the execution order of step S701 to step S706, in actual application, the execution order of step S701 to step S706 can also be adjusted. In addition, one or more interaction processes in step S701 to step S706 can be reordered, omitted or added.

[0143] From the above description, we can see that Figure 4 The processor 310 in the image 30 converts the asymmetric quantized data in the image 30 into corresponding symmetric quantized data by executing the operation of formula (1) through the processor 310, and then the processor 310 sends the symmetric quantized data of the image 30 to the coprocessor 320. Figure 6 or Figure 7 The coprocessor 320 in the image 30 can also convert the asymmetric quantized data in the image 30 into corresponding symmetric quantized data by constructing a two-dimensional convolution operation.

[0144] And, it is not difficult to understand that compared with Figure 4 In the data conversion process, Figure 6 or Figure 7 In the data conversion process, the coprocessor 320 only needs to obtain the first quantization coefficient and the second quantization coefficient from the processor 310 once, that is, the processor 310 only needs to execute steps S701 to S703 once. Then the coprocessor 320 uses the first quantization coefficient as the data in the convolution kernel and the second quantization coefficient as the data in the bias term to process a large number of images in the video stream. The processor 310 does not need to perform data conversion on the data of each frame of image for each processing of the data of the frame of image, which additionally occupies a large amount of computing resources of the processor 310. Moreover, converting asymmetric quantization data into symmetric quantization data in the coprocessor 320 can also improve the overall data processing efficiency of the coprocessor 320.

[0145] In some other embodiments, the data conversion method of the present application is also applicable to converting symmetric quantized data into asymmetric quantized data. For example, the processor 310 can determine the third quantization coefficient and the fourth quantization coefficient based on the acquired symmetric quantization coefficient, the asymmetric quantization coefficient and the zero point value of the asymmetric quantized data. And send the determined third quantization coefficient and the fourth quantization coefficient to the coprocessor 320. The third quantization coefficient is the operation factor in the operation formula for converting symmetric quantized data into asymmetric quantized data. The fourth quantization coefficient is the operation factor ZP in the operation formula for converting symmetric quantization data into asymmetric quantization data. The coprocessor 320 constructs a two-dimensional convolution operation based on the third quantization coefficient, the fourth quantization coefficient and the symmetric quantization data to generate asymmetric quantization data corresponding to the symmetric quantization data.

[0146] Fig. 9 FIG. 3 is a schematic diagram showing an interactive process of discrete components of a system on chip 300 converting symmetrical quantized data into asymmetrical quantized data. Fig. 9 As shown, specifically including:

[0147] S901: The processor 310 obtains type conversion parameters of symmetric quantized data.

[0148] In some embodiments, the type conversion parameter of the symmetric quantization data is used to represent the range parameter of the symmetric quantization data and the range parameter of the asymmetric quantization data corresponding to the symmetric quantization data. The type conversion parameter of the symmetric quantization data includes at least one of the following: an asymmetric quantization coefficient, a zero point value of the asymmetric quantization data, and a symmetric quantization coefficient.

[0149] S902: The processor 310 determines a third floating-point coefficient and a fourth quantization coefficient according to a type conversion parameter of the symmetric quantization data.

[0150] In some embodiments, the processor 310 may determine the third floating-point coefficient according to the symmetric quantization coefficient and the asymmetric quantization coefficient. The fourth quantization coefficient Wf may be expressed by formula (8):

[0151]

[0152] In formula (8), AS represents an asymmetric quantization coefficient, and S represents a symmetric quantization coefficient.

[0153] It is not difficult to see that the third floating-point coefficient Wf′ in formula (8) is the operation factor in the operation formula for converting symmetric quantized data into asymmetric quantized data. Since both the symmetric quantization coefficient S and the asymmetric quantization coefficient AS are floating point numbers, the third floating point coefficient Wf′ is also a floating point number.

[0154] In some embodiments, the processor 310 may use the zero point value of the asymmetric quantization data as the fourth quantization coefficient.

[0155] S903: The processor 310 converts the third floating-point coefficient into a third quantized coefficient.

[0156] Since the third floating-point coefficient is a floating-point number, the processor 310 needs to convert the third floating-point coefficient into corresponding symmetrical quantized data (i.e., the third quantized coefficient) before inputting it into the coprocessor 320. Then, the coprocessor 320 uses the symmetrical quantized data (i.e., the third quantized coefficient) corresponding to the third floating-point coefficient as the data of the convolution kernel and the fourth quantized coefficient as the data in the bias item. According to the data of the convolution kernel and the data in the bias item, the symmetrical quantized data input into the coprocessor 320 is subjected to a convolution operation, and the result of the convolution output is the asymmetrical quantized data corresponding to the symmetrical quantized data.

[0157] In some embodiments, the processor 310 can convert the floating-point number of the third floating-point coefficient into a corresponding symmetric quantization number according to the floating-point-symmetric quantization range conversion coefficient of the third floating-point coefficient. The symmetric quantization number corresponding to the floating-point number of the third floating-point coefficient is also called the third quantization coefficient.

[0158] In some embodiments, the processor 310 can calculate the third quantization coefficient Wq according to the range conversion coefficient of the floating-point-symmetric quantization of the third floating-point coefficient and the third floating-point coefficient by the following formula (4):

[0159]

[0160] In formula (4), Wf′ represents the third floating point coefficient, and Ws′ represents the floating point-symmetric quantization range conversion coefficient of the third floating point coefficient.

[0161] The processor 310 may calculate the floating-point-symmetric quantization range conversion coefficient Ws′ of the third floating-point coefficient according to the range of the third floating-point coefficient Wf′ and the number of bits occupied by the third quantization coefficient Wq′ by the following formula (5):

[0162]

[0163] In formula (5), b represents the number of bits occupied by the third quantized coefficient Wq′. Wf′_range represents the range of the third floating-point coefficient Wf′. abs() represents an absolute value function. max() represents a maximum value function.

[0164] S904 : The processor 310 sends the third quantization coefficient and the fourth quantization coefficient to the coprocessor 320 .

[0165] S905: The coprocessor 320 obtains symmetric quantization data.

[0166] S906: The coprocessor 320 constructs a two-dimensional convolution operation according to the first quantization coefficient, the fourth quantization coefficient and the symmetric quantization data to generate asymmetric quantization data corresponding to the symmetric quantization data. The specific process is referred to step S706 and will not be described in detail here.

[0167] It can be understood that the execution order of the data conversion process described above is not limited to the execution order of steps S901 to S905. In other embodiments of the present application, the coprocessor 320 may first obtain the symmetric quantization data, and then the processor 310 obtains the symmetric quantization coefficient, the asymmetric quantization coefficient and the zero point value of the asymmetric quantization data, and determines the third quantization coefficient and the fourth quantization coefficient based on the obtained symmetric quantization coefficient, the asymmetric quantization coefficient and the zero point value of the asymmetric quantization data. For example, first execute step S905, and then execute steps S901 to S904. In addition, one or more interactive processes in steps S901 to S906 may also be omitted or added. According to the actual application, the present application may further include the following steps: Fig. 9 The execution order of the data conversion process in is not specifically limited.

[0168] Fig.10 According to some embodiments of the present application, a structural block diagram of a data conversion device 1000 is shown. Fig.10 Specifically, it includes:

[0169] The acquisition module 1 is used for the first processor to acquire the type conversion parameters of the data to be converted, and the type conversion parameters of the data to be converted are used to represent the range parameters of the data to be converted and the range parameters of the data conversion result corresponding to the data to be converted.

[0170] The determination module 2 is used for the first processor to determine the first coefficient and the second coefficient according to the type conversion parameter of the data to be converted.

[0171] The convolution module 3 is used for the second processor to perform a convolution operation on the data to be converted based on the first coefficient and the second coefficient obtained from the first processor, using the first coefficient as the data in the convolution kernel and the second coefficient as the data in the bias item, to obtain a data conversion result corresponding to the data to be converted.

[0172] In some embodiments, the data conversion device 1000 further includes: the type conversion parameter of the data to be converted includes at least one of the following: an asymmetric quantization coefficient, a zero point value of the asymmetric quantization data, and a symmetric quantization coefficient. When the data to be converted is asymmetric quantization data and the data conversion result corresponding to the data to be converted is symmetric quantization data, the first coefficient is calculated by the following formula:

[0173] Wf=AS*S

[0174] The second coefficient is calculated by the following formula:

[0175] Bf=-ZP*AS*S

[0176] Among them, AS represents an asymmetric quantization coefficient, S represents a symmetric quantization coefficient, and ZP represents the zero point value of the asymmetric quantization data.

[0177] In some embodiments, the data conversion device 1000 further includes: the type conversion parameter of the data to be converted includes at least one of the following: an asymmetric quantization coefficient, a zero point value of the asymmetric quantization data, and a symmetric quantization coefficient. In the case where the data to be converted is symmetric quantization data and the data conversion result corresponding to the data to be converted is asymmetric quantization data, the second coefficient is the zero point value of the asymmetric quantization data, and the first coefficient is calculated by the following formula:

[0178]

[0179] Among them, AS represents an asymmetric quantization coefficient, and S represents a symmetric quantization coefficient.

[0180] In some embodiments, the data conversion device 1000 further includes: a height value and a width value of the convolution kernel are 1 respectively.

[0181] Fig.11 According to some embodiments of the present application, a block diagram of an electronic device 10 including a system on chip 300 is shown. Fig.11 An example electronic device 10 is schematically shown according to various embodiments. In one embodiment, the electronic device 10 may include one or more processors 1004, a system control logic 1008 connected to at least one of the processors 1004, a system memory 1012 connected to the system control logic 1008, a non-volatile memory (NVM) 1016 connected to the system control logic 1008, and a network interface 1020 connected to the system control logic 1008.

[0182] In some embodiments, the processor 1004 may include one or more single-core or multi-core processors. In some embodiments, the processor 1004 may include any combination of a general-purpose processor and a dedicated processor (e.g., a graphics processor, an application processor, a baseband processor, etc.). In an embodiment where the electronic device 10 uses an eNB (Evolved Node B, enhanced base station) or a RAN (Radio Access Network, radio access network) controller, the processor 1004 may be configured to execute various embodiments that comply with the present invention.

[0183] In some embodiments, system control logic 1008 may include any suitable interface controller to provide any suitable interface to at least one of processors 1004 and / or any suitable device or component in communication with system control logic 1008 .

[0184] In some embodiments, the system control logic 1008 may include one or more memory controllers to provide an interface to the system memory 1012. The system memory 1012 may be used to load and store data and / or instructions. In some embodiments, the memory 1012 of the system 1000 may include any suitable volatile memory, such as a suitable dynamic random access memory (DRAM).

[0185] NVM 1016 may include one or more tangible, non-transitory computer-readable media for storing data and / or instructions. In some embodiments, NVM 1016 may include any suitable non-volatile memory such as flash memory and / or any suitable non-volatile storage device, such as at least one of a HDD (Hard Disk Drive), a CD (CompactDisc) drive, and a DVD (Digital Versatile Disc) drive.

[0186] NVM 1016 may include a portion of storage resources on a device on which electronic device 10 is installed, or it may be accessible by the device but not necessarily a portion of the device. For example, NVM 1016 may be accessed over a network via network interface 1020.

[0187] In particular, the system memory 1012 and the NVM 1016 may include, respectively, a temporary copy and a permanent copy of the instruction 1024. The instruction 1024 may include instructions that, when executed by at least one of the processors 1004, cause the electronic device 10 to implement the data conversion method of the present application. In some embodiments, the instruction 1024, hardware, firmware, and / or software components thereof may be additionally / alternatively placed in the system control logic 1008, the network interface 1020, and / or the processor 1004.

[0188] The network interface 1020 may include a transceiver for providing a radio interface for the electronic device 10, and then communicating with any other suitable device (such as a front-end module, an antenna, etc.) through one or more networks. In some embodiments, the network interface 1020 may be integrated with other components of the electronic device 10. For example, the network interface 1020 may be integrated with at least one of the processor 1004, the system memory 1012, the NVM 1016, and a firmware device (not shown) having instructions. When at least one of the processors 1004 executes the instructions, the electronic device 10 implements the data conversion method of the present application.

[0189] The network interface 1020 may further include any suitable hardware and / or firmware to provide a multiple-input multiple-output radio interface. For example, the network interface 1020 may be a network adapter, a wireless network adapter, a telephone modem and / or a wireless modem.

[0190] In one embodiment, at least one of the processors 1004 may be packaged together with logic for one or more controllers of the system control logic 1008 to form a system in package (SiP). In one embodiment, at least one of the processors 1004 may be integrated on the same die with logic for one or more controllers of the system control logic 1008 to form a system on chip (SoC).

[0191] The electronic device 10 may further include an input / output (I / O) device 1032 .

[0192] The various embodiments disclosed in the present application may be implemented in hardware, software, firmware, or a combination of these implementation methods. The embodiments of the present application may be implemented as a computer program or program code executed on a programmable system, the programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0193] Program code can be applied to input instructions to perform the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0194] Program code can be implemented with high-level programming language or object-oriented programming language to communicate with the processing system. When necessary, program code can also be implemented with assembly language or machine language. In fact, the mechanism described in this application is not limited to the scope of any specific programming language. In either case, the language can be a compiled language or an interpreted language.

[0195] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, instructions may be distributed over a network or through other computer-readable media. Therefore, machine-readable media may include any mechanism for storing or transmitting information in a machine (e.g., computer) readable form, including, but not limited to, floppy disks, optical disks, optical disks, read-only memories (CD-ROMs), magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, flash memory, or a tangible machine-readable memory for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in electrical, optical, acoustic, or other forms of propagation signals. Therefore, machine-readable media include any type of machine-readable media suitable for storing or transmitting electronic instructions or information in a machine (e.g., computer) readable form.

[0196] In the accompanying drawings, some structural or method features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be required. Instead, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. In addition, the inclusion of structural or method features in a particular figure does not mean that such features are required in all embodiments, and in some embodiments, these features may not be included or may be combined with other features.

[0197] It should be noted that the units / modules mentioned in the various device embodiments of the present application are all logical units / modules. Physically, a logical unit / module can be a physical unit / module, or a part of a physical unit / module, or can be implemented as a combination of multiple physical units / modules. The physical implementation method of these logical units / modules themselves is not the most important. The combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed by the present application. In addition, in order to highlight the innovative part of the present application, the above-mentioned device embodiments of the present application do not introduce units / modules that are not closely related to solving the technical problems proposed by the present application, which does not mean that there are no other units / modules in the above-mentioned device embodiments.

[0198] It should be noted that in the examples and description of this patent, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0199] Although the present application has been illustrated and described with reference to certain preferred embodiments thereof, it will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present application.

Claims

1. A data conversion method, characterized in that: For an electronic device, the electronic device comprising a first processor and a second processor, the method comprising: The first processor obtains a type conversion parameter of the data to be converted, where the type conversion parameter of the data to be converted is used to represent a range parameter of the data to be converted and a range parameter of a data conversion result corresponding to the data to be converted; the type conversion parameter of the data to be converted includes at least one of the following: an asymmetric quantization coefficient, a zero point value of the asymmetric quantization data, and a symmetric quantization coefficient; When the data to be converted is asymmetric quantized data and the data conversion result corresponding to the data to be converted is symmetric quantized data, the first processor calculates the first coefficient using the following formula: Wf=AS*S And, the second coefficient is calculated by the following formula: Bf=-ZP*AS*S Wherein, AS represents the asymmetric quantization coefficient, S represents the symmetric quantization coefficient, and ZP represents the zero point value of the asymmetric quantization data; When the data to be converted is symmetrical quantized data and the data conversion result corresponding to the data to be converted is asymmetrical quantized data, the second coefficient is a zero point value of the asymmetrical quantized data, and the first coefficient is calculated by the following formula: The second processor performs a convolution operation on the data to be converted based on the first coefficient and the second coefficient obtained from the first processor, using the first coefficient as data in a convolution kernel and the second coefficient as data in a bias item, to obtain a data conversion result corresponding to the data to be converted.

2. The method according to claim 1, characterized in that The height and width of the convolution kernel are 1 respectively.

3. A data conversion device, characterized in that: The device comprises: An acquisition module is used for the first processor to acquire a type conversion parameter of the data to be converted, wherein the type conversion parameter of the data to be converted is used to represent a range parameter of the data to be converted and a range parameter of a data conversion result corresponding to the data to be converted; the type conversion parameter of the data to be converted includes at least one of the following: an asymmetric quantization coefficient, a zero point value of the asymmetric quantization data, and a symmetric quantization coefficient; A determination module is used for the first processor to calculate the first coefficient by the following formula when the data to be converted is asymmetric quantized data and the data conversion result corresponding to the data to be converted is symmetric quantized data: Wf=AS*S The second coefficient is calculated by the following formula: Bf=-ZP*AS*S Wherein, AS represents an asymmetric quantization coefficient, S represents a symmetric quantization coefficient, and ZP represents a zero point value of the asymmetric quantization data; The determination module is further configured for the first processor to obtain the first coefficient by calculating the following formula when the data to be converted is symmetrically quantized data and the data conversion result corresponding to the data to be converted is asymmetrically quantized data: A convolution module is used for the second processor to perform a convolution operation on the data to be converted based on the first coefficient and the second coefficient obtained from the first processor, using the first coefficient as the data in the convolution kernel and the second coefficient as the data in the bias item, to obtain a data conversion result corresponding to the data to be converted.

4. The device according to claim 3, characterized in that The height and width of the convolution kernel are 1 respectively.

5. An electronic device, characterized in that: include: a memory for storing instructions to be executed by one or more processors of the electronic device, and The processor is one of the one or more processors of the electronic device, and is used to execute the data conversion method according to any one of claims 1 to 2.

6. A readable medium, characterized in that: Instructions are stored on a readable medium of the electronic device, and when the instructions are executed, the electronic device executes the data conversion method according to any one of claims 1 to 2.

7. A computer program product, characterized in that The computer program product comprises instructions, and the instructions are used to implement the data conversion method according to any one of claims 1 to 2.

Images