Power on / off error detection system, method, control terminal, and device

Abstract

The present application relates to the field of chip testing technology, and specifically provides a power-on / off error detection system, method, control terminal, and device, wherein the system comprises: a control terminal, electrically connected to the chip to be tested, for obtaining error information of the chip to be tested, and generating first control information according to the error information; a microcontroller, electrically connected to the control terminal, for obtaining the first control information, and generating trigger information according to the first control information; a logic analyzer, electrically connected to the microcontroller and the chip to be tested, for obtaining the trigger information, and triggering the acquisition of the instantaneous abnormal timing when the chip to be tested generates the error information according to the trigger information; the power-on / off error detection system can not only accurately capture the instantaneous abnormal timing when the chip to be tested generates error information, but also does not need to modify the main control terminal program in the chip to be tested, thereby improving the versatility of the power-on / off error detection system.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and more specifically, to a power on / off error detection system, method, control terminal, and device. Background Art

[0002] In the field of semiconductor storage, NORFlash memory chips and NANDFlash memory chips are indispensable core components. NORFlash and NANDFlash are both non-volatile storage media, and chip data will not be lost after power failure. NORFlash and NANDFlash are often used to store embedded software system boot code and core data, so their reliability issues cannot be ignored. For NORFlash, there are reliability issues such as over-erase, disturbance, and tunnel oxidation. For NANDFlash, bit flipping is also inevitable, and bit flipping can only be corrected by the ECC algorithm. In addition, random power-off erasure of Flash may introduce other hidden dangers.

[0003] After the memory chip ages, it is more likely to have the above-mentioned errors, and the errors that occur are also more random. Therefore, power-on and power-off aging tests on memory chips that store embedded software systems are an indispensable key step in testing the reliability of memory chips.

[0004] In the prior art, the power on / off aging test is generally completed by verifying the error information that appears through the reporting file system in the storage chip. Not only is it difficult to accurately capture the instantaneous abnormal timing, but it is also necessary to modify the main control terminal program in the storage chip.

[0005] There is currently no effective technical solution to the above problems. Summary of the invention

[0006] The purpose of the present application is to provide a power on / off error detection system, method, control terminal, and device to accurately capture the instantaneous abnormal timing when the chip under test generates error information without modifying the main control terminal program in the storage chip.

[0007] In a first aspect, the present application provides a power on / off error detection system for detecting errors that occur during the power on / off process of a chip under test. The power on / off error detection system includes:

[0008] A control terminal, electrically connected to the chip to be tested, used to obtain error information of the chip to be tested and generate first control information according to the error information;

[0009] a microcontroller, electrically connected to the control terminal, configured to obtain the first control information and generate trigger information according to the first control information;

[0010] The logic analyzer is electrically connected to the microcontroller and the chip under test, and is used to obtain the trigger information and trigger the acquisition of the instantaneous abnormal timing when the chip under test generates the error information according to the trigger information.

[0011] The power on / off error detection system of the present application can not only accurately capture the instantaneous abnormal timing when the chip under test generates error information, but also does not require modification of the main control terminal program in the chip under test, thereby improving the versatility of the power on / off error detection system.

[0012] Optionally, in the power on / off error detection system of the present application, the microcontroller is also used to control the power on and / or power off of the chip to be tested.

[0013] The power on / off error detection system of the present application controls the power on / off of the chip under test through a microcontroller, which can not only control the chip under test to periodically start and / or shut down, but also detect errors that occur accidentally when the chip under test is turned on and / or shut down, thereby improving the accuracy of the power on / off error detection system.

[0014] Optionally, in the power on / off error detection system of the present application, the logic analyzer is electrically connected to the control terminal, and the logic analyzer sends the instantaneous abnormal timing to the control terminal so as to associate the instantaneous abnormal timing with the error information.

[0015] In the power-on / off error detection system of the present application, after the logic analyzer obtains the instantaneous abnormal timing when the chip under test generates error information, the instantaneous abnormal timing and the logic instructions analyzed based on the instantaneous abnormal timing are sent to the control terminal to associate the error information of the chip under test with the instantaneous abnormal timing and the logic instructions.

[0016] Optionally, in the power on / off error detection system mentioned above in the present application, the instantaneous abnormal timing includes an abnormal timing before and / or after the chip under test generates the error information.

[0017] In a second aspect, the present application further provides a power on / off error detection method for detecting a timing of an error in a chip under test. The power on / off error detection method includes:

[0018] Obtain error information of the chip under test;

[0019] The first control information is generated according to the error information, so that the microcontroller generates trigger information according to the first control information, and the trigger information is used to trigger the logic analyzer to obtain the instantaneous abnormal timing when the chip under test generates the error information.

[0020] The power on / off error detection method of the present application can not only accurately capture the instantaneous abnormal timing when the chip under test generates error information, but also does not require modification of the main control terminal program in the chip under test, thereby improving the versatility of the power on / off error detection method.

[0021] In a third aspect, the present application further provides a control terminal for detecting a timing of an error in a chip under test, the control terminal comprising:

[0022] A first acquisition module is used to obtain error information of the chip to be tested;

[0023] The first generating module is used to generate first control information according to the error information, so that the microcontroller generates trigger information according to the first control information, and the trigger information is used to trigger the logic analyzer to obtain the instantaneous abnormal timing when the chip under test generates the error information.

[0024] The control terminal of the present application is used to execute the power on / off error detection method of the second aspect mentioned above, which can not only accurately capture the instantaneous abnormal timing when the chip under test generates error information, but also does not need to modify the main control terminal program in the chip under test, thereby improving the versatility of the control terminal.

[0025] In a fourth aspect, the present application further provides a power on / off error detection method for detecting a timing of an error in a chip under test. The power on / off error detection method includes:

[0026] Acquire first control information, where the first control information is generated by the control terminal according to the error information of the chip under test;

[0027] The trigger information is generated according to the first control information, and the trigger information is used to trigger the logic analyzer to obtain the instantaneous abnormal timing when the chip under test generates the error information.

[0028] The power on / off error detection method of the present application can not only accurately capture the instantaneous abnormal timing when the chip under test generates error information, but also does not require modification of the main control terminal program in the chip under test, thereby improving the versatility of the power on / off error detection method.

[0029] In a fifth aspect, the present application further provides a power on / off error detection device for detecting the timing of an error in a chip to be tested. The power on / off error detection device comprises a microcontroller, and the microcontroller comprises:

[0030] A second acquisition module is used to acquire first control information, where the first control information is generated by the control terminal according to the error information of the chip under test;

[0031] The second generating module is used to generate trigger information according to the first control information, and the trigger information is used to trigger the logic analyzer to obtain the instantaneous abnormal timing when the chip under test generates the error information.

[0032] The power on and off error detection device of the present application includes a microcontroller, which is used to execute the power on and off error detection method of the fourth aspect. It can not only accurately capture the instantaneous abnormal timing when the chip under test generates error information, but also does not need to modify the main control end program in the chip under test, thereby improving the versatility of the power on and off error detection device.

[0033] In a sixth aspect, the present application further provides a power on / off error detection method for detecting a timing of an error in a chip under test. The power on / off error detection method comprises:

[0034] Acquire trigger information, where the trigger information is generated by the microcontroller according to first control information, and the first control information is generated by the control terminal according to error information of the chip to be tested;

[0035] The instantaneous abnormal timing when the above-mentioned chip under test generates the above-mentioned error information is obtained according to the above-mentioned trigger information.

[0036] The power on / off error detection method system of the present application can not only accurately capture the instantaneous abnormal timing when the chip under test generates error information, but also does not need to modify the main control terminal program in the chip under test, thereby improving the versatility of the power on / off error detection method.

[0037] In a seventh aspect, the present application further provides a power-on / off error detection device for detecting a timing of an error in a chip under test, wherein the power-on / off error detection device comprises a logic analyzer, and the logic analyzer comprises:

[0038] A third acquisition module is used to acquire trigger information, where the trigger information is generated by the microcontroller according to first control information, and the first control information is generated by the control terminal according to error information of the chip under test;

[0039] The fourth acquisition module is used to trigger the acquisition of the instantaneous abnormal timing when the above-mentioned chip under test generates the above-mentioned error information according to the above-mentioned trigger information.

[0040] The power-on and power-off error detection device of the present application includes a logic analyzer, which is used to execute the power-on and power-off error detection method of the sixth aspect. It can not only capture the instantaneous abnormal timing when the chip under test generates error information, but also does not need to modify the program of the chip under test, thereby improving the versatility of the power-on and power-off error detection device.

[0041] From the above, it can be seen that the power-on / off error detection system, method, control terminal, and device of the present application obtain error information of the chip under test through the control terminal and generate first control information according to the error information, the microcontroller obtains the first control information and generates trigger information according to the first control information, and the logic analyzer obtains the trigger information and obtains the instantaneous abnormal timing when the chip under test generates error information according to the trigger information; the power-on / off error detection system can not only accurately capture the instantaneous abnormal timing when the chip under test generates error information, but also does not need to modify the main control end program in the chip under test, thereby improving the versatility of the power-on / off error detection system.

[0042] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the embodiments of the present application. The purpose and other advantages of the present application can be realized and obtained by the structures specifically pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A schematic diagram of the structure of a power on / off error detection system provided in an embodiment of the present application.

[0044] Figure 2 A detailed structural diagram of the power on / off error detection system provided in Example 1 of the present application.

[0045] Figure 3 This is a log information diagram of the chip under test provided in Example 1 of the present application.

[0046] Figure 4 This is an interface diagram of the control terminal provided in Example 1 of the present application.

[0047] Figure 5 for Figure 4 Enlarged view of part A.

[0048] Figure 6 A flowchart of a power on / off error detection method provided in an embodiment of the present application.

[0049] Figure 7 A flowchart of a power on / off error detection method provided in an embodiment of the present application.

[0050] Figure 8 A flowchart of a power on / off error detection method provided in an embodiment of the present application.

[0051] Fig. 9 A schematic diagram of the structure of a control terminal provided in an embodiment of the present application.

[0052] Fig.10 A schematic diagram of the structure of a power on / off error detection device provided in an embodiment of the present application.

[0053] Fig.11 A schematic diagram of the structure of a power on / off error detection device provided in an embodiment of the present application.

[0054] Figure numerals: 1. chip to be tested; 2. control terminal; 3. microcontroller; 4. logic analyzer; 901. first acquisition module; 902. first generation module; 1001. second acquisition module; 1002. second generation module; 1101. third acquisition module; 1102. fourth acquisition module. DETAILED DESCRIPTION

[0055] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0056] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0057] After aging, memory chips are more prone to various errors, and the errors that occur are also more random. Therefore, power-on and power-off aging tests on memory chips are an indispensable key step in testing the reliability of memory chips. In the prior art, power-on and power-off aging tests are generally completed by verifying the error information that appears through the reporting file system in the memory chip. Not only is it difficult to accurately capture the instantaneous abnormal timing, but it also requires modifying the main control end program in the memory chip.

[0058] First, please refer to Figure 1 , Figure 1 is a schematic diagram of a power on / off error detection system in some embodiments of the present application. The power on / off error detection system of the present application is used to detect the timing of an error of a chip under test 1. The system includes:

[0059] The control terminal 2 is electrically connected to the chip under test 1, and is used to obtain error information of the chip under test 1 and generate first control information according to the error information;

[0060] The microcontroller 3 is electrically connected to the control terminal 2 and is used to obtain the first control information and generate trigger information according to the first control information;

[0061] The logic analyzer 4 is electrically connected to the microcontroller 3 and the chip under test 1, and is used to obtain trigger information, and trigger the acquisition of the instantaneous abnormal timing when the chip under test 1 generates error information according to the trigger information.

[0062] It should be understood that the power on / off error detection system of the present application can not only be used to detect errors on chips that have already had error information to find the exact cause of the error, but can also be used to detect errors on chips that have not had error information to eliminate potential hidden dangers in the chip. Therefore, in some embodiments, the chip to be tested 1 can be a chip that has already had error information. In some embodiments, the chip to be tested 1 can also be a chip that has not had error information.

[0063] Among them, the error information is an error that occurs when the chip is turned on or off or running, such as startup failure, downtime, abnormal operation, etc. The first control information is generated by the control terminal 2 according to the error information of the chip to be tested obtained by it, and is used to enable the microcontroller 3 to generate trigger information according to the first control information after obtaining the first control information. The microcontroller 3 includes a plurality of flags, one of which (hereinafter referred to as the trigger information flag) is used to generate trigger information, and the first control information is used to change the state of the trigger information flag to enable the microcontroller 3 to generate trigger information, such as: when the trigger information flag is at a high level, trigger information will be generated. After the microcontroller 3 obtains the first control information, the level of the trigger information flag is adjusted to a high level according to the first control information to generate trigger information. The trigger information is a trigger signal. Only when the logic analyzer 4 obtains the trigger information, will it trigger the acquisition of the instantaneous abnormal timing when the chip to be tested 1 generates error information. In some embodiments, the instantaneous abnormal timing is the timing of the moment when the chip to be tested 1 generates error information. In some embodiments, the instantaneous abnormal timing can also be a timing within a period of time (for example, 30 seconds).

[0064] The control terminal 2 may be a device such as a PLC (programmable logic device), a PC (personal computer), a laptop, a PDA (palm-held computer), or a tablet computer that can perform data acquisition and generation operations. The control terminal 2 can acquire the error information of the chip under test 1. The acquisition method may be active acquisition or passive acquisition. Specifically, the acquisition method may be any one of the following methods:

[0065] 1. The chip under test 1 sends error information, and the control terminal 2 receives the error information from the chip under test 1;

[0066] 2. The chip under test 1 sends operation log information including error information, the control terminal 2 receives the operation log information from the chip under test 1, and the control terminal 2 filters out the error information from the operation log information;

[0067] 3. The control terminal 2 continuously monitors the error information of the chip under test;

[0068] 4. The control terminal 2 continuously monitors the operation log information of the chip under test, and filters out error information from the operation log information.

[0069] Among them, the microcontroller 3 can be PIC16, PIC18, 8051, STM8, STM32, etc. The first control information is generated by the control terminal 2 according to the error information obtained by it, and is used to enable the microcontroller 3 to generate trigger information according to the first control information after obtaining the first control information. In some preferred embodiments, the microcontroller 3 is provided with a GPIO (general input / output port), and is electrically connected to the logic analyzer 4 using the GPIO pin, and the microcontroller 3 and the logic analyzer 4 complete data interaction through the GPIO. In some embodiments, in order to improve the anti-interference ability of the power on and off error detection system, the microcontroller 3 and the chip to be tested 1 share the same ground. The way in which the microcontroller 3 obtains the first control information can be divided into active acquisition or passive acquisition. Specifically, the acquisition method can be any one of the following methods:

[0070] 1. The control terminal 2 sends the first control information, and the microcontroller 3 receives the first control information from the control terminal 2;

[0071] 2. The microcontroller 3 continuously monitors the first control information.

[0072] Among them, the logic analyzer 4 of the present application can be used to obtain the timing and analyze the corresponding logic instructions based on the timing. The logic analyzer 4 is electrically connected to the PIN pin of the chip to be tested 1. The process of the logic analyzer 4 obtaining the instantaneous abnormal timing when the chip to be tested 1 generates error information is as follows: the logic analyzer 4 continuously records the timing of the operation of the chip to be tested 1. Due to the limited storage space of the logic analyzer 4, when the trigger information is not obtained, the timing of the chip to be tested 1 recorded by the logic analyzer 4 will be regarded as temporary storage data, and the logic analyzer 4 will not obtain the recorded timing (that is, the timing as temporary storage data will not be stored as non-volatile data); when the trigger information is obtained, the logic analyzer 4 obtains the instantaneous abnormal timing when the trigger information is generated from the recorded timing (that is, the timing as temporary storage data is stored as non-volatile data), and analyzes the logic instructions executed when the logic analyzer 4 obtains the trigger information based on the instantaneous abnormal timing. Since the control terminal 2 and the microcontroller 3 have fast response speeds, the time difference between the logic analyzer 4 obtaining the trigger information and the control terminal 2 obtaining the error information is very small. Therefore, the instantaneous abnormal timing obtained by the logic analyzer 4 is the instantaneous abnormal timing when the chip under test 1 generates error information, and the logic instruction analyzed by the logic analyzer 4 is the logic instruction executed when the chip under test 1 generates error information; at the same time, the logic analyzer 4 obtains the timing of the chip under test 1 through the PIN pin and analyzes the obtained timing, without modifying the main control end program in the chip under test 1. The way in which the logic analyzer 4 obtains the trigger information can be divided into active acquisition or passive acquisition. Specifically, the acquisition method can be any one of the following methods:

[0073] 1. The microcontroller 3 sends trigger information, and the logic analyzer 4 receives the trigger information from the microcontroller 3;

[0074] 2. The logic analyzer 4 continuously monitors the trigger information.

[0075] The above-mentioned sending, receiving, continuous monitoring and filtering are all common technologies and will not be described in detail here.

[0076] As can be seen from the above, the power-on / off error detection system provided in the embodiment of the present application obtains the error information of the chip under test 1 through the control terminal 2 and generates the first control information according to the error information, the microcontroller 3 obtains the first control information and generates the trigger information according to the first control information, the logic analyzer 4 obtains the trigger information and obtains the instantaneous abnormal timing when the chip under test 1 generates the error information according to the trigger information; the power-on / off error detection system can not only accurately capture the instantaneous abnormal timing when the chip under test 1 generates the error information, but also does not need to modify the main control end program in the chip under test 1, thereby improving the versatility of the power-on / off error detection system.

[0077] In actual applications, firstly, during the power on and off process of the chip under test, there may be a startup failure, inability to shut down, or program jamming; secondly, some errors of the chip under test occur accidentally, and these accidental errors may not appear in a single power on and off.

[0078] In order to solve the above problems, in some embodiments, the microcontroller 3 is electrically connected to the chip under test 1, and the microcontroller 3 can control the chip under test 1 to start and / or shut down. When the error information of the chip under test 1 is startup failure, the microcontroller 3 only controls the chip under test 1 to start; when the error information of the chip under test 1 is program stuck or downtime, the microcontroller 3 controls the chip under test 1 to start and power off; when the error information of the chip under test 1 is shutdown failure, the microcontroller 3 only controls the chip under test 1 to shut down; when the chip under test 1 generates error information but does not affect the startup and shutdown of the chip under test 1 or the chip under test 1 does not generate error information, the microcontroller 3 controls the chip under test 1 to start and shut down.

[0079] The working principle of the microcontroller 3 controlling the chip to be tested 1 to start and / or shut down is as follows: the control terminal 2 generates the second control information, so that after the microcontroller 3 obtains the second control information, the chip to be tested 1 is controlled to start and / or shut down according to the second control information. In some embodiments, the second control information may include a logic method for controlling the chip to be tested 1 to start and / or shut down, and after the microcontroller 3 obtains the second control information, the chip to be tested 1 is controlled to start and / or shut down according to the logic method for controlling the chip to be tested 1 to start and / or shut down. In some preferred embodiments, the second control information also includes interval time information, and the microcontroller 3 automatically executes the logic method for controlling the chip to be tested 1 to start and / or shut down at intervals (for example, 15 seconds or 30 seconds) according to the interval time information. In some embodiments, the second control information may be a trigger signal, and the microcontroller 3 includes a logic method for controlling the chip to be tested 1 to start and / or shut down, but the execution of the method requires a trigger signal to trigger, and only when the microcontroller 3 obtains the second control information will it trigger the control of the chip to be tested 1 to start and / or shut down. In some preferred embodiments, the control terminal 2 generates second control information at regular intervals (eg, 15 seconds or 30 seconds) so that the logic method for controlling the power on and / or power off of the chip under test 1 in the microcontroller 3 is triggered at regular intervals.

[0080] In some embodiments, the microcontroller 3 is electrically connected to the chip under test 1 through a relay. The working principle of the microcontroller 3 controlling the switch of the chip under test 1 is: the control terminal 2 generates the second control information, and after the microcontroller 3 obtains the second control information, it controls the relay switch according to the second control information to control the switch of the chip under test 1. This working principle is similar to the above working principle and will not be described in detail here. Through the above technical solution, the microcontroller 3 can periodically control the chip under test 1 to turn on and off; it can also enable the power on and off error detection system to detect certain accidental errors in the process of periodically turning on and off the chip under test 1, thereby improving the accuracy of error detection.

[0081] In some embodiments, the logic analyzer 4 is electrically connected to the control terminal 2. After the logic analyzer 4 triggers the acquisition of the instantaneous abnormal timing when the chip under test 1 generates error information according to the trigger information, the logic analyzer 4 will send the instantaneous abnormal timing and the logic instructions analyzed based on the instantaneous abnormal timing to the control terminal 2 to associate the error information of the chip under test with the instantaneous abnormal timing and the logic instructions.

[0082] In some embodiments, the instantaneous abnormal timing sequence includes the abnormal timing sequence before the chip under test 1 generates error information, and the total time from the time node before the chip under test 1 generates error information to the time node when the chip under test 1 generates error information is an adjustable value. For example, if the total time is 30 seconds, the instantaneous abnormal timing sequence includes the timing sequence from 30 seconds before the chip under test 1 generates error information to the time node when the chip under test 1 generates error information.

[0083] In some embodiments, the above-mentioned instantaneous abnormal timing sequence may also include abnormal timing sequences before and after the chip under test 1 generates error information, and the total time from the time node before the chip under test 1 generates error information to the time node after the chip under test 1 generates error information is an adjustable value. In some preferred embodiments, the part before the chip under test 1 generates error information accounts for 99% of the total time, and the part after the chip under test 1 generates error information accounts for 1% of the total time difference. For example, if the total time is 30 seconds, the instantaneous abnormal timing sequence includes the timing sequence from the time node 29.7 seconds before the chip under test 1 generates error information to the time node 0.3 seconds after the chip under test 1 generates error information.

[0084] In actual applications, there may be a situation where the chip under test 1 generates error information but the error information does not affect the operation of the chip under test 1. In order to obtain these error information that does not affect the operation of the chip under test 1. In some embodiments, the above-mentioned instantaneous abnormal timing includes the abnormal timing after the chip under test 1 generates error information. The abnormal timing is the timing of the time node when the chip under test 1 generates error information to the time node after the chip under test 1 generates error information. The time difference from the time node when the chip under test 1 generates error information to the time node after the chip under test 1 generates error information is an adjustable value. For example, if the time difference is 30 seconds, the instantaneous abnormal timing includes the timing from the time when the chip under test 1 generates error information to the time node 30 seconds after the chip under test 1 generates error information.

[0085] Embodiment 1

[0086] Please refer to Figures 2 to 4 , Figure 2 It is a detailed structural diagram of the power on / off error detection system of the embodiment of the present application. In the embodiment of the present application, a PC is used as a control terminal 2, and a python serial module is used to continuously monitor the error information of the chip to be tested 1. The PC is electrically connected to the chip to be tested 1 through a CRT serial port, and an STM32 is used as a microcontroller 3. The STM32 is electrically connected to the PC through a CRT serial port, and the GPIO pin of the STM32 is electrically connected to a logic analyzer 4. The STM32 is electrically connected to the chip to be tested 1 through a relay, and the logic analyzer 4 is electrically connected to the PIN pin of the chip to be tested 1. The PC can generate second control information, and the STM32 obtains the second control information through the CRT serial port and controls the relay to be turned on and / or off according to the second control information, thereby controlling the chip to be tested 1 to be turned on and / or off. Figure 3 : is a log information diagram of the chip under test of an embodiment of the present application, wherein BOOT[E]img hash verify fail[prim] is the error information in the log information of the chip under test 1. When the PC monitors the error information in the log information of the chip under test through the CRT serial port, the PC obtains the error information of the chip under test 1 through the CRT serial port and generates the first control information according to the error information. The STM32 obtains the first control information through the CRT serial port and generates the trigger information according to the first control information. The logic analyzer 4 obtains the trigger information through the GPIO and triggers the acquisition of the timing from 30 seconds before the chip under test 1 generates the error information to the time when the chip under test 1 generates the error information according to the trigger information. The logic analyzer 4 sends the acquired timing to the control terminal for display (such as Figure 4 FIG4 is an interface diagram of a control terminal according to an embodiment of the present application. Figure 5 for Figure 4 The enlarged view of part A in the figure. Figure 4 The upper part is the timing obtained by logic analyzer 4. Figure 4 The lower half is the logic instruction analyzed by the logic analyzer 4 based on the acquired timing, so that the error information generated by the chip under test 1 is associated with the timing acquired by the logic analyzer 4 and the analyzed logic instruction. In the chip under test 1 of the embodiment of the present application, the storage unit with address 2A0000 can only perform read operations. According to Figure 5, the chip under test 1 performed a write operation on the unit with address 2A0000 at the time node of 7:59:53:841 milliseconds, which caused the chip under test 1 to generate error information and generate Figure 3 Contains log information about errors.

[0087] Second, please refer to Figure 6 , Figure 6 1 is a flow chart of a power on / off error detection method in some embodiments of the present application. The power on / off error detection method is applied to a control terminal 2 to detect the timing of an error in a chip under test 1. The power on / off error detection method includes:

[0088] S601, obtaining error information of the chip under test 1;

[0089] S602 , generating first control information according to the error information, so that the microcontroller 3 generates trigger information according to the first control information, and the trigger information is used to trigger the logic analyzer 4 to obtain the instantaneous abnormal timing when the chip under test 1 generates error information.

[0090] As can be seen from the above, the power-on and power-off error detection method provided in the embodiment of the present application obtains error information of the chip under test 1; generates first control information based on the error information, so that the microcontroller 3 generates trigger information based on the first control information, and the trigger information is used to trigger the logic analyzer 4 to obtain the instantaneous abnormal timing when the chip under test 1 generates error information; the power-on and power-off error detection method can not only accurately capture the instantaneous abnormal timing when the chip under test 1 generates error information, but also does not need to modify the main control end program in the chip under test 1, thereby improving the versatility of the power-on and power-off error detection method.

[0091] Third, please refer to Figure 7 , Figure 7 1 is a flow chart of a power on / off error detection method in some embodiments of the present application. The power on / off error detection method is applied to a microcontroller 3 to detect the timing of an error in a chip under test 1. The power on / off error detection method includes:

[0092] S701, obtain first control information, which is generated by the control terminal 2 according to the error information of the chip under test 1; S702, generate trigger information according to the above first control information, which is used to trigger the logic analyzer 4 to obtain the instantaneous abnormal timing when the chip under test 1 generates error information.

[0093] As can be seen from the above, the power-on and power-off error detection method provided in the embodiment of the present application obtains the first control information, and the first control information is generated by the control terminal 2 according to the error information of the chip under test 1; trigger information is generated according to the first control information, and the trigger information is used to trigger the logic analyzer 4 to obtain the instantaneous abnormal timing when the chip under test 1 generates error information; the power-on and power-off error detection method can not only accurately capture the instantaneous abnormal timing when the chip under test 1 generates error information, but also does not need to modify the main control end program in the chip under test 1, thereby improving the versatility of the power-on and power-off error detection method.

[0094] Fourth, please refer to Figure 8 , Figure 8 1 is a flow chart of a power on / off error detection method in some embodiments of the present application. The power on / off error detection method is applied to a logic analyzer 4 to detect the timing of an error in a chip under test 1. The power on / off error detection method includes:

[0095] S801, acquiring trigger information, where the trigger information is generated by the microcontroller 3 according to first control information, and the first control information is generated by the control terminal 2 according to error information of the chip under test 1;

[0096] S802, triggering acquisition of the instantaneous abnormal timing when the chip under test 1 generates error information according to the trigger information.

[0097] As can be seen from the above, the power on and off error detection method provided in the embodiment of the present application obtains trigger information, the above trigger information is generated by the microcontroller 3 according to the first control information, and the above first control information is generated by the control terminal 2 according to the error information of the above chip under test 1; the instantaneous abnormal timing when the above chip under test 1 generates the above error information is obtained according to the above trigger information; the power on and off error detection method can not only accurately capture the instantaneous abnormal timing when the chip under test 1 generates error information, but also does not need to modify the main control end program in the chip under test 1, thereby improving the versatility of the power on and off error detection method.

[0098] Fifth, please refer to Fig. 9 , Fig. 9 1 is a schematic diagram of the structure of the control terminal 2 in some embodiments of the present application, which is used to detect the timing of the error of the chip under test 1. The control terminal 2 includes:

[0099] The first acquisition module, 901, is used to obtain the error information of the chip under test 1;

[0100] The first generating module 902 is used to generate first control information according to the error information, so that the microcontroller 3 generates trigger information according to the first control information, and the trigger information is used to trigger the logic analyzer 4 to obtain the instantaneous abnormal timing when the above-mentioned chip under test 1 generates the above-mentioned error information.

[0101] The control terminal 2 of the present application is used to execute the power on / off error detection method of the second aspect mentioned above, which can not only accurately capture the instantaneous abnormal timing when the chip under test 1 generates error information, but also does not need to modify the main control terminal program in the chip under test 1, thereby improving the versatility of the control terminal 2.

[0102] For the sixth aspect, please refer to Fig.10 , Fig.10 1 is a schematic diagram of the structure of a power-on / off error detection device in some embodiments of the present application, which is used to detect the timing of an error of a chip under test 1. The power-on / off error detection device includes a microcontroller 3, and the microcontroller 3 includes:

[0103] The second acquisition module 1001 is used to acquire first control information, where the first control information is generated by the control terminal 2 according to the error information of the chip under test 1;

[0104] The second generating module 1002 is used to generate trigger information according to the first control information, and the trigger information is used to trigger the logic analyzer 4 to obtain the instantaneous abnormal timing when the chip under test 1 generates error information.

[0105] The power on / off error detection device of the present application includes a microcontroller 3, which is used to execute the power on / off error detection method of the third aspect. It can not only accurately capture the instantaneous abnormal timing when the chip under test 1 generates error information, but also does not need to modify the main control end program in the chip under test 1, thereby improving the versatility of the power on / off error detection device.

[0106] The seventh aspect, please refer to Figure 11, Fig.11 1 is a schematic diagram of the structure of a power-on / off error detection device in some embodiments of the present application, which is used to detect the timing of an error of a chip under test 1. The power-on / off error detection device includes a logic analyzer 4, and the logic analyzer 4 includes:

[0107] The third acquisition module 1101 is used to acquire trigger information, where the trigger information is generated by the microcontroller 3 according to the first control information, and the first control information is generated by the control terminal 2 according to the error information of the chip under test 1;

[0108] The fourth acquisition module 1102 is used to trigger acquisition of the instantaneous abnormal timing when the chip under test 1 generates error information according to the trigger information.

[0109] The power-on / off error detection device of the present application includes a logic analyzer 4, which is used to execute the power-on / off error detection method of the fourth aspect. It can not only accurately capture the instantaneous abnormal timing when the chip under test 1 generates error information, but also does not need to modify the main control end program in the chip under test 1, thereby improving the versatility of the power-on / off error detection device.

[0110] As can be seen from the above, the power-on / off error detection system, method, control terminal, and device of the present application obtain the error information of the chip under test 1 through the control terminal 2 and generate the first control information according to the error information, the microcontroller 3 obtains the first control information and generates the trigger information according to the first control information, the logic analyzer 4 obtains the trigger information and obtains the instantaneous abnormal timing when the chip under test 1 generates the error information according to the trigger information; the power-on / off error detection system can not only accurately capture the instantaneous abnormal timing when the chip under test 1 generates the error information, but also does not need to modify the main control end program in the chip under test 1, thereby improving the versatility of the power-on / off error detection system.

[0111] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0112] In addition, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0113] Furthermore, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0114] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0115] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A power on / off error detection system is used to detect errors that occur during the power on / off process of the chip under test, and is characterized by: The power on / off error detection system comprises: A control terminal, electrically connected to the chip to be tested, and configured to obtain error information of the chip to be tested and generate first control information according to the error information; a microcontroller, electrically connected to the control terminal, and configured to obtain the first control information and generate trigger information according to the first control information; A logic analyzer, electrically connected to the microcontroller and the chip under test, for continuously recording the timing of the operation of the chip under test, and for obtaining the trigger information, and triggering the acquisition of the instantaneous abnormal timing when the chip under test generates the error information according to the trigger information; The process of obtaining the trigger information and triggering the acquisition of the instantaneous abnormal timing when the chip under test generates the error information according to the trigger information includes: When the trigger information is obtained, the instantaneous abnormal timing when the trigger information is generated is obtained from the recorded timing, and the logical instructions executed when the trigger information is obtained based on the instantaneous abnormal timing analysis, and the instantaneous abnormal timing includes the abnormal timing before the chip under test generates the error information.

2. The power on / off error detection system according to claim 1, characterized in that: The microcontroller is also used to control the chip to be tested to start up and / or shut down.

3. The power on / off error detection system according to claim 1, characterized in that: The logic analyzer is electrically connected to the control terminal, and the logic analyzer sends the instantaneous abnormal timing to the control terminal so as to associate the instantaneous abnormal timing with the error information.

4. A power on / off error detection method is used to detect errors that occur during the power on / off process of a chip under test, and is characterized in that: The power on / off error detection method is applied in a control terminal, and the power on / off error detection method includes: Obtaining error information of the chip to be tested; Generate first control information according to the error information so that the microcontroller generates trigger information according to the first control information, the trigger information is used to trigger the logic analyzer to obtain the instantaneous abnormal timing when the trigger information is generated from the timing recorded by it, and obtain the logic instructions executed when the trigger information is obtained based on the instantaneous abnormal timing analysis, the instantaneous abnormal timing includes the abnormal timing before the chip under test generates the error information, and the logic analyzer is used to continuously record the timing of the operation of the chip under test.

5. A control terminal, used to detect errors that occur during the power on and off process of a chip under test, characterized in that: The control terminal comprises: A first acquisition module, used to acquire error information of the chip to be tested; The first generating module is used to generate first control information according to the error information, so that the microcontroller generates trigger information according to the first control information, the trigger information is used to trigger the logic analyzer to obtain the instantaneous abnormal timing when the trigger information is generated from the timing recorded by it, and obtain the logic instructions executed when the chip under test generates the error information based on the instantaneous abnormal timing analysis, the instantaneous abnormal timing includes the abnormal timing before the chip under test generates the error information, and the logic analyzer is used to continuously record the timing of the operation of the chip under test.

6. A power on / off error detection method, used to detect errors that occur during the power on / off process of a chip under test, characterized in that: The power on / off error detection method is applied in a microcontroller, and the power on / off error detection method includes: Acquire first control information, where the first control information is generated by a control terminal according to error information of the chip to be tested; Generate trigger information according to the first control information, the trigger information is used to trigger the logic analyzer to obtain the instantaneous abnormal timing when the trigger information is generated from the timing recorded by it, and obtain the logic instructions executed when the chip under test generates error information based on the instantaneous abnormal timing analysis, the instantaneous abnormal timing includes the abnormal timing before the chip under test generates the error information, and the logic analyzer is used to continuously record the timing of the operation of the chip under test.

7. A power on / off error detection device, used to detect errors that occur during the power on / off process of a chip to be tested, characterized in that: A microcontroller is included, the microcontroller comprising: A second acquisition module, used to acquire first control information, where the first control information is generated by a control terminal according to error information of the chip to be tested; The second generating module is used to generate trigger information according to the first control information, and the trigger information is used to trigger the logic analyzer to obtain the instantaneous abnormal timing when the trigger information is generated from the timing recorded by it, and obtain the logic instructions executed when the chip under test generates error information based on the instantaneous abnormal timing analysis. The instantaneous abnormal timing includes the abnormal timing before the chip under test generates the error information. The logic analyzer is used to continuously record the timing of the operation of the chip under test.

8. A power on / off error detection method, used to detect errors that occur during the power on / off process of a chip under test, characterized in that: The power on / off error detection method is applied in a logic analyzer, and the logic analyzer is used to continuously record the timing of the operation of the chip under test. The power on / off error detection method includes: Acquire trigger information, where the trigger information is generated by the microcontroller according to first control information, and the first control information is generated by the control terminal according to error information of the chip to be tested; According to the trigger information, the logic analyzer is triggered to obtain the instantaneous abnormal timing when the chip under test generates error information from its recorded timing, and the logic instructions executed when the trigger information is obtained based on the instantaneous abnormal timing analysis, wherein the instantaneous abnormal timing includes the abnormal timing before the chip under test generates the error information.

9. A power on / off error detection device, used to detect errors that occur during the power on / off process of a chip to be tested, characterized in that: A logic analyzer is included, and the logic analyzer is used to continuously record the timing of the operation of the chip under test, and the logic analyzer includes: A third acquisition module is used to acquire trigger information, where the trigger information is generated by the microcontroller according to first control information, and the first control information is generated by the control terminal according to error information of the chip to be tested; The fourth acquisition module is used to obtain the instantaneous abnormal timing when the chip under test generates error information from the timing recorded by the logic analyzer according to the trigger information, and obtain the logic instructions executed when the trigger information is generated based on the instantaneous abnormal timing analysis, wherein the instantaneous abnormal timing includes the abnormal timing before the chip under test generates the error information.

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