Excitation signal generation method and system and digital eddy current sensor

Abstract

The embodiment of the invention provides an excitation signal generation method and system and a digital eddy current sensor, and the method comprises the steps: outputting a square wave signal through a pulse width modulation assembly of a microcontroller unit, and enabling the frequency and resolution of the square wave signal to be adaptive to eddy current probes with different inductance values; inputting the square wave signal into a low-pass filter for filtering, and setting the cut-off frequency of the low-pass filter, the suppression times of higher harmonics and the attenuation slope so as to output a sine wave signal with a target total harmonic distortion range; the amplitude of the sine wave signal is collected in real time, and the pulse width modulation duty ratio and the passband gain of a low-pass filter are dynamically adjusted in combination with a digital control algorithm, so that the sine wave signal is subjected to self-adaptive adjustment and correction and is output; and taking the sine wave signal as an excitation source of an eddy current probe, and driving the eddy current probe to carry out nondestructive testing. According to the invention, the excitation signal which gives consideration to high-frequency signal generation, deep harmonic suppression and digital adaptive adjustment can be generated.

Description

Technical Field

[0001] The present application belongs to the technical field of non-destructive testing, and specifically relates to an excitation signal generation method, system, and digital eddy current sensor. Background Art

[0002] The analog excitation source of traditional eddy current sensors is mostly implemented using LC oscillation circuits or function generator chips composed of discrete components. Its technical limitations are mainly reflected in the following three aspects: 1. Frequency adjustment relies on hardware reconstruction: Analog oscillators require changing the frequency by replacing capacitors and inductors or adjusting the feedback resistor divider ratio. This operation is cumbersome and difficult to achieve continuous adjustment, which cannot meet the dynamic matching requirements of multi-specification probes. 2. Signal stability is affected by the environment: Temperature drift and power supply fluctuations can cause the oscillator output frequency to shift. Actual measurements show that the frequency drift of a typical analog source can reach ±5%, directly affecting the phase consistency of the eddy current detection signal. 3. Insufficient harmonic suppression capability: The high-frequency components in the square wave excitation source, after being amplified by the probe coil, can easily induce parasitic oscillations and interfere with surrounding circuits. Conventional second-order RC filters can only achieve an attenuation slope of -40dB / dec, making it difficult to effectively suppress high-order harmonics.

[0003] To address the above problems, there is an urgent need for an excitation signal implementation method that takes into account high-frequency signal generation, deep harmonic suppression and digital adaptive adjustment. Summary of the Invention

[0004] The present application proposes an excitation signal generation method, system and digital eddy current sensor to address the above-mentioned defects of the prior art.

[0005] According to a first aspect of an embodiment of the present application, there is provided a method for generating an excitation signal, comprising: Outputting a square wave signal through a pulse width modulation component of a microcontroller unit, wherein the frequency and resolution of the square wave signal are adapted to eddy current probes of different inductances; Inputting the square wave signal into a low-pass filter for filtering, and setting the cutoff frequency, the suppression order of higher harmonics, and the attenuation slope of the low-pass filter to output a sine wave signal with a target total harmonic distortion range; The amplitude of the sine wave signal is collected in real time, and the pulse width modulation duty cycle and the passband gain of the low-pass filter are dynamically adjusted in combination with a digital control algorithm, so that the sine wave signal is adaptively adjusted and corrected and output; The sinusoidal wave signal is used as an excitation source of the eddy current probe to drive the eddy current probe to perform nondestructive testing.

[0006] In some embodiments, the frequency of the square wave signal is 1 MHz, the resolution of the square wave signal is less than or equal to 1 kHz, and the square wave signal is adapted to the eddy current probe whose inductance is in the range of 1 μH to 10 mH.

[0007] In some embodiments, the low-pass filter is a fourth-order Chebyshev low-pass filter, and inputting the square wave signal into the low-pass filter for filtering, and setting the cutoff frequency, the suppression order of higher harmonics, and the attenuation slope of the low-pass filter to output a sine wave signal with a target total harmonic distortion range includes: Inputting the square wave signal into the fourth-order Chebyshev low-pass filter; According to the Nyquist criterion that the fundamental wave energy proportion of the square wave signal is greater than or equal to 90%, the cutoff frequency of the fourth-order Chebyshev low-pass filter is set to 1.2 MHz to ensure that the fundamental wave signal passes completely and attenuates the high-frequency components; the suppression order of the higher harmonics is set to 3 or more; and the attenuation slope is set to be greater than -80 dB / dec; Based on the cutoff frequency of 1.2 MHz, the suppression order of the higher harmonics being 3 or above, and the attenuation slope being above -80 dB / dec, the output is controlled to have the sine wave signal with a target total harmonic distortion range of less than or equal to 1% of the total harmonic distortion rate.

[0008] In some embodiments, the real-time acquisition of the amplitude of the sinusoidal wave signal and the dynamic adjustment of the pulse width modulation duty cycle and the passband gain of the low-pass filter in combination with a digital control algorithm to adaptively adjust and correct the sinusoidal wave signal and output the signal include: The amplitude of the output sine wave signal is collected in real time by an analog-to-digital converter, wherein the sampling rate is greater than or equal to 10 MSps; Detecting impedance changes of the eddy current probe based on amplitude changes of the sinusoidal wave signal, and dynamically adjusting the pulse width modulation duty cycle to 20% to 80% in combination with the digital control algorithm and the impedance changes of the eddy current probe to optimize excitation intensity and reduce power consumption; The passband gain of the fourth-order Chebyshev low-pass filter is corrected through a feedback loop, and the passband fluctuation is controlled to be less than or equal to 0.1 dB; Based on the pulse width modulation duty cycle being 20% ​​to 80% and the passband fluctuation being less than or equal to 0.1 dB, the sinusoidal wave signal is controlled to achieve adaptive adjustment correction of the frequency in the range of 10 kHz to 1 MHz, and the output ripple effective value is less than or equal to 5 mVrms.

[0009] In some embodiments, modifying the passband gain of the fourth-order Chebyshev low-pass filter through a feedback loop includes: Based on a field programmable gate array, the passband gain of the fourth-order Chebyshev low-pass filter is corrected by adjusting the feedback resistor in the feedback loop.

[0010] In some embodiments, after acquiring the amplitude of the output sine wave signal in real time through an analog-to-digital converter, the method further includes: Noise interference is eliminated through sliding average filtering.

[0011] In some embodiments, the digital control algorithm adopts a proportional-integral-derivative control algorithm, wherein the proportional coefficient is 0.8, the integral coefficient is 0.05, and the differential coefficient is 0.01. The dynamically adjusting the pulse width modulation duty cycle in combination with the digital control algorithm includes: When it is detected that the amplitude fluctuation of the sine wave signal is greater than 0.1 dB, triggering adjustment of the pulse width modulation duty cycle; Otherwise, the current PWM duty cycle is maintained.

[0012] In some embodiments, the method further comprises: When the eddy current probe is replaced, the changed parameters are automatically identified and matched based on the field programmable gate array, and the operating parameters of the low-pass filter are configured in real time.

[0013] According to a second aspect of the present application, there is provided an excitation signal generating system, comprising: A square wave signal generating module is used to output a square wave signal through a pulse width modulation component of a microcontroller unit, wherein the frequency and resolution of the square wave signal are adapted to eddy current probes of different inductances; a low-pass filtering processing module, configured to input the square wave signal into a low-pass filter for filtering, and set the cutoff frequency, the suppression order of higher harmonics, and the attenuation slope of the low-pass filter to output a sine wave signal with a target total harmonic distortion range; a sine wave signal adjustment module for collecting the amplitude of the sine wave signal in real time and dynamically adjusting the pulse width modulation duty cycle and the passband gain of the low-pass filter in combination with a digital control algorithm, so as to adaptively adjust and correct the sine wave signal and output it; The driving and detecting module is used to use the sinusoidal wave signal as an excitation source of the eddy current probe to drive the eddy current probe to perform nondestructive testing.

[0014] According to a second aspect of the present application, a digital eddy current sensor is provided, which is equipped with the above-mentioned excitation signal generation system, including: A microcontroller unit is configured with a pulse width modulation component for outputting a square wave signal and acquiring the output signal amplitude in real time through an analog-to-digital converter; A field programmable gate array, connected to the microcontroller unit via a bus, for receiving data collected by the analog-to-digital converter and dynamically configuring low-pass filter parameters; An analog front-end circuit, comprising the low-pass filter and a post-stage amplifier circuit, wherein the input end of the analog front-end circuit is used to receive the square wave signal, and the output end of the analog front-end circuit is used to connect to an eddy current probe; A power management unit is used to provide independent isolated power supply for the microcontroller unit, the field programmable gate array and the analog front-end circuit.

[0015] The beneficial effects of the excitation signal generation method, system, and digital eddy current sensor of the embodiments of the present application include at least: The present embodiment dynamically adjusts the square wave frequency and resolution through a microcontroller to achieve compatibility with probes of different inductances, significantly improving the system's adaptability to different inspection targets. This design overcomes the limitations of traditional fixed-frequency solutions, enabling a single excitation source to cover a wider range of industrial inspection scenarios and improving the adaptability of the pulse-width modulation output. By setting precise cutoff frequencies and higher-order harmonic suppression parameters, high-frequency noise components in the square wave signal are effectively filtered out, outputting a low-distortion sine wave signal. This process ensures the purity of the excitation signal, providing a foundation for subsequent high-precision inspection and optimizing signal quality based on a low-pass filter. By real-time acquisition of the output signal amplitude and dynamic adjustment of the duty cycle and passband gain, a closed-loop control is formed to compensate for environmental interference and probe parameter fluctuations. This mechanism significantly enhances the system's anti-interference capability, ensures the stability of the excitation signal under complex working conditions, and establishes a closed-loop adaptive adjustment mechanism. By using the optimized sine wave as the excitation source for the eddy current probe, the probe's electromagnetic conversion efficiency in metal defect detection is enhanced. This design directly improves the sensitivity and reliability of nondestructive testing, reduces the missed detection rate and false positive rate, and achieves improved excitation source driving efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Schematic diagram of the flow of the excitation signal generation method according to an embodiment of the present application; Figure 2 This is a circuit diagram of a fourth-order Chebyshev filter according to an embodiment of the present application; Figure 3 This is a circuit diagram of the adaptive impedance matching of the eddy current probe according to an embodiment of the present application; Figure 4 This is a schematic diagram of the structure of the eddy current probe impedance adaptive matching according to an embodiment of the present application; Figure 5 This is a diagram showing the amplitude fluctuation effect of the adaptive impedance matching of the eddy current probe according to an embodiment of the present application; Figure 6 This is a diagram showing the effect of converting the time domain to the frequency domain for the adaptive impedance matching of the eddy current probe according to an embodiment of the present application; Figure 7 This is a diagram showing the combined effect of the normalized processing of the adaptive impedance matching of the eddy current probe in the embodiment of the present application; Figure 8 This is a schematic structural diagram of an excitation signal generating system according to an embodiment of the present application; Figure 9 This is a schematic structural diagram of a digital eddy current sensor according to an embodiment of the present application. DETAILED DESCRIPTION

[0017] In order to enable those skilled in the art to better understand the technical solution of the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0018] The following detailed description of the embodiments of the present application is provided in conjunction with the accompanying drawings and examples. The following detailed description of the embodiments and the accompanying drawings are used to illustrate the principles of the present application, but are not intended to limit the scope of the present application, that is, the present application is not limited to the described embodiments.

[0019] In some implementations, this application optimized functional requirements before development, including key metrics such as pulse-width modulation (PWM) signal generation accuracy (frequency resolution ≤ 1kHz), dynamic filter parameter configuration (Q range 2-10), and real-time analog-to-digital converter (ADC) feedback (sampling rate ≥ 10MSps). Based on the hardware architecture (microcontroller unit + field-programmable gate array + analog front-end), the software system was divided into three layers: the microcontroller unit (MCU) firmware layer, primarily responsible for PWM control, ADC acquisition, and digital control algorithms; the FPGA logic layer, responsible for filter parameter configuration and probe impedance identification; and the communication interface layer, responsible for handling I²C bus interactions between the MCU and the FPGA and for host computer command parsing.

[0020] Refer to the attached Figure 1 As shown, an embodiment of the present application discloses an excitation signal generation method, which is used to guide multiple operations of an excitation signal generation system so that the excitation signal generation system dynamically adapts to different working conditions. The method is also performed based on a digital eddy current sensor. The method includes steps 110-140.

[0021] Step 110: Output a square wave signal via a pulse width modulation component of the microcontroller unit.

[0022] The microcontroller unit includes a central processing unit (CPU), and the pulse width modulation component belongs to the CPU.

[0023] In some embodiments, the duty cycle and frequency resolution (eg, less than or equal to 1 kHz) are precisely controlled by a timer, and the frequency and resolution of the square wave signal are adapted to eddy current probes with different inductances.

[0024] Exemplarily, the frequency of the square wave signal is 1 MHz, the resolution of the square wave signal is less than or equal to 1 kHz, and the square wave signal is adapted to the eddy current probe whose inductance is in the range of 1 μH to 10 mH.

[0025] In some embodiments, the eddy current probe has an adaptation range covering metal thickness detection (for example, a range of 0.1 mm to 50 mm), and maintains a frequency drift less than or equal to ±0.5% (traditional analog sources are ±5%) within an ambient temperature range of -20°C to 85°C.

[0026] The embodiments of the present application solve the problems of frequency drift (±5%), insufficient harmonic suppression (THD ≥ 5%) and sensitivity to environmental interference of traditional analog excitation sources, and improve the accuracy and stability of eddy current detection.

[0027] Step 120: Input the square wave signal into a low-pass filter for filtering, and set the cutoff frequency, high-order harmonic suppression order, and attenuation slope of the low-pass filter to output a sine wave signal with a target total harmonic distortion range.

[0028] In some embodiments, the low-pass filter is a fourth-order Chebyshev low-pass filter.

[0029] In some embodiments, inputting the square wave signal into a low-pass filter for filtering, and setting the cutoff frequency, the suppression order of higher harmonics, and the attenuation slope of the low-pass filter to output a sinusoidal wave signal with a target total harmonic distortion range includes: inputting the square wave signal into the fourth-order Chebyshev low-pass filter; setting the cutoff frequency of the fourth-order Chebyshev low-pass filter to 1.2 MHz according to the Nyquist criterion that the fundamental wave energy proportion of the square wave signal is greater than or equal to 90% to ensure that the fundamental wave signal passes completely and attenuates the high-frequency components; setting the suppression order of the higher harmonics to 3 or above; setting the attenuation slope to be greater than -80 dB / dec; based on the cutoff frequency of 1.2 MHz, the suppression order of the higher harmonics to be 3 or above, and the attenuation slope to be greater than -80 dB / dec, controlling the output of the sinusoidal wave signal with a target total harmonic distortion (THD) range of less than or equal to 1% of the total harmonic distortion rate.

[0030] For example, refer to the attached Figure 2As shown in the figure, the fourth-order Chebyshev low-pass filter adopts a cascaded Sallen-Key topology. It achieves a steep attenuation slope (>-80dB / dec) by connecting two sets of second-order filter modules in series, effectively suppressing the third and higher-order harmonic components, and ultimately outputs a sine wave signal with a total harmonic distortion of ≤1%.

[0031] Step 130 , collecting the amplitude of the sine wave signal in real time, and dynamically adjusting the pulse width modulation duty cycle and the passband gain of the low-pass filter in combination with a digital control algorithm, so that the sine wave signal is adaptively adjusted and corrected and output.

[0032] In some embodiments, the real-time acquisition of the amplitude of the sinusoidal signal and the dynamic adjustment of the pulse width modulation duty cycle and the passband gain of the low-pass filter in combination with a digital control algorithm to adaptively adjust and correct the sinusoidal signal and output it include: real-time acquisition of the amplitude of the output sinusoidal signal through an analog-to-digital converter (ADC), wherein the sampling rate is greater than or equal to 10 MSps; detecting the impedance change of the eddy current probe based on the amplitude change of the sinusoidal signal, and dynamically adjusting the pulse width modulation duty cycle to 20% to 80% in combination with the digital control algorithm and the impedance change of the eddy current probe to optimize the excitation intensity and reduce power consumption; correcting the passband gain of the fourth-order Chebyshev low-pass filter through a feedback loop and controlling the passband ripple to be less than or equal to 0.1 dB; and based on the pulse width modulation duty cycle being 20% ​​to 80% and the passband ripple being less than or equal to 0.1 dB, controlling the sinusoidal signal to achieve adaptive adjustment and correction in the frequency range of 10 kHz to 1 MHz and outputting an effective ripple value of less than or equal to 5 mVrms. Actual measurements of the embodiments of the present application show that based on the filter passband fluctuation ≤0.1dB and the post-stage voltage stabilization circuit design, the output signal ripple effective value ≤5mVrms can be achieved, and the frequency adjustment range covers 10kHz~1MHz, which can adapt to the requirements of eddy current probes with different inductances (for example, in the range of 1μH~10mH).

[0033] Exemplarily, the modifying the passband gain of the fourth-order Chebyshev low-pass filter through the feedback loop includes: modifying the passband gain of the fourth-order Chebyshev low-pass filter by adjusting a feedback resistor in the feedback loop based on a field programmable gate array.

[0034] Exemplarily, after the amplitude of the output sine wave signal is collected in real time by an analog-to-digital converter, the method further includes: eliminating noise interference by sliding average filtering.

[0035] In some embodiments, the digital control algorithm utilizes a proportional-integral-derivative (PID) control algorithm, wherein the proportional coefficient (Kp) is 0.8, the integral coefficient (Ki) is 0.05, and the differential coefficient (Kd) is 0.01. Dynamically adjusting the pulse width modulation duty cycle in conjunction with the digital control algorithm includes triggering adjustment of the pulse width modulation duty cycle when the amplitude fluctuation of the sinusoidal wave signal is detected to be greater than 0.1 dB; otherwise, maintaining the current pulse width modulation duty cycle. For example, the sampled value of the analog-to-digital converter is compared with the target value, and the error is calculated before dynamically adjusting the pulse width modulation component duty cycle (range: 20%-80%). If the output amplitude drops by more than 0.1 dB, the duty cycle is increased to compensate; otherwise, the duty cycle is decreased.

[0036] Step 140: Use the sinusoidal wave signal as an excitation source for the eddy current probe to drive the eddy current probe to perform nondestructive testing.

[0037] In some embodiments, the method further includes: when the eddy current probe is replaced, automatically identifying and matching the changed parameters based on the field programmable gate array (FPGA) and configuring the operating parameters of the low-pass filter in real time. For example, the low-pass filter gain correction of the present application includes: the field programmable gate array adjusts the filter feedback resistor network (such as the attached) according to the feedback data of the analog-to-digital converter (i.e., the changed parameters). Figure 2 The system dynamically corrects passband gain fluctuations to be less than or equal to 0.1 dB, by adjusting the R3 / R4 ratio in the circuit. For example, when ambient temperature changes cause gain shifts, the feedback resistor value is modified to stabilize the output by modifying the registers of the field-programmable gate array via the integrated circuit bus (I²C) interface.

[0038] Refer to the attached Figure 5-7 As shown in the figure, the time domain waveform of the optimized excitation signal, the deep suppression capability of the fourth-order Chebyshev low-pass filter on high-frequency noise, and the merged result after normalization are respectively shown. Figure 5 It can be observed that the waveform is smooth and has no obvious distortion, reflecting the low ripple characteristics and high stability. By comparing the waveform of the traditional excitation source (which may have high-frequency glitches or amplitude fluctuations), the low-distortion sine wave output (total harmonic distortion ≤ 1%) achieved by the fourth-order Chebyshev low-pass filtering and closed-loop adaptive adjustment of the embodiment of the present application is demonstrated, verifying the optimization effect of the filtering processing and dynamic adjustment mechanism on signal quality. Figure 6 It can be seen that the sensor response signal is converted from the time domain to the frequency domain through Fourier transform, demonstrating the deep suppression capability of the fourth-order Chebyshev low-pass filter on high-frequency noise. Through spectrum comparison, it is intuitively demonstrated that this application has achieved the technical indicator of total harmonic distortion ≤ 1%. Figure 7 Demonstrated based on Figure 5 and Figure 6The results of normalizing and merging the data show the comprehensive Figure 5 and Figure 6 The composite result.

[0039] The present embodiment dynamically adjusts the square wave frequency and resolution through a microcontroller to achieve compatibility with probes of different inductances, significantly improving the system's adaptability to different inspection targets. This design overcomes the limitations of traditional fixed-frequency solutions, enabling a single excitation source to cover a wider range of industrial inspection scenarios and improving the adaptability of the pulse-width modulation output. By setting precise cutoff frequencies and higher-order harmonic suppression parameters, high-frequency noise components in the square wave signal are effectively filtered out, outputting a low-distortion sine wave signal. This process ensures the purity of the excitation signal, providing a foundation for subsequent high-precision inspection and optimizing signal quality based on a low-pass filter. By real-time acquisition of the output signal amplitude and dynamic adjustment of the duty cycle and passband gain, a closed-loop control is formed to compensate for environmental interference and probe parameter fluctuations. This mechanism significantly enhances the system's anti-interference capability, ensures the stability of the excitation signal under complex working conditions, and establishes a closed-loop adaptive adjustment mechanism. By using the optimized sine wave as the excitation source for the eddy current probe, the probe's electromagnetic conversion efficiency in metal defect detection is enhanced. This design directly improves the sensitivity and reliability of nondestructive testing, reduces the missed detection rate and false positive rate, and achieves improved excitation source driving efficiency.

[0040] The core of this method lies in optimizing the frequency regulation and harmonic suppression performance of the excitation signal through digital means. Specifically, it can be understood as a technological innovation for digital control and high-order filtering of high-frequency sinusoidal excitation sources. Combining pulse-width modulation signal synthesis, Chebyshev filter design, and impedance matching optimization, this method is suitable for the stable output requirements of signal sources in industrial scenarios such as metal defect detection and coating thickness measurement. The central processor's pulse-width modulation component outputs a 1MHz square wave signal (frequency resolution ≤1kHz), which is then processed by a fourth-order Chebyshev low-pass filter to generate a sine wave with total harmonic distortion ≤1%. This solution, combined with analog-to-digital converter feedback, enables adaptive frequency adjustment (ranging from 10kHz to 1MHz) to accommodate probes with varying inductances (1μH to 10mH). This solution addresses the issues of frequency drift (±5%), insufficient harmonic suppression (THD ≥5%), and sensitivity to environmental interference associated with traditional analog excitation sources. The output signal has an effective ripple value of ≤5mV rms, improving detection stability and accuracy.

[0041] In some embodiments, the method further includes: firmware development of the microcontroller unit, such as including initialization of the underlying driver, generation of pulse width modulation signals, and generation of feedback and control algorithms for the analog-to-digital converter. Among them, the initialization of the underlying driver includes: configuring the clock system of the microcontroller unit, increasing the main frequency to 400MHz to meet the pulse width modulation signal accuracy requirements. Initialize the pins of the general input and output interface (GPIO) to a multiplexed push-pull mode, and allocate two pulse width modulation channels (TIMx_CHy) for outputting square wave signals. The analog-to-digital converter needs to enable multi-channel synchronous sampling mode, and configure the digital-to-analog converter (DMA) channel to achieve high-speed data transfer to avoid interrupt overhead of the central processing unit. Pulse width modulation signal generation includes: setting the pulse width modulation period and duty cycle through the timer register (TIMx_ARR / TIMx_CCR), and using the center alignment mode to reduce signal jitter. The frequency adjustment logic needs to be embedded in the table lookup method, according to the probe inductance ( ) Calculate the matching frequency , dynamically updating timer parameters. The ADC feedback and control algorithm generation includes: The ADC acquisition unit must be set to a sample-and-hold time ≥ 80ns to ensure 1MHz signal accuracy. The collected data is filtered through a sliding average and then fed into the proportional-integral-derivative control algorithm. The proportional coefficient (Kp) is set to 0.8, the integral coefficient (Ki) to 0.05, and the differential coefficient (Kd) to 0.01. The output amplitude is stabilized by adjusting the PWM duty cycle (20%-80%). A deadband check (no adjustment if the error is <0.1dB) is implemented in the algorithm to prevent high-frequency oscillation.

[0042] In some embodiments, reference Figure 2-3As shown, the method also includes developing logic for a field-programmable gate array (FPGA), including, for example, filter parameter configuration and probe impedance identification configuration. The filter parameter configuration utilizes a specialized programming language for digital circuit design (such as Verilog HDL) to program the fourth-order Chebyshev filter control logic. A steep roll-off characteristic is achieved through a cascaded biquad active filter design architecture (Sallen-Key). The filter's Q value is dynamically adjusted by modifying the ratio of the feedback resistors (R3 / R4). For example, in high-Q mode (Q=10), R3 is set to 1kΩ and R4 to 10kΩ; in low-Q mode (Q=2), R3 = 10kΩ and R4 = 1kΩ. Parameter switching is controlled by the FPGA's internal state machine, with a response time of ≤1ms. The specific steps for implementing the control logic of a fourth-order Chebyshev filter in a field-programmable gate array using Verilog HDL include: constructing a structure by cascading two second-order Sallen-Key filters, using code to describe the logical relationship between the integrator and adder; designing a parameterized Q-value dynamic configuration module, storing preset coefficients in a lookup table (LUT) / register, and automatically adjusting the feedback resistor ratio based on external control signals; building a state machine to control mode switching, including initialization, parameter update, and steady-state phases, ensuring glitch-free switching within 1ms and rapidly loading stored coefficients into the arithmetic unit; optimizing timing control to achieve arithmetic clock synchronization and process data valid / ready signals; and defining an external interface for receiving control signals, outputting filtered data, and indicating switching status. Probe impedance identification configuration involves designing an I²C slave module to receive the impedance identification code (7-bit address) sent by the microcontroller unit and automatically matching the filter parameters using a pre-stored mapping table (Lx-Cx). For example, when address 0x12 (corresponding to a 1μH probe) is received, the high-Q value mode is triggered and the high-frequency compensation capacitor (Cx=10pF) is enabled. If the address is 0x2A (corresponding to a 10mH probe), the low-Q value mode is switched to and the low-frequency compensation inductor (Lx=100μH) is connected.

[0043] In some embodiments, the method further includes developing a communication interface, for example, including initializing the I²C bus and parsing host computer commands. I²C bus initialization involves using the standard I²C protocol for communication between the microcontroller unit and the field-programmable gate array (FPGA), with the main frequency configured in 400kHz fast mode. The microcontroller unit, acting as the master, sends a probe address frame (7 bits + a read / write bit). The FPGA slave interprets the address and responds via a hardware state machine. Data transmission utilizes a polling method to avoid the complexity of the digital-to-analog converter. Each communication consists of a 1-byte address and 2-byte parameters (e.g., filter Q value, compensation capacitor value). Host computer command parsing includes reserving an asynchronous receiver / transmitter (UART) interface for connecting to a PC debugging tool, using an 8N1 protocol format (8 data bits, no parity, 1 stop bit). The host computer can issue a frequency sweep command (e.g., 10kHz → 1MHz in 1kHz steps). Upon receiving the command, the microcontroller unit initiates a timer interrupt, sequentially updates the pulse-width modulation parameters, and records the amplitude-frequency characteristics of the output signal.

[0044] In some embodiments, the method further includes signal generation and filtering. For example, upon system startup, the microcontroller unit initializes the pulse-width modulation component to output a 1MHz square wave signal with an initial duty cycle of 50%. The square wave signal is filtered through an RC pre-filter circuit (100Ω + 1nF) to remove high-frequency spikes before being input into a fourth-order Chebyshev filter. The filter employs a voltage-controlled voltage source (VCVS) structure in the first stage and a multi-path feedback (MFB) structure in the second stage. The in-band gain fluctuation is controlled to ≤0.1dB by adjusting the ratio of feedback resistors R3 (1kΩ ± 1%) to R4 (10kΩ ± 1%). Measurements show that this structure attenuates the third harmonic by 42dB and the fifth harmonic by 68dB. The filtered signal is buffered and output by an AD811 op amp. The output amplitude is adjusted using an AD5142 digital potentiometer in 0.1Vpp steps, covering a range of 0.5Vpp to 5Vpp. The output signal ripple effective value measured by the oscilloscope is 4.7mV rms, which meets the design specification of ≤5mV rms.

[0045] In some embodiments, the method also includes closed-loop feedback regulation, such as a dual-loop feedback mechanism to enhance stability: the outer loop acquires the output signal amplitude via an analog-to-digital converter. When amplitude fluctuations greater than ±0.5dB are detected, the microcontroller unit executes a proportional-integral-derivative control algorithm to correct the pulse-width modulation duty cycle; the inner loop monitors the filter passband gain in real time and dynamically adjusts the feedback resistor network parameters via a field-programmable gate array. Regarding temperature compensation, the system has a built-in temperature sensor that triggers a gain calibration procedure when the ambient temperature changes by more than 5°C. Load adaptability testing shows that when the probe inductance switches from 1μH to 10mH, the system can complete impedance matching within 200ms, and the output signal amplitude fluctuation is controlled within ±0.1dB.

[0046] In some embodiments, the method also includes: system integration and test verification. For example, after completing the software and hardware development, multi-dimensional performance testing is required, which may include: signal quality testing, using a spectrum analyzer to measure the total harmonic distortion value; dynamic adjustment capability testing, setting the frequency scanning instruction (10kHz-1MHz) through the host computer, and the system response time is less than 50ms; environmental adaptability testing, verifying the frequency stability in a temperature box from -20°C to 85°C, with a drift of ≤±0.5%; actual detection application testing: in metal crack detection, the system resolution reaches 0.01mm level, and the coating thickness measurement repeatability error is less than 0.5%. Refer to the attached Figure 4 As shown, during testing, the probe coil should maintain a distance of 0.5mm ± 0.05mm from the metal being tested. The excitation signal frequency is dynamically optimized based on the material's conductivity (500kHz for aluminum and 200kHz for steel). The grounding strategy for the printed circuit board layout was also considered during implementation, with a single-point grounding preferred. The analog and digital grounds are connected via a ferrite bead to reduce high-frequency noise coupling.

[0047] Reference Figure 8 As shown, the embodiment of the present application further discloses an excitation signal generation system, including: a square wave signal generation module 610, a low-pass filtering processing module 620, a sine wave signal adjustment module 630 and a drive detection module 640.

[0048] The square wave signal generating module 610 is configured to output a square wave signal through a pulse width modulation component of a microcontroller unit, wherein the frequency and resolution of the square wave signal are adapted to eddy current probes of different inductances.

[0049] The low-pass filter processing module 620 is used to input the square wave signal into a low-pass filter for filtering, and set the cutoff frequency, high-order harmonic suppression order and attenuation slope of the low-pass filter to output a sine wave signal with a target total harmonic distortion range.

[0050] The sine wave signal adjustment module 630 is used to collect the amplitude of the sine wave signal in real time, and dynamically adjust the pulse width modulation duty cycle and the passband gain of the low-pass filter in combination with the digital control algorithm, so that the sine wave signal can be adaptively adjusted and corrected and output.

[0051] The driving detection module 640 is configured to use the sinusoidal wave signal as an excitation source for the eddy current probe to drive the eddy current probe to perform nondestructive testing.

[0052] Refer to the attached Figure 9 As shown, an embodiment of the present application further discloses a digital eddy current sensor, which is equipped with the above-mentioned excitation signal generation system, including: a microcontroller unit, a field programmable gate array, an analog front-end circuit and a power management unit.

[0053] The microcontroller unit is equipped with a pulse width modulation component for outputting a square wave signal and collecting the output signal amplitude in real time through an analog-to-digital converter.

[0054] The field programmable gate array is connected to the microcontroller unit via a bus and is used to receive data collected by the analog-to-digital converter and dynamically configure low-pass filter parameters.

[0055] The analog front-end circuit includes the low-pass filter and the post-stage amplifier circuit. The input end of the analog front-end circuit is used to receive the square wave signal, and the output end of the analog front-end circuit is used to connect to the eddy current probe.

[0056] A power management unit is used to provide independent isolated power supply for the microcontroller unit, the field programmable gate array and the analog front-end circuit.

[0057] In some embodiments, the microcontroller unit includes a central processing unit (CPU). Its main control chip features a 280MHz core, a double-precision floating-point unit (FPU), and a wealth of peripheral resources (such as a multi-channel PWM, a high-speed ADC, and an I²C interface). The microcontroller unit is powered by a 3.3V voltage regulator chip. A 10μF ceramic capacitor and a 0.1μF chip capacitor are connected in parallel at the input to suppress ripple. The clock circuit uses an 8MHz active crystal oscillator. The load capacitance must meet the datasheet's recommended values ​​(typically 5pF-20pF), and the PCB trace length must be kept within 3mm to reduce parasitic inductance. The reset circuit uses an SP706S chip for low-level reset. A 4.7kΩ pull-down resistor is used on the reset pin to ensure a stable reset signal. The clock circuit consists of an active crystal oscillator, load capacitors, resistors, and a printed circuit board (PCB). The 8MHz active crystal oscillator is the core component, with integrated amplification and oscillation circuitry. Upon power-up, it outputs a stable clock signal as a time reference. The load capacitor should be selected according to the manual, with a value between 5pF and 20pF. This will form a resonant circuit with the crystal's internal capacitance to adjust frequency accuracy. The crystal oscillator's traces on the printed circuit board should be within 3mm to prevent parasitic inductance from interfering with high-frequency signals. The operating principle is based on the piezoelectric effect of a quartz crystal: applied voltage generates mechanical vibration, which the oscillator circuit converts into an electrical signal. This signal is then continuously oscillated through positive feedback, and the shaping circuit ultimately outputs a square wave. The load capacitors form a voltage divider network to fine-tune the frequency. Short traces minimize the effects of parasitic parameters and ensure a stable clock base for the microcontroller unit / field-programmable gate array. The design should strictly follow the manual and optimize through simulation testing. The reset circuit primarily includes components such as the core chip and a 4.7kΩ pull-down resistor. The core chip monitors the power supply voltage. When the voltage falls below a set threshold, its reset pin outputs a low signal, triggering a system reset. The 4.7kΩ pull-down resistor is connected from one end to the reset pin to ground. This pull-down resistor maintains the pin low when the chip is not in reset mode, preventing signal instability that could occur if the pin is left floating. The operating principle is as follows: When the power supply is normal, the core chip detects that the voltage is above the threshold, and the reset pin remains high (or inactive). When the power supply voltage drops below the threshold, the chip's internal circuitry triggers, causing the reset pin to go low. This state is maintained by a pull-down resistor, sending a reset signal to the main control chip, forcing a system restart. After the voltage returns to normal, the chip delays for a period of time (determined by internal circuitry) before returning the reset pin to a high level, allowing the system to resume normal operation. This entire process, through chip monitoring and resistor stabilization, ensures the reliability and stability of low-level reset.

[0058] In some embodiments, the control logic for a field-programmable gate array (FPGA) includes the use of a chip that supports dynamic configuration of filter parameters and probe impedance recognition. Its power supply design utilizes a three-stage power supply scheme: a 1.0V core voltage regulator, a 1.5V auxiliary voltage, and a 3.3V input / output (I / O) voltage. The configuration chip uses a JTAG interface capable of downloading .bitstream files. Communication with the microcontroller unit utilizes an I²C bus with a 4.7kΩ pull-up resistor to ensure signal integrity in 400kHz fast mode. The FPGA input clock is provided by a separate 25MHz crystal oscillator, which is divided down by a low-phase noise buffer to generate the system clock.

[0059] In a specific implementation process, the analog front-end circuit implementation includes: arranging a fourth-order Chebyshev low-pass filter and power amplification and output regulation.

[0060] Among them, refer to the attached Figure 2 As shown, the fourth-order Chebyshev low-pass filter utilizes a cascaded biquad active filter design (Sallen-Key) architecture. The first stage utilizes a voltage-controlled voltage source (VCVS) topology, and the second stage utilizes a multiplexed feedback (MFB) structure. The op amp used is a high-speed current-feedback operational amplifier (such as the AD811), with a gain-bandwidth product (GBW) of 50MHz, ensuring distortion-free transmission of 1MHz signals. The filter cutoff frequency is set to 1.2MHz. Resistors R1-R4 are 1kΩ-10kΩ (1% accuracy), and capacitors C1-C4 are 1nF-10nF (C0G / NPO). During PCB layout, the op amp buffer should be placed close to the output, and 0.1μF decoupling capacitors should be added to the power supply pins. Furthermore, the first-stage voltage-controlled voltage source topology of the fourth-order Chebyshev low-pass filter components meets the requirements of a high-speed current-feedback operational amplifier (OPA), R1-R2 = 1kΩ ± 1%, and C1-C2 = 1nF C0G. The second-stage adopts a multi-path feedback structure, meeting the requirements of a high-speed current-feedback operational amplifier (OPA), R3-R4 = 10kΩ ± 1%, and C3-C4 = 10nF NPO. The fourth-order Chebyshev low-pass filter principle involves achieving a steep roll-off (attenuation slope > -80dB / dec) through the cascade of two second-order filters, a cutoff frequency of 1.2MHz (fundamental wave energy share ≥ 90%), and suppression of third and higher harmonics.

[0061] The power amplification and output regulation components include: The post-amplifier circuit utilizes a high-speed current-feedback operational amplifier (OPA) in a voltage-follower configuration with a drive capacity of 100mA. A 50Ω resistor is connected in series at the output to match a 50Ω load. Amplitude adjustment is achieved via a digital potentiometer, with control signals provided by a field-programmable gate array (FPGA) via an I²C interface. The adjustment step size is 0.1Vpp, and the range is 0.5Vpp-5Vpp. A 100pF ceramic capacitor and a 10μF electrolytic capacitor are connected in parallel at the output to suppress high-frequency noise and low-frequency ripple. The post-amplifier circuit components include a voltage-follower configuration of a high-speed current-feedback operational amplifier, a digital potentiometer, an output matching resistor, and a storage capacitor (100pF + 10μF in parallel). The post-amplifier circuit utilizes a high-speed current-feedback operational amplifier as a buffer to isolate the filter from the effects of load variations. The digital potentiometer adjusts the output amplitude (0.5Vpp-5Vpp) via I²C commands sent from the FPGA. A 100pF capacitor (100μF) is connected in parallel at the output to suppress high-frequency noise and low-frequency ripple.

[0062] In some embodiments, the power management and isolation layout of the present application includes a multi-channel independent power supply strategy and π-type filtering on all power input terminals. This strategy includes: the digital power supply for the microcontroller unit / field programmable gate array adopts a 5V→3.3V output voltage and a 3A output current; the analog circuit power supply adopts a ±12V (dual power module) layout with a ripple noise ≤30μVrms; the probe excitation power supply adopts adjustable voltage regulation and supports a 0.5A constant current output; and all power input terminals are equipped with π-type filtering, including a 10μF ceramic capacitor, a ferrite bead, a 0.1μF capacitor, and a single-point connection between the analog and digital grounds via a 0Ω ferrite bead to prevent ground loop interference.

[0063] In some embodiments, the layout and wiring structure of the printed circuit board includes: adopting a four-layer board design (signal layer → power layer → ground layer → signal layer), and key wiring rules include: implementing high-speed signal lines through a structure with a trace length of ≤5cm between pulse width modulation components and analog-to-digital converters, and using a stripline structure for ground processing; the analog circuit area is laid out by prohibiting digital signals from passing within 20mm around filters and operational amplifiers; the heat dissipation design is laid out in a manner such that the copper area on the bottom of the microcontroller is ≥50mm² and the number of vias is ≥9 (diameter 0.3mm); the interface layout is close to the edge of the board through the I²C bus and universal asynchronous receiver and transmitter (UART) interface, and electrostatic discharge protection (ESD) protection devices (such as TVS diodes) are reserved.

[0064] The embodiment of the present application innovatively introduces a software-hardware coordinated adjustment mechanism at the control logic level. The output signal amplitude is collected in real time through an analog-to-digital converter, and the pulse width modulation duty cycle is dynamically adjusted (adjustment range 20%~80%) in combination with a digital control algorithm, while correcting the filter passband gain fluctuation (≤0.1dB). This closed-loop feedback design not only optimizes the excitation intensity, but also significantly reduces power consumption. Actual measurements show that within the ambient temperature range of -20℃~85℃, the frequency drift can be controlled within ±0.5% (traditional analog sources are ±5%). In terms of system integration, a hybrid architecture of microcontroller unit + field programmable gate array + analog front end is adopted, in which the field programmable gate array is responsible for dynamic configuration of filter parameters and supports automatic recognition and impedance matching when the probe is replaced. The embodiments of this application are innovative in the following three dimensions: using pulse width modulation digital synthesis technology to replace the traditional RC oscillator, breaking the limitation of analog circuit frequency adjustment relying on hardware reconstruction; using a fourth-order Chebyshev filter, its roll-off characteristics more than double the ability to suppress high-order harmonics compared to conventional second-order RC filters; and through analog-to-digital converter feedback and microcontroller unit algorithm optimization, solving the matching problem caused by probe parameter differences, adapting to the metal thickness detection range of 0.1mm to 50mm. Based on this, this application is the city's technical solution that has achieved significant improvements in signal quality, dynamic adjustment capabilities, and environmental adaptability.

[0065] Experimental data from this application demonstrates that a fourth-order Chebyshev low-pass filter can achieve an attenuation slope exceeding -80dB / dec for third-order and higher harmonics. Combined with a 1.2MHz cutoff frequency designed according to the Nyquist criterion, which requires a fundamental energy fraction of ≥90%, this approach stabilizes the total harmonic distortion of the output sine wave within a range of ≤1%. Compared to the -40dB / dec attenuation capability of a traditional second-order RC filter, this solution more than doubles the harmonic suppression efficiency, effectively addressing the signal distortion caused by parasitic oscillations in eddy current probes. By collaboratively controlling the PWM duty cycle (adjustable from 20% to 80%) and filter gain through a closed-loop feedback mechanism, the effective value of the output signal ripple can be reduced to ≤5mV rms, an 80% reduction compared to existing technologies, significantly improving the detection signal-to-noise ratio. In terms of frequency adjustment flexibility, the central processing unit-based pulse width modulation unit achieves continuous frequency coverage from 10kHz to 1MHz, with a frequency resolution of ≤1kHz. Tests have shown that this solution can accommodate probes with an inductance range of 1μH to 10mH, meeting metal thickness detection requirements from 0.1mm to 50mm. Traditional analog sources require hardware parameter modifications to achieve similar coverage. Environmental adaptability tests have shown that frequency drift is ≤±0.5% within the -20°C to 85°C temperature range (compared to ±5% for traditional solutions). Furthermore, thanks to the ADC's real-time compensation mechanism, output amplitude fluctuations are controlled within ±0.1dB. This feature ensures system stability even in strong electromagnetic interference scenarios, with a measured ripple rejection ratio exceeding 40dB.

[0066] Compared with the existing technology, the embodiment of the present application realizes the dynamic configuration function of filter parameters through the hybrid architecture of microcontroller unit + field programmable gate array, and supports automatic recognition and matching when the probe is replaced. In addition, the steep roll-off characteristics of the fourth-order Chebyshev filter are also different from the conventional second-order filter design, avoiding the parasitic effects caused by high-order harmonics. After verification by the laboratory prototype, the solution has achieved a resolution of 0.01mm in metal crack detection, and the repeatability error of coating thickness measurement is less than 0.5%, and the performance has been fully improved.

[0067] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present application, and the present application is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present application, and such modifications and improvements are also considered to be within the scope of protection of the present application.

Claims

1. A method for generating an excitation signal, characterized in that: include: Outputting a square wave signal through a pulse width modulation component of a microcontroller unit, wherein the frequency and resolution of the square wave signal are adapted to eddy current probes of different inductances; Inputting the square wave signal into a low-pass filter for filtering, and setting the cutoff frequency, the suppression order of higher harmonics, and the attenuation slope of the low-pass filter to output a sine wave signal with a target total harmonic distortion range; The amplitude of the sine wave signal is collected in real time, and the pulse width modulation duty cycle and the passband gain of the low-pass filter are dynamically adjusted in combination with a digital control algorithm, so that the sine wave signal is adaptively adjusted and corrected and output; The sinusoidal wave signal is used as an excitation source of the eddy current probe to drive the eddy current probe to perform nondestructive testing.

2. The method according to claim 1, characterized in that The frequency of the square wave signal is 1 MHz, the resolution of the square wave signal is less than or equal to 1 kHz, and the square wave signal is suitable for the eddy current probe whose inductance is in the range of 1 μH to 10 mH.

3. The method according to claim 1, characterized in that The low-pass filter is a fourth-order Chebyshev low-pass filter, and the square wave signal is input into the low-pass filter for filtering, and the cutoff frequency, the suppression order of higher harmonics and the attenuation slope of the low-pass filter are set to output a sine wave signal with a target total harmonic distortion range. The steps include: Inputting the square wave signal into the fourth-order Chebyshev low-pass filter; According to the Nyquist criterion that the fundamental wave energy proportion of the square wave signal is greater than or equal to 90%, the cutoff frequency of the fourth-order Chebyshev low-pass filter is set to 1.2 MHz to ensure that the fundamental wave signal passes completely and attenuates the high-frequency components; the suppression order of the higher harmonics is set to 3 or more; and the attenuation slope is set to be greater than -80 dB / dec; Based on the cutoff frequency of 1.2 MHz, the suppression order of the higher harmonics being 3 or above, and the attenuation slope being above -80 dB / dec, the output is controlled to have the sine wave signal with a target total harmonic distortion range of less than or equal to 1% of the total harmonic distortion rate.

4. The method according to claim 1, wherein The real-time acquisition of the amplitude of the sine wave signal and the dynamic adjustment of the pulse width modulation duty cycle and the passband gain of the low-pass filter in combination with a digital control algorithm so as to adaptively adjust and correct the sine wave signal and output the signal include: The amplitude of the output sine wave signal is collected in real time by an analog-to-digital converter, wherein the sampling rate is greater than or equal to 10 MSps; Detecting impedance changes of the eddy current probe based on amplitude changes of the sinusoidal wave signal, and dynamically adjusting the pulse width modulation duty cycle to 20% to 80% in combination with the digital control algorithm and the impedance changes of the eddy current probe to optimize excitation intensity and reduce power consumption; The passband gain of the fourth-order Chebyshev low-pass filter is corrected through a feedback loop, and the passband fluctuation is controlled to be less than or equal to 0.1 dB; Based on the pulse width modulation duty cycle being 20% ​​to 80% and the passband fluctuation being less than or equal to 0.1 dB, the sinusoidal wave signal is controlled to achieve adaptive adjustment correction of the frequency in the range of 10 kHz to 1 MHz, and the output ripple effective value is less than or equal to 5 mVrms.

5. The method according to claim 4, characterized in that The passband gain of the fourth-order Chebyshev low-pass filter is corrected by a feedback loop, comprising: Based on a field programmable gate array, the passband gain of the fourth-order Chebyshev low-pass filter is corrected by adjusting the feedback resistor in the feedback loop.

6. The method according to claim 4, characterized in that After collecting the amplitude of the output sine wave signal in real time through the analog-to-digital converter, the method further includes: Noise interference is eliminated through sliding average filtering.

7. The method according to claim 1, characterized in that The digital control algorithm adopts a proportional-integral-differential control algorithm, wherein the proportional coefficient is 0.8, the integral coefficient is 0.05, and the differential coefficient is 0.

01. The dynamic adjustment of the pulse width modulation duty cycle in combination with the digital control algorithm includes: When it is detected that the amplitude fluctuation of the sine wave signal is greater than 0.1 dB, triggering adjustment of the pulse width modulation duty cycle; Otherwise, the current PWM duty cycle is maintained.

8. The method according to claim 5, characterized in that The method further comprises: When the eddy current probe is replaced, the changed parameters are automatically identified and matched based on the field programmable gate array, and the operating parameters of the low-pass filter are configured in real time.

9. An excitation signal generating system, configured to execute the excitation signal generating method according to any one of claims 1 to 8, characterized in that: include: A square wave signal generating module is used to output a square wave signal through a pulse width modulation component of a microcontroller unit, wherein the frequency and resolution of the square wave signal are adapted to eddy current probes of different inductances; a low-pass filtering processing module, configured to input the square wave signal into a low-pass filter for filtering, and set the cutoff frequency, the suppression order of higher harmonics, and the attenuation slope of the low-pass filter to output a sine wave signal with a target total harmonic distortion range; a sine wave signal adjustment module for collecting the amplitude of the sine wave signal in real time and dynamically adjusting the pulse width modulation duty cycle and the passband gain of the low-pass filter in combination with a digital control algorithm, so as to adaptively adjust and correct the sine wave signal and output it; The driving and detecting module is used to use the sinusoidal wave signal as an excitation source of the eddy current probe to drive the eddy current probe to perform nondestructive testing.

10. A digital eddy current sensor, equipped with the excitation signal generating system according to claim 9, characterized in that: include: A microcontroller unit is configured with a pulse width modulation component for outputting a square wave signal and acquiring the output signal amplitude in real time through an analog-to-digital converter; A field programmable gate array, connected to the microcontroller unit via a bus, for receiving data collected by the analog-to-digital converter and dynamically configuring low-pass filter parameters; An analog front-end circuit, comprising the low-pass filter and a post-stage amplifier circuit, wherein the input end of the analog front-end circuit is used to receive the square wave signal, and the output end of the analog front-end circuit is used to connect to an eddy current probe; A power management unit is used to provide independent isolated power supply for the microcontroller unit, the field programmable gate array and the analog front-end circuit.

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