System on Chip

Abstract

The present application discloses a system on a chip, which includes a plurality of host devices, a plurality of slave devices, a plurality of preprocessing components with the same structure and uniquely corresponding to each slave device, and a connector with one end connected to each host device and the other end connected to each preprocessing component. The preprocessing component includes a custom interface containing a custom write channel and a custom read channel, a read-write interface, a read-write operation conversion state machine, an asynchronous fifo module, and a slave error detection module, and the slave error detection module is connected to the read-write operation conversion state machine. The read-write operation conversion state machine completes the data interaction and timing conversion between the custom interface and the write interface and the read interface respectively; the write data operation and the read data operation achieve isolation of different clock domains through the asynchronous fifo module; the slave error detection module detects errors in the write address channel and the read address channel and responds to the error signal. The present application simplifies the interface timing of AXI and improves the reliability and availability of the entire system.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to a system on chip. Background Art

[0002] With the continuous development of IC (Integrated Circuit), the requirements for the processing speed performance of SOC (System on Chip) chips are getting higher and higher. As the central bridge connecting various functional modules, the system bus plays an important role in the performance of the SOC system, especially for a system with multiple master devices and multiple slave devices. The AMBA (Advanced Microcontroller Bus Architecture) bus was jointly developed by ARM and other chip companies including Qualcomm, Toshiba, and Ericsson to meet the requirements of the SOC system for multi-user, high-performance, and low-power consumption, and has been widely used at present. According to the bus development time and usage environment, the AMBA bus can be further divided into the APB (Advanced Peripheral Bus), AHB (Advanced High Performance Bus), and AXI (Advanced eXtensible Interface) buses. The functions supported by them are becoming more and more complex, and the development difficulty is also increasing. As a representative of high-performance buses, the AXI bus poses high requirements for developers and also brings great challenges to the development cycle of the SOC. There are often multiple slave devices in the SOC. The total number of host devices is generally less than the total number of slave devices, resulting in a very complex timing of the entire AXI interface and a relatively high development difficulty of the SOC system. Moreover, when detecting the working status of each slave device, it is necessary to rely on the error response signals generated by the slave devices, so the system reliability of the SOC is not high.

[0003] In view of this, how to optimize the data processing method between the slave device and the AXI bus it is mounted on, simplify the AXI interface timing, reduce the development difficulty of the SOC system, and improve the system reliability and system availability of the SOC are technical problems that need to be solved by those skilled in the art. Summary of the Invention

[0004] This application provides a system on chip, which optimizes the data processing method between the slave device and the AXI bus it is mounted on, simplifies the AXI interface timing, reduces the development difficulty of the SOC system, and improves the system reliability and system availability of the SOC.

[0005] To solve the above technical problems, the embodiments of the present invention provide the following technical solutions:

[0006] In one aspect, an embodiment of the present invention provides a system - on - chip, including an AXI bus system. The AXI bus system includes multiple host devices, multiple slave devices, and a connector, and also includes multiple pre - processing components with the same structure. Each pre - processing component uniquely corresponds to one slave device; one end of the connector is connected to each host device, and the other end is connected to each pre - processing component;

[0007] The pre - processing component includes a custom interface, a read - write operation conversion state machine, a write interface, a read interface, an asynchronous FIFO module, and a slave error detection module; the custom interface includes a custom write channel and a custom read channel, the write interface corresponds to a write data channel, and the read interface corresponds to a read data channel; the slave error detection module is connected to the read - write operation conversion state machine;

[0008] The read - write operation conversion state machine is used to complete data interaction and timing conversion between the custom interface and the write interface, and between the custom interface and the read interface;

[0009] The asynchronous FIFO module is used to isolate the write data operation and the read data operation in different clock domains;

[0010] The slave error detection module is used to detect errors in the write address channel and the read address channel and respond to error signals.

[0011] Optionally, when the slave error detection module determines that the base address of the write protection area is less than the write address signal of the write address channel, and the sum of the base address of the write protection area and the space address of the write protection area is greater than the write address signal, it generates an error signal, sets the write response signal to the slave error identification value, and at the same time raises the write response valid signal until the write response ready signal is 1 at the same time.

[0012] Optionally, when the slave error detection module determines that the base address of the read protection area is less than the read address signal of the read address channel, and the sum of the base address of the read protection area and the space address of the read protection area is greater than the read address signal, it generates an error signal, sets the read response signal to the slave error identification value, and at the same time raises the read response valid signal until the read response ready signal is 1 at the same time.

[0013] Optionally, when the slave error detection module detects that the write burst signal of the write address channel is the slave error identification value, it judges whether the write burst length is 1 or 3 or 7 or 15;

[0014] If the write burst length is not 1 or 3 or 7 or 15, it sets the write response signal to the slave error identification value, and at the same time raises the write response valid signal until the write response ready signal is 1 at the same time.

[0015] Optionally, the slave error detection module is configured to determine whether the read burst length is 1, 3, 7, or 15 when detecting that the read burst signal of the read address channel is the slave error identification value;

[0016] If the read burst length is not 1, 3, 7, or 15, the read response signal is set to the slave error identification value, and at the same time, the read response valid signal is pulled high until the read response ready signal is 1 at the same time.

[0017] Optionally, the preprocessing component further includes a slave offline detection module;

[0018] The slave offline detection module is configured to determine whether the corresponding slave device is in an offline state during each handshake time of the detection handshake signal pair in the custom write channel or the custom read channel.

[0019] Optionally, the read / write operation conversion state machine includes a write operation conversion state machine;

[0020] The write operation conversion state machine is configured to convert the write timing corresponding to the write address channel and the write data channel into the write data timing that meets the custom interface, and send the address and data after the timing conversion to the custom write channel.

[0021] Optionally, the write operation conversion state machine is further configured to: when the custom write data valid signal and the custom write data ready signal are pulled high and the handshake is successful, write data to the subsequent module, and at the same time, the subsequent module returns a corresponding signal to the current write operation.

[0022] Optionally, the write operation conversion state machine is further configured to: when a write operation is detected, send a write instruction carrying the write address, the write data occupied space capacity value, and the instruction valid flag; when the write instruction is successfully sent, send a data enable signal and the data to be written.

[0023] Optionally, the read / write operation conversion state machine includes a read operation conversion state machine;

[0024] The read operation conversion state machine is configured to:

[0025] When the read address valid signal is 1, store multiple types of data read from the read address channel, and convert the data of the target type into a signal of the custom write timing;

[0026] Pull high the custom read data instruction valid signal, and at the same time wait for the custom read data instruction ready signal to be pulled high to complete the handshake;

[0027] When the custom read data valid signal is valid, pull high the custom read data ready signal, and store the returned data into the asynchronous fifo module;

[0028] Convert the return data read from the asynchronous FIFO module into the data format of the AXI bus protocol and send it to the read data channel.

[0029] The advantages of the technical solution provided by this application are as follows: By means of a custom interface, the complex AXI interface timing is converted into a custom and simple interface timing, simplifying the complex AXI interface timing, reducing the development difficulty of the system, and improving the system development efficiency of the SOC. During the data preprocessing process between the slave device and the AXI bus it is mounted on by the slave error detection module in the preprocessing component, error detection is performed, so that the working state of the slave device can be detected without relying on the error detection and error response mechanisms of the slave device, enhancing the system reliability and system availability of the entire SOC.

[0030] It should be understood that the above general description and the following detailed description are only exemplary and do not limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present invention or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments or related technologies. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0032] Figure 1 It is a frame structure diagram of a specific implementation manner of the system on chip provided by the embodiment of the present invention;

[0033] Figure 2 It is a frame schematic diagram of an exemplary application scenario provided by the embodiment of the present invention;

[0034] Figure 3 It is a frame structure diagram of a specific implementation manner of the preprocessing component provided by the embodiment of the present invention;

[0035] Figure 4 It is a schematic diagram of the custom write operation timing of an exemplary application scenario provided by the embodiment of the present invention;

[0036] Figure 5 It is a schematic diagram of the custom write operation timing of another exemplary application scenario provided by the embodiment of the present invention;

[0037] Figure 6 It is a schematic diagram of the custom read operation timing of an exemplary application scenario provided by the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0038] To enable those skilled in the art to better understand the solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0039] The terms "first", "second", "third", "fourth", etc. in the description and claims of this application and the above drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may include steps or units that are not listed.

[0040] After introducing the technical solutions of the embodiments of the present invention, the various non-limiting embodiments of this application will be described in detail below.

[0041] First, refer to Figure 1 , Figure 1 which is a schematic diagram of the framework structure of a system-on-chip in an embodiment provided by the embodiments of the present invention. The embodiments of the present invention may include the following content:

[0042] The system-on-chip, i.e., SOC, may include an AXI bus system. That is, the SOC is based on the AXI bus protocol. The AXI bus system may include multiple host devices Master1, multiple slave devices Slave2, a connector Interconnect3, and a preprocessing component PRE4. As Figure 2 shown, the total number of host devices is less than the total number of slave devices, and the number of host devices and the number of slave devices can be flexibly selected according to the actual application scenario. This application does not make any limitation on this. Each slave device is mounted on the AXI bus of the system and performs data communication through the AXI bus. The number of preprocessing components 4 is the same as the number of slave devices 2, and each preprocessing component uniquely corresponds to a slave device; the structures and functions of each preprocessing component 4 are the same, and are used to preprocess the data between the slave device connected thereto and the AXI bus to which it is mounted. One end of the connector 3 is connected to each host device 1, and the other end is connected to each preprocessing component 3.

[0043] In this embodiment, each preprocessing component 4 may include a custom interface, a read / write operation conversion state machine, a write interface, a read interface, an asynchronous fifo module, and a slave error detection module. The AXI protocol is a transmission protocol based on the burst signal, and defines the following five independent transmission channels: a read address channel, a read data channel, a write address channel, a write data channel, and a write response channel. The address channels, i.e., the read address channel and the write address channel, carry control messages for describing the attributes of the data to be transmitted; the data transmission is implemented using the write channel for the transmission from the host device to the slave device, and the slave device uses the write response channel to complete a write transmission; the read channel is used to implement the transmission of data from the slave device to the host device. Based on this, as Figure 3 shown, in the preprocessing component 4, the write interface WR_interface corresponds to the AXI write data channel AXI_WR_DATA, the read interface RD_interface corresponds to the AXI read data channel AXI_RD_DATA, and the custom interface interfac includes a custom write channel LOCAL_WR_DATA and a custom read channel LOCAL_RD_DATA. The AXI read address channel AXI_RD_ADDR and the AXI write address channel AXI_WR_ADDR correspond to the slave error detection module Error_Detect, and the AXI write response channel AXI_WR_RESP corresponds to the write operation state transition machine FMS_WR in the read / write operation conversion state machine. For the custom interface, this embodiment also defines the corresponding interface signals, as shown in Tables 1 and 2. Table 1 is the signal of the local write data end, and Table 2 is the signal of the local read data end.

[0044] Table 1 Signal of the local write data end

[0045]

[0046]

[0047] Table 2 Signal of the local read data end

[0048]

[0049] Among them, the asynchronous fifo module is as Figure 3The async_fifi_pre / sync_fifi_pre in it is used to isolate the write data operation and the read data operation in different clock domains; that is, the read data operation and the write data operation are respectively isolated in different clock domains through an asynchronous fifo (First Input First Output). The read-write operation conversion state machine converts the AXI bus read-write operation timing into a dual-channel read-write data timing, that is, it is used to complete the data interaction and timing conversion between the custom interface and the write interface and the read interface respectively. Since the AXI protocol stipulates that its internal 5 channels (that is, the AXI_WR_RESP write response channel, the AXI_WR_DATA write data channel, the AXI_WR_ADDR write address channel, the AXI_RD_ADDR read address channel, and the AXI_RD_DATA read data channel) are completely independent, the read and write operations can be considered completely independent. Two state machines are used to complete the data interaction and timing conversion during design. That is to say, since there are two types of operations, read and write, correspondingly, the read-write operation conversion state machine can include a write operation conversion state machine FSM_WR and a read operation conversion state machine FSM_RD. The slave error detection module is connected to the read-write operation conversion state machine and is used to detect errors in the write address channel and the read address channel and respond to the error signal. In the AXI protocol, it is stipulated that there are 2-bit, that is, 2-bit response signals, namely RRESP (read response reply signal) and BRESP (write response reply signal). When their values are 2’b10, that is, representing the 2-bit binary numbers 1 and 0, it means that an error has occurred in the slave device. The detection and error response of the slave error are generally generated in the slave device, but in this application, they are calculated in the preprocessing component. The slave error detection module of the preprocessing component solves the drawback of the prior art relying on the fast response of the error signal of the slave device.

[0050] In the technical solution provided by the embodiment of the present invention, through the custom interface, the complex AXI interface timing is converted into a custom simple interface timing, simplifying the complex AXI interface timing, reducing the development difficulty of the system, and improving the system development efficiency of the SOC. Through the slave error detection module, error detection is performed during the data preprocessing process between the slave device and the AXI bus it is mounted on, so that the working state of the slave device can be detected without relying on the error detection and error response mechanism of the slave device, enhancing the system reliability and system availability of the entire SOC.

[0051] The above embodiment does not limit how the slave error detection module detects and responds to errors. This application also provides various error detection methods of the slave error detection module and the corresponding error response methods for each error, which may include the following content:

[0052] Error detection during the process of writing data to the write protection area can be as follows: The slave error detection module can be used to generate an error signal when it is determined that the base address of the write protection area is less than the write address signal of the write address channel and the sum of the base address of the write protection area and the space address of the write protection area is greater than the write address signal. At the same time, the write response signal is set to the slave error identification value, and the write response valid signal is pulled high until the write response ready signal is 1 at the same time.

[0053] In this embodiment, the slave error identification value can be the value defined by the AXI protocol to identify an error occurring in the slave. First, read the base address awprot_base of the write protection area and the space address prot_size_w of the write protection area, and determine whether the write address signal axi_awaddr in the AXI write address channel satisfies awprot_base + prot_size_w > axi_awaddr > awprot_base. If it is satisfied, the address is located in the write protection area at this time, that is, an error occurs during the write operation. At this time, an internal error signal is generated and enters the subsequent error response part. When an error is detected during the write operation, at this time, set axi_bresp (write response signal) = 2'b10, and at the same time pull high axi_bvalid (write response valid signal) until the axi_bready (write response ready signal) signal is 1 at the same time to complete this handshake.

[0054] Error detection during the process of reading data from the read protection area can be as follows: The slave error detection module is used to generate an error signal when it is determined that the base address of the read protection area is less than the read address signal of the read address channel and the sum of the base address of the read protection area and the space address of the read protection area is greater than the read address signal. At the same time, the read response signal is set to the slave error identification value, and the read response valid signal is pulled high until the read response ready signal is 1 at the same time.

[0055] Specifically, first obtain the base address arprot_base of the read protection area and the space address prot_size_r of the read protection area, and determine whether the read address signal axi_araddr in the AXI read address channel satisfies arprot_base + prot_size_r > axi_araddr > arprot_base. If it is satisfied, the address is located in the read protection area at this time, and an error occurs during the read operation. At this time, an internal error signal is generated and enters the subsequent error response part. When an error is detected during the read operation, at this time, set axi_rresp (read response signal) = 2'b10, and at the same time pull high axi_rvalid (read response valid signal) until the axi_rready (read response ready signal) signal is 1 at the same time to complete this handshake.

[0056] In the AXI protocol, it is stipulated that when the burst type is WRAP, the actual burst length must be 2, 4, 8, and 16 at this time. Therefore, the slave error detection module of this preprocessing component for the error detection process of the transmission method can include:

[0057] The slave error detection module is used to determine whether the write burst length is 1, 3, 7, or 15 when the write burst signal of the write address channel is detected as the slave error identification value; if the write burst length is not 1, 3, 7, or 15, the write response signal is set to the slave error identification value, and at the same time, the write response valid signal is pulled high until the write response ready signal is 1 at the same time.

[0058] The slave error detection module is used to determine whether the read burst length is 1, 3, 7, or 15 when the read burst signal of the read address channel is detected as the slave error identification value; if the read burst length is not 1, 3, 7, or 15, the read response signal is set to the slave error identification value, and at the same time, the read response valid signal is pulled high until the read response ready signal is 1 at the same time.

[0059] That is to say, awlen represents the write burst length, arlen represents the read burst length. When axi_awburst in the write address channel is 2’b10, if awlen = 1 or awlen = 3 or awlen = 7 or awlen = 15, the transmission method is correct; otherwise, an internal error signal is generated and enters the subsequent error response part. When axi_arburst in the read address channel is 2’b10, if arlen = 1 or arlen = 3 or arlen = 7 or arlen = 15, the transmission method is correct; otherwise, an internal error signal is generated and enters the subsequent error response part. When an error is detected during a read operation, at this time, axi_rresp (read response signal) = 2’b10, and at the same time, axi_rvalid (read response valid signal) is pulled high until the axi_rready (read response ready signal) is 1 at the same time to complete this handshake. When an error is detected during a write operation, at this time, axi_bresp (write response signal) = 2’b10, and at the same time, axi_bvalid (write response valid signal) is pulled high until the axi_bready (write response ready signal) is 1 at the same time to complete this handshake.

[0060] In order to further improve the reliability and availability of the entire system, based on the above embodiments, the present application also detects the offline state of the slave device, which may include the following content:

[0061] The preprocessing component further includes a slave offline detection module; the slave offline detection module is used to determine whether the corresponding slave device is in an offline state by detecting the handshake time of each handshake signal pair in the custom write channel or the custom read channel.

[0062] In this embodiment, the off-line state of the slave is detected by detecting the handshake time of each handshake signal pair, i.e., the valid signal and the ready signal, in the custom interface channel. The handshake signal pairs in this embodiment may include: l_wr_addr_val and l_wr_addr_rdy, l_wr_val and l_wr_rdy, l_rd_addr_val and l_rd_addr_rdy, l_rd_val and l_rd_rdy. When the rising edge of the valid signal is detected, a new operation is considered to be initiated. At this time, the counter is cleared, i.e., val_cnt = 0; when valid is 1, val_cnt is incremented by one, i.e., val_cnt = val_cnt + 1. When it is detected that val_cnt == TIME_OUT, that is, when the value of this counter is equal to the preset timeout time, it is considered at this time that the slave device is offline, and then the error response step is entered. That is, when an error is detected during a read operation, at this time, axi_rresp (read response signal) = 2'b10, and at the same time, axi_rvalid (read response valid signal) is pulled high until the axi_rready (read response ready signal) signal is 1 at the same time to complete this handshake. When an error is detected during a write operation, at this time, axi_bresp (write response signal) = 2'b10, and at the same time, axi_bvalid (write response valid signal) is pulled high until the axi_bready (write response ready signal) signal is 1 at the same time to complete this handshake. When it is detected that the valid and ready signals are pulled high at the same time, the counter is cleared at this time, val_cnt == 0.

[0063] The above embodiment does not make any limitation on how the read / write operation conversion state machine completes data interaction and conversion timing. This application also provides an alternative implementation, which may include the following contents:

[0064] The read / write operation conversion state machine may include a write operation conversion state machine and a read operation conversion state machine.

[0065] The write operation conversion state machine is used to convert the write timing corresponding to the write address channel and the write data channel into the write data timing that meets the custom interface, and send the address and data after the timing conversion to the custom write channel. The write operation conversion state machine completes the conversion of the write data timing, converts the complex AXI write timing into a simple custom interface specification, and supports two data timings at the same time, specifically as follows:

[0066] As an alternative implementation, as shown in the appendix Figure 4As shown in the figure, the write operation conversion state machine is further used for: when the custom write data valid signal and the custom write data ready signal are both pulled high and the handshake is successful, writing data to the subsequent module, and at the same time, the subsequent module replies with corresponding signals to the current write operation. In this embodiment, when l_wr_vld and l_wr_rdy are both pulled high and the handshake is successful, data can be written to the subsequent stage. Among them, each group of data corresponds to a write address, l_wr_be is the data valid flag, and at the same time, the subsequent module needs to reply with a response signal to this write operation. This interface timing is beneficial to the write operation of a single piece of data and is applicable to slave devices such as configuration registers, write RAM (Random Access Memory), and FIFO similar interfaces. The implementation steps are as follows:

[0067] A1: Receive data from the AXI write address channel: When the write address valid signal axi_aw_valid is 1, cache the write address axi_awaddr, write burst length axi_awlen, write burst type axi_awburst, and write data byte enable axi_ws_trb.

[0068] A2: Receive write data: When the write data valid axi_wv_alid signal is 1, write the write data axi_w_data into the data fifo.

[0069] A3: Calculate the address corresponding to each piece of data: There are 3 different burst modes specified in the AXI protocol, and the corresponding address calculations are as follows:

[0070] FIXED (fixed address): l_wr_addr = axi_awaddr

[0071] In this mode, each custom interface write address signal is the same as the AXI write address

[0072] INCR (incremental): l_wr_addr = axi_awaddr + add_addr

[0073] The initial address of the custom interface write address signal is the same as the AXI address, and subsequent addresses need to be incremented based on the initial address, with the increment amplitude being the same as the transfer width

[0074] WRAP (Wrap-Around Incremental): First, calculate the wrap-around width according to the actual burst length and burst data width of AXI: wrap_size = burst_len * burst_size, where Wrap_size is the wrap-around width, Burst_len is the actual burst length, and Burst_size is the data size per burst, with the unit of Byte. Second, calculate the lower wrap boundary (low wrap boundary): Temp0 = axi_awaddr / wrap_size, taking only the integer part. Temp0 represents an intermediate variable in the calculation process, and axi_awaddr represents the AXI write address. low wrap boundary = Temp0 * wrap_size. Third, calculate the upper wrap boundary high wrap boundary, high wrap boundary = low wrap boundary + wrap_size. Finally, calculate the address corresponding to each data: when the current address is less than the upper wrap boundary, the WRAP type is exactly the same as the INCR type, and the address increments. However, when the incremented address reaches the highest address, the address directly returns to the lower wrap boundary address and then increments again, repeating this cycle.

[0075] A4: Send the address and data to the custom write data terminal: Read the write data from the data fifo and give it to the l_wr_data data line. At the same time, give the corresponding address calculated in the previous step to l_wr_addr. When the handshake between l_wr_vld and l_wr_rdy is successful, send the next set of data.

[0076] As another alternative implementation, the write operation conversion state machine can further be used to: when a write operation is detected, send a write instruction carrying the write address, the occupied space capacity value of the write data, and the instruction valid flag; when the write instruction is successfully sent, send a data enable signal and the data to be written.

[0077] As shown in the Figure 5 appendix, the second custom write operation timing sequence is as follows. Before writing data, a set of write instructions needs to be sent, including the write address, the write data size, and the instruction valid flag. Then, immediately send the data and the data enable signal. This method is beneficial for the continuous writing process of multiple data, such as in the flash memory flash, PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard), and Gigabit Media Independent Interface GMII packet transmission processes.

[0078] B1: Receive data from the AXI write address channel: When the write address valid signal axi_aw_valid is 1, cache the write address axi_awaddr, write burst length axi_awlen, write burst type axi_awburst, and write data byte enable axi_ws_trb.

[0079] B2: Receive write data: When the write data valid axi_wv_alid signal is 1, write the write data axi_w_data into the data fifo.

[0080] B3: Convert the axi_awaddr and write burst length axi_awlen cached in step B1 into custom write operation signals according to the following relationships:

[0081] l_wr_addr = axi_awaddr;

[0082] l_wr_length = axi_awlen + 1;

[0083] At the same time, set the l_wr_addr_val signal to 1 and wait for the l_wr_addr_rdy signal to be pulled high to complete the handshake.

[0084] B4: Send data to the custom write data terminal: Read the write data from the data fifo and give it to the l_wr_data data line, and send the next set of data after the l_wr_vld and l_wr_rdy complete the handshake successfully.

[0085] As Figure 6 shown, for the read operation conversion state machine to complete the data interaction and timing conversion process can be: The read operation conversion state machine can be used to: When the read address valid signal is 1, store multiple types of data read from the read address channel, and convert the target type of data into a signal of the custom write timing; Pull high the custom read data instruction valid signal, and at the same time wait for the custom read data instruction ready signal to be pulled high to complete the handshake; When the custom read data valid signal is valid, pull high the custom read data ready signal, and store the returned data into the asynchronous fifo module; Convert the returned data read from the asynchronous fifo module into the data format of the AXI bus protocol and send it to the read data channel. The following uses a schematic example to illustrate the implementation manner of the above technical solution:

[0086] C1: Receive data from the AXI read address channel: When the read address valid signal axi_arvalid is 1, cache the read address axi_araddr, read burst length axi_arlen, read burst type axi_arburst, and read ID axi_arid.

[0087] C2: Convert the read address, read data length, and read ID of AXI cached in the previous step into signals with a custom write timing according to the following relationship:

[0088] l_rd_addr = axi_araddr;

[0089] l_rd_addr = axi_arlen + 1;

[0090] l_id = axi_arid.

[0091] C3: Pull up the l_rd_addr_vld signal and wait for the l_rd_addr_rdy signal to be pulled up to complete the handshake.

[0092] C4: When l_rd_vld is valid, it indicates that the returned read data is obtained. At this time, pull up l_rd_rdy and store the returned data in the returned data fifo.

[0093] C5: Read the data in the returned data fifo and convert it into the data format of AXI and send it to the read data channel of the AXI bus.

[0094] The preprocessing component mentioned above is described from the perspective of a functional module. Further, the present application also provides an electronic device, which is described from the perspective of hardware. The electronic device includes a memory for storing a computer program; a processor for implementing the steps of the on-chip system method as mentioned in any of the above embodiments when executing the computer program.

[0095] Among them, the processor may include one or more processing cores, such as a 4-core processor or an 8-core processor. The processor may also be a controller, a microcontroller, a microprocessor, or other data processing chips, etc. The processor may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), or PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is a processor used to process data in the wake state, also known as the CPU (Central Processing Unit); the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor may also include an AI (Artificial Intelligence) processor, and the AI processor is used to process computational operations related to machine learning.

[0096] The memory may include one or more computer-readable storage media, which may be non-transitory. The memory may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash storage devices. In some embodiments, the memory may be an internal storage unit of an electronic device, such as the hard disk of a server. In other embodiments, the memory may also be an external storage device of an electronic device, such as a plug-in hard disk equipped on a server, a Smart Media Card (SMC), a Secure Digital (SD) card, a Flash Card, etc. Further, the memory may include both an internal storage unit and an external storage device of the electronic device. The memory can be used not only to store application software installed in the electronic device and various types of data, such as the code of a program for executing a data preprocessing method, etc., but also to temporarily store data that has been output or will be output. In this embodiment, the memory is at least used to store the following computer program, wherein after the computer program is loaded and executed by the processor, it can implement the relevant steps of data preprocessing between each slave device disclosed in any of the foregoing embodiments and the AXI bus to which it is mounted. In addition, the resources stored in the memory may also include an operating system and data, etc., and the storage method may be transient storage or permanent storage. Among them, the operating system may include Windows, Unix, Linux, etc. The data may include, but is not limited to, data corresponding to the data preprocessing results between the slave device and the AXI bus to which it is mounted.

[0097] In some embodiments, the above-mentioned electronic device may further include a display screen, an input / output interface, a communication interface or a network interface, a power supply, and a communication bus. Among them, the display screen and the input / output interface such as a keyboard belong to user interfaces. Optional user interfaces may also include standard wired interfaces, wireless interfaces, etc. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch liquid crystal display, and an OLED (Organic Light-Emitting Diode) toucher, etc. The display may also be appropriately referred to as a display screen or a display unit, which is used to display the information processed in the electronic device and to display a visual user interface. The communication interface may optionally include a wired interface and / or a wireless interface, such as a WI-FI interface, a Bluetooth interface, etc., which are generally used to establish a communication connection between the electronic device and other electronic devices. The communication bus may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. This bus may be divided into an address bus, a data bus, a control bus, etc.

[0098] It can be understood that if the data preprocessing method between each slave device and the AXI bus it is mounted on in the above-mentioned embodiments is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the preprocessing component of the present application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods in the various embodiments of the present application. The aforementioned storage medium includes: USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), electrically erasable programmable ROMs, registers, hard disks, multimedia cards, card-type memories (such as SD or DX memories, etc.), magnetic memories, removable disks, CD-ROMs, magnetic disks, or optical disks, etc., which are various media that can store program codes.

[0099] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other.

[0100] Those skilled in the art may further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0101] The above has introduced in detail a system on a chip provided by the present application. Specific examples are used herein to elaborate on the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A system on chip, comprising an AXI bus system, the AXI bus system including a plurality of host devices, a plurality of slave devices and a connector, characterized in that, It also includes multiple preprocessing components with the same structure, and each preprocessing component uniquely corresponds to a slave device; one end of the connector is connected to each host device, and the other end is connected to each preprocessing component; The preprocessing component includes a custom interface, a read-write operation conversion state machine, a write interface, a read interface, an asynchronous fifo module, and a slave error detection module; the custom interface includes a custom write channel and a custom read channel, the write interface corresponds to a write data channel, and the read interface corresponds to a read data channel; The slave error detection module is connected to the read-write operation conversion state machine; The read-write operation conversion state machine is used to complete the data interaction and timing conversion between the custom interface and the write interface and the read interface respectively; The asynchronous fifo module is used to isolate the write data operation and the read data operation in different clock domains; The slave error detection module is used to detect errors in the write address channel and the read address channel and respond to error signals.

2. The system on chip according to claim 1, wherein The slave error detection module is used to generate an error signal when it is determined that the base address of the write protection area is less than the write address signal of the write address channel and the sum of the base address of the write protection area and the spatial address of the write protection area is greater than the write address signal, set the write response signal to the slave error identification value, and at the same time raise the write response valid signal until the write response ready signal is 1 at the same time.

3. The system on chip according to claim 1, wherein The slave error detection module is used to generate an error signal when it is determined that the base address of the read protection area is less than the read address signal of the read address channel and the sum of the base address of the read protection area and the spatial address of the read protection area is greater than the read address signal, set the read response signal to the slave error identification value, and at the same time raise the read response valid signal until the read response ready signal is 1 at the same time.

4. The system on chip according to claim 1, characterized in that, The slave error detection module is used to judge whether the write burst length is 1 or 3 or 7 or 15 when the write burst signal of the write address channel is detected as the slave error identification value; If the write burst length is not 1 or 3 or 7 or 15, the write response signal is set to the slave error identification value, and at the same time the write response valid signal is raised until the write response ready signal is 1 at the same time.

5. The system on chip according to claim 1, wherein The slave error detection module is used to judge whether the read burst length is 1 or 3 or 7 or 15 when the read burst signal of the read address channel is detected as the slave error identification value; If the read burst length is not 1 or 3 or 7 or 15, the read response signal is set to the slave error identification value, and at the same time the read response valid signal is raised until the read response ready signal is 1 at the same time.

6. The system on chip according to claim 1, characterized in that The preprocessing component further includes a slave offline detection module; The slave offline detection module is used to judge whether the corresponding slave device is in an offline state by detecting the handshake time of the handshake signal pair each time in the custom write channel or the custom read channel.

7. The system on chip according to any one of claims 1 to 6, characterized in that, The read-write operation conversion state machine includes a write operation conversion state machine; The write operation conversion state machine is used to convert the write timing corresponding to the write address channel and the write data channel into the write data timing satisfying the custom interface, and send the address and data after the timing conversion to the custom write channel.

8. The system on chip according to claim 7, wherein The write operation conversion state machine is further configured to: when the custom write data valid signal and the custom write data ready signal are both pulled high for a successful handshake, write data to the subsequent module, and at the same time, the subsequent module replies with corresponding signals to the current write operation.

9. The system-on-chip according to claim 7, characterized in that, The write operation conversion state machine is further configured to: when a write operation is detected, send a write instruction carrying a write address, a write data occupied space capacity value, and an instruction valid flag; when the write instruction is successfully sent, send a data enable signal and the data to be written.

10. The system on chip according to any one of claims 1 to 6, characterized in that The read / write operation conversion state machine includes a read operation conversion state machine; The read operation conversion state machine is used for: When the read address valid signal is 1, store multiple types of data read from the read address channel, and convert the data of the target type into a signal with a custom write timing; Pull high the custom read data instruction valid signal, and at the same time wait for the custom read data instruction ready signal to also be pulled high to complete the handshake; When the custom read data valid signal is valid, pull high the custom read data ready signal, and store the returned data into the asynchronous FIFO module; Convert the returned data read from the asynchronous FIFO module into the data format of the AXI bus protocol, and send it to the read data channel.

Images