Apparatus and method for cyclic redundancy calculation for semiconductor devices

Abstract

The present disclosure relates to apparatuses and methods for cyclic redundancy computation for semiconductor devices. Apparatuses and methods for data error checking for semiconductor devices are described. An example apparatus includes a plurality of data queue circuits and a CRC combination circuit. The plurality of data queue circuits includes a plurality of CRC calculator circuits. The plurality of CRC calculator circuits includes one CRC calculator circuit. The CRC calculator circuit receives a plurality of data bits and one or more check bits, and further provides a plurality of CRC calculated bits. The CRC combination circuit receives the plurality of CRC calculated bits from the plurality of CRC calculator circuits, and further provides a result signal responsive, at least in part, to the plurality of CRC calculated bits.

Description

Technical Field

[0001] This disclosure relates to apparatus and methods for cyclic redundancy calculation of semiconductor devices. Background Technology

[0002] Semiconductor memories require high data reliability, high-speed memory access, low power consumption, and reduced chip size. To increase data capacity, multiple memory cell arrays with multiple memory banks have been employed. Typically, each data bus of a specific memory bank group is adjacent to the data buses of other memory bank groups. However, to prevent noise on the data buses, the data buses of memory bank groups are spaced apart, or shielding lines are placed between the data buses. Additionally, Cyclic Redundancy Check (CRC) is used in semiconductor devices to detect unexpected data changes. The CRC calculator receives data input from the data queue (DQ) and CRC bits and uses the CRC bits to determine the accuracy of the data. The CRC bits are transmitted on additional signal lines on the data bus. Transmitting the CRC bits requires additional data bus area due to the additional signal lines used for the CRC bits, and the data buses need to be spaced apart.

[0003] In recent years, three-dimensional (3D) memory devices have been introduced. Some 3D memory devices are formed by vertically stacking dies and interconnecting them using through-silicon (or through-substrate) vias (TSVs). The benefits of 3D memory devices include shorter interconnects that reduce circuit latency and power consumption, several vertical vias that allow wide-bandwidth buses between functional blocks in different layers, and a relatively small footprint. Therefore, 3D memory devices contribute to higher memory access speeds, lower power consumption, and smaller chip size. Indicative 3D memory devices include Hybrid Memory Cubes (HMCs) and High Bandwidth Memory (HBMs). Another type of 3D memory device is called "master-slave memory." For example, master-slave memory is a type of memory that includes multiple random access memory (DRAM) dies stacked vertically on top of each other, where the bottommost DRAM die acts as the master die, and one or more of the remaining DRAM dies act as slave dies.

[0004] Recently, many memory devices have supported CRC checksum functionality for error detection. When CRC error detection is implemented in such devices, the main die and the slave die perform CRC calculations. Numerous TSVs between layers further contain a large number of TSVs for transmitting CRC bits, as well as a large number of data bits. These TSVs occupy additional area on each die. Summary of the Invention

[0005] On one hand, this disclosure provides an apparatus comprising: a data queue circuit, the data queue circuit including: a sampler configured to receive a plurality of data bits and one or more check bits, and further configured to provide the plurality of data bits and the one or more check bits based on an internal clock; and a cyclic redundancy check (CRC) calculator circuit configured to receive the plurality of data bits and the one or more check bits and further configured to provide a plurality of CRC calculation bits.

[0006] On the other hand, this disclosure provides an apparatus comprising: a plurality of data queue circuits, each of the plurality of data queue circuits including a corresponding CRC calculator circuit among the cyclic redundancy check (CRC) calculator circuits, each corresponding CRC calculator circuit being configured to receive a plurality of data bits and one or more check bits and further configured to provide a plurality of CRC calculation bits based on at least a portion of the plurality of data bits; and a CRC combination circuit being configured to receive the plurality of CRC calculation bits from each of the plurality of CRC calculator circuits and further configured to provide a result signal at least partially in response to the plurality of CRC calculation bits.

[0007] In another aspect, this disclosure provides an apparatus comprising: a first die including: a plurality of first memory cells; a plurality of data queue circuits including a plurality of CRC calculator circuits, wherein each of the plurality of CRC calculator circuits in each of the plurality of data queue circuits is configured to receive a corresponding plurality of data bits and one or more corresponding check bits, and is further configured to provide a corresponding plurality of CRC calculation bits; a CRC combination circuit configured to receive the corresponding plurality of CRC calculation bits from the plurality of CRC calculator circuits, and is further configured to provide a result signal at least partially in response to the corresponding plurality of CRC calculation bits from the plurality of CRC calculator circuits; and a second die stacked with the first die, the second die including a plurality of second memory cells. Attached Figure Description

[0008] Figure 1 This is a block diagram of an apparatus according to an embodiment of the present disclosure.

[0009] Figure 2A This is a schematic diagram of a memory device according to an embodiment of the present disclosure.

[0010] Figure 2B This is a schematic diagram of a portion of a memory device according to an embodiment of the present disclosure.

[0011] Figure 2C This is a schematic diagram of a portion of a central region in a memory device according to an embodiment of the present disclosure.

[0012] Figure 3 This is a block diagram of an apparatus according to an embodiment of the present disclosure.

[0013] Figure 4 This is a schematic diagram of a device according to an embodiment of the present disclosure.

[0014] Figure 5A This is a table of CRC data bit mappings for a device comprising eight DQ circuits and one DM circuit according to embodiments of the present disclosure.

[0015] Figure 5B It is for calculating according to embodiments of the present disclosure Figure 5A A list of equations for each of the multiple CRC bits in the equation.

[0016] Figure 5C This is a schematic diagram illustrating the decomposition of a calculation associated with a CRC checksum bit into eight DQ circuits and the DM circuit according to an embodiment of the present disclosure.

[0017] Figure 6 According to embodiments of this disclosure Figure 4 A schematic diagram of the logic calculation process in the device.

[0018] Figure 7 This is a block diagram of an apparatus according to an embodiment of the present disclosure.

[0019] Figure 8 This is a schematic diagram of a memory device comprising a plurality of dies according to an embodiment of the present disclosure.

[0020] Figure 9 This is a block diagram of an apparatus according to an embodiment of the present disclosure. Detailed Implementation

[0021] Various embodiments of the present disclosure will now be explained in detail with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which illustratively illustrate specific aspects and details in which embodiments of the present disclosure may be practiced. This detailed description contains sufficient detail to enable those skilled in the art to practice the embodiments of the present disclosure. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0022] Figure 1This is a schematic block diagram of a semiconductor device 100 according to an embodiment of the present disclosure. The semiconductor device 100 may include a clock input circuit 105, an internal clock generator 107, an address command input circuit 115, an address decoder 120, a command decoder 125, multiple row (e.g., first access line) decoders 130, a memory cell array 145 including a sense amplifier 150 and a transmission gate 195, multiple column (e.g., second access line) decoders 140, multiple read / write amplifiers 165, input / output (I / O) circuitry 170, and a voltage generator 190. The semiconductor device 100 may include multiple external terminals, including address and command terminals coupled to a command / address bus 110, clock terminals CK_t and CK_c, data terminals DQ171, DQS, and DM172, and power supply terminals VDD, VSS, VDDQ, and VSSQ. In some instances, the terminals and signal lines associated with the command / address bus 110 may include a first set of terminals and signal lines configured to receive command signals and a separate second set of terminals and signal lines configured to receive address signals. In other instances, the terminals and signal lines associated with the command and address bus 110 may include shared terminals and signal lines configured to receive both command signals and address signals. The semiconductor device may be mounted on a substrate, for example, on a memory module substrate, motherboard, etc.

[0023] The memory cell array 145 includes multiple memory banks BANK0-N, where N is a positive integer, such as 3, 7, 15, 31, etc. Each memory bank BANK0-N may include multiple word lines WL, multiple digital lines DL and their complementary digital lines DLb, and multiple memory cells MC arranged at the intersections of the multiple word lines WL and the multiple digital lines DL. The selection of the word lines WL for each memory bank BANK0-N is performed by the corresponding row decoder 130, while the selection of the digital lines DL is performed by the corresponding column decoder 140. Multiple sense amplifiers 150 are positioned for their corresponding digital lines DL and their corresponding complementary digital lines DLb, and are coupled to at least one corresponding local I / O line via a transmission gate TG 195, which is further coupled to a corresponding one of at least two main I / O line pairs, the transmission gate TG acting as a switch. The sensing amplifier 150 and the transmission gate TG 195 can operate based on control signals from the decoder circuit, which may include any control circuitry of the command decoder 120, row decoder 130, column decoder 140, memory cell array 145 of memory banks BANK0-N, or any combination thereof.

[0024] Address / command input circuit 115 can receive address signals and memory address signals from the outside via command / address bus 110 at the command / address terminal, and transmit the address signals and memory address signals to address decoder 120. Address decoder 120 can decode the address signals received from address / command input circuit 115, and provide row address signal XADD to row decoder 130 and column address signal YADD to column decoder 140. Address decoder 120 can also receive memory address signals and provide memory address signal BADD to row decoder 130 and column decoder 140.

[0025] Address / command input circuitry 115 can receive command signals from external sources (such as a memory controller, for example, at a command / address terminal) via command / address bus 110 and provide the command signals to command decoder 125. Command decoder 125 can decode the command signals and generate various internal command signals. Internal command signals can be used to control the operation and timing of various circuits in semiconductor device 100. For example, internal command signals can include row and column command signals to control circuitry to perform access operations on selected word lines and digital lines, such as read or write commands.

[0026] In response to activation and read commands provided along with row and column addresses, read data is read from the memory cell array 145 specified by the row and column addresses. Read / write amplifier 165 can receive read data DQ and provide it to I / O circuit 170. I / O circuit 170 can provide read data DQ, along with a data strobe signal at DQS and a signal at DM, to the outside via data terminals DQ, DQS, and DM. Similarly, when activation and write commands are provided, along with row and column addresses, input / output circuit 170 can receive write data at data terminals DQ, DQS, and DM, along with a data strobe signal at DQS and a data mask signal at DM, and provide the write data to memory cell array 145 via read / write amplifier 165. Therefore, write data can be written to the memory cell specified by the row and column addresses. I / O circuit 170 can be coupled to multiple CRC combination circuits 170. Multiple CRC combination circuits 170 and multiple CRC calculator circuits included in IO circuit 170 can perform CRC calculations together for data error checking.

[0027] Turning to the explanation of the external terminals included in the semiconductor device 100, the clock terminals CK_t and CK_c can receive an external clock signal and a complementary external clock signal, respectively. The external clock signal (including the complementary external clock signal) can be supplied to the clock input circuit 105. The clock input circuit 105 can receive the external clock signal and generate an internal clock signal ICLK. The clock input circuit 105 can provide the internal clock signal ICLK to the internal clock generator 107. The internal clock generator 107 can generate a phase-controlled internal clock signal LCLK based on the internal clock signal ICLK received from the address / command input circuit 115 and the clock enable signal CKE. Although not limited thereto, a DLL circuit can be used as the internal clock generator 107. The internal clock generator 107 can provide the phase-controlled internal clock signal LCLK to the IO circuit 170 and the timing generator 109. The IO circuit 170 can use the phase controller internal clock signal LCLK as a timing signal for determining the output timing of read data. The timing generator 109 can receive the internal clock signal ICLK and generate various internal clock signals.

[0028] The power supply terminals can receive power supply voltages VDD and VSS. These power supply voltages VDD and VSS can be supplied to voltage generator circuit 190. Voltage generator circuit 190 can generate various internal voltages VPP, VOD, VARY, VPERI, etc., based on the power supply voltages VDD and VSS. Internal voltage VPP is mainly used in line decoder 130, internal voltages VOD and VARY are mainly used in sense amplifier 150 contained in memory cell array 145, and internal voltage VPERI is used in many other circuit blocks. I / O circuit 170 can receive power supply voltages at power supply terminals VDDQ and VSSQ. For example, the power supply voltages can be the same as the power supply voltages VDD and VSS, respectively. However, dedicated power supply voltages from power supply terminals VDDQ and VSSQ can be used for I / O circuit 170.

[0029] Figure 2A This is a schematic diagram of a memory device 20 according to an embodiment of the present disclosure. For example, the memory device 20 may be... Figure 1 Device 100. Memory device 20 may be a memory die, such as a DRAM die. Memory device 20 may include multiple memory bank groups BG0 to BG3 21. The multiple memory bank groups BG0 to BG3 may include Figure 1The memory device 20 comprises multiple memory banks BANKS-N in the memory cell array 145. Each of the multiple memory bank groups BG0 to BG3 can be divided into two regions. The memory device 20 may also include a central region 22, which spans the multiple memory bank groups BG0 to BG3 and is disposed between the two regions of each memory bank group. The memory device 20 may further include a first plurality of data queue (DQ) circuits 23a and a second plurality of DQ circuits 23b disposed in the central region 22. For example, the first plurality of data queue (DQ) circuits 23a and the second plurality of DQ circuits 23b may be in I / O circuit 170. For example, the first plurality of DQ circuits 23a may receive and transmit lower data bits, while the second plurality of DQ circuits may receive and transmit higher data bits. The memory device 20 may further include CRC combination circuits 24a and 24b disposed in the central region 22. For example, CRC circuit 24a can receive the CRC calculation bits of each DQ circuit of the first plurality of DQ circuits 23a, while CRC circuit 24b can receive the CRC calculation bits of each DQ circuit of the first plurality of DQ circuits 23b.

[0030] The memory device 20 may include a portion 20' that includes two regions of the memory bank group BG1 and a portion of the central region 22. Figure 2BThis is a schematic diagram of a portion 20' of a memory device 20 according to an embodiment of the present disclosure. Portion 20' may include memory bank groups BG1 21 divided into two regions across a central region 22. Portion 20' may further include a first plurality of data queue (DQ) circuitry 23a and CRC combination circuitry 24a shared across multiple memory bank groups BG0 to BG3. The top region of the two regions may include arrays 210 and 211, while the bottom region of the two regions may include arrays 212 and 213. The top region may also include data sense amplifiers 250 and 251 and row decoders 260 and 261, which may be provided for arrays 210 and 211, respectively. The bottom region may also include data sense amplifiers 252 and 253 and row decoders 262 and 263, which may be provided for arrays 212 and 213, respectively. The memory device 20 may include a first plurality of DQ circuits 23a, which include DQ circuits DQ0 230 to DQ7 237 and a data mask (DM) circuit 238 disposed in the central region 22. The memory device 20 may also include a CRC combining circuit 24a disposed in the central region 22. The CRC combining circuit 24a may receive CRC calculation bits from the DQ circuits DQ0 230 to DQ7 237 and the DM circuit 238. The memory device 20 may include a global read / write data bus and buffer (global RWDB) 270 disposed in the central region 22. For example, the global RWDB 270 may be disposed between the I / O circuit 170 and the RWAMP 165.

[0031] Figure 2C This is a schematic diagram of a portion of the central region 270 in a memory device 20 according to an embodiment of the present disclosure. Figure 2C As shown, each of the DQ circuits DQ0 230 to DQ7 237 and DM circuit 238 provides data to multiple memory bank groups BG0 to BG3 on a global read / write data bus (line) dedicated to each circuit. Therefore, DQ circuits DQ2 232 and DQ3 233 do not share data. Figure 2C The global read / write data bus is used. Similarly, DQ circuits DQ0 230 to DQ7 237 and DM circuit 238 do not share the global read / write data bus with another DQ circuit among the multiple DQ circuits 230 to 237. Figure 2C The diagram shows the global read / write data bus for DQ2 and DQ3. However, the central region 270 further includes additional read / write data buses for each of the other DQ circuits DQ0, DQ1, DQ4 through DQ7, and the DM circuit.

[0032] Figure 3This is a block diagram of device 30 according to an embodiment of the present disclosure. Device 30 may be included in memory device 20. Device 30 may include DQ circuit 33 and CRC combination circuit 34. In some embodiments of the present disclosure, DQ circuit 33 may be... Figures 2A to 2C The DQ circuits DQ0 230 to DQ7 237 and DM circuit 238 can be used, while the CRC combination circuit 34 can be... Figures 2A to 2B The CRC combination circuits 24a and 24b are used. The DQ circuit 33 may include a DQ buffer 331 that can receive multiple bits from the data terminal 31. For example, the data terminal 31 may be either the data terminals DQ 171 and DM 172. The multiple bits include multiple data bits constituting an 8-bit data byte [7:0] and one or more CRC check bits. For example, one or more CRC bits may be provided by a memory controller (not shown). The number of CRC check bits for each data byte depends on the data structure, which will be discussed later. Figure 5A and 5B Provide its details. For example... Figure 3As shown in the example, the number of data bits is 8, while the number of CRC check bits is 1 or 2. The number of data bits and the number of CRC check bits can depend on the data size and the required accuracy. The multiple bits received at buffer 331 can be captured by sampler 332. Sampler 332 can provide multiple data bits to global data bus 37 at timings based on an internal clock (e.g., a local clock LCLK or DQS clock). Global data bus 37 can be, for example, a global read / write data bus dedicated to DQ circuitry 33 in global RWDB 270. Sampler 332 can further provide multiple data bits and one or two CRC check bits to CRC calculator circuitry 333. CRC calculator circuitry 333 can include a combination of logic XOR circuitry. CRC calculator circuitry 333 can provide multiple CRC calculation bits. The multiple CRC calculation bits are the result of a CRC calculation, which can be based on at least a portion of the multiple data bits and one or two CRC check bits. In this example, the number of CRC calculation bits is 8. The CRC calculator circuit 333 provides CRC calculation bits to the CRC combination circuit 34. For example, in some embodiments of this disclosure, the device 30 may include a signal line 36, one end of which is coupled to the CRC calculator circuit 333 and the other end to the CRC combination circuit 34. The CRC calculator circuit 333 provides CRC calculation bits to the CRC combination circuit 34 on the signal line 36, which is separate from the global data bus 37. By providing the CRC calculation bits on the signal line 36, which is separate from the global data bus 37, the global data bus 37 can use less layout space compared to an arrangement in which the CRC bits are provided via the global data bus. The CRC combination circuit 34 may be coupled to the CRC calculator circuit 333 and may receive eight CRC calculation bits from the CRC calculator circuit 333 on the signal line 36. Similarly, the CRC combination circuit 34 may receive eight CRC calculation bits from other circuits among a plurality of DQ circuits and DM circuits (e.g., seven DQ circuits and one DM circuit). Therefore, the CRC combination circuit 34 can receive a total of 72 CRC calculation bits (e.g., (8 DQ circuits × 8 CRC calculation bits per DQ circuit) + (1 DM circuit × 8 CRC calculation bits per DM circuit) = 64 CRC calculation bits + 8 CRC calculation bits) and provide a CRC result signal CRCerr, which is a binary signal indicating whether the data bits containing multiple data bits contain any errors.

[0033] Figure 4This is a schematic diagram of device 40 according to an embodiment of the present disclosure. Device 40 may be included in memory device 20. Device 40 may include a plurality of DQ circuits DQ0 430 to DQ7 437, DM circuit 438, and CRC combination circuit 44. In some embodiments of the present disclosure, DQ circuits DQ0 430 to DQ7 437 and DM circuit 438 may be included in Figures 2A to 2C The DQ circuits DQ0230 to DQ7237 and DM circuit 238 are included, and the CRC combination circuit 44 can be used as... Figures 2A to 2B Either of the CRC combination circuits 24a and 24b. In some embodiments of this disclosure, the DQ circuits DQ0 430 to DQ7 437 and the DM circuit 438 may have the structure of the DQ circuit 33.

[0034] The CRC combination circuit 44 may include multiple logic XOR circuits 440 to 447 and a logic OR circuit 448. Each logic XOR circuit performs a logic XOR operation on eight bits received from each of the two DQ circuits and provides eight bits. For example, logic XOR circuit 440 may receive eight CRC calculated bits from DQ circuit DQ0 430 and DQ circuit DQ1 430, and provide eight intermediate CRC calculated bits to another logic XOR circuit 441. Logic XOR circuit 441 may receive eight intermediate CRC calculated bits from logic XOR circuit 441 and DQ circuit 438, and provide eight intermediate CRC calculated bits to another logic XOR circuit 443. Logic XOR circuit 442 may receive eight CRC calculated bits from each of DQ circuits DQ2 432 and DQ3 433, and provide eight intermediate CRC calculated bits to logic XOR circuit 443. Logic XOR circuit 443 can receive intermediate CRC calculation bits from each of logic XOR circuits 441 and 442, and provide eight intermediate CRC calculation bits to logic OR circuit 447. Logic XOR circuit 444 can receive eight CRC calculation bits from each of DQ circuits DQ4 434 and DQ5 435, and provide eight intermediate CRC calculation bits to another logic XOR circuit 446. Logic XOR circuit 445 can receive eight CRC calculation bits from each of DQ circuits DQ6 436 and DQ7 437, and provide eight intermediate CRC calculation bits to another logic XOR circuit 446. Logic XOR circuit 446 can receive intermediate CRC calculation bits from both logic XOR circuits 444 and 445, and provide eight intermediate CRC calculation bits to logic NOR circuit 447. Logic NOR circuit 447 can receive intermediate CRC calculation bits from both logic XOR circuits 443 and 446, and provide eight intermediate CRC calculation bits to logic OR circuit 448. The logic OR circuit 448 can perform a logical OR operation on all eight intermediate CRC calculation bits and provide a CRC result signal CRCerr, which is a binary signal indicating whether the data contains any errors.

[0035] Figure 5A This is a table of CRC data bit mappings for a device comprising eight DQ circuits and one DM circuit according to embodiments of the present disclosure. The eight DQ circuits and the DM circuit can receive nine bits, comprising eight data bits and one CRC bit. For example, in this table, the DQ0 circuit can receive data bits d0 to d7 (D[0] to D[7]) and a checksum bit CRC0. Figure 5B It is for calculating according to embodiments of the present disclosure Figure 5AA list of equations for each CRC bit in the multiple CRC bits. The multiple equations provide multiple results of multiple XOR operations on corresponding combinations of data bits obtained from corresponding data bytes from corresponding circuits in the DQ and DM circuits. Figure 5C This is a schematic diagram illustrating the decomposition of a calculation associated with a CRC checksum bit into eight DQ circuits and the DM circuit according to an embodiment of the present disclosure. For example, regarding Figure 5B The equation for CRC[0] in the equation can perform an XOR operation on the data bits D

[69] , D

[68] , D

[67] , D

[66] , D

[64] , D

[63] , D

[60] , D

[56] , D

[54] , D

[53] , D

[52] , D

[50] , D

[49] , D

[48] , D

[45] , D

[43] , D

[40] , D

[39] , D

[35] , D

[34] , D

[31] , D

[30] , D

[28] , D

[23] , D

[21] , D

[19] , D

[18] , D

[16] , D

[14] , D

[12] , D[8], D[7], D[6] and D[0]. The equation for calculating CRC[0] can be decomposed into a calculation of groups of data bits received in the DQ and DM circuits, and each circuit in the DQ and DM circuits can calculate intermediate CRC bits based on corresponding groups of data bits that are subsets of the data bits received by each circuit. In some embodiments, the calculation of intermediate CRC bits can be an XOR operation performed on corresponding groups of data bits. For example, the above data bits of CRC[0] can be divided into a set of data bits D

[69] , D

[68] , D

[67] , D

[66] and D

[64] that can be received and calculated in the DM circuit, a set of data bits D

[63] , D

[60] and D

[56] that can be received and calculated in the DQ7 circuit, a set of data bits D

[54] , D

[53] , D

[52] , D

[50] , D

[49] and D

[48] that can be received and calculated in the DQ6 circuit, a set of data bits D

[45] , D

[43] and D

[40] that can be received and calculated in the DQ5 circuit, and a set of data bits D

[45] , D

[43] and D

[40] that can be received and calculated in the DQ5 circuit. The DQ4 circuit receives and calculates a set of data bits D

[39] , D

[35] and D

[34] , the DQ3 circuit receives and calculates a set of data bits D

[31] , D

[30] , D

[28] , the DQ2 circuit receives and calculates a set of data bits D

[23] , D

[21] , D

[19] , D

[18] , D

[16] , the DQ1 circuit receives and calculates a set of data bits D

[14] , D

[12] , D[8], the DQ0 circuit receives and calculates a set of data bits D[7], D[6], D[0] and the checksum bit CRC0, such as Figure 5CAs shown. Similarly, the other equations concerning CRC[1] to CRC[7] can be decomposed into groups of data bits received in the DQ circuit and the DM circuit, and each circuit in the DQ circuit and the DM circuit can calculate intermediate CRC bits based on the corresponding group of data bits.

[0036] Figure 6 According to embodiments of this disclosure Figure 4 A schematic diagram of the logic calculation process in device 40. Figure 6 Only the logical decomposition of CRC calculation is shown, and Figure 6 The arrows in the diagram do not necessarily indicate actual circuit connections. The CRC calculator circuits 630 to 638 in the DQ and DM circuits respectively calculate multiple XOR operations on corresponding groups of data bits. In some embodiments, each of the CRC calculator circuits 630 to 638 may include multiple logical XOR circuits. The CRC calculator circuit 630 in the DQ0 circuit may perform eight calculations 6300 to 6307 regarding CRC[0] to CRC[7] using at least a portion of the data bits received at the DQ0 circuit. In some embodiments of this disclosure, calculations 6300 to 6307 may be performed as previously referenced. Figures 5A to 5C As described. For example, calculation 6300 can be an XOR operation of data bits D[7], D[6], and D[0] in CRC[0] calculation with checksum bit CRC[0]; calculation 6301 can be an XOR operation of data bits D[6], D[1], and D[0] in CRC[1] calculation; calculation 6302 can be an XOR operation of data bits D[6], D[2], D[1], and D[0] in CRC[2] calculation; calculation 6303 can be an XOR operation of data bits D[7], D[3], D[2], and D[0] in CRC[3] calculation. The XOR operation of ] and D[1]; Calculation 6304 can be the XOR operation of data bits D[4], D[4] and D[2] in CRC[3] calculation; Calculation 6305 can be the XOR operation of data bits D[5], D[5] and D[3] in CRC[4] calculation; Calculation 6306 can be the XOR operation of data bits D[6], D[6] and D[4] in CRC[5] calculation; and Calculation 6307 can be the XOR operation of data bits D[7], D[6] and D[5] in CRC[7] calculation.

[0037] Similarly, the CRC calculator circuit 637 in the DQ7 circuit can perform eight calculations 6370 to 6377 about CRC[0] to CRC[7] by performing an XOR operation on groups of data bits that are subsets of data bits D

[56] to D

[63] and CRC checksum bits CRC[7] received by the DQ7 circuit, respectively. The CRC calculator circuit 638 in the DM circuit can perform eight calculations 6380 to 6387 about CRC[0] to CRC[7] by performing an XOR operation on groups of data bits that are subsets of data bits D

[64] to D

[71] received by the DM circuit, respectively.

[0038] The CRC combination circuit 64 may include multiple XOR tree circuits 640 to 647. For example, the XOR tree circuit 640 may receive the result of a CRC calculation bit from each of the calculations 6300, ... 6370 and 6380 with respect to CRC[0], perform an XOR operation on these 8 bits, and provide a result bit CRCresult[0] to the OR circuit 648. If there are no errors in the data bits D[0] to D[7], then CRCresult[0] is “0” (e.g., at a logic low level) because the calculations in the CRC calculator circuit 630 include the CRC checksum bit CRC[0]. Similarly, the XOR tree circuit 641 may receive the result of a bit from each of the calculations 6301, ... 6371 and 6381 with respect to CRC[1], perform an XOR operation on these 8 bits, and provide a bit result CRCresult[1] to the OR circuit 648. Furthermore, the XOR tree circuit 647 can receive the result of one bit of the calculation from each of the calculations 6307, ... 6377 and 6387 of CRC[7], perform an XOR operation on these 8 bits, and provide a bit result CRCresult[7] to the OR circuit 648. The OR circuit 648 can receive a total of eight bits (which are CRC results[0] to [7]) and perform a logical OR operation on the total of eight bits. Since any of the CRC results[0] to [7] can indicate an error as "1" (e.g., logic high) if any error exists, the result of the logical OR operation is also "1", and the CRC result (CRCerr) is at logic high "1", indicating a data fault. If there is no error in the data, all CRC results[0] to [7] are "0" (e.g., logic low), indicating that the data bits do not contain an error, so the result of the logical OR operation is also "0", and the CRC result (CRCerr) is at logic low "0", indicating that the data does not contain an error (=pass).

[0039] By decomposing the CRC calculation into a CRC calculator circuit with multiple DQ and DM circuits and a CRC combination circuit directly coupled to the multiple DQ and DM circuits, the area of ​​the data bus dedicated to CRC data can be reduced. As shown here, most of the XOR operation is performed in the multiple DQ and DM circuits. Because the XOR operation is performed on the data bits received at the CRC calculator circuit in the multiple DQ and DM circuits, the logic XOR gates that perform the same combination of XOR operations on the CRC calculation in each CRC calculator circuit (e.g., the XOR operation of D[0] and D[6] in CRC calculator circuit 630) can be shared by multiple calculations (such as calculation 6300 on CRC[0] and calculation 6301 on CRC[1]).

[0040] Figure 7 This is a block diagram of device 70 according to an embodiment of the present disclosure. In some embodiments of the present disclosure, device 70 may be included in memory device 20. Figure 7 The circuit structure of device 70 is similar to that of the previous reference. Figure 3 The circuit structure is described. Therefore, for brevity, detailed descriptions of the data terminal 71, buffer 731, and CRC calculator circuit 733 included in the DQ circuit 73 and CRC combination circuit 74 are omitted. The sampler 732 can provide multiple bits from the buffer 731 to the CRC calculator circuit 733 and the memory bank group selector circuit 734 at timings based on an internal clock (e.g., the local clock LCLK or DQS clock). The memory bank group selector 734 can select a memory bank group based on an address (such as a portion of a memory bank address). For example, the memory bank group selector 734 can receive one or more memory bank group signals BG based on a memory bank address and provide multiple data bits to the data bus on multiple global data buses 77 corresponding to the selected memory bank group indicated by the memory bank group signal BG. Figure 7In this circuit, the bank group selector 734 can be included within the DQ circuit 73; however, the bank group selector 734 can be located externally to the DQ circuit 73. The CRC combining circuit 74 can receive eight CRC calculation bits from the CRC calculator circuit 733 on signal line 76. Similarly, the CRC combining circuit 74 can receive eight CRC calculation bits from other circuits in the multiple DQ and DM circuits. Therefore, the CRC combining circuit 74 can receive a total of 72 CRC calculation bits and provide a CRC result signal CRCerr, which is a binary signal indicating whether the data contains any errors. Since the CRC combining circuit 74 receives CRC calculation bits directly from the multiple DQ and DM circuits on the signal line instead of from multiple global data buses, the multiple global data buses 77 do not need to include a data bus for transmitting CRC bits, and the CRC combining circuit 74 does not need to include a bank group selector circuit for receiving data from the multiple global data buses 77.

[0041] Figure 8 This is a schematic diagram of a memory device 80 comprising a plurality of dies 81 according to an embodiment of the present disclosure. In this embodiment, the number of dies 81 is eight. Modifications including changing the number of dies to replace the plurality of dies 81 are within the scope of this disclosure. In some embodiments, the plurality of dies 81 may be identical to each other in terms of circuit configuration and operation. For example, the plurality of dies 81 may be a stack of dies comprising a master die (die-0) 82 and a plurality of slave dies (die-1 to die-7) 83. In some embodiments, the plurality of dies 81 may all have the same design (e.g., comprising the same circuitry). Dies 81 may be configured during later manufacturing processes to function as master dies or slave dies. For example, the plurality of dies 81 may be configured such that one die can act as a master die 82 and the other dies can act as slave dies 83. Alternatively, in some embodiments, the master die 82 and the slave die 83 may be designed and manufactured as native master dies and native slave dies.

[0042] The main die 82 can be used to include one or more pads 84 coupled to the package substrate 85 via one or more bonding lines 86. One or more bonding lines 16 can be coupled to pads (not shown) of the package substrate 85. The pads (PADs) of each of the plurality of dies 83 can be in a floating state, decoupled from the package substrate 85. The main die 81 can communicate with each of the dies 83 via a through-silicon via (TSV) 87 (e.g., through-substrate or through-silicon via). A protruding electrode 88 can be disposed on the outer surface of the package substrate 88. The protruding electrode 88 can be coupled to a power line or signal channel.

[0043] Figure 9This is a block diagram of a device 90 according to an embodiment of the present disclosure. Device 90 may be a master chip 82 in a memory device 80. Figure 9 The circuit structure is similar to the previous reference. Figure 3The circuit structure is described. In device 90, the main die includes a data queue circuit 93 and a CRC combination circuit 94. The data queue circuit 93 may include a buffer 931, a CRC calculator circuit 933, and a memory bank group selector 934. Therefore, for the sake of brevity, a detailed description of the data terminal 91, buffer 931, and CRC combination circuit 94 is omitted. Sampler 932 can provide multiple bits from buffer 931 to the CRC calculator circuit 933 and interconnect controller 95 at timings based on an internal clock (e.g., a local clock LCLK or DQS clock). Interconnect controller 95 can provide multiple data bits to the main die and slave dies, such as slave die 83 in memory device 80. For example, interconnect controller 95 can provide multiple data bits of a memory cell array assigned to one of the slave dies, along with one or more memory bank group signals BG, through vias (such as via TSV 87) to a memory bank group selector in one of the slave dies (not shown). Interconnect controller 95 can provide multiple data bits of the memory cell array assigned to the master core to bank group selector 934. Bank group selector 934 can select a bank group based on bank group address BG and provide multiple data bits to the data bus corresponding to the selected bank group among multiple global data buses 97. CRC calculator circuit 933 can provide multiple CRC calculation bits as a result of a CRC calculation on at least a portion of the multiple data bits and one or two CRC check bits. CRC combination circuit 94, acting as the master core in device 90, can receive eight CRC calculation bits from CRC calculator circuit 933 on signal line 96. Similarly, CRC combination circuit 94 can receive eight CRC calculation bits from other CRC calculator circuits among multiple DQ circuits and DM circuits. Therefore, CRC combination circuit 94 can receive a total of 72 CRC calculation bits from multiple data bits and provide a CRC result signal CRCerr, which is a binary signal indicating whether the data contains any errors. Because the CRC calculation is performed in the CRC calculator circuit 933 and CRC combination circuit 94, which are all contained in the multiple DQ and DM circuits within the main die 90, no TSV transmits or receives CRC bits from or to the slave die. In some embodiments, the main die and slave die can be uniformly formed to be configured as either a main die or a slave die through post-manufacturing, and the data terminals, buffers, samplers, and CRC-related circuitry in the slave die are not activated. The bank group selector in the DQ circuitry on the slave die can be activated to receive data and the bank group signal BG from the main die through a via (such as via TSV 87). In some embodiments, the main die and slave die can be manufactured separately, and the slave die does not contain CRC-related circuitry.

[0044] Figure 3 , 7 9 and 9 are examples of the portion of the DQ circuit that performs CRC calculations on write operations. However, the DQ circuit can also perform CRC calculations on read operations. The logic levels of the signals and combinations of logic gates used in the above embodiments are merely examples. However, in other embodiments, combinations of logic levels of signals and combinations of logic gates other than those specifically described in this disclosure may be used without departing from the scope of this disclosure.

[0045] Although various embodiments have been disclosed in this disclosure, those skilled in the art will understand that the scope of this disclosure extends beyond the specifically disclosed embodiments to other alternative embodiments and / or their uses and obvious modifications and equivalents. Furthermore, other modifications within the scope of this disclosure will be apparent to those skilled in the art based on this disclosure. It is also contemplated that various combinations or sub-combinations of specific features and aspects of the embodiments can be made, and such combinations or sub-combinations still fall within the scope of this disclosure. It should be understood that various features and aspects of the disclosed embodiments can be combined or substituted with each other to form different embodiments. Therefore, the scope of at least a portion of this disclosure should not be limited to the specifically disclosed embodiments described above.

Claims

1. A semiconductor device comprising a data queue circuit; said data queue circuit comprising: A sampler configured to receive a plurality of data bits and one or more parity bits, and further configured to provide the plurality of data bits and the one or more parity bits to a first output and provide the plurality of data bits to a second output based on timing of an internal clock; as well as A Cyclic Redundancy Check (CRC) calculator circuit, the CRC calculator circuit being configured to receive the plurality of data bits and the one or more check bits from the first output of the sampler and being further configured to generate a plurality of CRC calculation bits, wherein each of the plurality of CRC calculation bits is based on a subset of the plurality of data bits, and wherein one of the plurality of CRC calculation bits is based on a portion of the plurality of data bits and the one or more check bits. The one or more check bits are at least partially based on the portion of the plurality of data bits and on one or more data bits that are different from the plurality of data bits and are received by another data queue circuit.

2. The semiconductor device according to claim 1, further comprising: A global data bus coupled to the data queue circuit, wherein the global data bus is configured to receive the plurality of data bits from the second output of the sampler of the data queue circuit; as well as Multiple signal lines, wherein the multiple signal lines are separated from the global data bus; The CRC calculator circuit is configured to provide the plurality of CRC calculation bits on the plurality of signal lines.

3. The semiconductor device of claim 1, further comprising a plurality of global data buses coupled to the data queue circuit, wherein each of the plurality of global data buses is configured to transmit data to a corresponding memory bank group in a plurality of memory bank groups; The data queue circuit further includes a memory bank group selector configured to receive the plurality of data bits from the sampler and further configured to provide the plurality of data bits to the corresponding global data bus of the corresponding memory bank group in the plurality of global data buses.

4. The semiconductor device of claim 1, wherein the CRC calculator circuit is configured to perform a plurality of calculations using at least a portion of the plurality of data bits to generate the plurality of CRC calculation bits.

5. The semiconductor device of claim 4, wherein the CRC calculator circuit comprises: Multiple logic XOR circuits are configured to perform the multiple calculations.

6. The semiconductor device of claim 5, wherein the plurality of calculations includes a first calculation and a second calculation, and The first calculation and the second calculation are configured to share one of the plurality of logical XOR circuits.

7. The semiconductor device according to claim 1, further comprising: A CRC combining circuit, the CRC combining circuit being configured to receive the plurality of CRC calculation bits and further configured to generate a result signal indicating whether a data bit containing the plurality of data bits contains an error, at least in part based on the plurality of CRC calculation bits; as well as A wire, one end of which is coupled to the CRC calculator circuit and the other end of which is coupled to the CRC combination circuit, wherein the wire is configured to transmit at least one of the plurality of CRC calculation bits from the CRC calculator circuit to the CRC combination circuit.

8. The semiconductor device of claim 7, wherein the CRC combination circuit comprises: A plurality of logic XOR circuits, wherein each logic XOR circuit is configured to receive a corresponding CRC calculation bit from the plurality of CRC calculation bits and is further configured to provide a result bit at least in part in response to the corresponding CRC calculation bit; and A logic or circuit configured to receive the result bit and further configured to provide the result signal at least in part in response to the result bit.

9. A semiconductor device comprising: A plurality of data queue circuits, each of the plurality of data queue circuits including a corresponding one of a plurality of cyclic redundancy check (CRC) calculator circuits, each of the plurality of CRC calculator circuits being configured to receive a plurality of data bits and one or more check bits and further configured to generate a plurality of CRC calculation bits, wherein each of the plurality of CRC calculation bits is based on a subset of the plurality of data bits, and wherein one of the plurality of CRC calculation bits is based on a portion of the plurality of data bits and the one or more check bits; and A CRC combination circuit, configured to receive the plurality of CRC calculation bits from each of the plurality of CRC calculator circuits and further configured to generate a result signal at least in part based on the plurality of CRC calculation bits, wherein the one or more check bits are based on the portion of the plurality of data bits and on one or more data bits received by each of the plurality of data queue circuits.

10. The semiconductor device of claim 9, further comprising a plurality of signal lines, each of the plurality of signal lines having one end coupled to the CRC calculator circuit and the other end coupled to the CRC combination circuit, wherein the plurality of signal lines are configured to carry the plurality of CRC calculation bits.

11. The semiconductor device of claim 9, wherein the CRC calculator circuit comprises a plurality of logic XOR circuits.

12. The semiconductor device of claim 9, further comprising a plurality of data terminals, each of the plurality of data terminals being coupled to a respective data queue circuit of the plurality of data queue circuits. Each of the respective CRC calculator circuits is configured to perform a plurality of calculations, wherein each of the plurality of calculations is configured to provide a corresponding CRC calculation bit from the plurality of CRC calculation bits in response to at least a portion of the plurality of data bits from the data terminal.

13. The semiconductor device of claim 12, wherein the plurality of data queue circuits includes a first data queue circuit and a second data queue circuit; The CRC calculator circuit is the first CRC calculator circuit in the first data queue circuit. The first CRC calculator circuit is configured to receive the plurality of data bits as a first plurality of data bits and the one or more check bits as one or more first check bits, and is further configured to provide the plurality of CRC calculation bits as a first plurality of CRC calculation bits. The plurality of CRC calculator circuits further include a second CRC calculator circuit in the second data queue circuit, the second CRC calculator circuit being configured to receive a second plurality of data bits and one or more second check bits, and being further configured to provide a second plurality of CRC calculation bits.

14. The semiconductor device of claim 13, wherein the first plurality of CRC calculation bits includes a first CRC calculation bit and a second CRC calculation bit; The second plurality of CRC calculation bits includes a third CRC calculation bit and a fourth CRC calculation bit; The CRC combination circuit includes: A first logic XOR circuit is configured to receive the first CRC calculation bit and the third CRC calculation bit, and is further configured to provide a first result bit; as well as A second logic XOR circuit is configured to receive the second CRC calculation bit and the fourth CRC calculation bit, and is further configured to provide a second result bit.

15. The semiconductor device of claim 14, further comprising a logic OR circuit configured to receive the first result bit and the second result bit, and further configured to provide the result signal at least in part in response to the first result bit and the second result bit.

16. A semiconductor device comprising: A first die and a second die stacked with the first die; The first die includes: Multiple first memory units; A plurality of data queue circuits including multiple CRC calculator circuits, wherein each of the multiple CRC calculator circuits in each of the multiple data queue circuits is configured to receive a corresponding plurality of data bits and a corresponding one or more check bits, and is further configured to generate a corresponding plurality of CRC calculation bits, wherein each of the plurality of CRC calculation bits is based on a subset of the corresponding plurality of data bits and wherein one of the plurality of CRC calculation bits is based on a portion of the plurality of data bits and the one or more check bits; and A CRC combining circuit, configured to receive the corresponding plurality of CRC calculation bits from the plurality of CRC calculator circuits, and further configured to generate a result signal based at least in part on the corresponding plurality of CRC calculation bits from the plurality of CRC calculator circuits; and The second die includes a plurality of second memory cells, wherein the corresponding one or more parity bits received by the first data queue circuit of the plurality of data queue circuits are at least partially based on the portion of the plurality of data bits and based on one or more data bits received by the second data queue circuit of the plurality of data queue circuits that are different from the plurality of data bits received by the first data queue circuit.

17. The semiconductor device of claim 16, wherein the first die further comprises a plurality of signal lines, one end of each of the plurality of signal lines being coupled to each CRC calculator circuit and the other end being coupled to the CRC combination circuit, wherein the plurality of signal lines are configured to carry the plurality of CRC calculation bits.

18. The semiconductor device of claim 16, wherein the plurality of data queue circuits includes a first data queue circuit, the first data queue circuit comprising: A first CRC calculator circuit, which is included in the plurality of CRC calculator circuits; and A sampler configured to receive a first plurality of data bits and one or more first check bits, and further configured to provide the first plurality of data bits and the one or more first check bits to the first CRC calculator circuit. The sampler is further configured to provide the first plurality of data bits to the second die.

19. The semiconductor device of claim 18, further comprising a plurality of global data buses coupled to the first data queue circuit, wherein each of the plurality of global data buses is configured to transmit data to a corresponding memory bank group in a plurality of memory bank groups; The first data queue circuit further includes a memory bank group selector, which is configured to receive the first plurality of data bits from the second die, and The memory bank group selector is configured to provide the first plurality of data bits to the corresponding global data bus of the corresponding memory bank group in the plurality of global data buses.

20. The semiconductor device of claim 16, wherein the first die and the second die have the same design, and wherein the first die is configured to perform as a master die and the second die is configured to perform as a slave die.

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