A storage master control architecture and flash memory particle control method

Abstract

The present application discloses a storage master control architecture and a flash memory particle control method, and relates to the field of storage technology. The storage master control architecture is used to adapt to flash memory particles of different types and page capacities, including a high-speed storage master control interface module, an adjustable cache and control module, a write data channel processing module, a read data channel processing module, a flash memory interface module, and a firmware control module. The present application introduces a plurality of different types of adjustable cache interval designs, and can adaptively configure the page capacity (Page size) required for data processing from 1K, 2K to 4K, 8K through the firmware program (Firmware), as well as a multi-channel processing architecture design. On the one hand, the present storage master control design can be widely used by multiple different types of flash memory particle products. On the other hand, the present application can greatly improve the read and write performance of the storage master control architecture through a parallel processing mechanism of multiple data channels for write operations (WP) and read operations (RP).

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a storage master control architecture and a flash memory particle control method. Background Art

[0002] With the rapid development of flash storage, multiple generations of flash memory products have been produced, including SLC (Single-Level Cell, 1 bit / cell), MLC (Multi-Level Cell, 2 bits / cell), TLC (Tri-Level Cell, 3 bits / cell) and QLC (Quad-Level Cell, 4 bits / cell), as well as 5 bits / cell five-level cell PLC products that are still under development. Due to different manufacturers and processes, each generation of products also has two-dimensional (2D) and three-dimensional (3D) design products, such as 2D SLC, 2D MLC, 3D MLC, 3D TLC, 3D QLC and other products. The data storage page capacity (Page Size) of each flash memory product is not exactly the same, including 1024 bytes (1K), 2048 bytes (2K), 4096 bytes (4K) and 8192 bytes (8k), as well as 16384 (16K) for greater efficiency. Moreover, due to different applications, flash memory chips also have byte bus mode (x8) and word bus mode (x16). Therefore, the flash memory particle products on the market include but are not limited to SLC 1K x16, SLC 2k x8, MLC 2Kx8, MLC 4K x8, TLC 4k x8, QLC 8k x8 and other flash memory particle chips. At the same time, due to the use of different software designs and host designs from different manufacturers in the previous flash storage system applications, the size of the data transmission block will also be inconsistent. Therefore, when designing a storage control architecture based on different models of flash memory particles, it is often impossible to achieve compatibility and convenient and fast application.

[0003] In addition, there are also multiple interface protocols in the current storage master control architecture, each protocol supports different storage cards, such as multimedia (Multi-Media Card-MMC) interface, SD (Secure Digital Memory Card-SD) interface, UFS (Universal Flash Storage-UFS) interface, etc. Since these interface protocols have large differences in data processing, such as half-duplex operation (reading and writing must be executed separately) or full-duplex operation (reading and writing can be executed separately), it is currently difficult to have a flash memory storage master control architecture that can be suitable for different storage interfaces and capacities. Summary of the invention

[0004] The purpose of this application is to provide a storage master control architecture, which solves the problem in the prior art that a storage master control architecture cannot be adapted to flash memory particles of different types and page capacities by adopting an adjustable cache (Switch Buffer) plus a multi-channel processing (Multi Pipe) architecture (SBMP) and greatly improves the read and write performance of the storage master control architecture.

[0005] To achieve the above purpose, the embodiment of the present application adopts the following technical solution: a storage master control architecture, including:

[0006] A high-speed storage main control interface module, which is used to receive signals from the HOST host and data to be written or read;

[0007] An adjustable cache and control module, which is connected to the high-speed storage master control interface module, and is used to determine the cache structure required by the flash memory particles and the page size required for data processing, select cache types and cache intervals with different page sizes, and write the data to be written or read into the cache interval or read it out from the cache interval;

[0008] A write data channel processing module, which is connected to the adjustable cache and control module, and is used to generate a write instruction to read the data to be written from the cache interval;

[0009] A read data channel processing module, which is connected to the adjustable cache and control module, and is used to generate a read instruction, send the data to be read to the adjustable cache and control module, and write it into the cache interval;

[0010] A flash memory interface module, which is connected to the write data channel processing module and is used to receive write instructions and data to be written, and send them to external flash memory particles; the flash memory interface module is also connected to the read data channel processing module, receives read instructions and reads data from external flash memory particles;

[0011] A firmware control module, which is connected to the high-speed storage master interface module, the adjustable cache and control module, the write data channel processing module, the read data channel processing module and the flash memory interface module, and is used to control the high-speed storage master interface module, the adjustable cache and control module, the write data channel processing module, the read data channel processing module and the flash memory interface module.

[0012] In the above technical scheme, the embodiment of the present application introduces adjustable multiple different types of cache interval designs, and can adaptively configure the page capacity (Page size) required for data processing from 1K, 2K to 4K, 8K through the firmware program (Firmware), as well as a multi-channel processing architecture design. On the one hand, this storage master control design can be widely used with multiple different types of flash memory particle products. On the other hand, through the parallel processing mechanism of multiple data channels for write operations (WP) and read operations (RP), the read and write performance of the storage master control architecture can be greatly improved.

[0013] Further, according to an embodiment of the present application, the high-speed storage master control interface module supports multiple storage master control interfaces with different functions, including MMC / eMMC, SD, TF, UFS, USB interfaces, etc.

[0014] Further, according to an embodiment of the present application, the high-speed storage master control interface module parses the signal from the HOST host to obtain a high-speed data link control signal, an address signal, a data signal and a storage particle model.

[0015] Further, according to an embodiment of the present application, the adjustable cache and control module includes: a control module, which is used to parse input instructions and control data processing; a data calibration module, which is connected to the control module; an adaptively adjustable cache module, which is connected to the control module, and the adaptively adjustable cache module can be divided into cache intervals of different capacities.

[0016] Further, according to an embodiment of the present application, the write data channel processing module includes: a buffer write control interface module, the buffer write control interface module is connected to the adjustable cache and control module, and receives the data to be written read from the cache area; a data write instruction parsing module, the data write instruction parsing module is used to parse the write instruction; a write instruction state machine conversion and processing module, the write instruction state machine conversion and processing module is used to control the state machine to analyze and determine the write instruction operation, address and data information; a data error correction coding module, the data error correction coding module is used to encode the data to be written; a write operation and data processing module, the write operation and data processing module is connected to the flash memory interface module, and the write operation and data processing module is used to send the write instruction and the data to be written to the flash memory interface module.

[0017] Further, according to an embodiment of the present application, the read data channel processing module includes: a buffer read control interface module, the buffer read control interface is connected to the adjustable cache and control module; a data read instruction parsing module, the data read instruction parsing module is used to parse read instructions; a read instruction state machine conversion and processing module, the read instruction state machine conversion and processing module is used to control the state machine to distinguish and generate read operation instructions; a data error correction decoding module, the data error correction decoding module is used to decode the data to be read; a read operation and data processing module, the read operation and data processing module is connected to the flash memory interface module, and the read operation and data processing module is used to send read instructions to the flash memory interface module and receive the data to be read from the flash memory interface module.

[0018] Further, according to an embodiment of the present application, the firmware control module is used to run the firmware program, detect the storage particle type, different time stages and functional requirements of writing / reading data, and generate accurate control signals.

[0019] In order to achieve the above object, the embodiment of the present application further discloses a flash memory particle control method for writing data into the flash memory particle, comprising the following steps:

[0020] Receive signals from the HOST host and data to be written;

[0021] Determine the type and page capacity of the flash memory particle;

[0022] Select or adjust a cache interval, and write the data to be written into the cache interval;

[0023] Generate a write instruction acceptable to the flash memory particle, and write the data to be written into the flash memory particle.

[0024] In order to achieve the above object, the embodiment of the present application further discloses a flash memory particle control method for reading data from the flash memory particle, comprising the following steps:

[0025] Generate a read instruction acceptable to the flash memory particle, and read the data to be read from the flash memory particle;

[0026] Determine the type and page capacity of the flash memory particle;

[0027] Select or adjust a cache interval, and write the to-be-read data into the cache interval;

[0028] Send the data to be read to the HOST host.

[0029] Compared with the prior art, the present application has the following beneficial effects: by introducing adjustable multiple different types of cache area designs, the present application can adaptively configure the page capacity (Page size) required for data processing from 1K, 2K to 4K, 8K through the firmware program (Firmware), as well as the multi-channel processing architecture design. On the one hand, the present storage master control design can be widely used with multiple different types of flash memory particle products. On the other hand, through the parallel processing mechanism of multiple data channels for write operations (WP) and read operations (RP), the read and write performance of the storage master control architecture can be greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The present application is further described below in conjunction with the accompanying drawings and embodiments.

[0031] Figure 1 It is a structural diagram of a storage master control architecture in this application.

[0032] Figure 2 It is a schematic diagram of the framework of the adjustable cache and control module in this application.

[0033] Figure 3 It is a schematic diagram of the framework of the write data channel processing module in this application.

[0034] Figure 4 It is a schematic diagram of the framework of the read data channel processing module in this application.

[0035] Figure 5 It is a flowchart of the firmware control module.

[0036] Figure 6 It is a system application diagram of a storage master control architecture in this application. DETAILED DESCRIPTION

[0037] In order to make the purpose and technical solution of the present invention clearly and completely described, and the advantages more clearly understood, the embodiments of the present invention are further described in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are part of the embodiments of the present invention, rather than all of the embodiments, and are only used to explain the embodiments of the present invention, and are not used to limit the embodiments of the present invention. All other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] In the description of the present invention, it should be noted that the terms "center", "middle", "upper", "lower", "left", "right", "inner", "outer", "top", "bottom", "side", "vertical", "horizontal" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "one", "first", "second", "third", "fourth", "fifth", "sixth" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0039] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0040] For the purpose of simplicity and illustration, the principles of the embodiments are mainly described by reference to examples. In the following description, many specific details are proposed to provide a thorough understanding of the embodiments. However, it is obvious that for those of ordinary skill in the art, these embodiments may not be limited to these specific details in practice. In some instances, known methods and structures are not described in detail to avoid making these embodiments unnecessarily difficult to understand. In addition, all embodiments can be used in combination with each other.

[0041] [Example 1]

[0042] Figure 1 The specific structure of a storage control architecture in this embodiment is shown. Figure 1 As shown, the storage master control architecture is used to adapt to flash memory particles of different types and page capacities, including a high-speed storage master control interface module, an adjustable cache and control module, a write data channel processing module, a read data channel processing module, a flash memory interface module and a firmware control module.

[0043] The high-speed storage master interface module is used to receive signals from the HOST host and data to be written or read, and supports multiple storage master interfaces with different functions, including but not limited to MMC / eMMC, SD, TF, UFS, USB interface, etc. The high-speed storage master interface module parses the received information to obtain high-speed data link control signals, address signals, data signals, and different storage particle models.

[0044] The adjustable cache and control module is connected to the high-speed storage master interface module. The adjustable cache and control module is used to determine the cache structure required by the flash memory particles and the page capacity (Page Size) required for data processing, select cache types and cache intervals with different page capacities, and write the data to be written or read into the cache interval or read out from the cache interval. Specifically, the adjustable cache and control module receives high-speed data link control signals, address signals, data signals, and information such as different storage particle models from the high-speed storage master interface module, determines the required cache structure and capacity, determines the flash memory particle model and performance used by decoding, adaptively determines the flash memory particle chip category, dynamically adjusts the size of the allocated cache interval, writes the data to be written or read into the allocated cache interval, and finally outputs the input and output signals required by the read data channel processing module and the write data channel processing module according to the determination result.

[0045] The write data channel processing module is connected to the adjustable cache and control module. The write data channel processing module is used to receive write instructions and read the data to be written from the cache interval. Specifically, the write data channel processing module receives the signal required for the data write operation, and generates a write instruction according to the internal state machine judgment; there is an ECC encoding module inside the write data channel processing module. The chip design transmits the data to be written to the ECC encoding module according to the control signal, encodes the data to be written according to the relevant ECC algorithm, and generates new data with error correction information and returns it to the write data channel processing module. At the same time, the write data channel processing module is also connected to the flash memory interface module. The write data channel processing module parses the write instruction and generates commands, addresses and new data that can be accepted by the flash memory particle chip after encoding. According to the design requirements, after being processed by the flash memory interface module, the data can be written into the corresponding storage particle chip.

[0046] The read data channel processing module is connected to the adjustable cache and control module. The read data channel processing module is used to generate a read instruction, send the data to be read to the adjustable cache and control module and write it into the cache interval. Specifically, the read data channel processing module is connected to the flash memory interface module, and the data is read from the storage particles through the flash memory interface module. There is a corresponding ECC decoding module inside the read data channel processing module. The chip design transmits the read data to the ECC decoding module according to the control signal, decodes the data according to the error correction level and different requirements, determines whether the read data has errors and error conditions, and performs data error correction according to the error type and location. The read data channel processing module determines and generates various instructions for read operations according to the internal state machine of the read data channel processing module based on the required signal for the read operation generated by the adjustable cache and control module, and transmits the corrected data to the adjustable cache and control module.

[0047] The flash memory interface module is connected to the write data channel processing module, and is used to receive the write instruction and the data to be written, and send them to the external flash memory particles. Specifically, the flash memory interface module receives the write command, address and data to be stored that are acceptable to the flash memory particle chip from the write data channel processing module, and then generates a signal that complies with the relevant storage protocol, and writes the data to be written into the storage particle.

[0048] The flash memory interface module is connected to the read data channel processing module, receives the read instruction and reads data from the external flash memory particles. Specifically, the flash memory interface module receives the read instruction and address synthesis processing that are acceptable to the flash memory particles from the read data channel processing module, transmits it to the flash memory storage particle chip, and reads the data from the storage particle chip to the read data channel processing module.

[0049] The firmware control module is connected with the high-speed storage master control interface module, the adjustable cache and control module, the write data channel processing module, the read data channel processing module and the flash memory interface module, and is used to control the high-speed storage master control interface module, the adjustable cache and control module, the write data channel processing module, the read data channel processing module and the flash memory interface module. Specifically, the firmware control module writes the firmware program in C language, and detects the storage particle type used by the matching system, the different time stages of writing / reading data and the functional requirements, and generates accurate control signals.

[0050] In the above technical solution, this embodiment introduces a plurality of different types of adjustable cache interval designs, which can adaptively configure the page capacity (Page size) required for data processing from 1K, 2K to 4K, 8K through the firmware program (Firmware), as well as a multi-channel processing architecture design. On the one hand, this storage master control design can be widely used in a variety of different types of storage products. On the other hand, through the parallel processing mechanism of multiple data channels for write operations (WP) and read operations (RP), the read and write performance of the storage master control architecture can be greatly improved.

[0051] [Example 2]

[0052] Figure 2 The schematic diagram shows the framework structure of the adjustable cache and control module in this application. Figure 2 As shown, based on Example 1, the functional modules in the switch buffer control module include a control module for parsing input instructions and controlling data processing, a data alignment module (DataAlign), and an adaptively adjustable cache module. Among them, the control module is used to parse input instructions and control data processing; the data alignment module is connected to the control module; the adaptively adjustable cache module is connected to the control module, and the adaptively adjustable cache module can be divided into cache intervals of different capacities. The adaptively adjustable cache module discriminates and decodes the flash storage particle chip used by the terminal of this system according to the various information signals and data information generated after the firmware program (Firmware) processes and proofreads, determines whether the storage particle chip used is one of SLC, MLC, TLC and QLC, and the storage page size (page size), and adaptively adjusts the required cache interval and various related configurations through internal modules.

[0053] [Example 3]

[0054] Figure 3 The framework structure of the write data channel processing module in this application is shown. Figure 3 As shown, based on Example 1, the data channel processing module includes a buffer write control interface module, a data write instruction parsing module, a write instruction state machine conversion and processing module, an ECC encoding module, and a write operation and data processing module. Among them, the buffer write control interface module is connected to the adjustable cache and control module to receive the data to be written from the cache area; the data write instruction parsing module is used to parse the write instruction; the write instruction state machine conversion and processing module is used to control the state machine to analyze and determine the write instruction operation, address and data information; the data error correction encoding module is used to encode the data to be written; the write operation and data processing module is connected to the flash memory interface module, and the write operation and data processing module is used to send the write instruction and the data to be written to the flash memory interface module.

[0055] In addition, there can be multiple write data channel processing modules. According to different data interfaces provided by the HOST host side, a multi-channel (Multi Pipe) write data channel design is adopted. Since the write data storage needs to wait when writing data to the flash memory particles through the flash interface module (FlashInterface-FIF), when one write channel is busy (Busy), the instruction discrimination, data encoding / decoding, etc. sent from the HOST host side can be continued in other multi-channel write data processing channels at the same time. Through this parallel and continuous processing of read or write operations, the read and write performance of the storage master control architecture described in this application can be greatly improved.

[0056] [Example 4]

[0057] Figure 4 The framework structure of the data read channel processing module in this application is shown. Figure 4 As shown, based on Example 1, the read data channel processing module (RP) also includes a buffer read control interface module, a data read instruction parsing module, a read instruction state machine conversion and processing module, an ECC decoding module, and a read operation and data processing module. Among them, the buffer read control interface is connected to the adjustable cache and control module; the data read instruction parsing module is used to parse the read instruction; the read instruction state machine conversion and processing module is used to control the state machine to distinguish and generate the read operation instruction; the data error correction decoding module is used to decode the data to be read; the read operation and data processing module is connected to the flash memory interface module, and the read operation and data processing module is used to send the read instruction to the flash memory interface module and receive the data to be read from the flash memory interface module.

[0058] In addition, there can be multiple read data channel processing modules. According to different data interfaces provided by the HOST host side, a multi-channel (Multi Pipe) read data channel design is adopted. Since the read data storage needs to wait for a time when reading the flash memory particles through the flash interface module (FlashInterface-FIF), when one read channel is busy (Busy), the instruction discrimination, data encoding / decoding, etc. sent from the HOST host side can be continued in other multi-channel read data processing channels at the same time. Through this parallel and continuous processing of read or write operations, the read and write performance of the storage master control architecture described in this application can be greatly improved.

[0059] [Example 5]

[0060] Figure 5 The specific process of the firmware control module is shown. Figure 5As shown, based on Example 1, the following firmware program is run in the firmware control module: first, determine whether it is a restart (Power on / Reset) operation, if it is, perform initialization configuration (Init), then perform addressing configuration according to the read / write instructions transmitted by the read data channel processing module or the write data channel processing module, including external flash memory particle type discrimination (SLC / MLC / TLC / QLC), external flash memory particle page capacity discrimination (page size 1K / 2K / 4K / etc.) and whether to perform read or write operation discrimination and other processing; then process respectively according to the write channel program or read channel program corresponding to the storage master control architecture in the above embodiment. If it is a write data operation, according to the characteristics of different flash memory types (SLC / MLC / TLC / QLC), especially the different mapping orders of the word lines (WordLine-WL) representing the page address in the flash memory particle chips of 2 bits / cell and above, perform processing and storage (BufferSwitch and Storage), and then save the data to a configurable and adjustable cache for subsequent writing to the external flash memory particles for operation processing. If it is a data read operation, wait for the data to be read from the external flash memory particles into the configurable cache area and then transferred to the data bus of the interface.

[0061] [Example 6]

[0062] Figure 6 The specific application of a storage control architecture in this application is shown. Figure 6 As shown, according to the different protocols and transmission speed requirements of the system, the system selects a storage master control architecture that supports different interface protocols and different flash memory particles. In this embodiment, the host HOST system starts to write data into the storage or read data from the flash memory particles, and sends instructions that comply with the MMC / SD / UFS protocol standards to the storage master control architecture based on the SBMP (Switch Buffer & Multi Pipe) architecture design according to the interface. The storage master control architecture can adjust the automatic configuration cache interval according to the flash memory storage particle chips of different types or different page sizes used by the system, and then according to the read or write instruction, through multi-channel parallel or when a channel receives an instruction and is busy, other channels continue the system's next read or write instruction, and through multi-channel parallel or pipeline operations, write data to the flash memory particles, or read data from the flash memory particles to the data bus of the HOST host.

[0063] [Example 7]

[0064] This embodiment also discloses a flash memory particle control method, which can be used to write data into a flash memory particle or to read data from a flash memory particle, and specifically includes the following steps:

[0065] Write data:

[0066] Receive signals from the HOST host and data to be written;

[0067] Determine the type and page capacity of the flash memory particle;

[0068] Select or adjust a cache interval, and write the data to be written into the cache interval;

[0069] Generate a write instruction acceptable to the flash memory particle, and write the data to be written into the flash memory particle;

[0070] Reading data:

[0071] Generate a read instruction acceptable to the flash memory particle, and read the data to be read from the flash memory particle;

[0072] Determine the type and page capacity of the flash memory particle;

[0073] Select or adjust a cache interval, and write the to-be-read data into the cache interval;

[0074] Send the data to be read to the HOST host.

[0075] Although the above describes the illustrative specific implementation methods of the present application so that technicians in this technical field can understand the present application, the present application is not limited to the scope of the specific implementation methods. For ordinary technicians in this technical field, as long as various changes are within the spirit and scope of the present application defined and determined by the attached claims, all application creations using the concept of the present application are protected.

Claims

1. A storage control architecture, characterized in that: include: A high-speed storage main control interface module, the high-speed storage main control interface module is used to receive signals from the HOST host and data to be written or read; An adjustable cache and control module, the adjustable cache and control module is connected to the high-speed storage master control interface module, the adjustable cache and control module is used to determine the cache structure required by the flash memory particles and the page size required for data processing, select cache types and cache intervals with different page sizes, and write the data to be written or read into the cache interval or read it out from the cache interval; A write data channel processing module, the write data channel processing module is connected to the adjustable cache and control module, and the write data channel processing module is used to generate a write instruction to read the data to be written from the cache interval; A read data channel processing module, the read data channel processing module is connected to the adjustable cache and control module, and the read data channel processing module is used to generate a read instruction, send the to-be-read data to the adjustable cache and control module, and write the data into the cache interval; A flash memory interface module, the flash memory interface module is connected to the write data channel processing module, and is used to receive the write instruction and the data to be written, and send them to the external flash memory particles; the flash memory interface module is connected to the read data channel processing module, and is used to receive the read instruction and read data from the external flash memory particles; A firmware control module, the firmware control module is connected to the high-speed storage master control interface module, the adjustable cache and control module, the write data channel processing module, the read data channel processing module and the flash memory interface module, and the firmware control module is used to control the high-speed storage master control interface module, the adjustable cache and control module, the write data channel processing module, the read data channel processing module and the flash memory interface module; The adjustable cache and control module includes: a control module, the control module is used to parse input instructions and control data processing; a data calibration module, the data calibration module is connected to the control module; an adaptively adjustable cache module, the adaptively adjustable cache module is connected to the control module, and the adaptively adjustable cache module can be divided into cache intervals of different capacities; The adaptively adjustable cache module can process and proofread various information signals and data information generated by the firmware program, identify and decode the flash memory storage particle chip used by the terminal of this system, determine the storage particle chip used, and the storage page size, and adaptively adjust the required cache interval through the internal module.

2. A storage master control architecture according to claim 1, characterized in that: The high-speed storage master control interface module supports multiple storage master control interfaces with different functions, including MMC / eMMC, SD, TF, UFS, and USB interfaces.

3. A storage master control architecture according to claim 1, characterized in that: The high-speed storage main control interface module analyzes the signal from the HOST host to obtain the high-speed data link control signal, address signal, data signal and storage particle model.

4. A storage master control architecture according to claim 1, characterized in that: The write data channel processing module comprises: A buffer write control interface module, the buffer write control interface module is connected to the adjustable buffer and control module, and receives the to-be-written data read from the buffer interval; A data writing instruction parsing module, the data writing instruction parsing module is used to parse the writing instruction; A write instruction state machine conversion and processing module, which is used to control the state machine to analyze and determine the write instruction operation, address and data information; A data error correction coding module, wherein the data error correction coding module is used to encode the data to be written; A write operation and data processing module, wherein the write operation and data processing module is connected to the flash memory interface module, and the write operation and data processing module is used to send write instructions and data to be written to the flash memory interface module.

5. A storage master control architecture according to claim 1, characterized in that: The read data channel processing module comprises: A buffer read control interface module, wherein the buffer read control interface is connected to the adjustable cache and control module; A data read instruction parsing module, the data read instruction parsing module is used to parse the read instruction; A read instruction state machine conversion and processing module, the read instruction state machine conversion and processing module is used to control the state machine to distinguish and generate read operation instructions; A data error correction decoding module, wherein the data error correction decoding module is used to decode the data to be read; A read operation and data processing module, wherein the read operation and data processing module is connected to the flash memory interface module, and is used to send a read instruction to the flash memory interface module and receive data to be read from the flash memory interface module.

6. A storage master control architecture according to claim 1, characterized in that: The firmware control module is used to run the firmware program, detect the storage particle type, different time stages of writing / reading data and functional requirements, and generate accurate control signals.

7. A flash memory particle control method based on the storage master control architecture of claim 1, characterized in that: The method for writing data into the flash memory particles comprises the following steps: Receive signals from the HOST host and data to be written; Determine the type and page capacity of the flash memory particle; Select or adjust a cache interval, and write the data to be written into the cache interval; Generate a write instruction acceptable to the flash memory particle, and write the data to be written into the flash memory particle.

8. A flash memory particle control method based on the storage master control architecture of claim 1, characterized in that: The method is used to read data from the flash memory particles, comprising the following steps: Generate a read instruction acceptable to the flash memory particle, and read the data to be read from the flash memory particle; Determine the type and page capacity of the flash memory particle; Select or adjust a cache interval, and write the to-be-read data into the cache interval; Send the data to be read to the HOST host.

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