System-level verification method, system, device and storage medium for chip registers

Abstract

The present application discloses a system-level verification method for chip registers, including: establishing a one-to-one correspondence between each bus signal of the CPU of the chip to be tested and each interface signal of the verification platform, so that in the process of system-level verification of the registers of the chip to be tested, the bus signal of the CPU is replaced by the interface signal sent by the verification platform; generating test cases, and establishing corresponding register models for each register of the chip to be tested, and determining the actual address of each register according to a preset address mapping table; for the target register of the chip to be tested, executing the test case based on the register model corresponding to the target register, and obtaining the system-level verification result of the target register. Applying the scheme of the present application, the system-level verification of chip registers can be conveniently and effectively performed. The present application also discloses a system-level verification system, device and storage medium for chip registers, which have corresponding technical effects.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a system-level verification method, system, device and storage medium for a chip register. Background Art

[0002] In the process of chip development, verification plays a vital role and is also a key step to ensure chip quality. The commonly used verification method is to use UVM (Universal Verification Methodology) to verify the chip under test. Register verification is an important part of the verification process. Only by ensuring that the configuration and function of the register are correct can the "interaction" between hardware be correct. In the process of verifying whether the register is correct, it is necessary to frequently read and write the registers inside the chip under test. Generally, there are two main ways to obtain the internal registers of the chip under test in TB (Test Beach): front door access and back door access. However, front door access consumes simulation time, and back door access will cause the verification environment to be bloated and complex, and prone to errors. Therefore, the register model came into being. The register model corresponds to the registers in the chip under test and is a behavioral model of the real hardware registers in the software environment. This model can be used to easily read and write the registers in the chip under test.

[0003] After testing each register in the chip under test, that is, after the registers of the chip under test have been verified at the module level, it can be guaranteed that the functions of the registers themselves are normal. After that, the functions of the registers of the chip under test in the chip under test will continue to be tested, that is, the system-level verification of the registers of the chip under test will be performed. In the actual chip, various read and write operations on the registers are controlled by the CPU, and when performing system-level verification on the registers of the chip under test in the verification platform, random read and write operations are required on the registers. In some cases, the CPU may not be able to support various random operations on all registers, which brings difficulties to the system-level verification of the registers of the chip under test, and requires verification personnel to verify through other methods, which is time-consuming and labor-intensive.

[0004] In summary, how to conveniently and effectively perform system-level verification of chip registers is a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0005] The purpose of the present invention is to provide a system-level verification method, system, device and storage medium for chip registers, so as to conveniently and effectively perform system-level verification of chip registers.

[0006] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0007] A system-level verification method for a chip register, comprising:

[0008] Establishing a one-to-one correspondence between each bus signal of the CPU of the chip under test and each interface signal of the verification platform, so that in the process of performing system-level verification of the register of the chip under test, the bus signal of the CPU is replaced by the interface signal sent by the verification platform;

[0009] Generate test cases, and establish corresponding register models for each register of the chip to be tested, and determine the actual address of each register according to a preset address mapping table;

[0010] For the target register of the chip to be tested, the test case is executed based on a register model corresponding to the target register to obtain a system-level verification result of the target register.

[0011] Preferably, the generated test cases include: register default value test cases, register read and write test cases, and register bit test cases;

[0012] The step of executing the test case for the target register of the chip under test based on a register model corresponding to the target register to obtain a system-level verification result of the target register includes:

[0013] For the target register of the chip to be tested, the register default value test case, the register read and write test case, and the register bit test case are executed in sequence based on the register model corresponding to the target register, and the default value test result of the target register, the read and write test result of the target register, and the bit test result of the target register are obtained in sequence.

[0014] Preferably, executing the register default value test case based on the register model corresponding to the target register to obtain the default value test result of the target register includes:

[0015] When the target register is a write-only register, executing the register default value test case based on the register model corresponding to the target register, obtaining the actual default value of the target register in a back-door read manner, and determining that the default value test result of the target register is passed only when the actual default value is consistent with the mirror value obtained by the register model corresponding to the target register;

[0016] When the target register is not a write-only register, the register default value test case is executed based on the register model corresponding to the target register, and the actual default value of the target register is obtained in a front-door read manner, and only when the actual default value is consistent with the mirror value obtained by the register model corresponding to the target register, the default value test result of the target register is determined to be passed.

[0017] Preferably, executing the register read and write test case based on the register model corresponding to the target register to obtain the read and write test result of the target register includes:

[0018] Executing the register read and write test case based on the register model corresponding to the target register, obtaining an actual default value of the target register in a back-door read manner, and generating first write data;

[0019] When the target register is a read-only register, the first write data is written in a back-door write manner, and after writing, it is read in a front-door read manner, and only when the read value is consistent with the first write data, the register read-write test result of the target register is determined to be passed;

[0020] When the target register is a write-only register, the first write data is written in a front-gate write manner, and after writing, it is read in a back-gate read manner, and only when the read value is 0, the register read-write test result of the target register is determined to be passed;

[0021] When the target register is a read-write register, the first write data is written in a front-door write manner, and is read in a front-door read manner after writing, and only when the read value is consistent with the first write data, the register read-write test result of the target register is determined to be passed.

[0022] Preferably, it also includes:

[0023] After determining the register read / write test result of the target register, determining whether the register read / write test operation performed on the target register has caused a change in a value in any other register other than the target register;

[0024] If yes, then the first warning prompt is output.

[0025] Preferably, executing the register bit test case based on the register model corresponding to the target register to obtain the bit test result of the target register includes:

[0026] When the target register is a read-write register, for any bit of the target register, a first inverse number of the value corresponding to the bit is written in a front-gate writing manner, and the expected value in the register model of the target register is updated to the first inverse number;

[0027] Obtain the expected value after update through the get function;

[0028] Read the value of the bit where the first inverse number is written in a front-door reading manner, and determine whether the value of the bit read in the front-door reading manner is consistent with the expected value obtained by the get function;

[0029] If not, determining that the register bit test result of the target register is failed;

[0030] If yes, write a second inverted number corresponding to the first inverted number in a front-gate writing manner, and update the expected value in the register model of the target register to the second inverted number;

[0031] Obtain the expected value after update through the get function;

[0032] Read the value of the bit where the second inverse number is written in a front-door reading manner, and determine whether the value of the bit read in the front-door reading manner is consistent with the expected value obtained by the get function;

[0033] If not, determining that the register bit test result of the target register is failed;

[0034] If yes, determining that the register bit test result of the target register is passed;

[0035] Among them, the inverse number corresponding to 0 is 1, and the inverse number corresponding to 1 is 0.

[0036] Preferably, the preset address mapping table includes base address information of the reserved area.

[0037] A system-level verification system for a chip register, comprising:

[0038] A bus signal replacement unit, used to establish a one-to-one correspondence between each bus signal of the CPU of the chip under test and each interface signal of the verification platform, so that in the process of system-level verification of the register of the chip under test, the bus signal of the CPU is replaced by the interface signal sent by the verification platform;

[0039] A configuration unit, used to generate test cases, establish corresponding register models for each register of the chip to be tested, and determine the actual address of each register according to a preset address mapping table;

[0040] The execution unit is used to execute the test case for the target register of the chip to be tested based on the register model corresponding to the target register to obtain the system-level verification result of the target register.

[0041] A system-level verification device for a chip register, comprising:

[0042] Memory for storing computer programs;

[0043] A processor is used to execute the computer program to implement the steps of the system-level verification method for chip registers as described in any one of the above items.

[0044] A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the system-level verification method for a chip register as described in any one of the above.

[0045] By applying the technical solution provided by the embodiment of the present invention, a one-to-one correspondence between each bus signal of the CPU of the chip to be tested and each interface signal of the verification platform will be established, so that in the process of system-level verification of the register of the chip to be tested, the bus signal of the CPU is replaced by the target interface signal sent by the verification platform, and the problem caused by the inability of the CPU to support various random operations on all module registers in the traditional solution will not occur. In addition, in the process of system-level verification of the register of the chip to be tested, the present application establishes corresponding register models for each register module of the chip to be tested to realize the system-level verification of the register, which can effectively improve the convenience and efficiency of verification. However, unlike the module-level verification, in the real SoC environment, the address space used by each register is completely different, that is, the actual physical address is the base address plus the offset address. When the corresponding register model is established for each register of the chip to be tested, only the offset address of each register can be obtained. Therefore, in the scheme of the present application, the actual address of each register will be determined according to the preset address mapping table, so that when the system-level verification of the register is performed, the access to each register can be effectively realized. In summary, the scheme of the present application can conveniently and effectively perform system-level verification of chip registers. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0047] Figure 1 It is a flow chart of the implementation of a system-level verification method for a chip register in the present invention;

[0048] Figure 2 A schematic diagram of reflecting the actual addresses of various registers through an address mapping table in a specific implementation manner of the present invention;

[0049] Figure 3 It is a structural schematic diagram of a system-level verification system for a chip register in the present invention. DETAILED DESCRIPTION

[0050] The core of the present invention is to provide a system-level verification method for a chip register, which can conveniently and effectively perform system-level verification of the chip register.

[0051] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0052] Please refer to Figure 1 , Figure 1 The following is a flow chart of an implementation of a system-level verification method for a chip register in the present invention. The system-level verification method for a chip register may include the following steps:

[0053] Step S101: Establish a one-to-one correspondence between each bus signal of the CPU of the chip under test and each interface signal of the verification platform, so that during the system-level verification of the registers of the chip under test, the bus signal of the CPU is replaced by the interface signal sent by the verification platform.

[0054] Specifically, the CPU of the chip under test can be hollowed out, that is, the CPU is removed, and then replaced with the interface signal of the verification platform. It can be understood that when replacing, a one-to-one correspondence between each bus signal of the CPU of the chip under test and each interface signal of the verification platform should be established, so that the interface signal sent by the verification platform can effectively replace the bus signal of the CPU. For example, Table 1 is a correspondence table between the bus signal of the CPU and the interface signal of the verification platform in a specific embodiment of the present invention.

[0055] Table 1:

[0056]

[0057]

[0058] In the implementation of Table 1, the bus signal of the CPU is specifically an AHB bus signal, and the interface signal of the verification platform adopts a VIP (verification IP) interface signal. In other implementations, other methods can be used to effectively replace the bus signal of the CPU through the interface signal sent by the verification platform.

[0059] Step S102: Generate a test case, and establish a corresponding register model for each register of the chip to be tested, and determine the actual address of each register according to a preset address mapping table.

[0060] In practical applications, the generation of test cases and the establishment of corresponding register models for each register of the chip to be tested can be achieved using the register model automatic generation tool. The specific content of the generated test cases can be set and adjusted according to actual needs.

[0061] The register model corresponds to the registers in the chip under test. It is a behavioral model of the real hardware registers in the software environment. This model can be used to easily read and write registers in the chip under test. The register model is mainly used to model registers and memories with address mapping in the chip under test. It can generate incentives to act on the chip under test and perform register function checks. Through the register model, it is possible to simply and efficiently implement front-door or back-door operations on the registers of the chip under test. In the UVM platform, the register model is highly abstract, and an intermediate variable uvm_reg_bus_op can be used to describe the access information of the register. Therefore, it is necessary to create a class inherited from uvm_reg_adapter to realize the mutual conversion between uvm_reg_bus_op and the transaction that actually acts on the specific chip under test.

[0062] In addition, in practical applications, after establishing corresponding register models for each register of the chip to be tested, these register models can be put into a general register model, which is a two-layer register model from a logical perspective.

[0063] In a real SoC (System on Chip) environment, the address space used by each register is completely different, that is, the actual physical address is the base address plus the offset address, which is the biggest difference from the module-level verification of the register. In the solution of this application, it is necessary to perform system-level verification of the registers of the chip to be tested, and it is necessary to be able to determine the actual physical address of each register to ensure the correct execution of the system-level verification.

[0064] Specifically, the solution of the present application can determine the actual address of each register according to a preset address mapping table, so that when performing system-level verification of the register, access to each register can be effectively achieved.

[0065] See also Figure 2 , which is a schematic diagram of reflecting the actual addresses of each register through an address mapping table in a specific implementation method. Figure 2 Uart0_reg_block, Uart1_reg_block and I2C_reg_block represent different register models. Taking Uart0_reg_block as an example, through the preset address mapping table, it can be determined that the base address of the register corresponding to the register model is 32'h1000_0000, and the offset address of the register can be obtained through the default address mapping deault_map. Therefore, the actual address of the register can be determined through the base address and offset address.

[0066] Furthermore, in a specific implementation of the present invention, the preset address mapping table includes base address information of the reserved area. Figure 2 In the implementation manner, Reserved 32'h3000_0000 represents the base address information of the reserved area, so that the reserved area can also be tested by using the front door or back door read and write operation of the register, thereby improving the flexibility and scalability of the solution.

[0067] Step S103: for the target register of the chip to be tested, execute the test case based on the register model corresponding to the target register to obtain the system-level verification result of the target register.

[0068] The target register can be any register in the chip to be tested. The test case can be executed based on the register model corresponding to the target register. Specifically, the sequence of the test case can be instantiated based on the register model corresponding to the target register, and then mounted on the interface signal of the verification platform. For example, the start function is used to mount it on the VIP interface signal of the verification platform, so as to perform system-level verification of the target register and obtain the system-level verification result of the target register.

[0069] In a specific implementation of the present invention, the generated test cases include: register default value test cases, register read and write test cases, and register bit test cases;

[0070] For the target register of the chip under test, the test case is executed based on the register model corresponding to the target register to obtain the system-level verification result of the target register, including:

[0071] For the target register of the chip to be tested, the register default value test case, register read and write test case, and register bit test case are executed in sequence based on the register model corresponding to the target register, and the default value test result of the target register, the read and write test result of the target register, and the bit test result of the target register are obtained in sequence.

[0072] In this implementation, the generated test cases include three, namely, a register default value test case, a register read and write test case, and a register bit test case. By executing these three test cases, the system-level verification results of the target register can be more comprehensively reflected.

[0073] Further, in a specific implementation of the present invention, executing a register default value test case based on a register model corresponding to a target register to obtain a default value test result of the target register may specifically include:

[0074] When the target register is a write-only register, a register default value test case is executed based on a register model corresponding to the target register, an actual default value of the target register is obtained in a back-door read manner, and only when the actual default value is consistent with a mirror value obtained by the register model corresponding to the target register, the default value test result of the target register is determined to be passed;

[0075] When the target register is not a write-only register, a register default value test case is executed based on the register model corresponding to the target register, and the actual default value of the target register is obtained by front-door reading. Only when the actual default value is consistent with the mirror value obtained by the register model corresponding to the target register, the default value test result of the target register is determined to be passed.

[0076] In this implementation manner, the method for determining the default value test result of the target register is different according to the type of the target register.

[0077] Specifically, when the target register is a write-only register, since it cannot be read directly through the bus, the actual default value of the target register is obtained by backdoor reading. For example, the actual default value of the target register can be obtained by backdoor reading using the mirror function. When the actual default value is consistent with the mirror value obtained by the register model corresponding to the target register, it can be determined that the default value test result of the target register is passed. Otherwise, it can be determined that the default value test result of the target register is not passed, which may be caused by an error in the connection relationship of the target register in the chip to be tested, abnormal reading and writing, and other reasons.

[0078] When the target register is not a write-only register, the actual default value of the target register can be obtained by front-end reading, and then compared with the mirror value obtained by the register model corresponding to the target register. When the two are consistent, it can be determined that the default value test result of the target register has passed. The default value of the target register refers to the value in the initial state when the target register does not store data.

[0079] In a specific implementation of the present invention, executing a register read / write test case based on a register model corresponding to a target register to obtain a read / write test result of the target register may include:

[0080] Execute a register read and write test case based on a register model corresponding to a target register, obtain an actual default value of the target register in a back-gate read manner, and generate first write data;

[0081] When the target register is a read-only register, the first write data is written in a back-gate write manner, and after the writing, it is read in a front-gate read manner, and only when the read value is consistent with the first write data, the register read-write test result of the target register is determined to be passed;

[0082] When the target register is a write-only register, the first write data is written in a front-gate write manner, and after writing, it is read in a back-gate read manner, and only when the read value is 0, the register read-write test result of the target register is determined to be passed;

[0083] When the target register is a read-write register, the first write data is written in a front-gate write manner, and after writing, it is read in a front-gate read manner, and only when the read value is consistent with the first write data, the register read-write test result of the target register is determined to be passed.

[0084] In this implementation manner, the manner of determining the read and write test results of the target register is different according to the type of the target register.

[0085] Specifically, the actual default value of the target register is first obtained by backdoor reading, and the first write data is generated, for example, the first write data is randomly generated.

[0086] If the target register is a read-only register, since it cannot be written through the bus, it is necessary to write the first write data to the target register in a back-door write manner, and read it in a front-door read manner after writing, and when the read value is consistent with the first write data, it can be determined that the register read and write test result of the target register has passed, otherwise it has failed.

[0087] If the target register is a write-only register, after writing the first write data, it cannot be read through the bus. Therefore, the value read by the back-door read method should theoretically be 0, otherwise it can be determined that the register read and write test result of the target register has failed.

[0088] If the target register is a read-write register, the first write data can be written in a front-door write manner, and the first write data can be read in a front-door read manner. When the read data is consistent with the written data, it can be determined that the register read-write test result of the target register is passed, otherwise it is failed.

[0089] Furthermore, in a specific embodiment of the present invention, it may also include:

[0090] After determining the register read / write test result of the target register, determining whether the register read / write test operation performed on the target register has caused a change in a value in any other register other than the target register;

[0091] If yes, then the first warning prompt is output.

[0092] In this implementation, considering that the solution of the present application is to perform system-level verification of registers, due to reasons such as wiring errors, it may cause the situation where other registers are affected when operating a single register. Therefore, in this implementation, after determining the register read and write test results of the target register, it can be further determined whether the operation of the register read and write test performed on the target register will affect the value in any register other than the target register. If it does, a first alarm prompt can be output to remind the staff to pay attention to the situation. In actual applications, whenever the register read and write test results of a register are determined, the operation of this implementation can be performed once to ensure the comprehensiveness of the system-level verification of registers performed by this application.

[0093] In a specific implementation of the present invention, executing a register bit test case based on a register model corresponding to a target register to obtain a bit test result of the target register may specifically include:

[0094] When the target register is a read-write register, for any bit of the target register, write the first inverse of the value corresponding to the bit in a front-gate write manner, and update the expected value in the register model of the target register to the first inverse;

[0095] Get the expected value after update through the get function;

[0096] Read the value of the bit where the first inverted number is written in the front door reading mode, and determine whether the value of the bit read in the front door reading mode is consistent with the expected value obtained by the get function;

[0097] If not, determining that the register bit test result of the target register is failed;

[0098] If yes, write the second inverted number corresponding to the first inverted number in a front-gate writing manner, and update the expected value in the register model of the target register to the second inverted number;

[0099] Get the expected value after update through the get function;

[0100] Read the value of the bit where the second inverse number is written in the front door reading mode, and determine whether the value of the bit read in the front door reading mode is consistent with the expected value obtained by the get function;

[0101] If not, determining that the register bit test result of the target register is failed;

[0102] If yes, then determining that the register bit test result of the target register is passed;

[0103] Among them, the inverse number corresponding to 0 is 1, and the inverse number corresponding to 1 is 0.

[0104] In this implementation, two inversion operations are performed so that after the bit test of the target register is performed, the value in the target register will not be changed.

[0105] Specifically, the bit test of the target register is only required when the target register is a read-write register. For any bit of the target register, write the first negation in the front-door writing mode. For example, if the default value of the bit is 1, the first negation is 0, and write 0 in the front-door writing mode. At the same time, the expected value in the register model of the target register is updated to 0. Then the updated expected value is obtained through the get function, and the value of the bit with the first negation 0 written is read in the front-door reading mode. Under normal circumstances, the value of the bit read in the front-door reading mode and the value obtained by the get function are both 0. Of course, if the two are inconsistent, it can be determined that the register bit test result of the target register is failed.

[0106] If the two are consistent, the second negation corresponding to the first negation is written in the front-door writing mode. In this example, the second negation 1 corresponding to the first negation 0 is written, and the expected value in the register model of the target register is updated to the second negation 1. Then the updated expected value is obtained through the get function, and the value of the bit where the second negation 1 is written is read in the front-door reading mode. Under normal circumstances, the value of the bit read in the front-door reading mode and the value obtained by the get function are both 1. Of course, if the two are inconsistent, it can be determined that the register bit test result of the target register is failed.

[0107] It can be seen that by writing the inverted number twice, after the register bit test of the target register is performed, the value of each bit of the target register remains the original value.

[0108] By applying the technical solution provided by the embodiment of the present invention, a one-to-one correspondence between each bus signal of the CPU of the chip to be tested and each interface signal of the verification platform will be established, so that in the process of system-level verification of the register of the chip to be tested, the bus signal of the CPU is replaced by the target interface signal sent by the verification platform, and the problem caused by the inability of the CPU to support various random operations on all module registers in the traditional solution will not occur. In addition, in the process of system-level verification of the register of the chip to be tested, the present application establishes corresponding register models for each register module of the chip to be tested to realize the system-level verification of the register, which can effectively improve the convenience and efficiency of verification. However, unlike the module-level verification, in the real SoC environment, the address space used by each register is completely different, that is, the actual physical address is the base address plus the offset address. When the corresponding register model is established for each register of the chip to be tested, only the offset address of each register can be obtained. Therefore, in the scheme of the present application, the actual address of each register will be determined according to the preset address mapping table, so that when the system-level verification of the register is performed, the access to each register can be effectively realized. In summary, the scheme of the present application can conveniently and effectively perform system-level verification of chip registers.

[0109] Corresponding to the above method embodiment, an embodiment of the present invention further provides a system-level verification system for a chip register, which can be referred to in correspondence with the above.

[0110] See also Figure 3 As shown, it is a schematic diagram of the structure of a system-level verification system for a chip register in the present invention, including:

[0111] The bus signal replacement unit 301 is used to establish a one-to-one correspondence between each bus signal of the CPU of the chip under test and each interface signal of the verification platform, so that during the system-level verification of the register of the chip under test, the bus signal of the CPU is replaced by the interface signal sent by the verification platform;

[0112] The configuration unit 302 is used to generate a test case, establish a corresponding register model for each register of the chip to be tested, and determine the actual address of each register according to a preset address mapping table;

[0113] The execution unit 303 is used to execute the test case for the target register of the chip under test based on the register model corresponding to the target register to obtain a system-level verification result of the target register.

[0114] In a specific implementation of the present invention, the generated test cases include: register default value test cases, register read and write test cases, and register bit test cases;

[0115] The execution unit 303 is specifically used for:

[0116] For the target register of the chip to be tested, the register default value test case, the register read and write test case, and the register bit test case are executed in sequence based on the register model corresponding to the target register, and the default value test result of the target register, the read and write test result of the target register, and the bit test result of the target register are obtained in sequence.

[0117] In a specific implementation of the present invention, the execution unit 303 executes the register default value test case based on the register model corresponding to the target register to obtain the default value test result of the target register, specifically including:

[0118] When the target register is a write-only register, executing the register default value test case based on the register model corresponding to the target register, obtaining the actual default value of the target register in a back-door read manner, and determining that the default value test result of the target register is passed only when the actual default value is consistent with the mirror value obtained by the register model corresponding to the target register;

[0119] When the target register is not a write-only register, the register default value test case is executed based on the register model corresponding to the target register, and the actual default value of the target register is obtained in a front-door read manner, and only when the actual default value is consistent with the mirror value obtained by the register model corresponding to the target register, the default value test result of the target register is determined to be passed.

[0120] In a specific implementation of the present invention, the execution unit 303 executes the register read and write test case based on the register model corresponding to the target register to obtain the read and write test result of the target register, including:

[0121] Executing the register read and write test case based on the register model corresponding to the target register, obtaining an actual default value of the target register in a back-door read manner, and generating first write data;

[0122] When the target register is a read-only register, the first write data is written in a back-door write manner, and after writing, it is read in a front-door read manner, and only when the read value is consistent with the first write data, the register read-write test result of the target register is determined to be passed;

[0123] When the target register is a write-only register, the first write data is written in a front-gate write manner, and after writing, it is read in a back-gate read manner, and only when the read value is 0, the register read-write test result of the target register is determined to be passed;

[0124] When the target register is a read-write register, the first write data is written in a front-door write manner, and is read in a front-door read manner after writing, and only when the read value is consistent with the first write data, the register read-write test result of the target register is determined to be passed.

[0125] In a specific implementation of the present invention, the execution unit 303 is further configured to:

[0126] After determining the register read / write test result of the target register, determining whether the register read / write test operation performed on the target register has caused a change in a value in any other register other than the target register;

[0127] If yes, then the first warning prompt is output.

[0128] In a specific implementation of the present invention, the execution unit 303 executes the register bit test case based on the register model corresponding to the target register to obtain the bit test result of the target register, including:

[0129] When the target register is a read-write register, for any bit of the target register, a first inverse number of the value corresponding to the bit is written in a front-gate writing manner, and the expected value in the register model of the target register is updated to the first inverse number;

[0130] Obtain the expected value after update through the get function;

[0131] Read the value of the bit where the first inverse number is written in a front-door reading manner, and determine whether the value of the bit read in the front-door reading manner is consistent with the expected value obtained by the get function;

[0132] If not, determining that the register bit test result of the target register is failed;

[0133] If yes, write a second inverted number corresponding to the first inverted number in a front-gate writing manner, and update the expected value in the register model of the target register to the second inverted number;

[0134] Obtain the expected value after update through the get function;

[0135] Read the value of the bit where the second inverse number is written in a front-door reading manner, and determine whether the value of the bit read in the front-door reading manner is consistent with the expected value obtained by the get function;

[0136] If not, determining that the register bit test result of the target register is failed;

[0137] If yes, determining that the register bit test result of the target register is passed;

[0138] Among them, the inverse number corresponding to 0 is 1, and the inverse number corresponding to 1 is 0.

[0139] In a specific implementation manner of the present invention, the preset address mapping table includes base address information of the reserved area.

[0140] Corresponding to the above method and system embodiments, an embodiment of the present invention further provides a system-level verification device for a chip register and a computer-readable storage medium, which can be referenced in correspondence with the above.

[0141] The system-level verification equipment of the chip register may include:

[0142] Memory for storing computer programs;

[0143] A processor is used to execute the computer program to implement the steps of the system-level verification method of the chip register as described in any of the above embodiments.

[0144] The computer readable storage medium stores a computer program, and when the computer program is executed by the processor, the steps of the system-level verification method of the chip register described in any of the above embodiments are implemented. The computer readable storage medium mentioned here includes random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the technical field.

[0145] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0146] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0147] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the technical solution and core ideas of the present invention. It should be pointed out that for ordinary technicians in this technical field, the present invention can also be improved and modified without departing from the principles of the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A system-level verification method for chip registers, It is characterized in that include: Establishing a one-to-one correspondence between each bus signal of the CPU of the chip under test and each interface signal of the verification platform, so that in the process of performing system-level verification of the register of the chip under test, the bus signal of the CPU is replaced by the interface signal sent by the verification platform; Generate test cases, and establish corresponding register models for each register of the chip to be tested, and determine the actual address of each register according to a preset address mapping table; For the target register of the chip to be tested, the test case is executed based on a register model corresponding to the target register to obtain a system-level verification result of the target register.

2. The system-level verification method for chip registers according to claim 1, It is characterized in that The generated test cases include: register default value test cases, register read and write test cases, and register bit test cases; The step of executing the test case for the target register of the chip under test based on a register model corresponding to the target register to obtain a system-level verification result of the target register includes: For the target register of the chip to be tested, the register default value test case, the register read and write test case, and the register bit test case are executed in sequence based on the register model corresponding to the target register, and the default value test result of the target register, the read and write test result of the target register, and the bit test result of the target register are obtained in sequence.

3. The system-level verification method for chip registers according to claim 2, It is characterized in that Executing the register default value test case based on the register model corresponding to the target register to obtain a default value test result of the target register includes: When the target register is a write-only register, executing the register default value test case based on the register model corresponding to the target register, obtaining the actual default value of the target register in a back-door read manner, and determining that the default value test result of the target register is passed only when the actual default value is consistent with the mirror value obtained by the register model corresponding to the target register; When the target register is not a write-only register, the register default value test case is executed based on the register model corresponding to the target register, and the actual default value of the target register is obtained in a front-door read manner, and only when the actual default value is consistent with the mirror value obtained by the register model corresponding to the target register, the default value test result of the target register is determined to be passed.

4. The system-level verification method for chip registers according to claim 2, It is characterized in that Executing the register read and write test case based on the register model corresponding to the target register to obtain the read and write test result of the target register includes: Executing the register read and write test case based on the register model corresponding to the target register, obtaining an actual default value of the target register in a back-door read manner, and generating first write data; When the target register is a read-only register, the first write data is written in a back-door write manner, and after writing, it is read in a front-door read manner, and only when the read value is consistent with the first write data, the register read-write test result of the target register is determined to be passed; When the target register is a write-only register, the first write data is written in a front-gate write manner, and after writing, it is read in a back-gate read manner, and only when the read value is 0, the register read-write test result of the target register is determined to be passed; When the target register is a read-write register, the first write data is written in a front-door write manner, and is read in a front-door read manner after writing, and only when the read value is consistent with the first write data, the register read-write test result of the target register is determined to be passed.

5. The system-level verification method for chip registers according to claim 4, It is characterized in that Also includes: After determining the register read / write test result of the target register, determining whether the register read / write test operation performed on the target register has caused a change in a value in any other register other than the target register; If yes, the first warning prompt is output.

6. The system-level verification method for chip registers according to claim 2, It is characterized in that Executing the register bit test case based on the register model corresponding to the target register to obtain the bit test result of the target register includes: When the target register is a read-write register, for any bit of the target register, a first inverse number of the value corresponding to the bit is written in a front-gate writing manner, and the expected value in the register model of the target register is updated to the first inverse number; Obtain the expected value after update through the get function; Read the value of the bit where the first inverse number is written in a front-door reading manner, and determine whether the value of the bit read in the front-door reading manner is consistent with the expected value obtained by the get function; If not, determining that the register bit test result of the target register is failed; If yes, write a second inverted number corresponding to the first inverted number in a front-gate writing manner, and update the expected value in the register model of the target register to the second inverted number; Obtain the expected value after update through the get function; Read the value of the bit where the second inverse number is written in a front-door reading manner, and determine whether the value of the bit read in the front-door reading manner is consistent with the expected value obtained by the get function; If not, determining that the register bit test result of the target register is failed; If yes, determining that the register bit test result of the target register is passed; Among them, the inverse number corresponding to 0 is 1, and the inverse number corresponding to 1 is 0.

7. The system-level verification method for chip registers according to claim 1, It is characterized in that The preset address mapping table includes base address information of the reserved area.

8. A system-level verification system for chip registers, It is characterized in that include: A bus signal replacement unit, used to establish a one-to-one correspondence between each bus signal of the CPU of the chip under test and each interface signal of the verification platform, so that in the process of system-level verification of the register of the chip under test, the bus signal of the CPU is replaced by the interface signal sent by the verification platform; A configuration unit, used to generate test cases, establish corresponding register models for each register of the chip to be tested, and determine the actual address of each register according to a preset address mapping table; The execution unit is used to execute the test case for the target register of the chip to be tested based on the register model corresponding to the target register to obtain the system-level verification result of the target register.

9. A system-level verification device for chip registers, It is characterized in that include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the system-level verification method for a chip register as described in any one of claims 1 to 7.

10. A computer-readable storage medium, It is characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the system-level verification method for a chip register as described in any one of claims 1 to 7 are implemented.

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