A Layout Structure Design Method for High-Precision DCOC

Abstract

The present invention discloses a layout structure design method for a highly accurate DCOC. The overall layout is centrosymmetrically distributed. The MOS transistors of the Q path are distributed in the upper left to lower right diagonal direction, and the MOS transistors of the I path are distributed in the upper right to lower left diagonal direction. Dummy MOS transistors are distributed on the outermost side of the entire DCOC; dummy MOS transistors are distributed in the middle of the left and right layouts of the entire layout structure; dummy MOS transistors are distributed on the diagonals of the entire layout; in the left and right layouts of the layout, the number of MOS transistors of each multiple current source in the I path is the same as that of the MOS transistors of each multiple current source in the Q path. By adopting the centrosymmetric matching method, the present invention not only reduces the signal mismatch caused by the process from the aspect of layout, reduces the layout area, and then improves the performance index of the frequency divider, but also improves the work efficiency of the layout designer from the design method.

Description

Technical Field

[0001] The present invention relates to the technical field of layout design of DCOC, and specifically to a layout structure design method for high-precision DCOC. Background Art

[0002] DCOC (Direct Current Offset Calibration) is an auxiliary circuit that assists the receiver to work. It can eliminate the DC mismatch of the receiver, thereby ensuring the normal operation of the receiver and stabilizing the circuit performance of the receiver.

[0003] With the widespread use of DCOC in the field of radio frequency communication, its performance indicators are getting higher and higher, and the rationality of the layout is becoming more and more critical. Generally, the DCOC layout adopts a left-right symmetric manner for the IQ two paths, which is prone to process mismatch, thus affecting the performance indicators of DCOC. Summary of the Invention

[0004] The purpose of the present invention is to provide a layout structure design method for high-precision DCOC, which adopts a central symmetric structure layout method to suppress process errors, so that each current source is affected by almost the same process error, in order to solve the problems raised in the above background art.

[0005] To achieve the above purpose, the present invention provides the following technical solutions:

[0006] A layout structure design method for high-precision DCOC, the overall layout of the layout adopts a central symmetric distribution. The mosfets of the Q path are distributed in the upper left to lower right diagonal direction, and the mosfets of the I path are distributed in the upper right to lower left diagonal direction. Dummy mosfets are distributed on the outermost side of the entire DCOC; dummy mosfets are distributed in the middle of the left and right sides of the entire layout structure; dummy mosfets are distributed at the diagonal corners of the entire layout; the left side layout of the layout is symmetrically arranged up and down with the mosfet of the 1-fold current source of the Q path, the mosfet of the 8-fold current source of the Q path, the mosfet of the 32-fold current source of the Q path, and the dummy mosfet as the center line; the right side layout of the layout is symmetrically arranged up and down with the mosfet of the 1-fold current source of the I path, the mosfet of the 8-fold current source of the I path, the mosfet of the 32-fold current source of the I path, and the dummy mosfet as the center line.

[0007] Further, in the layout on the left side of the layout, the overall is symmetrically arranged up and down along the middle MOS transistor. 1 represents the MOS transistor of the Q-channel 1x current source, 2 represents the MOS transistor of the Q-channel 2x current source, and its quantity is one-half of the total number of the entire layout. 4 represents the MOS transistor of the Q-channel 4x current source, and its quantity is one-half of the total number of the entire layout. 8 represents the MOS transistor of the Q-channel 8x current source, and its quantity is one-half of the total number of the entire layout. 16 represents the MOS transistor of the Q-channel 16x current source, and its quantity is one-half of the total number of the entire layout. 32 represents the MOS transistor of the Q-channel 32x current source, and its quantity is one-half of the total number of the entire layout. 64 represents the MOS transistor of the Q-channel 64x current source, and its quantity is one-half of the total number of the entire layout. 2` represents the MOS transistor of the I-channel 2x current source, and its quantity is one-half of the total number of the entire layout. 4` represents the MOS transistor of the I-channel 4x current source, and its quantity is one-half of the total number of the entire layout. 8` represents the MOS transistor of the I-channel 8x current source, and its quantity is one-half of the total number of the entire layout. 16` represents the MOS transistor of the I-channel 16x current source, and its quantity is one-half of the total number of the entire layout. 32` represents the MOS transistor of the I-channel 32x current source, and its quantity is one-half of the total number of the entire layout. 64` represents the MOS transistor of the I-channel 64x current source, and its quantity is one-half of the total number of the entire layout.

[0008] Further, in the layout on the right side of the layout, the overall is symmetrically arranged up and down along the middle MOS transistor. 1` represents the MOS transistor of the I-channel 1x current source, 2` represents the MOS transistor of the I-channel 2x current source, and its quantity is one-half of the total number of the entire layout. 4` represents the MOS transistor of the I-channel 4x current source, and its quantity is one-half of the total number of the entire layout. 8` represents the MOS transistor of the I-channel 8x current source, and its quantity is one-half of the total number of the entire layout. 16` represents the MOS transistor of the I-channel 16x current source, and its quantity is one-half of the total number of the entire layout. 32` represents the MOS transistor of the I-channel 32x current source, and its quantity is one-half of the total number of the entire layout. 64` represents the MOS transistor of the I-channel 64x current source, and its quantity is one-half of the total number of the entire layout. 2 represents the MOS transistor of the Q-channel 2x current source, and its quantity is one-half of the total number of the entire layout. 4 represents the MOS transistor of the Q-channel 4x current source, and its quantity is one-half of the total number of the entire layout. 8 represents the MOS transistor of the Q-channel 8x current source, and its quantity is one-half of the total number of the entire layout. 16 represents the MOS transistor of the Q-channel 16x current source, and its quantity is one-half of the total number of the entire layout. 32 represents the MOS transistor of the Q-channel 32x current source, and its quantity is one-half of the total number of the entire layout. 64 represents the MOS transistor of the Q-channel 64x current source, and its quantity is one-half of the total number of the entire layout.

[0009] The present invention adopts a central symmetry matching method, reduces signal mismatch caused by the process, has a compact layout, simple wiring, and a small layout area. The present invention not only reduces the signal mismatch caused by the process from the layout aspect, reduces the layout area, and then improves the performance index of the frequency divider, but also improves the work efficiency of the layout designer from the design method. Brief Description of the Drawings

[0010] Figure 1 It is a schematic structural diagram of the left layout in a layout structure design method of a high-precision DCOC.

[0011] Figure 2 It is a schematic structural diagram of the right layout in a layout structure design method of a high-precision DCOC.

[0012] Figure 3 It is the overall layout of the high-precision DCOC of the present invention. Detailed Description of the Invention

[0013] The technical solutions of this patent will be further described in detail below in conjunction with the specific embodiments.

[0014] Please refer to Figures 1-3 , a layout structure design method of a high-precision DCOC, adopts a central symmetry structure layout method, which can suppress process errors, so that each current source is affected by almost the same process error, greatly improving the performance index of the DCOC.

[0015] The left layout of the present invention is as shown in Figure 1 . The whole is symmetrically arranged up and down along the middle MOS transistor. 1 represents the MOS transistor of the Q-channel 1-fold current source, 2 represents the MOS transistor of the Q-channel 2-fold current source, and its quantity is one-half of the total number of the whole layout. 4 represents the MOS transistor of the Q-channel 4-fold current source, and its quantity is one-half of the total number of the whole layout. 8 represents the MOS transistor of the Q-channel 8-fold current source, and its quantity is one-half of the total number of the whole layout. 16 represents the MOS transistor of the Q-channel 16-fold current source, and its quantity is one-half of the total number of the whole layout. 32 represents the MOS transistor of the Q-channel 32-fold current source, and its quantity is one-half of the total number of the whole layout. 64 represents the MOS transistor of the Q-channel 64-fold current source, and its quantity is one-half of the total number of the whole layout; 2` represents the MOS transistor of the I-channel 2-fold current source, and its quantity is one-half of the total number of the whole layout. 4` represents the MOS transistor of the I-channel 4-fold current source, and its quantity is one-half of the total number of the whole layout. 8` represents the MOS transistor of the I-channel 8-fold current source, and its quantity is one-half of the total number of the whole layout. 16` represents the MOS transistor of the I-channel 16-fold current source, and its quantity is one-half of the total number of the whole layout. 32` represents the MOS transistor of the I-channel 32-fold current source, and its quantity is one-half of the total number of the whole layout. 64` represents the MOS transistor of the I-channel 64-fold current source, and its quantity is one-half of the total number of the whole layout.

[0016] The right layout is as Figure 2 shown, and the whole is symmetrically arranged up and down along the middle MOS transistor. 1` represents the MOS transistor of the I-channel 1x current source, 2` represents the MOS transistor of the I-channel 2x current source, and its quantity is one-half of the total number of the whole layout. 4` represents the MOS transistor of the I-channel 4x current source, and its quantity is one-half of the total number of the whole layout. 8` represents the MOS transistor of the I-channel 8x current source, and its quantity is one-half of the total number of the whole layout. 16` represents the MOS transistor of the I-channel 16x current source, and its quantity is one-half of the total number of the whole layout. 32` represents the MOS transistor of the I-channel 32x current source, and its quantity is one-half of the total number of the whole layout. 64` represents the MOS transistor of the I-channel 64x current source, and its quantity is one-half of the total number of the whole layout. 2 represents the MOS transistor of the Q-channel 2x current source, and its quantity is one-half of the total number of the whole layout. 4 represents the MOS transistor of the Q-channel 4x current source, and its quantity is one-half of the total number of the whole layout. 8 represents the MOS transistor of the Q-channel 8x current source, and its quantity is one-half of the total number of the whole layout. 16 represents the MOS transistor of the Q-channel 16x current source, and its quantity is one-half of the total number of the whole layout. 32 represents the MOS transistor of the Q-channel 32x current source, and its quantity is one-half of the total number of the whole layout. 64 represents the MOS transistor of the Q-channel 64x current source, and its quantity is one-half of the total number of the whole layout.

[0017] Figure 3 The overall layout of DCOC adopts a central symmetry distribution. The MOS transistors of the Q-channel are distributed in the upper left - lower right diagonal direction, and the MOS transistors of the I-channel are distributed in the upper right - lower left diagonal direction. The dummy MOS transistors are distributed on the outermost side of the whole DCOC. Adopting the central symmetry matching method can reduce the signal mismatch caused by the process, with a compact layout, simple wiring, and a small layout area.

[0018] Dummy MOS transistors are distributed at the diagonals of the whole layout. The left layout of the layout is symmetrically arranged up and down with the MOS transistors of the Q-channel 1x current source, Q-channel 8x current source, Q-channel 32x current source, and dummy MOS transistors in the middle as the center line. The right layout of the layout is symmetrically arranged up and down with the MOS transistors of the I-channel 1x current source, I-channel 8x current source, I-channel 32x current source, and dummy MOS transistors in the middle as the center line.

[0019] The MOS transistors in the overall layout are designed in a form that diverges from the center. Generally, the low - multiple current source MOS transistors are roughly located inside the high - multiple current source MOS transistors.

[0020] In the layouts on the left and right sides of the layout, excluding the MOS transistors on the up - down symmetry center line, the quantities of the MOS transistors of each multiple current source in the I-channel are the same as those of the MOS transistors of each multiple current source in the Q-channel.

[0021] The above describes in detail the preferred embodiments of the present patent. However, the present patent is not limited to the above embodiments, and various changes can be made without departing from the gist of the present patent within the knowledge scope of those of ordinary skill in the art.

Claims

1. A layout structure design method for a highly accurate DCOC, characterized in that The overall layout of the layout adopts a central symmetry distribution. The MOS transistors of the Q path are distributed in the diagonal direction from the upper left to the lower right, and the MOS transistors of the I path are distributed in the diagonal direction from the upper right to the lower left. Dummy MOS transistors are distributed on the outermost side of the entire DCOC; dummy MOS transistors are distributed in the middle of the left and right sides of the entire layout structure; dummy MOS transistors are distributed at the diagonals of the entire layout; the left side layout of the layout is symmetrically arranged up and down with the MOS transistors of the 1x current source of the Q path, the 8x current source MOS transistors of the Q path, the 32x current source MOS transistors of the Q path, and the dummy MOS transistors as the center line; the right side layout of the layout is symmetrically arranged up and down with the MOS transistors of the 1x current source of the I path, the 8x current source MOS transistors of the I path, the 32x current source MOS transistors of the I path, and the dummy MOS transistors as the center line.

2. The layout structure design method of a high-precision DCOC according to claim 1, characterized in that In the overall layout of the layout, the MOS transistor of the 1x current source of the Q path is labeled 1, the MOS transistor of the 2x current source of the Q path is labeled 2, the MOS transistor of the 4x current source of the Q path is labeled 4, the MOS transistor of the 8x current source of the Q path is labeled 8, the MOS transistor of the 16x current source of the Q path is labeled 16, the MOS transistor of the 32x current source of the Q path is labeled 32, and the MOS transistor of the 64x current source of the Q path is labeled 64; the MOS transistor of the 1x current source of the I path is labeled 1`, the MOS transistor of the 2x current source of the I path is labeled 2`, the MOS transistor of the 4x current source of the I path is labeled 4`, the MOS transistor of the 8x current source of the I path is labeled 8`, the MOS transistor of the 16x current source of the I path is labeled 16`, the MOS transistor of the 32x current source of the I path is labeled 32`, and the MOS transistor of the 64x current source of the I path is labeled 64`.

3. A layout structure design method for a high-precision DCOC according to claim 1, characterized in that In the layouts on the left and right sides of the layout, the number of MOS transistors of each multiple current source in the I path is the same as that of the MOS transistors of each multiple current source in the Q path.

4. A layout structure design method for a high-precision DCOC according to claim 1, characterized in that The MOS transistors in the overall layout are designed in a form that diverges from the center, and the low-current-source MOS transistors are located inside the high-current-source MOS transistors.

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