Circuit and method for implementing convolution operation

Abstract

The present invention provides a circuit for implementing convolution operations, including an encoding module, a digital-to-analog conversion module, a memory array, a reference array, an adjustment module, a symbol column processing module, and a calculation module; the encoding module is used to obtain a sign bit and a weight code; the digital-to-analog conversion module is used to convert an input digital signal into a voltage signal; the memory array is used to map the weight code and output a first current signal; the adjustment module is used to obtain the first current signal based on the first current signal; the symbol column processing module is used to obtain a symbol column and output a symbol column output value; and the calculation module is used to obtain a convolution output value. The circuit for implementing convolution operations provided by the present invention saves the amount of memory, reduces the complexity of convolution operations, and improves the efficiency and accuracy of convolution operations. The present invention also provides a method for implementing convolution operations.

Description

Technical Field

[0001] The present invention relates to the fields of digital circuits and analog circuits, and in particular to a circuit and method for implementing convolution operations. Background Art

[0002] Implementing convolutional neural networks using resistive random access memory (RRAM) circuits requires quantizing the neural network's inputs and weights. The inputs to RRAM circuits are typically positive numbers. The previous layer, an activation function, is first quantized to positive integers and then converted to voltages via a DAC as the circuit input. Weights can be either positive or negative, and there are several common methods for mapping them to RRAM conductivity: First, using an asymmetric quantization algorithm, quantizing the weights to positive integers and then directly mapping them to RRAM conductivity. This method requires additional circuitry to handle the shift factor, increasing circuit complexity. Second, using a symmetric quantization algorithm, quantizing the weights to integers (both positive and negative) and using RRAM pairs to represent positive and negative values ​​requires a larger amount of memory, increasing circuit complexity and cost.

[0003] Therefore, it is necessary to provide a circuit and method for implementing convolution operation to solve the above-mentioned problems in the prior art. Summary of the Invention

[0004] The purpose of the present invention is to provide a circuit and method for implementing convolution operations to solve the problem that the circuit for implementing convolutional neural network operations requires more memory.

[0005] To achieve the above-mentioned object, the circuit for implementing convolution operation of the present invention includes an encoding module, a digital-to-analog conversion module, a memory array, an adjustment module, a symbol column processing module and a calculation module;

[0006] The encoding module is used to obtain a sign bit according to the range of the quantized weight signal, and encode the quantized weight signal to obtain a weight code;

[0007] The digital-to-analog conversion module is used to convert an externally input digital signal into a voltage signal, and transmit the voltage signal to the memory array as an input of the memory array;

[0008] The memory array is used to map the weight code, and after receiving the voltage signal, each column of the memory array outputs a first current signal;

[0009] The adjustment module is used to obtain a first output signal according to the first current signal;

[0010] The sign column processing module is configured to obtain a sign column according to the sign bit, the sign column being a column in the memory array where the sign bit is located, and output a sign column output value according to the sign column and the first output signal;

[0011] The calculation module is used to obtain a convolution output value according to the symbol column output value and the first output signal.

[0012] The beneficial effects of the circuit for implementing convolution operation of the present invention are:

[0013] The encoding module encodes the quantized weight signal to obtain a weight code and obtains a sign bit; the adjustment module obtains a first output signal, the sign column is obtained by the sign column processing module, and a sign column output value is output based on the sign column and the first output signal, so that the memory array can map both positive integer weights and negative integer weights, thereby eliminating the need to use a resistive memory pair method to represent the positive and negative values ​​of the weights, saving the amount of memory, solving the problem that a circuit for implementing convolutional neural network operations requires a large number of resistive memories, reducing the complexity of convolution operations, and improving the efficiency and accuracy of convolution operations.

[0014] Optionally, the memory array includes several convolution kernel mapping units, each of the convolution kernel mapping units maps one of the weight codes, each of the convolution kernel mapping units includes one of the symbol columns and several non-symbol columns, and the symbol column and the non-symbol columns respectively output the first current signal.

[0015] Optionally, the symbol column processing module is connected to the output end of the symbol column and is configured to perform a negation operation on the first output signal output by the symbol column to output the symbol column output value. This advantageously allows the memory array to map both positive and negative integer weights, thereby reducing the amount of memory required, reducing the complexity of convolution operations, improving the efficiency and accuracy of convolution operations, and saving circuit board area and cost.

[0016] Optionally, the symbol column and the non-symbol column each include m first storage units, where m is a positive integer;

[0017] All the first storage units in the same row are connected and receive an input voltage signal;

[0018] All the first storage units in the same column are connected.

[0019] Optionally, the circuit for implementing the convolution operation further includes a reference array, the reference array being connected to an output end of the digital-to-analog conversion module to receive the voltage signal, the output end of the reference array being connected to the adjustment module, and the output end of the adjustment module being connected to the symbol column processing module;

[0020] The adjustment module adjusts the first current signal according to the reference current signal to obtain the first output signal.

[0021] Optionally, the reference array includes m second storage units distributed in a column, where m is a positive integer, and each second storage unit is connected to the first storage unit in the same column.

[0022] Optionally, the adjustment module includes a current subtraction circuit, a first current-to-voltage conversion unit, and a first analog-to-digital conversion unit;

[0023] The input end of the current subtraction circuit is connected to the current output end of the memory array and the current output end of the reference array, and the current subtraction circuit is used to perform a subtraction operation on the first current signal output by each column of the memory array and the reference current signal to output a plurality of second current signals;

[0024] An input end of the first current-to-voltage unit is connected to an output end of the current subtraction circuit, and the first current-to-voltage unit is used to convert the second current signal into a first voltage signal;

[0025] The input end of the first analog-to-digital conversion unit is connected to the output end of the first current-to-voltage conversion unit, and the first analog-to-digital conversion unit is used to perform analog-to-digital signal conversion on the first voltage signal to output the first output signal. Its beneficial effect is that, because the first current signal output by each column of the memory array is equal to the multiplication and addition result of the voltage and conductivity of the storage cell in the current column, the first current signal affects the first output signal, and the first output signal affects the final output value of the convolution operation. Therefore, the leakage current generated by the memory array will affect the final output value of the convolution operation. The leakage current is the current generated by the high-resistance storage cell in the memory array. The current subtraction circuit performs subtraction operations on the first current signal output by each column of the memory array and the reference current signal to output a plurality of second current signals, thereby reducing the leakage current in the memory array and weakening the influence of the leakage current on the first output signal, thereby avoiding the influence of the leakage current generated in the memory array on the convolution operation result, and improving the accuracy of the convolution operation.

[0026] Optionally, the adjustment module includes a second current-to-voltage unit, a third current-to-voltage unit, a second analog-to-digital conversion unit, a third analog-to-digital conversion unit, and a digital domain subtractor;

[0027] An input end of the second current-to-voltage unit is connected to a current output end of the memory array, an output end of the second current-to-voltage unit is connected to an input end of the second analog-to-digital conversion unit, the second current-to-voltage unit is used to convert the first current signal into a second voltage signal, and the second analog-to-digital conversion unit is used to convert the second voltage signal into a first digital signal;

[0028] The input end of the third current-to-voltage unit is connected to the current output end of the reference array, the output end of the third current-to-voltage unit is connected to the input end of the third analog-to-digital conversion unit, the third current-to-voltage unit is used to convert the reference current signal into a third voltage signal, and the third analog-to-digital conversion unit is used to convert the third voltage signal into a second digital signal;

[0029] The output end of the second analog-to-digital conversion unit is connected to the first input end of the digital domain subtractor, and the output end of the third analog-to-digital conversion unit is connected to the second input end of the digital domain subtractor. The digital domain subtractor is used to perform a subtraction operation on the first digital signal and the second digital signal to output the first output signal. Its beneficial effect is that the first current signal and the reference current signal are converted into a second voltage signal and a third voltage signal respectively by the second current-to-voltage unit and the third current-to-voltage unit, and the second voltage signal and the third voltage signal are converted into a first digital signal and a second digital signal respectively by the second analog-to-digital conversion unit and the third analog-to-digital conversion unit; the first digital signal and the second digital signal are subtracted by the digital domain subtractor to output the first output signal, thereby reducing leakage current in the memory array, weakening the impact of the leakage current on the final result of the convolution operation, and improving the accuracy of the convolution operation.

[0030] The present invention also provides a method for implementing a convolution operation, comprising the steps of:

[0031] Obtaining a sign bit according to a range of the quantized weight signal, and encoding the quantized weight signal to obtain a weight code;

[0032] mapping the weight codes through a memory array;

[0033] Converting an input digital signal into a voltage signal as an input voltage signal of the memory array, so that each column of the memory array outputs a first current signal;

[0034] obtaining a first output signal according to the first current signal;

[0035] Obtaining a sign column according to the sign bit, the sign column being a column in the memory array where the sign bit is located, and outputting a sign column output value according to the sign column and the first output signal;

[0036] A convolution output value is obtained according to the symbol column output value and the first output signal.

[0037] The method for implementing convolution operation of the present invention has the following beneficial effects:

[0038] The quantized weight signal is encoded to obtain a weight code and a sign bit, and the weight code is mapped through a memory array; the input digital signal is converted into a voltage signal as the input voltage signal of the memory array, so that each column of the memory array outputs a first current signal; a first output signal is obtained according to the first current signal; a sign column is obtained according to the sign bit, and a sign column output value is output according to the sign column and the first output signal; a convolution output value is obtained according to the sign column output value and the first output signal; and positive integer weights and negative integer weights are mapped through a memory array, thereby saving the amount of memory and improving the efficiency and accuracy of the convolution operation.

[0039] Optionally, the step of obtaining a first output signal according to the first current signal includes:

[0040] A reference current signal is set to adjust the first current signal to obtain the first output signal.

[0041] Optionally, the step of setting a reference current signal to adjust the first current signal to obtain a first output signal includes:

[0042] performing a subtraction operation on the first current signal outputted by each column of the memory array and the reference current signal to obtain a plurality of second current signals;

[0043] converting the second current signal into a first voltage signal;

[0044] Performing analog-to-digital conversion on the first voltage signal to output the first output signal has the beneficial effect of reducing the influence of leakage current on the convolution operation result and improving the accuracy of the convolution operation.

[0045] Optionally, the step of setting a reference current signal to adjust the first current signal to obtain a first output signal includes:

[0046] converting the first current signal into a second voltage signal, and converting the second voltage signal into a first digital signal;

[0047] Converting the reference current signal into a third voltage signal, and converting the third voltage signal into a second digital signal;

[0048] A subtraction operation is performed on the first digital signal and the second digital signal to output the first output signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 A block diagram of a circuit for implementing a convolution operation according to an embodiment of the present invention;

[0050] Figure 2 A circuit diagram of a circuit for implementing a convolution operation according to an embodiment of the present invention;

[0051] Figure 3 Schematic diagram of convolution operation according to an embodiment of the present invention;

[0052] Figure 4 This is a structural diagram of an adjustment module in a first embodiment of the present invention;

[0053] Figure 5 Schematic diagram of the current subtraction circuit structure according to an embodiment of the present invention;

[0054] Figure 6 This is a schematic diagram of the structure of the adjustment module in the second implementation mode of the embodiment of the present invention;

[0055] Figure 7 Flowchart of a method for implementing a convolution operation according to an embodiment of the present invention;

[0056] Figure 8 This is a flow chart of obtaining a first output signal in a first implementation manner of an embodiment of the present invention;

[0057] Figure 9 This is a flowchart of obtaining a first output signal in the second implementation manner of an embodiment of the present invention. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be the common meanings understood by people with ordinary skills in the field to which the invention belongs. The words "including" and similar words used in this article mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0059] In order to solve the problems existing in the prior art, the present invention provides a circuit for implementing convolution operation. Figure 1 This is a structural block diagram of a circuit for implementing convolution operations according to an embodiment of the present invention.

[0060] Reference Figure 1 The circuit for implementing convolution operation of the present invention includes an encoding module 1, a digital-to-analog conversion module 5, a memory array 2, an adjustment module 4, a symbol column processing module 6 and a calculation module 7;

[0061] The encoding module 1 is used to obtain a sign bit according to the range of the quantized weight signal, and encode the quantized weight signal to obtain a weight code;

[0062] The digital-to-analog conversion module 5 is used to convert an external input digital signal into a voltage signal, and transmit the voltage signal to the memory array 2 as an input voltage signal of the memory array 2;

[0063] The memory array 2 is used to map the weight code, and after receiving the input voltage signal, each column of the memory array 2 outputs a first current signal;

[0064] The adjustment module 4 is used to obtain a first output signal according to the first current signal;

[0065] The sign column processing module 6 is configured to obtain a sign column according to the sign bit and the first output signal, the sign column being a column in the memory array 2 where the sign bit is located, and output a sign column output value according to the sign column and the first output signal;

[0066] The calculation module 7 is used to obtain a convolution output value according to the symbol column output value and the first output signal.

[0067] The advantages of the circuit for implementing convolution operation of the present invention are: the quantized weight signal is encoded by the encoding module 1 to obtain a weight code, and a sign bit is obtained; the first output signal is obtained by the adjustment module 4, the sign column is obtained by the sign column processing module 6, and the sign column output value is output based on the sign column and the first output signal, so that the memory array 2 can map both positive integer weights and negative integer weights, thereby eliminating the need to use a resistive memory pair method to represent the positive and negative values ​​of the weights, saving the amount of memory, solving the problem that the circuit for implementing convolutional neural network operation requires a large number of resistive memories, reducing the complexity of the convolution operation, and improving the efficiency and accuracy of the convolution operation.

[0068] Figure 2 FIG4 is a circuit diagram of a circuit for implementing a convolution operation according to an embodiment of the present invention.

[0069] In some specific embodiments, referring to Figure 1 and Figure 2The encoding module 1 is used to encode the quantized weight signal to obtain the weight code, and the step of obtaining the sign bit according to the range of the quantized weight signal includes:

[0070] The quantized integer weight is encoded as:

[0071]

[0072] in: is the quantized weight, is the number of resistance states of RRAM, ,Will Mapped to the corresponding resistance value, so that the weight is represented by RRAM, Indicates RRAM is used to map one weight, that is, m weights need m rows and n columns of RRAM to represent, where m is a positive integer; it is determined according to the value of i. The value of The calculation formula is:

[0073]

[0074] else indicates that the value of i is an integer other than i=j, j is the specified sign bit, and the position of the sign bit is determined according to the range of the weight signal.

[0075] In some specific embodiments, the step of determining the sign bit according to the range of the weight signal includes:

[0076] When the quantization accuracy of the weight signal is 8 bits (i.e., 8 RRAMs are used to map one weight, n=8), and the number of resistance states of the RRAM is 2 (i.e., k=2), the original range of the weight signal can be considered to be , shifting the data range of the weight signal to a data range with positive and negative integers;

[0077] like When calculating the step size, the step size is: 0-(-127)=255-128=127;

[0078] Obviously 127=2 7 -1=2 8 -129,2 7 is the number closest to 127 and greater than 127, so the sign bit j=7. According to the above encoding method, the specific value can be expressed as:

[0079] -127=(-1) 0 ×1×2 0 +(-1) 0×0×2 1 +(-1) 0 ×0×2 2 +(-1) 0 ×0×2 3 +(-1) 0 ×0×2 4 +(-1) 0 ×0×2 5 +(-1) 0 ×0×2 6 +(-1) 1 ×1×2 7 ;

[0080] 40=(-1) 0 ×0×2 0 +(-1) 0 ×0×2 1 +(-1) 0 ×0×2 2 +(-1) 0 ×1×2 3 +(-1) 0 ×0×2 4 +(-1) 0 ×1×2 5 +(-1) 0 ×0×2 6 +(-1) 1 ×0×2 7 ;

[0081] Similarly, if , we can calculate the sign bit j=3, and 40 can be expressed as:

[0082] 40=(-1) 0 ×0×2 0 +(-1) 0 ×0×2 1 +(-1) 0 ×0×2 2 +(-1) 1 ×1×2 3 +(-1) 0 ×1×2 4 +(-1) 0 ×1×2 5 +(-1) 0 ×0×2 6 +(-1) 0 ×0×2 7 .

[0083] As an optional embodiment of the present invention, refer to Figure 2The memory array 2 includes a plurality of convolution kernel mapping units 20, each of which maps a weight code. Each convolution kernel mapping unit 20 includes a symbol column 201 and a plurality of non-symbol columns. The symbol column 201 and the plurality of non-symbol columns respectively output the first current signal, wherein the non-symbol column is a column in the convolution kernel mapping unit 20 other than the symbol column 201.

[0084] As an optional embodiment of the present invention, the symbol column 201 and the non-symbol column each include m first storage units 202, where m is a positive integer;

[0085] All the first storage units 202 in the same row are connected and receive the input voltage signal;

[0086] All the first storage units 202 in the same column are connected.

[0087] In some embodiments, the first storage unit 202 is an RRAM. The resistance state of the RRAM is not limited to high resistance and low resistance, but can also be a multi-resistance RRAM. For example, a binary RRAM has only two states, high resistance and low resistance, which can represent 0 and 1. In this case, the number of resistance states of the RRAM is 2.

[0088] In addition to high-resistance and low-resistance states, multi-value RRAM also has intermediate states. For example, the resistance values ​​of a multi-value RRAM are 6000Ω, 600Ω, 300Ω, and 200Ω, which can represent 0, 1, 2, and 3 respectively. The number of resistance states of this multi-value RRAM is 4.

[0089] In some embodiments, the conductivity of the RRAM is related to the input voltage and the output current as follows:

[0090] ;

[0091]

[0092] Where R is the resistance of RRAM, G is the conductivity of RRAM, I is the output current of RRAM, and U is the input voltage of RRAM;

[0093] As can be seen from the above formula, after conversion by the memory array 2, the current ultimately output by each column of RRAM is the first current signal, and the final output current value of each convolution kernel mapping unit 20 is equal to the product of the input voltage of all columns of RRAM and the conductivity of the current column of RRAM. Since the input voltage of the RRAM corresponds to the input digital signal, and the first current signal corresponds to the convolution output value after conversion by the analog-to-digital converter, different positive integer weights and negative integer weights can be mapped through RRAM arrays of different conductivities.

[0094] In the present application, an encoding rule is also set, which is: the range of all RRAM mappings in the symbol column is larger than the range of the weight signal, so that an array composed of fewer RRAMs can map a weight signal, that is, a weight signal can be represented by fewer RRAMs, saving the number of RRAMs and chip area, and saving power consumption.

[0095] Figure 3 Schematic diagram of convolution operation in an embodiment of the present invention, where Input is the digital signal input by convolution, Weight is the weight signal, and Output is the digital signal output by convolution.

[0096] In some specific embodiments, referring to Figure 2 and Figure 3 , the convolution weight is 1 and -2, j=0, For 2, encode 1: 1=(-4)×0+2×0+1×1, encode -2: -2=(-4)×1+2×1+1×0;

[0097] The weight weight is mapped to the RRAM array, where m is 2 and n is 3. The weight weight is mapped through the memory array 2, which includes several columns of RRAM, including high-resistance RRAM and low-resistance RRAM. The conductivity of the low-resistance RRAM is set to 1, and the number 1 is mapped through the low-resistance RRAM. The conductivity of the high-resistance RRAM is set to 0.1, and the number 0 is mapped through the high-resistance RRAM.

[0098] The convolution input digital signals Input are 1 and 2. After 1 is converted into a voltage signal through the digital-to-analog conversion module 5, it is input into all the first storage units 202 in the first row as the input voltage of the first storage units 202 in the first row; after 2 is converted into a voltage signal through the digital-to-analog conversion module 5, it is input into the first storage unit 202 in the second row as the input voltage of the first storage unit 202 in the second row.

[0099] In some embodiments, the digital-to-analog conversion module 5 of the present invention is a digital-to-analog converter (DAC), which converts an external input digital signal into a voltage signal through the DAC to serve as the input of the memory array 2 .

[0100] In some embodiments, reference Figure 1 and Figure 2The circuit for implementing the convolution operation further includes a reference array 3, the reference array 3 is connected to the output end of the digital-to-analog conversion module 5 to receive the voltage signal, the output end of the reference array 3 is connected to the adjustment module 4, and the output end of the adjustment module 4 is connected to the symbol column processing module;

[0101] The adjustment module 4 adjusts the first current signal according to the reference current signal to obtain the first output signal.

[0102] As an optional embodiment of the present invention, the reference array 3 includes m second storage cells 30 arranged in a column. The number of rows of the first storage cells 202 and the number of rows of the second storage cells 30 are the same, namely, m rows. m is a positive integer, and each second storage cell 30 is connected to the first storage cell 202 in the same row.

[0103] In some embodiments, the second memory cell 30 is an RRAM. Specifically, the second memory cell 30 is a high-resistance RRAM with a conductivity of 0.1.

[0104] In existing RRAM technology, the current output by the high-resistance RRAM cannot be reduced to zero. Therefore, the reference current generated by the high-resistance RRAM in the reference array 3 described above reduces the leakage current output in the memory array 1, weakening the impact of the leakage current on the convolution output result, thereby better mapping the weight signal and improving the accuracy of the mapped weight signal.

[0105] Figure 4 This is a structural diagram of an adjustment module in a first embodiment of the present invention. Figure 5 Schematic diagram of the structure of the current subtraction circuit 40 according to an embodiment of the present invention; Figure 4 and Figure 5 I in the equation is the second current signal, I singal The first current signal output by the first memory cell in each column of the memory array 2, I ref is the reference current signal output by the reference array 3.

[0106] In some optional embodiments of the present invention, referring to Figure 4 , the adjustment module 4 includes a current subtraction circuit 40, a first current-to-voltage conversion unit 41 and a first analog-to-digital conversion unit 42;

[0107] The input end of the current subtraction circuit 40 is connected to the current output end of the memory array 2 and the current output end of the reference array 3. The current subtraction circuit 40 is used to perform a subtraction operation on the first current signal output by each column of the memory array 2 and the reference current signal output by the reference array 3, so as to output a plurality of second current signals.

[0108] An input end of the first current-to-voltage unit 41 is connected to an output end of the current subtraction circuit 40 , and the first current-to-voltage unit 41 is used to convert the second current signal into a first voltage signal;

[0109] The input end of the first analog-to-digital conversion unit 42 is connected to the output end of the first current-to-voltage conversion unit 41. The first analog-to-digital conversion unit 42 is used to perform analog-to-digital signal conversion on the first voltage signal to output the first output signal. This has the advantage that, since the convolution input digital signal is converted into a voltage signal as the voltage input of the memory array 2, and since the first current signal output by each column of the memory array 2 is equal to the multiplication and addition result of the voltage and conductivity of the storage cell in the current column, the first current signal affects the first output signal, and the first output signal affects the final output value of the convolution operation. Therefore, the leakage current generated by the memory array 2 will affect the final output value of the convolution operation. The leakage current is the current generated by the high-resistance storage cell in the memory array. The current subtraction circuit 40 performs a subtraction operation on the first current signal output by each column of the memory array 2 and the reference current signal to output a plurality of second current signals, thereby reducing the influence of the leakage current on the first output signal, thereby avoiding the influence of the leakage current generated in the memory array 2 on the convolution operation result, and improving the accuracy of the convolution operation.

[0110] As an optional embodiment of the present invention, refer to Figure 5 The current subtraction circuit 40 includes a current mirror, which includes an adjusted current output terminal, a first NMOS transistor 401, and a second NMOS transistor 402. The drain of the first NMOS transistor 401 is connected to the current output terminal of the memory array 2 to receive the first current signal. The node between the drain of the first NMOS transistor 401 and the current output terminal of the memory array 2 is connected to the adjusted current output terminal. A current mirror output terminal is further provided between the drain of the first NMOS transistor 401 and the current output terminal of the memory array 2 to output the second current signal. The gate of the first NMOS transistor 401 is connected to the gate of the second NMOS transistor 402, and the source of the first NMOS transistor 401 is connected to the source of the second NMOS transistor 402.

[0111] The drain of the second NMOS transistor 402 is connected to the current output terminal of the reference array 3 to receive the reference current signal, and the drain and gate of the second NMOS transistor 402 are short-circuited;

[0112] The first NMOS transistor 401 is controlled to operate in a saturation region, so that the adjustment current output terminal outputs the second current signal.

[0113] In some embodiments, reference Figure 5The drain of the first NMOS transistor 401 receives the first current signal I output by each column in the memory array 2. singal The drain of the second NMOS tube 402 receives the reference current signal I output by the reference array 3. ref , the calculation formula of the second current signal I output by the adjustment current output terminal is as follows:

[0114] I=I singal -I ref

[0115] Where, I is the second current signal, I singal The first current signal output by the first memory cell in each column of the memory array 2, I ref is the reference current signal output by the reference array 3.

[0116] Figure 6 FIG1 is a schematic diagram of the structure of the adjustment module in the second embodiment of the present invention; FIG1 singal The first current signal output by the first memory cell in each column of the memory array 2, I ref is the reference current signal output by the reference array 3.

[0117] In some other optional embodiments of the present invention, referring to Figure 6 , the adjustment module includes a second current-to-voltage unit 43, a third current-to-voltage unit 44, a second analog-to-digital conversion unit 45, a third analog-to-digital conversion unit 46 and a digital domain subtractor 47;

[0118] An input terminal of the second current-to-voltage unit 43 is connected to a current output terminal of the memory array 2 , an output terminal of the second current-to-voltage unit 43 is connected to an input terminal of the second analog-to-digital conversion unit 45 , and an output terminal of the second analog-to-digital conversion unit 45 is connected to a first input terminal of the digital domain subtractor 47 ;

[0119] The input end of the third current-to-voltage unit 44 is connected to the current output end of the reference array 3 , the output end of the third current-to-voltage unit 44 is connected to the input end of the third analog-to-digital conversion unit 46 , and the output end of the third analog-to-digital conversion unit 46 is connected to the second input end of the digital domain subtractor 47 .

[0120] As an optional embodiment of the present invention, refer to Figure 6 The second current-to-voltage conversion unit 43 is used to convert the first current signal into a second voltage signal, and the second analog-to-digital conversion unit 45 is used to convert the second voltage signal into a first digital signal;

[0121] The third current-to-voltage conversion unit 44 is used to convert the reference current signal into a third voltage signal, and the third analog-to-digital conversion unit 46 is used to convert the third voltage signal into a second digital signal;

[0122] The digital domain subtractor 47 is used to perform a subtraction operation on the first digital signal and the second digital signal to output the first output signal. This has the advantage that the first current signal and the reference current signal are converted into a second voltage signal and a third voltage signal, respectively, by the second current-to-voltage conversion unit 43 and the third current-to-voltage conversion unit 44, and the second voltage signal and the third voltage signal are converted into a first digital signal and a second digital signal, respectively, by the second analog-to-digital conversion unit 45 and the third analog-to-digital conversion unit 46. Furthermore, the digital domain subtractor 47 performs a subtraction operation on the first digital signal and the second digital signal to output the first output signal, thereby eliminating leakage current in the memory array 2, reducing the impact of leakage current on the final result of the convolution operation, and improving the accuracy of the convolution operation.

[0123] It can be explained that the present invention provides two implementations of the adjustment module. In actual operation, if circuit performance is not considered, any one of the two adjustment modules can be selected.

[0124] The adjustment module may also be selected by compromise based on requirements such as energy consumption and area of ​​the circuit to improve the performance of the circuit for implementing the convolution operation of the present invention.

[0125] In some embodiments, reference Figure 4 and Figure 6 The first current-to-voltage unit 41, the second current-to-voltage unit 43, and the third current-to-voltage unit 44 can adopt a current-to-voltage circuit. Specifically, by controlling the current to charge and discharge the capacitor, the current is converted into a voltage across the capacitor, thereby achieving the purpose of converting the current signal into a voltage signal. The conversion calculation formula is as follows:

[0126]

[0127] Where I is the current to be converted, T is the time to charge the capacitor device, and C is the capacitance value.

[0128] In some embodiments, reference Figure 4 and Figure 6 The first analog-to-digital conversion unit 42, the second analog-to-digital conversion unit 45 and the third analog-to-digital conversion unit 46 are all analog-to-digital converters (ADCs) for converting voltage signals into digital signals.

[0129] As an optional embodiment of the present invention, refer to Figure 2 The symbol column processing module 6 is connected to the output end of the symbol column 201 and is configured to perform a negation operation on the first output signal output by the symbol column 201 to output the output value of the symbol column 201. This has the advantage that after the symbol column processing module 6 obtains the symbol column 201, it performs a negation operation on the first output signal output by the symbol column 201 to output the output value of the symbol column 201. This allows the memory array 2 to map both positive integer weights and negative integer weights, thereby saving memory, reducing the complexity of convolution operations, improving the efficiency and accuracy of convolution operations, and saving circuit board area and cost.

[0130] In some specific embodiments, the step of performing a negation operation on the first output signal output by the symbol sequence 201 to output the output value of the symbol sequence 201 includes:

[0131] In computers, numerical values ​​are often expressed in the form of two's complement. Performing a negation operation on the first output signal is equivalent to multiplying the first output signal by -1. When performing a negation operation on the first output signal corresponding to the sign column 201 through a binary logic operation circuit, it is equivalent to calculating the two's complement of the negation of the first output signal corresponding to the sign column 201, that is, taking the one's complement of the first output signal corresponding to the sign column 201 and then adding 1.

[0132] In some embodiments, the symbol column processing module 6 includes a Verilog language generation circuit in the digital domain, which is used to perform a negation operation on the first output signal output by the symbol column 201 to output the output value of the symbol column 201 .

[0133] In some embodiments, reference Figure 2 The calculation module 7 includes a plurality of first adders 71 and second adders 72, and each of the convolution kernel mapping units 20 corresponds to one first adder 71;

[0134] The first adder 71 is connected to the output end of the symbol column processing module 6, and is used to perform a weighted sum operation on the output value of the symbol column 201 corresponding to each convolution kernel mapping unit 20 and the first output signal to obtain a weighted value;

[0135] The second adder 72 is connected to all of the first adders 71 and is configured to sum the weighted values ​​output by all of the first adders 71 to obtain the convolution output value. This has the advantage of performing a weighted summation operation on the output value of the symbol column 201 corresponding to each of the convolution kernel mapping units 20 and the first output signal by the calculation module 7 to obtain a weighted value, and summing the weighted values ​​output by all of the first adders 71 to obtain the convolution output value, thereby achieving complete convolution calculation of the circuit for implementing convolution operation of the present invention.

[0136] In other embodiments, referring to Figure 2 The calculation module 7 may further include a total adder (not shown), connected to the output terminals of all the symbol column processing modules 6, for receiving the output values ​​of all the symbol columns 201 and the first output signal and performing weighted summation. Although using a total adder to perform weighted summation may increase the pressure on the calculation module 7 and extend the calculation time, it can save chip area and cost. One or more adders can be provided to calculate the final convolution output value according to actual needs.

[0137] Figure 7 The figure is a flow chart of a method for implementing a convolution operation according to an embodiment of the present invention.

[0138] Reference Figure 7 The present invention also provides a method for implementing a convolution operation, comprising the steps of:

[0139] S1: Obtain a sign bit according to a range of a quantized weight signal, and encode the quantized weight signal to obtain a weight code;

[0140] S2: Mapping the weight code through a memory array;

[0141] S3: converting the input digital signal into a voltage signal as an input voltage signal of the memory array, so that each column of the memory array outputs a first current signal;

[0142] S4: Obtaining a first output signal according to the first current signal;

[0143] S5: acquiring a sign column according to the sign bit, where the sign column is a column in the memory array where the sign bit is located, and outputting a sign column output value according to the sign column and the first output signal;

[0144] S6: Obtain a convolution output value according to the symbol column output value and the first output signal.

[0145] The advantages of the method for implementing convolution operation of the present invention are: by encoding the quantized weight signal to obtain the weight code and obtaining the sign bit, the weight code is mapped through the memory array; by converting the input digital signal into a voltage signal as the input voltage signal of the memory array, each column of the memory array outputs a first current signal; by setting the reference current signal, the first current signal is adjusted to obtain a first output signal; a sign column is obtained according to the sign bit, and a sign column output value is output according to the sign column and the first output signal; a convolution output value is obtained according to the sign column output value and the first output signal; and positive integer weights and negative integer weights are mapped through the memory array, thereby saving the amount of memory and improving the efficiency and accuracy of the convolution operation.

[0146] In step S2, the memory array includes t convolution kernel mapping units, each of the convolution kernel mapping units uses n resistive memory units to map a weight, and both t and n are positive integers;

[0147] The resistive memory cell includes a high-resistance RRAM and a low-resistance RRAM. The conductivity of the high-resistance RRAM is lower than that of the low-resistance RRAM. The high-resistance RRAM is used to map the number 0, and the low-resistance RRAM is used to map the number 1.

[0148] In some specific embodiments, in step S1, the step of obtaining a sign bit according to a range of the quantized weight signal and encoding the quantized weight signal to obtain a weight code includes:

[0149] The quantized integer weight is encoded as follows:

[0150]

[0151] in: is the quantized weight, is the number of resistance states of RRAM, i is a positive integer, ,Will Mapped to the corresponding resistance value, so that the weight is represented by RRAM, Indicates RRAM to map a weight; determined by the value of i The value of The calculation formula is:

[0152]

[0153] else indicates that the value of i is an integer other than i=j, j is the specified sign bit, and the position of the sign bit is determined according to the range of W.

[0154] In some specific embodiments, the steps of step S2 include:

[0155] Reference Figure 1 and Figure 2 , the convolution weights are 1 and -2, 1 is represented as 1=(-4)×0+2×0+1×1, and -2 is represented as -2=(-4)×1+2×1+1×0, at which time the sign bit j=2;

[0156] Map the above weights to the RRAM memory array, where m is 2 and n is 3. Figure 1 , mapping the number 1 through the low-resistance RRAM, setting the conductivity of the low-resistance RRAM to 1; mapping the number 0 through the high-resistance RRAM, and setting the conductivity of the high-resistance RRAM to 0.1;

[0157] The steps of step S3 include:

[0158] The convolution input digital signals are 1 and 2. 1 is converted into a voltage signal by the DAC and then input into the first row of RRAM as the input voltage of the first row of RRAM. 2 is converted into a voltage signal by the DAC and then input into the second row of RRAM as the input voltage of the second row of RRAM.

[0159] After conversion by the memory array, the final output current value of each column of RRAM is equal to the product of the input voltage of the current column of RRAM and the conductivity of the current column of RRAM. Therefore, the final output current value of each column of RRAM is the first current signal.

[0160] In step S4 , the step of obtaining a first output signal according to the first current signal includes: setting a reference current signal to adjust the first current signal to obtain the first output signal.

[0161] Figure 8 This is a flowchart of obtaining a first output signal in the first implementation manner of an embodiment of the present invention.

[0162] In some embodiments, reference Figure 8 The step of setting a reference current signal to adjust the first current signal to obtain a first output signal includes:

[0163] S401: performing a subtraction operation on a first current signal outputted by each column of the memory array and the reference current signal to obtain a plurality of second current signals;

[0164] S402: Convert the second current signal into a first voltage signal;

[0165] S403: Perform analog-to-digital conversion on the first voltage signal to output the first output signal. This has the advantage of reducing the influence of leakage current on the convolution operation result and improving the accuracy of the convolution operation.

[0166] Figure 9 This is a flowchart of obtaining a first output signal in the second implementation manner of an embodiment of the present invention.

[0167] In other embodiments, referring to Figure 9 The step of setting a reference current signal to adjust the first current signal to obtain a first output signal includes:

[0168] S411: Convert the first current signal into a second voltage signal, and convert the second voltage signal into a first digital signal;

[0169] S412: Convert the reference current signal into a third voltage signal, and convert the third voltage signal into a second digital signal;

[0170] S413: Perform a subtraction operation on the first digital signal and the second digital signal to output the first output signal.

[0171] As an optional embodiment of the present invention, in step S5, the step of outputting a symbol sequence output value according to the symbol sequence and the first output signal includes:

[0172] The first output signal of the symbol column is negated to output the symbol column output value. This method has the advantage of processing the output value of the symbol column, thereby enabling the memory array of the present invention to map both positive integer weights and negative integer weights, reducing the number of storage cells required, saving chip area, and lowering the cost of convolution operations.

[0173] In some embodiments, in step S6, the step of obtaining a convolution output value according to the symbol column output value and the first output signal includes:

[0174] A weighted sum operation is performed on the symbol column output value and the first output signal to obtain a weighted value, and a sum operation is performed on all the weighted values ​​to obtain the convolution output value.

[0175] While the embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations of these embodiments are possible. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the claims. Furthermore, the invention described herein is susceptible to other embodiments and may be practiced or implemented in a variety of ways.

Claims

1. A circuit for implementing a convolution operation, characterized in that: It includes an encoding module, a digital-to-analog conversion module, a memory array, an adjustment module, a symbol column processing module and a calculation module; The encoding module is used to obtain a sign bit according to the range of the quantized weight signal, and encode the quantized weight signal to obtain a weight code; The digital-to-analog conversion module is used to convert an externally input digital signal into a voltage signal, and transmit the voltage signal to the memory array as an input of the memory array; The memory array is used to map the weight code, and after receiving the voltage signal, each column of the memory array outputs a first current signal; The adjustment module is used to obtain a first output signal according to the first current signal; The sign column processing module is configured to obtain a sign column according to the sign bit, the sign column being a column in the memory array where the sign bit is located, and output a sign column output value according to the sign column and the first output signal; The calculation module is used to obtain a convolution output value according to the symbol column output value and the first output signal.

2. The circuit for implementing convolution operation according to claim 1, wherein: The memory array includes a plurality of convolution kernel mapping units, each of which maps a weight code, and each of which includes a symbol column and a plurality of non-symbol columns, and the symbol column and the non-symbol columns respectively output the first current signal.

3. The circuit for implementing convolution operation according to claim 2, wherein: The symbol column processing module is connected to the output end of the symbol column and is used to perform a negation operation on a first output signal output by the symbol column to output the symbol column output value.

4. The circuit for implementing convolution operation according to claim 2, wherein: The symbol column and the non-symbol column each include m first storage units, where m is a positive integer; All the first storage units in the same row are connected and receive an input voltage signal; All the first storage units in the same column are connected.

5. The circuit for implementing convolution operation according to claim 4, wherein: The module further comprises a reference array, wherein the reference array is connected to the output end of the digital-to-analog conversion module to receive the voltage signal, the output end of the reference array is connected to the adjustment module, and the output end of the adjustment module is connected to the symbol column processing module; The adjustment module adjusts the first current signal using a reference current signal to obtain the first output signal.

6. The circuit for implementing convolution operation according to claim 5, wherein: The reference array includes m second storage units distributed in a column, where m is a positive integer, and each second storage unit is connected to the first storage unit in the same column.

7. The circuit for implementing convolution operation according to claim 5, wherein: The adjustment module includes a current subtraction circuit, a first current-to-voltage conversion unit, and a first analog-to-digital conversion unit; The input end of the current subtraction circuit is connected to the current output end of the memory array and the current output end of the reference array, and the current subtraction circuit is used to perform a subtraction operation on the first current signal output by each column of the memory array and the reference current signal to output a plurality of second current signals; The input end of the first current-to-voltage conversion unit 5 is connected to the output end of the current subtraction circuit, and the first current-to-voltage conversion unit is used to convert the second current signal into a first voltage signal; An input end of the first analog-to-digital conversion unit is connected to an output end of the first current-to-voltage conversion unit, and the first analog-to-digital conversion unit is configured to perform analog-to-digital signal conversion on the first voltage signal to output the first output signal.

8. The circuit for implementing convolution operation according to claim 5, wherein: The adjustment module includes a second current-to-voltage unit, a third current-to-voltage unit, a second analog-to-digital conversion unit, a third analog-to-digital conversion unit, and a digital domain subtractor; An input end of the second current-to-voltage unit is connected to a current output end of the memory array, an output end of the second current-to-voltage unit is connected to an input end of the second analog-to-digital conversion unit, the second current-to-voltage unit is used to convert the first current signal into a second voltage signal, and the second analog-to-digital conversion unit is used to convert the second voltage signal into a first digital signal; The input end of the third current-to-voltage unit is connected to the current output end of the reference array, the output end of the third current-to-voltage unit is connected to the input end of the third analog-to-digital conversion unit, the third current-to-voltage unit is used to convert the reference current signal into a third voltage signal, and the third analog-to-digital conversion unit is used to convert the third voltage signal into a second digital signal; The output end of the second analog-to-digital conversion unit is connected to the first input end of the digital domain subtractor, and the output end of the third analog-to-digital conversion unit is connected to the second input end of the digital domain subtractor. The digital domain subtractor is used to perform a subtraction operation on the first digital signal and the second digital signal to output the first output signal.

9. A method for implementing a convolution operation, characterized in that: Including steps: Obtaining a sign bit according to a range of the quantized weight signal, and encoding the quantized weight signal to obtain a weight code; mapping the weight codes through a memory array; Converting an input digital signal into a voltage signal as an input voltage signal of the memory array, so that each column of the memory array outputs a first current signal; obtaining a first output signal according to the first current signal; Obtaining a sign column according to the sign bit, the sign column being a column in the memory array where the sign bit is located, and outputting a sign column output value according to the sign column and the first output signal; A convolution output value is obtained according to the symbol column output value and the first output signal.

10. The method for implementing convolution operation according to claim 9, wherein: The step of obtaining a first output signal according to the first current signal includes: A reference current signal is set to adjust the first current signal to obtain the first output signal.

11. The method for implementing a convolution operation according to claim 10, wherein: The step of setting a reference current signal to adjust the first current signal to obtain the first output signal includes: performing a subtraction operation on the first current signal outputted by each column of the memory array and the reference current signal to obtain a plurality of second current signals; converting the second current signal into a first voltage signal; Perform analog-to-digital conversion on the first voltage signal to output the first output signal.

12. The method for implementing convolution operation according to claim 10, wherein: The step of setting a reference current signal to adjust the first current signal to obtain the first output signal includes: converting the first current signal into a second voltage signal, and converting the second voltage signal into a first digital signal; Converting the reference current signal into a third voltage signal, and converting the third voltage signal into a second digital signal; A subtraction operation is performed on the first digital signal and the second digital signal to output the first output signal.

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