Floating point arithmetic device and operating method thereof

Abstract

The invention discloses a floating-point arithmetic device with two floating-point number operands and an operation method of the floating-point arithmetic device. The floating-point arithmetic device comprises an index subtraction circuit, an index calculation circuit, a mantissa calculation circuit and a conversion circuit. The exponent subtraction circuit is used for calculating the difference between the exponents of the two operands to generate a sign bit and an exponent difference. The exponent calculation circuit generates a post-operation exponent bit according to a larger exponent in the exponents of the two operands. The mantissa calculation circuit aligns mantissa bits of the two operands, and performs one of addition and subtraction on the aligned mantissa bits. In order to improve the calculation efficiency and reduce the power consumption, the floating-point arithmetic device can complete floating-point addition or subtraction operation in one step (one clock cycle) without moving intermediate floating-point number data between a temporary memory and each functional circuit unit like multi-step operation.

Description

Technical Field

[0001] The present invention relates to a floating-point addition and subtraction circuit device, and more particularly to a floating-point arithmetic device and an operating method thereof. Background Art

[0002] In digital computer systems, all numbers are represented in binary format. For example, an integer A is represented in m-bit binary format as follows:

[0003] A=a m-1 2 m-1 +a m-2 2 m-2 +…+a12 1 +a0=(a m-1 a m-2 …a1a0)b,

[0004] Among them, a i = [0, 1], i = 0, ..., (m-1), and the symbol b represents the integer A in binary format. To perform binary addition / subtraction operations, another m-bit integer B is represented as follows:

[0005] B=b m-1 2 m-1 +b m-2 2 m-2 +…+b12 1 +b0=(b m-1 b m-2 …b1b0)b, where b i =[0,1], i=0,…,(m-1).

[0006] The resulting integer C is represented as follows:

[0007] C=A±B=(a m-1 ±b m-1 )2 m-1 +(a m-2 ±b m-2 )2 m-2 +…+(a1±b1)2 1 +(a0±b0)2 0 =(c m s m-1 …s1s0)b.

[0008] For each bit operation: (a k ±b k ), where k = 0, ..., (m-1), the output can be summed up using the bit s k and carry-over bit c k Write to the next more significant bit. Note that the most significant carry bit cm represents the carry bit of an m-bit addition, and s g Represents the negation (or borrow) bit of an m-bit subtraction, such as Figure 1 As shown. Bit-by-bit addition / subtraction of binary numbers s k and c k+1 It is constructed by a combinational logic gate circuit 110 (including a full adder 112 and an XOR gate 111). Therefore, the configuration of the addition / subtraction circuit 100 for two m-bit integers is as follows: Figure 1 As shown in FIG. 1 , the m-bit binary integer addition / subtraction circuit 100 includes an m-bit addition / subtraction circuit 11 (composed of m sub-circuits 110) in the first row, a two's complement conversion circuit 12 in the second row, and a logic circuit 13. Meanwhile, the voltage signal Sub at the node 101 has a value of V SS (Logical value 0) represents the addition operation of C=A+B. If V DD (Logical value 1) indicates that a subtraction operation of C=AB is performed. According to the voltage signal Sub on the node 101 and the carry bit c on the node 102 from the m-bit addition / subtraction circuit 11, ′ m , the logic circuit 13 generates a signal s at the node 103 during the subtraction operation. g (V representing the negation of bit 1 DD ), generates a signal c at node 104 during the addition operation m (V representing the carry bit 1 DD By verifying the voltage signals of the logic values ​​of the bit-to-bit operation subcircuits 11 and 12 , the correctness of the addition and subtraction operations of two m-bit binary integers A and B can be easily verified.

[0009] In addition to representing integers in m-bit binary format in numerical calculations, floating-point representation has also been introduced to expand the dynamic range of calculations in electronic computer systems with a fixed bit length. According to the IEEE 754 binary floating-point format, a binary floating-point number A is represented by a sign bit sa, a q-bit exponent ea, and a p-bit mantissa a as follows:

[0010]

[0011] Where ea=(ea q-1 2 q-1 +ea q-2 2 q-2 +…+ea12 1 +ea02 0 )-2 q-1+1, and

[0012]

[0013] Among them, the binary numbers sa and ea i and a j = [0,1]; i = 0, 1, ..., (q-1) and j = 0, 1, ..., (p-1); the symbol f represents a floating-point binary expression. Note that the exponent ea can be used to represent the floating-point binary expression. i (where i = 0, 1, ..., (q-1)) is decoded to represent a subnormal floating point number (all ea i =0) of the binary value (a p-1 = 0) and represents a normal floating point number (with any non-zero ea i )'s binary value (a p-1 =1), usually when storing or transmitting a floating point number, the most significant bit (MSB) of the mantissa is not included. p-1 Therefore, the total number of bits used to store and transmit floating-point numbers in the IEEE 754 format remains (p+q). For example, in a computer system, floating point 8 uses 8 bits (p+q=8) to store a floating-point number, half precision floating point uses 16 bits (p+q=16) to store a floating-point number, single precision floating point uses 32 bits (p+q=32) to store a floating-point number, double precision floating point uses 64 bits (p+q=64) to store a floating-point number, quadruple precision floating point uses 128 bits (p+q=128) to store a floating-point number, octal precision floating point uses 256 bits (p+q=256) to store a floating-point number, and so on. Before performing binary arithmetic operations, the floating-point decoder in the computing hardware is always used to convert the q-bit exponent (ea0, ..., ea q-1 )b decodes the MSB of the pth digit of the mantissa a p-1 The binary value of .

[0014] The format of the binary floating-point number A is the same as above. The binary floating-point number B is represented as follows with a sign bit sb, a q-bit exponent eb, and a p-bit mantissa b:

[0015]

[0016] Where, eb=(eb q-1 2 q-1 +eb q-2 2 q-2 +…+eb12 1+eb02 0 )-2 q-1 +1, and

[0017]

[0018] Among them, the binary numbers sb and eb i and b j = [0, 1]; i = 0, 1, ..., (q-1) and j = 0, 1, ..., (p-1); the symbol f represents a floating-point binary expression. Therefore, the floating-point number C is the value after the addition or subtraction of A and B, that is, C = A ± B, expressed as follows:

[0019]

[0020] From the above equation, we can see that because ea≠eb and the mantissa bits of A are not aligned with the mantissa bits of B, the final floating-point number C cannot be directly obtained through bit-by-bit operations. Summary of the Invention

[0021] In response to the problems in the prior art, the present application provides a floating-point arithmetic device and an operating method thereof.

[0022] To solve the above technical problems, this application provides the following technical solutions:

[0023] In a first aspect, the present application provides a floating-point arithmetic device for performing an arithmetic operation on a first operand and a second operand according to an external operator to generate a final number, wherein the external operator represents one of addition and subtraction, wherein the first operand, the second operand, and the final number are all binary floating-point numbers and each includes a sign bit, a q-bit exponent, and a p-bit mantissa, the device comprising:

[0024] an exponent subtraction circuit for calculating a difference between the q-bit exponents of the first operand and the second operand to generate a first sign bit and an exponent difference;

[0025] an exponent calculation circuit, coupled to the exponent subtraction circuit, configured to select a larger exponent from the q-bit exponents of the first and second operands according to the first sign bit, and generate an intermediate (q+1)-bit exponent according to the larger exponent;

[0026] a mantissa calculation circuit coupled to the exponent subtraction circuit for (1) selecting a smaller exponent from the q-bit exponents of the first and second operands based on the first sign bit, (2) right-shifting one of the p-bit mantissas of the first and second operands corresponding to the smaller exponent based on a first q-bit binary shift code to generate a right-shifted p-bit mantissa, and (3) performing one of addition and subtraction on the right-shifted p-bit mantissa and the other of the p-bit mantissas of the first and second operands based on an inner operator to generate an intermediate (p+1)-bit mantissa, wherein the inner operator is related to the outer operator and the sign bits of the first and second operands, and wherein the first q-bit binary shift code is equal to the exponent difference; and

[0027] A conversion circuit is coupled to the exponent calculation circuit and the mantissa calculation circuit, for converting the intermediate (q+1)-bit exponent and the intermediate (p+1)-bit mantissa into the q-bit exponent and the p-bit mantissa of the final number respectively.

[0028] In a second aspect, the present application provides a method for operating a floating-point arithmetic device, wherein the floating-point arithmetic device performs an arithmetic operation on a first operand and a second operand according to an external operator to generate a final number, wherein the floating-point arithmetic device comprises a first barrel shifter circuit and a conversion circuit, wherein the external operator represents one of addition and subtraction, wherein the first operand, the second operand, and the final number are all binary floating-point numbers and each comprises a sign bit, a q-bit exponent, and a p-bit mantissa, and the method comprises the following steps:

[0029] calculating a difference between the q-bit exponents of the first and second operands to generate a first sign bit and an exponent difference;

[0030] right-shifting one of the p-bit mantissas of the first and second operands corresponding to a smaller exponent using the first barrel shifter circuit according to a first q-bit binary shift code to generate a right-shifted p-bit mantissa, wherein the first q-bit binary shift code is equal to the exponent difference;

[0031] performing one of addition and subtraction on the right-shifted p-bit mantissa and the other of the p-bit mantissas of the first and second operands according to an inner operator to generate an intermediate (p+1)-bit mantissa, wherein the inner operator is related to the outer operator and the sign bits of the first and second operands;

[0032] obtaining an intermediate (q+1)-bit exponent according to a larger exponent, wherein the larger exponent is selected from one of the q-bit exponents of the first and second operands according to the first sign bit; and

[0033] The intermediate (q+1)-bit exponent and the intermediate (p+1)-bit mantissa are converted into the q-bit exponent and the p-bit mantissa of the final number respectively.

[0034] Based on the floating-point arithmetic device and its operation method provided in this specification, floating-point addition or subtraction operations can be completed within one clock cycle without moving intermediate floating-point data between the register and each functional circuit unit as in multi-step operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A conventional m-bit binary addition / subtraction circuit is shown.

[0036] Figure 2 A schematic diagram of a floating-point addition and subtraction circuit device 200 is shown according to the present invention.

[0037] Figure 3 A circuit diagram of a most significant bit circuit 210 is shown according to an embodiment of the present invention. The most significant bit circuit 210 obtains the most significant mantissa bits of two floating-point operands in IEEE 754 format.

[0038] Figure 4 A schematic diagram of a q-bit exponent subtraction circuit 220 is shown for exponents of two floating-point operands according to an embodiment of the present invention.

[0039] Figure 5A According to an embodiment of the present invention, a circuit diagram of a mantissa alignment circuit 221 is shown. The mantissa alignment circuit 221 is used to right-shift the mantissa of a floating-point operand with a smaller exponent.

[0040] Figure 5B A circuit diagram of a barrel shifter circuit 520 is shown according to an embodiment of the present invention.

[0041] Figure 6 A schematic diagram of the addition / subtraction circuit 222 for calculating the aligned mantissas of two floating-point operands is shown according to an embodiment of the present invention.

[0042] Figure 7 According to one embodiment of the present invention, a circuit diagram of the exponent selection / addition circuit 223 is shown. The exponent selection / addition circuit 223 is used to select a larger exponent to be added with an extra carry bit mc(p).

[0043] Figure 8According to an embodiment of the present invention, a circuit diagram of a leading zero detection circuit 231 is shown. The leading zero detection circuit 231 is configured to detect the first / leading non-zero mantissa bit of the mantissa mc(0:p).

[0044] Figure 9 According to an embodiment of the present invention, a circuit diagram of the leading zero shift code generating circuit 232 is shown. The leading zero shift code generating circuit 232 is configured to generate a non-zero shift code LZCk(0:q-1).

[0045] Figure 10 According to an embodiment of the present invention, a circuit diagram of the LZ barrel shifter circuit 233 is shown. The LZ barrel shifter circuit 233 is used to left-shift the mantissa bits after operation to comply with the IEEE 754 mantissa format.

[0046] Figure 11 A schematic diagram of a subnormal barrel shifter circuit 234 conforming to the IEEE 754 subnormal mantissa format is shown according to one embodiment of the present invention.

[0047] Figure 12 A schematic diagram illustrating an exponent adjustment circuit 235 that complies with the IEEE 754 exponent format is shown according to an embodiment of the present invention.

[0048] Figure 13 According to one embodiment of the present invention, a logic table 1310 is shown showing the “subtraction” bit output by the addition / subtraction selection and sign logic circuit 240 and the sign bit (sc) of the final floating point number.

[0049] Figure 14 A schematic diagram of the addition / subtraction (A / S) selection and sign logic circuit 240 is shown in accordance with an embodiment of the present invention, in accordance with the IEEE 754 sign format.

[0050] Figure Number:

[0051] 11 m-bit addition / subtraction circuit

[0052] 12 Two's complement conversion circuit

[0053] 13 Logic Circuits

[0054] 110 circuits

[0055] 200 Floating-point addition / subtraction circuit device

[0056] Nodes 101-104, 201m, 201e, 201s, 201m, 201, 202, and 202e

[0057] Nodes 202s, 202m, 203, 204, 205, 205s, 205e, 205m, and 206

[0058] Nodes 314, 315, 411-416, 501, 503, 504, 506, 531, 532, 604-606

[0059] Nodes 705, 802, 902, 1003, 1005, 1202, 1221, 1222, and 1231

[0060] 1406-1407 nodes

[0061] 210 Most Significant Bit Circuit

[0062] 220 Exponential Subtraction Circuit

[0063] 221 Mantissa Alignment Circuit

[0064] 100, 222 Addition / Subtraction Circuits

[0065] 223 Index selection / addition circuit

[0066] 230 IEEE 754 format conversion circuit

[0067] 231 Leading Zero Detection Circuit

[0068] 232 Leading Zero Shift Code Generator Circuit

[0069] 233 Leading Zero Barrel Shifter Circuit

[0070] 234th regular barrel shifter circuit

[0071] 235 Index Adjustment Circuit

[0072] 240 Addition / Subtraction Selection and Symbolic Logic Circuits

[0073] 301, 302 NMOSFET devices

[0074] 410 q-bit exponential subtraction circuit

[0075] 420 Two's complement conversion circuit

[0076] 430, 720 Adder Circuit

[0077] 510 selection circuit

[0078] 520 barrel shifter circuit

[0079] 530 Operation Sequence Circuit

[0080] 610 p-bit addition / subtraction circuit

[0081] 620 p-bit two's complement conversion circuit

[0082] 630 Carry / Negation Logic Circuit

[0083] 710 transmission gates in one row

[0084] 910 transistors

[0085] 911 Metal Contact

[0086] 1210, 1230 "plus one" circuit

[0087] 1220 Subtraction Circuit

[0088] 1240, 1421-1423 Logic Circuit

[0089] 1310 Logic Table DETAILED DESCRIPTION

[0090] The following detailed description is provided by way of example only and is not intended to be limiting. It should be understood that other embodiments of floating point formats other than the IEEE 754 format may be used, for example, to manipulate the mantissa and exponent bits of two floating point numbers without departing from the scope of the present invention. Furthermore, it should be understood that the grammar and terminology used in this specification are provided for illustrative purposes only and should not be construed as limiting. Those skilled in the art will appreciate that the embodiments of the methods and schematic diagrams in this specification are provided by way of example only and are not intended to be limiting. Those skilled in the art who understand the spirit of the present invention as a result of the disclosure of this specification may use other embodiments and all of these embodiments will fall within the scope of the claims of the present invention.

[0091] To achieve better operational efficiency and save operational power, the floating-point addition and subtraction circuit device of the present invention performs a single-step floating-point addition or subtraction operation without the need to move intermediate data into and out of a memory and an arithmetic circuit unit as in a multi-step operation. To achieve the single-step floating-point addition / subtraction operation, the floating-point addition and subtraction circuit device of the present invention includes: (1) a circuit for converting two input operand codes in the IEEE 754 floating-point format into a complete floating-point binary representation including two most significant mantissa bits; (2) a circuit for aligning the mantissa bits of the operands according to the difference in exponents of the two input operand codes; (3) a circuit for performing an addition or subtraction operation on the aligned mantissa bits, and a circuit for performing a sign bit operation; and (4) a circuit for converting the final binary code into a floating-point number format in accordance with the IEEE 754 floating-point format for subsequent arithmetic operation or memory storage.

[0092] To address the problem in the prior art of being unable to directly obtain the final floating-point number C through bit-by-bit operations, the present invention requires adjusting the operand exponents to the same exponent and aligning the mantissas of the numbers to obtain the correct floating-point number and avoid errors, such as A+B≠B+A and AB≠-(BA), so as to correctly perform addition / subtraction operations.

[0093] According to one main aspect of the present invention, an addition and subtraction circuit device is designed to perform addition / subtraction operations on two floating-point numbers represented in a floating-point format in a single operation step, and output a final floating-point number represented in the same floating-point format. Compared to the present invention, conventional floating-point number addition or subtraction circuit devices require multiple operation steps, typically including the transmission of intermediate data between a temporary data memory storage circuit and other logic circuits (such as a comparison circuit and a shift circuit) via bus lines. Therefore, because no intermediate data transmission and temporary memory storage are required, the addition and subtraction circuit device of the present invention can significantly improve computational efficiency through a single-step operation.

[0094] According to another aspect of the present invention, since there is no intermediate data transmission between the memory circuit and other computing circuits, the power consumed by the intermediate data transmission between circuit modules via bus lines can be completely reduced. The power consumption of data transmission via fixed-bandwidth bus lines is considered to be a major factor in the power consumption of digital computing systems.

[0095] According to another aspect of the present invention, when the final floating-point number obtained by the circuit operation cannot be represented in a floating-point number format with a finite bit length (e.g., IEEE 754), the operation circuit should generate an overflow flag signal to indicate that the final floating-point number exceeds the numerical representation range. The out-of-range floating-point number cannot be used for further arithmetic operations and memory storage, thereby preventing calculation errors with the same finite bit length floating-point number representation method.

[0096] According to another aspect of the present invention, since the input / output floating-point numbers of the addition and subtraction circuit devices of the present invention all adopt the same floating-point format as the complete numerical elements for data transmission and memory storage in the computer system, it is easier to master the data management of complete numerical elements for arithmetic operations and memory access, so that the addition and subtraction circuit devices of the present invention can be effectively applied to matrix calculations, and are particularly suitable for neural network model calculations in machine learning (ML) to expand large-scale model systems.

[0097] The equations for floating-point addition / subtraction operations are expressed as follows:

[0098]

[0099] Further expression is as follows:

[0100] where ed ≥ 0, and

[0101] Where ed<0,

[0102] Among them, the index difference ed = ea - eb.

[0103] The exponential difference ed is a binary representation of a sign bit sed (= logical value [0,1]) and an absolute value |ed|. "sed = logical value 1" represents a negative value, and "sed = logical value 0" represents a positive value or the same value as ed. The binary representation of the absolute value |ed| is as follows: (ed q-1 ed q-2 ...ed1ed0)b represents |ed|=ed q-1 2 q-1 +ed q-2 2 q-2 +…+ed12 1 +ed02 0 , among which, ed i = logical value [0,1], and i = (q-1), ..., 0. When the sign bit sed is "0", ed is a positive number or zero (ed≥0), the digital range of A is greater than or equal to the digital range of B, then the exponent of the value A is selected as the exponent for the addition or subtraction operation of the two floating-point numbers A and B, and at the same time, all the mantissa bits of the floating-point number B are shifted down (or right) by the amount of the shift in binary code (ed q-1 ed q-2 ...ed1ed0)b is used to align the mantissa of value A with the value A for addition or subtraction. When the sign bit sed is "1", ed is a negative number (ed<0), and the exponent of A is less than or equal to the exponent of B. Then, the exponent of value B is selected as the exponent for the addition or subtraction of the two floating-point numbers A and B. At the same time, all the mantissa bits of floating-point number A are shifted down (or right) by the amount expressed in binary code (ed). q-1 ed q-2 ...ed1ed0)b represents the |ed| value so that it is aligned with the mantissa of the value B for addition or subtraction operations.

[0104] According to the above two operation rules for addition or subtraction of binary floating-point numbers that conform to the IEEE 754 format, Figure 2The addition and subtraction circuit device 200 of the present invention includes: (1) an addition / subtraction (A / S) selection and sign logic circuit 240 for selecting one of the addition and subtraction operations (i.e., generating a "subtraction" bit) and the sign bit operation of the final floating-point number; (2) a most significant bit circuit 210 for decoding the two most significant mantissa bits of two floating-point numbers A and B in the IEEE 754 format; (3) an exponent subtraction (ea-eb) circuit 220 for obtaining a sign bit (sed) and an exponent difference bit (ed(0:q-1)) representing the absolute value of the difference between the exponents of the two floating-point numbers A and B; (4) a mantissa alignment circuit 221 for aligning the mantissa bits; (5) an addition / subtraction circuit 222 for performing an addition or subtraction operation based on the "subtraction" bit; (6) an exponent selection / addition circuit 223 for obtaining the exponent bits es(0:q) after the operation; and (7) an IEEE 754 format. IEEE 754 format conversion circuit 230. The IEEE 754 format conversion circuit 230 includes: (i) a leading zero (LZ) detection circuit 231 for detecting the first / leading non-zero mantissa bit from mc(0:p) and outputting SL(0:p); (ii) a leading zero shift code generation circuit 232 for encoding the output SL(0:p) of the LZ detection circuit 231 into a shifted binary code LZC k (0:q-1); (iii) LZ barrel shifter circuit 233, for shifting the code LZC k (0:q-1), shifting the entire post-operation mantissa mc(0:p-1) to the left to the first non-zero position; (iv) a subnormal barrel shifter circuit 234, for right-shifting the entire mantissa ml(0:p-1) output from the LZ barrel shifter circuit 233 to conform to the subnormal floating-point format according to the output Sb(0:q-1) of the exponent adjustment circuit 235; (v) an exponent adjustment circuit 235, for shifting the entire mantissa es(0:q) output from the LZ barrel shifter circuit 233 to conform to the subnormal floating-point format according to the output Sb(0:q-1) of the exponent adjustment circuit 235; k (0:q-1), adjust the exponent bits to conform to the IEEE 754 exponent format.

[0105] When the addition / subtraction selection and sign logic circuit 240 is driven by the voltage signal V on the node Enb 204 DDUpon activation, the addition / subtraction select signal on node A / S 203 (i.e., an external operator) is input to circuit 240 along with the voltage signal of the sign bit sa of floating-point number A on node 201s and the voltage signal of the sign bit sb of floating-point number B on node 202s to generate a voltage signal for a "subtraction" bit (i.e., an internal operator). Addition / subtraction circuit 222 then uses this "subtraction" bit to perform addition or subtraction operations. After receiving the voltage signal of the "negation" bit / flag generated by addition / subtraction circuit 222, the voltage signal for the sign bit sc of the final floating-point number C is output on node 205s.

[0106] The input voltage signal of the floating point number A in IEEE 754 format includes: the voltage signal of the sign bit sa on the node 201s, the exponent bit “(ea)” on the node 201e, and the floating point number “(ea)” on the node 201e. q-1 ,...,ea0)b≡ea(0:q-1)” and the tail digit “(a p-2 ,...,a0)b≡a(0:q-2)”. The voltage input nodes 201s, 201e and 201m constitute the voltage input node 201 of the floating-point number A in the IEEE 754 format. The input voltage signal of the floating-point number B in the IEEE 754 format includes: the voltage signal of the sign bit sb on the node 202s, the exponent bit “(eb” on the node 202e q-1 ,...,eb0)b≡eb(0:q-1)” and the tail digit “(b p-2 ,...,b0)b≡b(0:p-2)". The voltage input nodes 202s, 202e and 202m constitute the voltage input node 202 having the floating point number B in the IEEE 754 format.

[0107] The most significant bit circuit 210 is based on the index (ea) on the node 201e. q-1 ,...,ea0)b and the index on 202e (eb q-1 ,...,eb0)b voltage signal to get the most significant mantissa of two floating point numbers A and B "a p-1 ≡a(p-1)" and "b p-1 ≡b(p-1)". The voltage signals a(p-1) and b(p-1) together with the last digit "(a p-2 ,...,a0)b≡a(0:p-2)” and the last digit of node 202m “(b p-2 ,...,b0)b≡b(0:p-2)” constitutes the voltage signals of the p mantissa bits of the two floating point numbers A and B. The exponential subtraction (ea-eb) circuit 220, according to the exponent bit “(eaq-1 ,...,ea0)b≡ea(0:q-1)” and the index bit “(eb q-1 ,...,eb0)b≡eb(0:q-1)” voltage signal, generates a signed binary exponent difference: a sign bit (sed) and an exponent difference bit (ed(0:q-1)). Afterwards, the voltage signals of sed and ed(0:q-1) are fed to the mantissa alignment circuit 221 to parallel right shift the mantissa of the floating-point number A or B (the one with the smaller exponent) so as to align the mantissas of each other in the mantissa alignment circuit 221 for addition and subtraction operations. After the mantissa alignment circuit 221 shifts the mantissa bits of the floating-point number A or B, the mantissa bit m of the floating-point number A is aligned. The voltage signal of a(0:p-1) and the voltage signal of the aligned mantissa bit mb(0:p-1) of B are fed to the addition / subtraction circuit 220 for addition / subtraction operation. Please note that in the mantissa alignment circuit 221, the mantissa of the floating-point operand with a larger exponent is shifted by 0 positions, and the barrel shifter circuit 520 right-shifts the mantissa of the floating-point operand with a smaller exponent according to the shift code ed(0:q-1). For the floating-point operand with a smaller exponent, the shifted mantissa bits are truncated at the least significant bit (LSB) of the "p" mantissa bits so that the precision of the truncated mantissa is 1 / 2. (p-1) .

[0108] At the same time, the voltage signal of the sign bit sed is fed to the exponent selection / addition circuit 223 to select the larger exponent between ea(0:q-1) and eb(0:q-1) for addition with the carry bit mc(p) generated by the addition / subtraction circuit 222 to generate the calculated exponent es(0:q). Subsequently, the voltage signal of the calculated mantissa bit mc(0:p) from the addition / subtraction circuit 222 and the calculated exponent bit es(0:q) from the exponent selection / addition circuit 223 are fed to the format conversion circuit 230 to convert the calculated exponent es(0:q) and the calculated mantissa bit mc(0:p) into a final floating-point number in the IEEE 754 format.

[0109] In a general embodiment, Figure 2 A schematic diagram of a floating-point addition and subtraction circuit device 200 is shown for performing addition / subtraction operations on (q+p)-bit floating-point numbers in accordance with the IEEE 754 format. Figure 3 The circuit 210 for displaying the most significant bit generates voltage signals for the most significant mantissa bits a(p-1) and b(p-1) according to the input voltage signal of the exponent bit "ea(0:q-1)" of the floating point number A at the node 201e and the input voltage signal of the exponent bit "eb(0:q-1)" of the floating point number B at the node 202e. When the voltage signal Enb at the node 204 is equal to the voltage signal V DDDuring startup, NMOSFET devices 301 and 302 output voltage signals of the most significant mantissa bits a(p-1) and b(p-1) at nodes 314 and 315, respectively. The gate of NMOSFET device 301 is connected to node 201e to receive voltage signal ea(0:q-1), while the gate of NMOSFET device 302 is connected to node 202e to receive voltage signal eb(0:q-1). If the ea(0:q-1) voltage signals are all input V SS (ie, all digital values ​​are 0), then all NMOSFET devices 301 are turned off and output voltage signal V at node 314. SS (digital value 0). If the voltage signal of any bit in ea(0:q-1) is input to V DD (i.e. digital value 1), the gate voltage is V DD The corresponding NMOSFET device 301 is turned on and outputs a voltage signal V at the node 314. DD (digital value 1). Similarly, if the eb(0:q-1) voltage signals are all input V SS (ie, all digital values ​​are 0), then all NMOSFET devices 302 are turned off and output voltage signal V at node 315. SS (digital value 0). If the voltage signal of any bit in eb(0:q-1) is input to V DD (i.e. digital value 1), the gate voltage is V DD The corresponding NMOSFET device 302 is turned on and outputs a voltage signal V at the node 315. DD (numeric value 1).

[0110] like Figure 4 As shown, the exponential subtraction circuit 220 is implemented as a q-bit binary subtraction circuit. Figure 4 In FIG, the exponential subtraction circuit 220 includes a q-bit exponential subtraction circuit 410 in the first row, a two's complement conversion circuit 420 in the second row, an addition circuit 430 (for operations on a normal floating-point number and a normal floating-point number) in the third row, and an XOR gate 411. The voltage signal ea (0:q-1) on the node 201e and the voltage signal eb (0:q-1) on the node 202e are input to the subtraction circuit 410 to generate a sign bit sed on the node 412 for selecting the floating-point operand with the smaller exponent, and a shift code ed (0:q-1) on the node 416 for shifting down the mantissa position of the floating-point operand with the smaller exponent to align the mantissa position of the floating-point operand with the larger exponent. If the voltage signal of the sign bit sed outputted on the node 412 is V SS(digital value 0), indicating that the exponent of floating point operand A is greater than or equal to the exponent of floating point number B, that is, the exponent difference is positive or zero. If the voltage signal of the sign bit sed output on node 412 is V DD (i.e., digital value 1), indicating that the exponent of floating-point operand A is less than the exponent of floating-point operand B, i.e., the exponent difference is negative. For a negative exponent difference, the two's complement conversion circuit 420 in the second row converts the binary code input voltage signal at output node 413 of the first row circuit 410 into a two's complement binary code output voltage signal at output node 414. Otherwise, for a positive or zero exponent difference, the voltage signal outputted from the two's complement conversion circuit 420 in the second row at node 414 is the same as the voltage signal outputted from output node 413 of the first row circuit 410.

[0111] In finite floating-point binary representation, subnormal floating-point numbers are represented by binary exponents containing all zeros and a leading mantissa of 0, while regular floating-point numbers are represented by at least one non-zero binary exponent and a leading mantissa of 1. To properly align the mantissa of a regular floating-point operand with the mantissa of a regular floating-point operand for addition and subtraction, the mantissa of the subnormal floating-point operand must be shifted down one position, because the leading mantissa bits of 0 and 1 are different. Therefore, the addition circuit 430 in the third row adds the output binary value (“1” represents a(p-1)≠b(p-1), and “0” represents a(p-1)=b(p-1)) on the output node 415 of the XOR gate 411 to the output of the circuit 420 in the second row to obtain the correct shift code ed(0:q-1) of the mantissa of a regular floating-point operand, so as to align the mantissa of another regular floating-point operand in subsequent addition and subtraction operations.

[0112] Figure 5A According to one embodiment of the present invention, the display Figure 2 FIG2 is a circuit diagram of a mantissa alignment circuit 221 for right-shifting the mantissa of a floating-point operand with a smaller exponent to align the mantissa of a floating-point operand with a larger exponent. Figure 5AIn the embodiment, the mantissa alignment circuit 221 includes a selection circuit 510, a barrel shifter circuit 520, and an operation sequence circuit 530. The selection circuit 510 is used to select the mantissa bit with the smaller exponent as si(0:p-1) to be fed into the input of the barrel shifter circuit 520; the barrel shifter circuit 520 shifts down the input mantissa bit si(0:p-1) in parallel and fills the blank bits with "0" to serve as the mantissa bit so(0:p-1) with the smaller exponent; the operation sequence circuit 530 is used to restore the operands to the original operation order (always placing the mantissa bit of A in the first operation position and the mantissa bit of B in the second operation position, no matter which floating-point number has the smaller exponent). Figure 5B The barrel shifter circuit 520 includes 2p columns of transmission gates (Clm(0) to Clm(2p-1)), wherein the input nodes of the first p columns of transmission gates (Clm(0) to Clm(p-1)) are connected to the ground voltage V at the node 501. SS (digital value 0), fill the blank significant mantissa bits shifted down with "0", and output it at node 504 as the left part of so(0:p-1). Figure 4 The voltage signal of the shift code ed(0:q-1) inputted to the node 416 of the circuit 220 is used to control the mantissa position of the right shift of the input signal si(0:p-1) at the node 503 to obtain the signal so(0:p-1) at the output node 504. When the signal sed at the node 412 is equal to the voltage signal V SS When (A>=B), the selection circuit 510 transmits the input voltage signal a(0:p-1) to the node 506 as the voltage signal o(0:p-1), and transmits the input voltage signal b(0:p-1) to the input node 503 of the barrel shifter circuit 520 as the input signal si(0:p-1), so as to right-shift the mantissa position of the floating-point operand B with a smaller exponent; at the same time, if the signal sed on the node 412 is equal to the voltage signal V SS (A>=B), the operation sequence circuit 530 transmits the voltage signal o(0:p-1) on the node 506 to the output node 531 as the voltage signal ma(0:p-1), and transmits the voltage signal so(0:p-1) on the output node 504 of the barrel shifter circuit 520 to the output node 532 as the voltage signal mb(0:p-1). When the signal sed on the node 412 is equal to the voltage signal V DDWhen (A < B), the selection circuit 510 transfers the input voltage signal b(0:p - 1) to the node 506 as the voltage signal o(0:p - 1), and transfers the input voltage signal a(0:p - 1) to the input node 503 of the barrel shifter circuit 520 as the input signal si(0:p - 1), so as to shift the mantissa position of the floating - point number A with a smaller exponent to the right; at the same time, if the signal sed on the node 412 is equal to the voltage signal V DD (A < B), the operation sequence circuit 530 transfers the voltage signal o(0:p - 1) on the node 506 to the output node 532 as the voltage signal mb(0:p - 1), and transfers the voltage signal so(0:p - 1) on the output node 504 of the barrel shifter circuit 520 to the output node 531 as the voltage signal ma(0:p - 1).

[0113] Figure 6 Display Figure 2 Schematic diagram of the addition / subtraction circuit 222. The addition / subtraction circuit 222 includes a p - bit addition / subtraction circuit 610, a p - bit two's complement conversion circuit 620, and a carry / negation logic circuit 630. Figure 6 In Figure 5A The aligned mantissas ma(0:p - 1) and mb(0:p - 1) generated by the circuit 221 are respectively fed into the nodes 531 and 532. Figure 14 The voltage signal V of the "subtraction" bit (i.e., an internal operator) output by the addition / subtraction selection and sign logic circuit 240 to the node 1406 DD (numerical value 1) and V SS (numerical value 0) respectively select the subtraction operation (i.e., the subtraction operation of the aligned mantissas: (ma(0:p - 1)-mb(0:p - 1))) and the addition operation (i.e., the addition operation of the aligned mantissas: (ma(0:p - 1)+mb(0:p - 1))). After the addition / subtraction operation, the voltage signal mc(0:p - 1) is output at the node 604 and a carry bit mc(p) is output at the node 605. The carry bit on the node 605: "mc(p) is equal to V DD (numerical value 1)" represents an extra carry after the addition operation, otherwise, "mc(p) is equal to V SS (numerical value 0)" represents no extra carry after the addition operation. At the same time, the "negation" bit / flag on the node 606 is equal to V DD (numerical value 1) represents that the result of the subtraction operation is negative, i.e., ma(0:p - 1)<mb(0:p -​(digital value 0) represents that the result of the subtraction operation is a positive value or 0, that is, ma(0:p-1)>=mb(0:p-1). Then, the voltage signal of the "negative" bit / flag on node 606 is fed to the addition / subtraction selection and sign logic circuit 240 to obtain Figure 2 The voltage signal of the sign sc of the final floating point number C on the node 205s.

[0114] Figure 7 According to one embodiment of the present invention, a circuit diagram of exponent selection / addition circuit 223 is shown. Exponent selection / addition circuit 223 includes a row of transmission gates 710 and an addition circuit 720. The row of transmission gates 710 uses a select control voltage signal sed to select the larger exponent between ea(0:q-1) at output node 201e and eb(0:q-1) at node 202e. Addition circuit 720 is configured to add the selected larger exponent to the carry bit mc(p) at node 605 to generate the post-operation exponent es(0:q) at nodes 705 and 206. Figure 7 The post-operation index es(0:q) on nodes 705 and 206 and Figure 6 The mantissa mc(0:p) after operation on nodes 604 and 605 respectively represents the exponent bit and mantissa bit of the floating point number after operation, and does not include the sign bit. Figure 2 The IEEE 754 format conversion circuit 230 converts the post-calculation exponent es(0:q) and the post-calculation mantissa mc(0:p).

[0115] For the IEEE 754 format conversion circuit 230, Figure 8 A circuit diagram of a leading zero detection circuit 231 is shown. The leading zero detection circuit 231 is used to detect the first / leading non-zero mantissa bit relative to the MSB mc(p) in the mantissa mc(0:p). Figure 8 In the example, the voltage signal of mc(0:p) (including the carry bit mc(p)) is input at nodes 604 and 605. When the first non-zero bit mc(k) relative to the MSB mc(p) is detected from mc(0:p), the circuit 231 outputs a voltage signal V at the corresponding row SL(pk) of node 802. DD (“1”), and the other columns SL(n) output voltage signals V SS (“0”), where n=0~p but n≠(pk). Then, the voltage signal of SL(0:p) is fed to Figure 9 The leading zero shift code generating circuit 232 generates the shift code LZC k The voltage signal of (0:q-1) is Figure 10The LZ barrel shifter circuit 233 shifts up (or left) the mantissa bits mc(0:p-1) to the first non-zero leading mantissa position (i.e., ml(p-1)). Note that Figure 9 The shift code generating circuit 232 includes a read-only memory (ROM) array having a plurality of ROM cells, wherein each metal contact 911 is predefined and used to connect the drain active area of ​​the corresponding transistor 910 to two metal lines (to which V DD and V SS ), that is, a plurality of predefined binary codes are stored in the plurality of ROM cells. Only the selected word line SL(pk) in the input node 802 is V DD is turned on to output the corresponding ROM code LZC at node 902 k (0:q-1), that is: value (pk) = LZC k (q-1)2 q-1 +LZC k (q-2)2 q-2 +...+LZC k (1)2 1 +LZC k (0)2 0 For example, if mc(p-2)=1 and mc(p)=mc(p-1)=0, then mc(p-2) is called the leading / first non-zero bit in mc(0:p), resulting in SL(2)=1 and SL(k)=0 for all other digits, where k=0,1,3,…,p. Figure 9 The bit line node 902 of the circuit 232 outputs the shift code LZC k (0:q-1)=(00…10)b voltage signal.

[0116] Figure 10 The circuit diagram of the LZ barrel shifter circuit 233 is shown. The LZ barrel shifter circuit 233 is used to Figure 9 The shift code LZC of the node 902 of the leading zero shift code generating circuit 232 is k (0:q-1), shifting mc(0:p-1) on input node 604 to ml(0:p-1) on output node 1003 in parallel, i.e., the first non-zero leading digit position. The barrel shifter circuit 233 includes 2p columns of transmission gates (Clm(0) to Clm(2p-1)), where the input nodes of the last p columns of transmission gates (Clm(p) to Clm(2p-1)) are connected to the ground voltage V at node 1005. SS (digital value 0). After that, the voltage signal of ml(0:p-1) is fed into Figure 11Input node 1003 of the subnormal barrel shifter circuit 234 . Figure 11 In the embodiment, the subnormal barrel shifter circuit 234 is based on Figure 12 The exponent adjustment circuit 235 shifts the mantissa bits ml(0:p-1) downward based on the shift code Sb(0:q-1) at the node 1202 and fills the leading subnormal blank mantissa bits with 0s to output c(0:p-2) at the output node 205m. The subnormal barrel shifter circuit 234 includes 2p columns of transmission gates (Clm(0) to Clm(2p-1)), where the input nodes of the first p columns of transmission gates (Clm(0) to Clm(p-1)) are connected to the ground voltage V at the node 1205. SS (numeric value 0). Figure 11 Subnormal barrel shifter circuit 234 shifts the mantissa of the normal floating-point number by zero positions according to shift code Sb(0:q-1)=(0…0)b, thereby outputting c(0:p-2) at output node 205m. In other words, the voltage signal ml(0:p-1) at node 1003 is directly transferred to node 205m to output the voltage signal c(0:p-2). Figure 12 The exponent adjustment circuit 235 generates a voltage signal of the subnormal shift code Sb(0:q-1). Figure 5B and Figure 10-11 The barrel shifter circuits 520, 233, and 234 are provided for illustrative purposes only and are not intended to be limiting of the present invention. In actual implementation, as long as the same results can be achieved, the barrel shifter circuits 520, 233, and 234 may be implemented using other types of barrel shifters, such as a crossbar barrel shifter and a barrel shifter implemented by connecting multiple parallel multiplexers in series, which also falls within the scope of the present invention.

[0117] Figure 12 In the example, the index adjustment circuit 235 includes an “add one” circuit 1210, a subtraction circuit 1220, an “add one” circuit 1230, and a logic circuit 1240. The “add one” circuit 1210 is used to convert the shift code LZC k (0:q-1) is added with the value 1, and the subtraction circuit 1220 is used to subtract the output (LZC) of the circuit 1210 from the calculated exponent es(0:q-1). k (0:q-1)+(0...1)b). The "add one" circuit 1230 is used to add the value 1 back to compensate for the extra value 1 subtracted from the regular floating point number, that is, output [es(0:q-1)-(LZC k(0:q-1)+(0...1)b)+(0...1)b]; the logic circuit 1240 generates a voltage signal of the final exponent ec(0:q-1) at the node 205e, and generates a voltage signal of the shift code Sb(0:q-1) at the node 1202. In the logic circuit 1240, the voltage signal of the exponent symbol esg at the node 1221 is used to determine whether the floating-point number after the above operation is a subnormal or normal floating-point number. The voltage signal V of the exponent symbol esg at the node 1221 is used to determine whether the floating-point number after the above operation is a subnormal or normal floating-point number. DD This means that the floating point number after the above operation is a subnormal floating point number, and its exponent bits are all equal to 0. Therefore, the exponent ec(0:q-1) on the node 205e is set to V SS (“0”), and at the same time, the voltage signal of the non-zero-order normal shift code Sb (0:q-1) generated by the output node 1222 of the subtraction circuit 1220 and output at the node 1202 is fed into Figure 11 The subnormal barrel shifter circuit 234 shifts down (or right) the subnormal mantissa bits and fills the leading blank mantissa bits with 0. On the other hand, the voltage signal V of the exponent symbol esg on the node 1221 SS The floating point number after the above operation is a normal floating point number with a non-zero exponent. The output of the node 1222 of the subtraction circuit 1220 is fed into the "add one" circuit 1230, which adds the value 1 back to compensate for the extra subtracted value 1 to obtain a correct non-zero exponent ec(0:q-1) of a normal floating point number. At the same time, because the voltage signal of the exponent sign esg on the node 1221 is V SS , the logic circuit 1240 generates the zero shift code Sb(0:q-1)=(0...0)b, so Figure 11 The subnormal barrel shifter circuit 2341 does not shift down any mantissa positions, but instead passes ml(0:p-2) directly to the output c(0:p-2) at node 205m. Note that Figure 7 The most significant exponent bit es(q) generated by the exponent selection / addition circuit 223 is directly passed to the overflow node 206 to flag an overflow condition.

[0118] Figure 13 and 14Schematic diagrams of the logic table 1310 and the corresponding addition / subtraction selection and sign logic circuit 240 are shown respectively. The first column of the logic table 1310 defines the addition / subtraction operation formula for the absolute values ​​of two floating-point numbers A and B. The first row of the logic table 1310 shows the inputs: the sign bits sa and sb of the two floating-point numbers A and B, the A / S bit for selecting addition or subtraction (i.e., an external operator), the "subtraction" bit (i.e., an internal operator, provided to the addition / subtraction circuit 222 to perform addition or subtraction operations on the absolute values ​​of the two floating-point numbers A and B), and the sign bit sc of the final floating-point number C. The sign bits sa, sb, and sc of the floating-point numbers A, B, and C, if 1, represent a negative number, and if 0, represent a positive number or equal to 0; the A / S bit equal to 0 represents addition, and equal to 1 represents subtraction. The logic value of sc in the last column includes the "negation" bit and " (the inverse of the negation bit)" bit, where the "negation" bit represents the negative sign of the floating-point number obtained after the addition / subtraction circuit 222 subtracts the two aligned p-bit mantissas ma(0:p-1) and mb(0:p-1) of the absolute values ​​of the two floating-point operands A and B. The "negation" bit / sign of the floating-point number obtained from the addition / subtraction circuit 222 is defined as 0 to represent a positive value or a value equal to 0, and as 1 to represent a negative value.

[0119] Figure 14 A schematic diagram of the addition / subtraction selection and sign logic circuit 240 implementing the logic table 1310 is shown. The addition / subtraction selection and sign logic circuit 240 receives Figure 2 Voltage signals sa, sb and A / S on nodes 201s, 202s and 203. According to the logic values ​​of the 2nd, 3rd and 4th columns of the logic table 1310 and the input voltage signals of sa, sb and A / S, the logic circuit 1421 obtains the voltage signal of the "subtraction bit" on the node 1406 (corresponding to the 5th column of the logic table 1310). Afterwards, the voltage signal of the "subtraction bit" on the node 1406 is fed to the addition / subtraction circuit 222 to subtract the two aligned mantissa bits ma (0: p-1) and mb (0: p-1) of the absolute value of the floating-point operand A and the absolute value of the floating-point operand B. At the same time, the voltage signal of the "negation bit" from the addition / subtraction circuit 222 is fed to the logic circuit 1422. The logic circuit 1422 responds to the "negation" bit or " (negated inverse)" bit (selected by the control voltage signal sa (corresponding to the logic value of the second column of the logic table 1310)), and outputs a voltage signal at node 1407. Therefore, according to the voltage signal sa (corresponding to the logic value of the second column of the logic table 1310) or The circuit 1423 generates an output signal sc of the sign of the final floating-point number C at node 205s based on the “subtraction” bit (corresponding to the logic value of the 5th column of the logic table 1310) selected by the “subtraction” bit on node 1406 (corresponding to the logic value of the 4th column of the logic table 1310)).

[0120] In one embodiment, a circuit device for adding and subtracting 16-bit floating-point numbers in the IEEE 754 format has been designed and fabricated using a 40nm CMOS process technology. The circuit device has been verified to produce a final floating-point number from an addition / subtraction operation of two floating-point numbers, rounded to the nearest floating-point number in the IEEE 754 16-bit format. Based on post-circuit simulations and circuit RC loads, the circuit device operates in approximately 0.6 nanoseconds. At V DD = 1.2V high voltage power supply, the average peak current of various floating-point operations is about tens of microamperes (μA).

[0121] The preferred embodiments provided above are merely illustrative of the present invention and are not intended to limit the present invention to a specific type or exemplary embodiment. Therefore, this description should be viewed as illustrative rather than restrictive. The preferred embodiments provided above are intended to effectively illustrate the present invention and its best mode of implementation, thereby enabling those skilled in the art to understand the various embodiments and modifications of the present invention as appropriate for a particular use or implementation. The scope of the present invention is defined by the claims and their equivalents, in which all terms are to be given their broadest reasonable meanings unless otherwise indicated. Therefore, the use of "the present invention" and similar terms does not limit the scope of the claims to a specific embodiment, and any reference to specific preferred embodiments of the present invention is not intended to limit the present invention, and no such limitation should be inferred. The present invention is defined solely by the scope and spirit of the appended claims. This abstract is provided as required by law to enable searchers to quickly identify the subject matter of this disclosure from any patents issued herein and is not intended to interpret or limit the scope or meaning of the claims. Any advantages and benefits may not apply to all embodiments of the present invention. It should be understood that various modifications or variations can be made by those skilled in the art and all of them should fall within the scope of the present invention as defined by the claims. Furthermore, all elements and components in this specification are not intended to be dedicated to the public, regardless of whether the claims list such elements and components.

Claims

1. A floating-point arithmetic device, characterized in that The apparatus is configured to perform an arithmetic operation on a first operand and a second operand according to an external operator to generate a final number, wherein the external operator represents one of addition and subtraction, wherein the first operand, the second operand, and the final number are all binary floating-point numbers and each includes a sign bit, a q-bit exponent, and a p-bit mantissa, the apparatus comprising: an exponent subtraction circuit for calculating a difference between the q-bit exponents of the first operand and the second operand to generate a first sign bit and an exponent difference; an exponent calculation circuit, coupled to the exponent subtraction circuit, configured to select a larger exponent from the q-bit exponents of the first operand and the second operand according to the first sign bit, and generate an intermediate (q+1)-bit exponent according to the larger exponent; a mantissa calculation circuit coupled to the exponent subtraction circuit for (1) selecting a smaller exponent from the q-bit exponents of the first operand and the second operand according to the first sign bit, (2) right-shifting one of the p-bit mantissas of the first operand and the second operand corresponding to the smaller exponent according to a first q-bit binary shift code to generate a right-shifted p-bit mantissa, and (3) performing one of addition and subtraction on the right-shifted p-bit mantissa and the other of the p-bit mantissas of the first operand and the second operand according to an inner operator to generate an intermediate (p+1)-bit mantissa, wherein the inner operator is related to the outer operator and the sign bits of the first operand and the second operand, and wherein the first q-bit binary shift code is equal to the exponent difference; as well as A conversion circuit is coupled to the exponent calculation circuit and the mantissa calculation circuit, for converting the intermediate (q+1)-bit exponent and the intermediate (p+1)-bit mantissa into the q-bit exponent and the p-bit mantissa of the final number respectively.

2. The device according to claim 1, wherein Also includes: A sign and operator logic circuit is coupled to the mantissa calculation circuit, and generates a sign bit of the final number and the inner operator based on the outer operator, the sign bits of the first operand and the second operand, and a negation flag, wherein the negation flag indicates whether the absolute value of the right-shifted p-bit mantissa is less than the absolute value of the other p-bit mantissa of the first operand and the second operand.

3. The device according to claim 2, wherein The symbol and operator logic circuit includes: Two XOR gate devices connected in series have three input terminals for receiving the outer operator and the sign bits of the first operand and the second operand to generate the inner operator.

4. The device according to claim 1, wherein The index calculation circuit comprises: A first adding circuit adds the larger exponent to the most significant bit (MSB) of the middle (p+1)-bit mantissa to generate the middle (q+1)-bit exponent.

5. The device according to claim 1, wherein The exponential subtraction circuit comprises: a first subtraction circuit that subtracts the q-bit exponent of the second operand from the q-bit exponent of the first operand to produce a signed intermediate exponent difference; an XOR gate device having two input terminals for receiving the MSBs of the p-bit mantissa of the first operand and the second operand to generate an output bit; and A second adding circuit adds the output bit and the signed intermediate exponent difference to generate the first sign bit and the exponent difference.

6. The device according to claim 1, wherein The mantissa calculation circuit comprises: A first barrel shifter circuit right-shifts one of the p-bit mantissas of the first operand and the second operand corresponding to the smaller exponent in parallel according to the first q-bit shift binary code to generate the right-shifted p-bit mantissa.

7. The device according to claim 1, wherein The mantissa calculation circuit comprises: An arithmetic circuit performs one of addition and subtraction on the right-shifted p-bit mantissa and the other p-bit mantissa of the first operand and the second operand according to the internal operator to generate the intermediate (p+1)-bit mantissa.

8. The device according to claim 1, wherein The MSB of the middle (q+1)-bit exponent indicates whether the final number is outside the numerical representation range.

9. The device according to claim 1, wherein The conversion circuit is configured to (a) discriminate a leading non-zero bit position from the intermediate (p+1)-bit mantissa relative to the MSB position of the intermediate (p+1)-bit mantissa, (b) convert the leading non-zero bit position into a second q-bit shifted binary code, (c) parallel left-shift the p less significant bits of the intermediate (p+1)-bit mantissa according to the second q-bit shifted binary code to generate an intermediate p-bit mantissa, and (d) generate a q-bit exponent of the final value according to a difference between the intermediate (q+1)-bit exponent and the second q-bit shifted binary code.

10. The device according to claim 9, wherein The conversion circuit comprises: a third adding circuit for adding a value 1 to the second q-bit shifted binary code to generate a first q-bit sum binary code; a second subtraction circuit for subtracting the first q-bit sum binary code from the intermediate (q+1)-bit exponent to generate a second sign bit esg and a q-bit difference binary code; a fourth adding circuit for adding a value 1 to the q-bit difference binary code to generate a second q-bit sum binary code; and a logic circuit coupled to the second subtraction circuit and the fourth addition circuit to generate a q-bit exponent of the final number and a third q-bit shifted binary code; If the second sign bit esg is equal to 1, the logic circuit sets the q-bit exponent of the final number to a binary code of a zero vector, and sets the third q-bit shift binary code to the q-bit difference binary code; and If the second sign bit esg is equal to 0, the logic circuit sets the q-bit exponent of the final number to be equal to the second q-bit sum binary code, and sets the third q-bit shift binary code to be equal to a binary code of a zero vector.

11. The device according to claim 10, wherein The conversion circuit comprises: a second barrel shifter circuit for parallel left-shifting p less significant bits of the intermediate (p+1)-bit mantissa according to the second q-bit shift binary code to generate the intermediate p-bit mantissa; as well as A third barrel shifter circuit right-shifts the intermediate p-bit mantissa in parallel according to the third q-bit shift binary code to generate the p-bit mantissa of the final value.

12. The device according to claim 11, wherein The conversion circuit comprises: a detection circuit coupled to the mantissa calculation circuit and having (p+1) output terminals, for distinguishing the leading non-zero bit position from the middle (p+1)-bit mantissa relative to the MSB position of the middle (p+1)-bit mantissa, and generating an active bit and p invalid bits on the (p+1) output terminals; and A read-only memory array receives the enable bit and the p invalid bits to output the second q-bit shifted binary code.

13. The device according to claim 12, wherein The detection circuit comprises: (p-1) logic blocks and a logic element connected in series are used to respectively check the (p-1)th bit to the 0th bit of the middle (p+1)-bit mantissa to provide data to the 1st to pth output terminals of the (p+1)-bit output terminals; The MSB of the middle (p+1)-bit mantissa is provided to the 0th output terminal among the (p+1) output terminals, and the data provided to the (p+1) output terminals form the enable bit and the p invalid bits.

14. The device according to claim 12, wherein The ROM array comprises: A plurality of ROM cells are arranged in a circuit configuration having rows and columns for pre-storing a plurality of predefined binary codes; (p+1) word lines are respectively connected to the (p+1) output terminals of the detection circuit; as well as q bit lines coupled to the second barrel shifter; When one of the (p+1) word lines is activated by the activation bit, the ROM cells in a corresponding row are turned on to output the second q-bit shifted binary code on the q bit lines.

15. A method of operating a floating point arithmetic device, characterized in that The floating-point arithmetic device performs an arithmetic operation on a first operand and a second operand according to an external operator to generate a final number, wherein the floating-point arithmetic device includes a first barrel shifter circuit and a conversion circuit, wherein the external operator represents one of addition and subtraction, wherein the first operand, the second operand, and the final number are all binary floating-point numbers and each includes a sign bit, a q-bit exponent, and a p-bit mantissa, and the method includes the following steps: calculating a difference between the q-bit exponents of the first operand and the second operand to generate a first sign bit and an exponent difference; right-shifting one of the p-bit mantissas of the first operand and the second operand corresponding to a smaller exponent using the first barrel shifter circuit according to a first q-bit binary shift code to generate a right-shifted p-bit mantissa, wherein the first q-bit binary shift code is equal to the exponent difference; performing one of addition and subtraction on the right-shifted p-bit mantissa and the other of the p-bit mantissas of the first operand and the second operand according to an inner operator to generate an intermediate (p+1)-bit mantissa, wherein the inner operator is related to the outer operator and the sign bits of the first operand and the second operand; obtaining an intermediate (q+1)-bit exponent according to a larger exponent, wherein the larger exponent is selected from one of the q-bit exponents of the first operand and the second operand according to the first sign bit; and The intermediate (q+1)-bit exponent and the intermediate (p+1)-bit mantissa are converted into the q-bit exponent and the p-bit mantissa of the final number respectively.

16. The method according to claim 15, wherein Also includes: The sign bit of the final number and the inner operator are obtained according to the outer operator, the sign bits of the first and second operands, and a negation flag, wherein the negation flag indicates whether the absolute value of the right-shifted p-bit mantissa is less than the absolute value of another p-bit mantissa among the p-bit mantissas of the first and second operands.

17. The method according to claim 16, wherein The step of obtaining the sign bit of the final number and the internal operator comprises: performing an XOR operation on the outer operator and the sign bits of the first operand and the second operand to obtain the inner operator; and The sign bit of the final number is obtained according to the sign bit of the first operand, the negation flag and the internal operator.

18. The method according to claim 15, wherein The step of obtaining the intermediate (q+1)-bit index comprises: The larger exponent is added to the most significant bit (MSB) of the middle (p+1)-bit mantissa to obtain the middle (q+1)-bit exponent.

19. The method according to claim 15, wherein The calculation step comprises: subtracting the q-bit exponent of the second operand from the q-bit exponent of the first operand to produce a signed intermediate exponent difference; performing an XOR operation on the MSBs of the p-bit mantissas of the first operand and the second operand to obtain an output bit; and The output bit is added to the signed intermediate exponent difference to obtain the first sign bit and the exponent difference.

20. The method of claim 15, wherein: The respective conversion steps include: Using a detection circuit, distinguish a leading non-zero bit position from the middle (p+1)-bit mantissa relative to the MSB position of the middle (p+1)-bit mantissa; Converting the leading non-zero bit position into a second q-bit shifted binary code using a read-only memory (ROM) array; and Using a second barrel shifter circuit, the p less significant bits of the middle (p+1)-bit mantissa are parallel-left-shifted according to the second q-bit shift binary code to generate a middle p-bit mantissa; The conversion circuit includes the detection circuit, the second barrel shifter circuit, and the ROM array.

21. The method according to claim 20, wherein The respective conversion steps include: After the distinguishing step and the converting step, the q-bit index of the final value is obtained according to the difference between the intermediate (q+1)-bit index and the second q-bit shifted binary code.

22. The method according to claim 21, wherein The step of obtaining the q-bit exponent of the final value comprises: Adding a value 1 to the second q-bit shift binary code to obtain a first q-bit sum binary code; Subtracting the first q-bit sum binary code from the middle (q+1)-bit exponent to obtain a second sign bit esg and a q-bit difference binary code; Adding a value 1 to the q-bit difference binary code to obtain a second q-bit sum binary code; If the second sign bit esg is equal to 1, the q-bit exponent of the final number is set to a binary code of a zero vector, and the third q-bit shift binary code is set to the q-bit difference binary code; as well as If the second sign bit esg is equal to 0, the q-bit exponent of the final number is set equal to the second q-bit sum binary code, and the third q-bit shift binary code is set to a binary code of a zero vector.

23. The method according to claim 22, wherein The respective conversion steps further include: After the step of parallel left shifting the p less significant bits of the intermediate (p+1)-bit mantissa, a third barrel shifter circuit is used to parallel right shift the intermediate p-bit mantissa according to the third q-bit shift binary code to output the p-bit mantissa of the final value; The conversion circuit further includes the third barrel shifter circuit.

24. The method of claim 20, wherein: The distinguishing step comprises: Using the detection circuit, distinguish the leading non-zero bit position from the middle (p+1)-bit mantissa relative to the MSB position of the middle (p+1)-bit mantissa to obtain a positive bit and p invalid bits; The detection circuit includes (p-1) logic blocks connected in series and a logic element.

25. The method of claim 24, wherein: The step of converting the leading non-zero bit position into the second q-bit shifted binary code comprises: Applying the enable bit and the p invalid bits to (p+1) word lines of the ROM array; and When the activation bit activates one of the (p+1) word lines, the ROM cells in a corresponding row are turned on to output the second q-bit shifted binary bits through the q bit lines of the ROM array; The ROM array includes a plurality of ROM cells arranged in a circuit configuration of rows and columns for pre-storing a plurality of pre-defined binary codes.

26. The method of claim 15, wherein: The MSB of the middle (q+1)-bit exponent indicates whether the final number is outside the numerical representation range.

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