FPGA multiplier optimization method and device

Abstract

The present invention provides an FPGA multiplier optimization method, which detects the actual effective bit width of data at two input ends, generates a bit width control signal, and selects a small bit width parallel calculation mode or a full bit width calculation mode based on the bit width control signal; in the small bit width parallel calculation mode, multiple groups of input data with effective bits of small bit width are sign-bit extended to generate parallel calculation data including sign bits, and the generated parallel calculation data are shifted and spliced ​​before being sent to a multiplier for parallel calculation; in the full bit width calculation mode, the data directly enters the multiplier for calculation. The present invention also provides an FPGA multiplier optimization device.

Description

Technical Field

[0001] The present invention belongs to the technical field of digital integrated circuits, and in particular relates to a FPGA multiplier optimization method and device. Background Art

[0002] With the rapid advancement of modern electronics and digital signal processing (DSP) technology, FPGA-based DSP modules have found widespread application in signal computation and processing. These advanced modules efficiently implement complex algorithms, providing flexible and powerful solutions to meet the growing demand for high-performance computing. By leveraging the DSP resources integrated in FPGAs, engineers can design more efficient and precise digital signal processing systems for a variety of industries, including communications, audio processing, and image processing.

[0003] The multiplier in the DSP module is a core component. The traditional 18-bit × 18-bit fixed-bit-width multiplier is highly efficient in hardware implementation. However, for certain specific application scenarios, such as audio processing, neural networks, and embedded computing tasks, the actual bit width of the input data is often less than 18 bits and is highly random. In this case, the unused high bits lead to a waste of hardware resources. The traditional multiplier can only process one set of multiplication operations at a time and cannot use the remaining free bit width resources for parallel computing, reducing computing efficiency. Summary of the Invention

[0004] The present invention provides an FPGA multiplier optimization method and device, which merges data with a smaller actual bit width input into the multiplier to improve the utilization efficiency of the multiplier space.

[0005] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0006] To achieve one, part, or all of the above-mentioned objectives or other objectives, a technical solution of the present invention provides an FPGA multiplier optimization method, which detects the actual effective bit width of data at two input ends, generates a bit width control signal, and selects a small bit width parallel computing mode or a full bit width computing mode based on the bit width control signal; in the small bit width parallel computing mode, multiple groups of input data with effective bits of small bit width are sign-bit extended to generate parallel computing data including sign bits, and the generated parallel computing data are shifted and spliced ​​before being sent to the multiplier for parallel computing; in the full bit width computing mode, the data directly enters the multiplier for computing.

[0007] A leading zero circuit is used to determine the number of leading zeros in the input data, determine the highest non-zero bit in the input data, and then output the leading zero detection result to represent the effective bit width of the input data; a bit width control signal is generated based on the leading zero detection result; and the corresponding calculation mode is selected based on the bit width control signal and the set small bit width data merging threshold.

[0008] The leading zero circuit captures input data at the effective edge of the clock signal, scans the data bit by bit from the highest bit to the lowest bit, counts consecutive zeros until the first 1 is counted, and outputs the leading zero detection result.

[0009] The bit width control signal is obtained based on the multiplier bit width of the data input minus the leading zero detection result; if the bit width control signals of the two input end data are both less than or equal to the small bit width data merging threshold, the small bit width parallel calculation mode is started; if any one of the bit width control signals of the two input end data is greater than the small bit width data merging threshold, the full bit width calculation mode is started.

[0010] The multiplier bit width is 18, and the small bit width data merging threshold is 8.

[0011] When the small bit width parallel computing mode is selected, the small bit width valid bit data is compounded, including: performing bit width detection and sign bit extension processing on the input data to obtain valid bit data including the sign bit, performing a shift operation on the valid bit data after the sign bit extension processing, including performing a shift operation on the valid bit data after the sign bit extension processing based on the actual bit width of the detected input data and the preset shift amount of each group of data. After the shift operation, multiple groups of small bit width operation data are obtained, and the multiple groups of small bit width operation data are then spliced ​​together through logical "or" and aligned to a specific segment of the multiplier; the multiple groups of the spliced ​​small bit width operation data are sent to the multiplier, and each group of small bit width operation data is independently calculated.

[0012] The bit width control signal determines the input data shift amount.

[0013] The multiplier output result is divided into multiple segments, and each segment of the output result corresponds to the operation result of a group of small-bit-width operation data; the shifter extracts the operation result of each segment to obtain the operation result of each group of small-bit-width effective bit data.

[0014] Before splicing small-bit-width arithmetic data, dynamic control logic is used to monitor the total bit width of the multiple groups of spliced ​​small-bit-width arithmetic data, including calculating the total bit width of the multiple groups of currently spliced ​​small-bit-width arithmetic data, and before each splicing, judging the relationship between the remaining bit width of the multiplier input data and the bit width of the small-bit-width arithmetic data to be spliced. When the remaining bit width of the multiplier input data is greater than or equal to the bit width of the small-bit-width arithmetic data to be spliced, the data splicing continues; otherwise, the splicing is stopped and the spliced ​​data is sent to the subsequent module for calculation.

[0015] After multiple groups of small-bit-width operation data are spliced ​​together, they are arranged bit by bit starting from the low bit to the input of the multiplier, and the highest vacant bit is filled with 0.

[0016] Another technical solution of the present invention provides an FPGA multiplier optimization device for implementing the FPGA multiplier optimization method described above. The multiplier optimization device includes: an input bit width detection module, which uses a leading zero detection circuit to detect the bit width of the valid bit of the input data, generates a bit width control signal, and selects a small bit width parallel computing mode or a full bit width computing mode based on the bit width control signal; a bit width detection and sign bit extension module, which performs bit width detection and sign bit extension processing on the input data when the small bit width parallel computing mode is started, and performs a shift operation on the valid bit data after the sign bit extension processing, including performing a shift operation on the valid bit data after the sign bit extension processing based on the actual bit width of the detected input data and a preset shift amount for each group of data, and obtaining a multi-bit multiplier after the shift operation. The module is used to group small-bit-width operation data; the splicing judgment module judges the relationship between the remaining bit width of the multiplier input data and the bit width of multiple groups of small-bit-width operation data to be spliced, and decides whether to continue splicing the data; the bit width splicing and multiplexing module, in the small-bit-width parallel computing mode, splices the small-bit-width operation data to be spliced, and after the splicing of multiple groups of small-bit-width operation data is completed, it starts from the low bit and arranges them bit by bit to the input end of the multiplier, and fills the high-bit vacant bits with 0; the parallel multiplication calculation module calculates the input spliced ​​small-bit-width operation data in parallel, and outputs multiple segments of operation results, each segment of output result corresponds to the operation result of a group of small-bit-width operation data; the shifter extracts each segment of operation result to obtain the operation result of each group of small-bit-width valid bit data; when the full-bit-width calculation mode is enabled, the data is directly input into the multiplier for operation to output the multiplication result.

[0017] Compared with the prior art, the beneficial effects of the present invention mainly include: 1. The method of implementing adaptive data bit width detection using leading zero circuit logic in the present invention can dynamically identify the effective bit width of the input data and adjust the data splicing and calculation strategy based on the detection results. When the bit width is 1 to 8 bits, resource reuse is achieved through splicing; when the bit width is 9 to 18 bits, it is directly input to the multiplier for calculation without additional operations. This feature enables the present invention to flexibly adapt to a variety of bit width scenarios and meet different accuracy requirements.

[0018] 2. The data bit width splicing and multiplexing mode adopted by the present invention greatly improves the efficiency of bit width resource utilization, can make full use of the input resources of the multiplier, and supports bit-by-bit splicing of multiple small bit width data to the input end of the multiplier when performing small bit width multiplication operations (such as 1×1, 2×2, 3×3, ..., 8×8), thereby realizing multiple groups of small bit width calculations in one operation. This feature significantly improves the computing power of the multiplier, especially in low bit width and high frequency computing scenarios (such as audio processing and image processing), greatly improving the utilization and computing efficiency of hardware resources and reducing hardware redundancy.

[0019] 3. The FPGA multiplier optimization device of the present invention is simple and highly scalable. The adaptive detection, shifting, splicing, and multiplexer modules employed in the present invention implement bit-width adaptive detection and multiplexing. The concise and clear structural design facilitates hardware implementation and subsequent optimization. Furthermore, the design is highly scalable and can accommodate multipliers of varying bit widths, making the design more flexible.

[0020] In order to make the above and other objects, features and advantages of the present invention more clearly understood, preferred embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 This is a structural diagram of the FPGA multiplier optimization device of the present invention.

[0023] Figure 2 This is a schematic diagram of splicing multiple groups of small-bit-width operation data in the present invention. DETAILED DESCRIPTION

[0024] The foregoing and other technical aspects, features, and functions of the present invention are clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. Directional terms such as up, down, left, right, front, and back, used in the following embodiments, are intended solely to refer to the directions in the accompanying drawings. Therefore, the directional terms used are for illustrative purposes only and are not intended to limit the present invention.

[0025] Example 1

[0026] Embodiment 1 provides an FPGA multiplier optimization method, which detects the actual effective bit width of data at two input ends, generates a bit width control signal, and selects a small bit width parallel computing mode or a full bit width computing mode based on the bit width control signal. In the small bit width parallel computing mode, multiple groups of input data with effective bits of small bit width are sign-bit extended to generate parallel computing data including sign bits. The generated parallel computing data are shifted and spliced, and then sent to the multiplier for parallel computing. In the full bit width computing mode, the data directly enters the multiplier for computing.

[0027] The following is a detailed explanation of an FPGA multiplier optimization method of the present invention with reference to the accompanying drawings.

[0028] See also Figure 1 The FPGA multiplier optimization method in the first embodiment includes the following steps:

[0029] Step 1: Detect the bit width of the data data_ina and data_inb at the two input ends, and use the leading zero detection circuit to detect the bit width of the input data. The specific detection method is that the leading zero circuit captures the input data at the valid edge of the clock signal, scans the data bit by bit from the highest bit to the lowest bit, counts consecutive zeros until the first 1 is counted, and outputs the leading zero detection result, thereby determining the highest non-zero bit in the input data. The output leading zero detection result is used to represent the effective bit width of the input data.

[0030] Step 2: Generate a bit width control signal based on the leading zero detection result. Specifically, generate the bit width control signals bit_width_a and bit_width_b based on the leading zero detection results LZD_A and LZD_B, where bit_width_a represents the effective bit width of the input data data_ina, and bit_width_b represents the effective bit width of the input data data_inb. The bit width control signal is then generated through the following logic:

[0031] bit_width_a=18-LZD_A;

[0032] bit_width_b=18-LZD_B;

[0033] The above-mentioned bit width control signal generation logic uses the bit width 18 of the 18-bit×18-bit multiplier minus the leading zero detection result of each input data. This application uses an 18-bit×18-bit multiplier as the core of the parallel multiplication calculation. The multiplier bit width commonly used in FPGA is 18. Of course, multipliers of other bit widths can also be used as the core of the parallel multiplication calculation. The logic generation of the bit width control signal here can also be calculated according to the bit width of the selected multiplier.

[0034] Based on the above logic, the generated bit width control signal can be used not only to indicate the effective bit width of the data, but also to indicate the shift amount required when the data is shifted (left shifted).

[0035] Step S3: Based on the bit width control signal, select the small bit width parallel computing mode or the full bit width computing mode. Specifically, a small bit width data merging threshold is pre-set. When the generated bit width control signal is less than or equal to the small bit width data merging threshold, the small bit width parallel computing mode is started; if any of the bit width control signals of the two input end data is greater than the small bit width data merging threshold, the full bit width computing mode is started. In Example 1, the small bit width data merging threshold is set to 8. The judgment logic of the above process is as follows:

[0036] When bit_width_a≤8 and bit_width_b≤8, start the small bit width parallel computing mode;

[0037] When bit_width_a>8 or bit_width_b>8, full-bit-width calculation mode is enabled.

[0038] Step S3-1: When the small bit-width parallel computing mode is selected, the small bit-width valid bit data is compounded.

[0039] Step S3-11: perform bit width detection and sign bit extension processing on the input data, including sign bit extension of the valid bit data. The sign bit extension means that the sign bit extension occupies 1 bit. Figure 2 In the , each set of data input has one more bit after expansion compared to the original input data. Setting 1-bit sign bit extension can support signed bit operations, which is the basic operation for processing two's complement numbers. It can also prevent overflow and sign errors in the operation results.

[0040] The effective bit data after the sign bit extension processing is shifted, including the shift amount of each group of data determined by the bit width control signal based on the actual bit width of the detected input data. After the shift operation, multiple groups of small bit width operation data are obtained. The multiple groups of small bit width operation data are then combined together through logical "OR" to align them to a specific segment of the multiplier. (The alignment to the specific segment of the multiplier here means that after the multiple groups of small bit width operation data are spliced ​​together, they are arranged in sequence from the low bit to the input end of the multiplier, and the remaining high bit bits are filled with 0)

[0041] Multiple groups of small bit width operation data are spliced ​​together as follows Figure 2 As shown, Figure 2A schematic diagram of stitching small-bitwidth operation data with the same bitwidth is given. It should be noted that the stitching of small-bitwidth operation data with different bitwidths is similar to that of small-bitwidth operation data with the same bitwidth. The stitching of small-bitwidth operation data with different bitwidths can be directly referred to the stitching of small-bitwidth operation data with the same bitwidth, and this application will not repeat the explanation.

[0042] Step S3-12: To prevent overflow after stitching multiple groups of small-bitwidth operation data, use dynamic control logic to control the stitching bitwidth. Specifically:

[0043] Use dynamic control logic to calculate the total bitwidth of the stitched data. The calculation formula is as follows:

[0044]

[0045] Where bit_width[i] is the effective bitwidth of the i-th segment of data, and +1 represents that the sign extension occupies 1 bit. According to the calculation result of the total bitwidth Total_Width, dynamically control the number of segments to be stitched. Before each stitching, judge the relationship between the current remaining bitwidth and the small-bitwidth operation data to be stitched. If 18 - Total_Width < bit_width[i+1], stop stitching and send the stitched data to the subsequent module for calculation; if 18 - Total_Width ≥ bit_width[i+1], continue to shift and stitch. Through dynamic bitwidth limitation and stitching control logic, the bitwidth overflow problem can be effectively avoided.

[0046] Step S3-2: When selecting the full-bitwidth calculation mode, directly input the data into the multiplier.

[0047] Step S4: The data enters the multiplier for multiplication operation.

[0048] Step S4-1: After stitching, multiple groups of small-bitwidth operation data are sent to the multiplier. After the stitching of multiple groups of small-bitwidth operation data is completed, starting from the low bit, arrange them bit by bit to the input end of the multiplier in sequence, and fill the high-bit empty bits with 0. Each group of small-bitwidth operation data is calculated independently. For example Figure 2 In, 3 groups of 4-bit small-bitwidth numbers are shifted and filled into data[14:10], [9:5], [4:0], and the highest empty bit is filled with 0.

[0049] The Figure 1 , the input data dataa[data_ina1, data_ina2,...] and datab[data_inb1, data_inb2,...] after stitching processing are input into the parallel calculation multiplication calculation module for calculation, and the calculation result result[result1, result2,...] is obtained.

[0050] After parallel multiplication, the output results are divided into multiple segments, each corresponding to the result of a group of small-bit-width data. The shifter extracts each segment of the results, obtaining the results of each group of small-bit-width significant bits. Taking the 6-bit multiplication mentioned above as an example, the extracted results are result1 = result[11:0], result2 = result[23:12], and result3 = result[35:24]. Each result represents the result of a group of small-bit-width significant bits. By implementing this method, the bit width of the multiplier can be reused, reducing unused multiplier space and improving efficiency.

[0051] Step S4-2: When the full-bit-width calculation mode is selected, the data is directly input into the multiplier for calculation, and the calculation result is output.

[0052] Example 2

[0053] The second embodiment provides an FPGA multiplier optimization device for implementing the FPGA multiplier optimization method described in the first embodiment. Figure 1 The multiplier optimization device includes: an input bit width detection module, which uses a leading zero detection circuit to detect the effective bit width of the input data data_ina and data_inb; generates a bit width control signal, and selects a small bit width parallel computing mode or a full bit width computing mode based on the bit width control signal; specifically, the computing mode selection based on the bit width control signal includes comparing the effective bit width of the input data with the small bit width data merging threshold to determine whether to start the small bit width parallel computing mode (i.e. Figure 1 The bit width < 8bit judgment module in the multiplier input data is used to judge the relationship between the remaining bit width of the multiplier input data and the bit width of the small bit width operation data to be spliced, and decide whether to continue splicing the data (that is, Figure 1 18-Total_Width≥bit_width judgment module).

[0054] A bit width detection and sign bit extension module performs bit width detection and sign bit extension processing on input data in a small bit width parallel computing mode, and performs a shift operation on the valid bit data after the sign bit extension processing, including performing a shift operation on the valid bit data after the sign bit extension processing based on the actual bit width of the input data detected and the preset shift amount of each group of data, and obtaining multiple groups of small bit width operation data after the shift operation;

[0055] The splicing judgment module judges the relationship between the remaining bit width of the multiplier input data and the bit width of the multiple groups of small bit width operation data to be spliced, and decides whether to continue the data splicing; the bit width splicing and multiplexing module, in the small bit width parallel computing mode, splices the small bit width operation data to be spliced, and after the splicing of the multiple groups of small bit width operation data is completed, it arranges them in sequence from the low bit to the input end of the multiplier, and fills the remaining high bit with 0;

[0056] The parallel multiplication calculation module performs parallel calculations on the spliced ​​small-bit-width operation data and outputs multiple segments of operation results. Each segment of the output result corresponds to the operation result of a group of small-bit-width operation data. The shifter extracts each segment of the operation result to obtain the operation result of each group of small-bit-width effective bit data.

[0057] When the full-bit-width calculation mode is enabled, data is directly input into the multiplier for operation to output the multiplication result.

[0058] in, Figure 1 The sign_a and sign_b fields represent the signed and unsigned states of the two input data (data_ina and data_inb), respectively. A logical 1 indicates a signed value, while a logical 0 indicates an unsigned value. signa corresponds to data_ina, and signb corresponds to data_inb.

[0059] The above describes in detail the FPGA multiplier optimization method and apparatus provided by the present invention. Specific examples are used herein to illustrate the structure and operating principles of the present invention. The above embodiments are intended only to facilitate understanding of the method and core concepts of the present invention. It should be noted that those skilled in the art will readily appreciate that various improvements and modifications may be made to the present invention without departing from the principles of the present invention, and such improvements and modifications fall within the scope of protection of the claims.

Claims

1. A FPGA multiplier optimization method, characterized in that: Detect the actual effective bit width of the data at the two input ends, use the leading zero circuit to determine the number of leading zeros in the input data, determine the highest non-zero bit in the input data, and then output the leading zero detection result to indicate the effective bit width of the input data; Generate a bit width control signal according to the leading zero detection result, and select a small bit width parallel computing mode or a full bit width computing mode based on the bit width control signal and a set small bit width data merging threshold; In the small bit width parallel computing mode, multiple groups of input data with small effective bit width are sign-bit extended to generate parallel computing data including sign bits, and the generated parallel computing data are shifted and spliced ​​before being sent to the multiplier for parallel computing; In full-bit-width calculation mode, data directly enters the multiplier operation.

2. The FPGA multiplier optimization method according to claim 1, wherein: The leading zero circuit captures input data at the effective edge of the clock signal, scans the data bit by bit from the highest bit to the lowest bit, counts consecutive zeros until the first 1 is counted, and outputs the leading zero detection result.

3. The FPGA multiplier optimization method according to claim 1, wherein: The bit width control signal is obtained by subtracting the leading zero detection result from the multiplier bit width of the data input; If the bit width control signals of the two input end data are both less than or equal to the small bit width data merging threshold, the small bit width parallel computing mode is started; If any one of the bit width control signals of the two input end data is greater than the small bit width data merging threshold, the full bit width calculation mode is started.

4. The FPGA multiplier optimization method according to claim 3, wherein: The multiplier bit width is 18, and the small bit width data merging threshold is 8.

5. The FPGA multiplier optimization method according to claim 1, wherein: When the small bit width parallel computing mode is selected, the small bit width valid bit data is compounded, including: performing bit width detection and sign bit extension processing on the input data to obtain valid bit data including the sign bit, performing a shift operation on the valid bit data after the sign bit extension processing, including performing a shift operation on the valid bit data after the sign bit extension processing based on the actual bit width of the detected input data and the preset shift amount of each group of data, after the shift operation, multiple groups of small bit width operation data are obtained, the multiple groups of small bit width operation data are then spliced ​​together through logical "or", and after the multiple groups of small bit width operation data are spliced ​​together, starting from the low bit, they are arranged in sequence from the low bit to the input end of the multiplier, and the remaining high bit bits are filled with 0; The spliced ​​multiple groups of small-bit-width operation data are sent to the multiplier, and each group of small-bit-width operation data is independently operated.

6. The FPGA multiplier optimization method according to claim 5, wherein: The bit width control signal determines the input data shift amount.

7. The FPGA multiplier optimization method according to claim 5, wherein: The multiplier output result is divided into multiple segments, and each segment of the output result corresponds to the operation result of a group of small bit width operation data; The shifter extracts the operation result of each segment to obtain the operation result of each group of small-bit-width valid bit data.

8. The FPGA multiplier optimization method according to claim 5, wherein: Before splicing small-bit-width arithmetic data, dynamic control logic is used to monitor the total bit width of the multiple groups of spliced ​​small-bit-width arithmetic data, including calculating the total bit width of the multiple groups of currently spliced ​​small-bit-width arithmetic data, and before each splicing, judging the relationship between the remaining bit width of the multiplier input data and the bit width of the small-bit-width arithmetic data to be spliced. When the remaining bit width of the multiplier input data is greater than or equal to the bit width of the small-bit-width arithmetic data to be spliced, the data splicing continues; otherwise, the splicing is stopped and the spliced ​​data is sent to the subsequent module for calculation.

9. An FPGA multiplier optimization device, characterized in that: A method for optimizing an FPGA multiplier according to any one of claims 1 to 8, wherein the multiplier optimization device comprises: An input bit width detection module detects the bit width of the valid bits of the input data using a leading zero detection circuit, generates a bit width control signal, and selects a small bit width parallel computing mode or a full bit width computing mode based on the bit width control signal; A bit width detection and sign bit extension module performs bit width detection and sign bit extension processing on input data in a small bit width parallel computing mode, and performs a shift operation on the valid bit data after the sign bit extension processing, including performing a shift operation on the valid bit data after the sign bit extension processing based on the actual bit width of the input data detected and the preset shift amount of each group of data, and obtaining multiple groups of small bit width operation data after the shift operation; The splicing judgment module judges the relationship between the remaining bit width of the multiplier input data and the bit width of multiple groups of small bit width operation data to be spliced, and decides whether to continue splicing the data; The bit width splicing and multiplexing module, in the small bit width parallel computing mode, splices the small bit width operation data to be spliced. After the splicing of multiple groups of small bit width operation data is completed, it arranges them bit by bit from the low bit to the input end of the multiplier, and fills the empty high bit with 0; The parallel multiplication calculation module performs parallel calculations on the spliced ​​small-bit-width operation data and outputs multiple segments of operation results. Each segment of the output result corresponds to the operation result of a group of small-bit-width operation data. The shifter extracts each segment of the operation result to obtain the operation result of each group of small-bit-width effective bit data. When the full-bit-width calculation mode is enabled, data is directly input into the multiplier for operation to output the multiplication result.

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