Dynamic random access memory and method of controlling the same

Abstract

The present disclosure provides a dynamic random access memory (DRAM) and a control method thereof. The DRAM has a first operation mode and a second operation mode, including a control module and a connection module. The connection module includes an input / output (I / O) pad and a judgment circuit. The I / O pad is configured to receive a first input signal. The judgment circuit includes a detector and a first judgment unit. The detector is configured to compare the first input signal with a reference signal to generate a first signal. The first judgment unit is configured to receive the first signal and generate a first output signal according to the first signal. The control module is configured to control the DRAM to operate in the first operation mode or the second operation mode according to the first output signal.

Description

Technical Field

[0001] This disclosure relates to a dynamic random access memory (DRAM) and a control method thereof. More particularly, it relates to a dynamic random access memory and a control method for its operation in different operating modes. Background Technology

[0002] Existing Dynamic Random Access Memory (DRAM) has seen rapid improvements in processing speed, and DRAM instructions are designed to have different processing speeds in different operating modes. When DRAM is being tested, it receives the instructions to be tested in a preset operating mode. However, the testing process can be performed more efficiently in other operating modes. Executing the test in an inappropriate operating mode increases time costs. Therefore, improving the efficiency of DRAM testing is a key issue in this technical field.

[0003] The above description of "prior art" is merely to provide background information and does not constitute an admission that the above description of "prior art" reveals the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0004] One embodiment of this disclosure provides a dynamic random access memory (DRAM) having a first operating mode and a second operating mode, including a control module and a connection module. The connection module includes input / output (I / O) pads and a determination circuit. The I / O pads are configured to receive a first input signal. The determination circuit includes a detector and a first determination unit. The detector is configured to compare the first input signal with a reference signal to generate a first signal. The first determination unit is configured to receive the first signal and generate a first output signal based on the first signal. The control module is configured to control the DRAM to operate in the first operating mode or the second operating mode based on the first output signal.

[0005] In some embodiments, when the first output signal has a first logic level, the control module controls the DRAM to operate in a first operating mode, and when the first output signal has a second logic level, the control module controls the DRAM to operate in a second operating mode.

[0006] In some embodiments, the detector generates the first signal having a first logic level when the voltage level of the first input signal is lower than the voltage level of the reference signal, and generates the first signal having a second logic level when the voltage level of the first input signal is higher than the voltage level of the reference signal.

[0007] In some embodiments, the first determination unit is further configured to receive a second input signal and generate a first output signal based on the first signal and the second input signal.

[0008] In some embodiments, when the first signal has a second logic level and the second input signal has a first logic level, the first determination unit generates a first output signal to enable the DRAM to operate in a first operating mode.

[0009] In some embodiments, the first determination unit is further configured to receive a third input signal and generate a first output signal based on the first signal, the second input signal, and the third input signal.

[0010] In some embodiments, when the first signal has a second logic level and the third input signal has a first logic level, the first determination unit generates a first output signal to enable the DRAM to operate in a first operating mode.

[0011] In some embodiments, when the first input signal, the second input signal, and the third input signal have a second logic level, the first determination unit generates a first output signal to enable the DRAM to operate in the second operation mode.

[0012] In some embodiments, the first determination unit includes a first inverter, a second inverter, a first inverter, and a second inverter. The first inverter has a first input terminal, a second input terminal, and an output terminal. The second inverter has a first input terminal, a second input terminal, and an output terminal. The first inverter has an input terminal and an output terminal. The second inverter has an input terminal and an output terminal. The first input terminal of the first inverter is coupled to a detector and configured to receive a first signal; the second input terminal of the first inverter is coupled to the output terminal of the first inverter; the output terminal of the first inverter is coupled to the first input terminal of the second inverter; the input terminal of the first inverter is configured to receive a second input signal; the second input terminal of the second inverter is configured to receive a third input signal; the output terminal of the second inverter is coupled to the input terminal of the second inverter; and the output terminal of the second inverter is configured to output a first output signal.

[0013] In some embodiments, the determination circuit further includes a receiver and a second determination unit. The receiver is configured to receive a first input signal and generate a second signal based on the first input signal. The second determination unit is configured to receive the first signal and the second signal, and is configured to generate a second output signal based on the first signal and the second signal. The control module is configured to control the testing of the connection module based on the second output signal.

[0014] In some embodiments, when the voltage level of the input signal is lower than the voltage level of the reference signal, the receiver generates a second signal with a first logic level, and when the voltage level of the input signal is substantially equal to the voltage level of the reference signal, the receiver generates a second signal with a second logic level.

[0015] In some embodiments, the second determination unit is further configured to receive a fourth input signal and generate a second output signal based on the first signal, the second signal, and the fourth input signal. When the first signal and the second signal have a first logic level, the second determination unit generates a second output signal to prevent the connection module from being tested; when the first signal has a first logic level and the second signal has a second logic level, the second determination unit generates a second output signal to allow the connection module to be tested; when the first signal and the second signal have the second logic level and the fourth signal has a first logic level, the second determination unit generates a second output signal to prevent the connection module from being tested; and when the first signal, the second signal, and the fourth signal all have a second logic level, the second determination unit generates a second output signal to allow the connection module to be tested.

[0016] In some embodiments, the second determination unit includes a third inverter, a fourth inverter, a third inverter, and a fourth inverter. The third inverter has a first input terminal, a second input terminal, and an output terminal; the fourth inverter has a first input terminal, a second input terminal, and an output terminal; the third inverter has an input terminal and an output terminal; and the fourth inverter has an input terminal and an output terminal. The first input terminal of the third inverter is coupled to a detector and configured to receive a first signal; the second input terminal of the third inverter is coupled to the output terminal of the third inverter; the output terminal of the third inverter is coupled to the second input terminal of the fourth inverter; the input terminal of the third inverter is configured to receive a fourth input signal; the first input terminal of the fourth inverter is coupled to a receiver and configured to receive a second signal; the output terminal of the fourth inverter is coupled to the input terminal of the fourth inverter; and the output terminal of the fourth inverter is configured to output a second output signal.

[0017] In some embodiments, the first operating mode is the 1N mode of the double data rate fifth-generation synchronous dynamic random access memory (DDR5 SDRAM), and the second operating mode is the 2N mode of the DDR5 SDRAM.

[0018] Another embodiment of this disclosure provides a DRAM control method, including: receiving a first input signal through an input / output (I / O) pad of a DRAM connection module; generating a first signal based on a voltage level of the first input signal and a voltage level of a reference signal; and generating a first output signal based on the first signal to control the DRAM to operate in a first operating mode or a second operating mode. When the first output signal has a first logic level, the DRAM is controlled to operate in the second operating mode, and when the first output signal has a second logic level, the DRAM is controlled to operate in the first operating mode.

[0019] In some embodiments, generating a first signal based on the voltage level of a first input signal and the voltage level of a reference signal includes: comparing the voltage level of the first input signal with the voltage level of the reference signal; generating a first signal having a second logic level when the voltage level of the first input signal is lower than the voltage level of the reference signal; and generating a first signal having a first logic level when the voltage level of the first input signal is greater than the voltage level of the reference signal.

[0020] In some embodiments, generating a first output signal includes: receiving a second input signal; and generating a second signal based on the first signal and the second input signal.

[0021] In some embodiments, generating a first output signal includes: receiving a third input signal; generating a third signal based on a second signal and the third input signal; and generating a first output signal based on the third signal. When the first input signal, the second input signal, and the third input signal have a first logic level, the DRAM is controlled to operate in a second operating mode. When the first signal has a first logic level, the second input signal has a second logic level, and the third input signal has a second logic level, the DRAM is controlled to operate in a first operating mode. When the first signal has a first logic level, the second input signal has a first logic level, and the third input signal has a second logic level, the DRAM is controlled to operate in a first operating mode. When the first signal has a first logic level, the second input signal has a second logic level, and the third input signal has a first logic level, the DRAM is controlled to operate in a first operating mode.

[0022] In some embodiments, the control method further includes: generating a second output signal based on a first input signal, including: generating a fourth signal based on the first input signal; receiving the fourth input signal; generating a fifth signal based on the first signal, the fourth signal, and the fourth input signal; and generating the second output signal based on the fifth signal. The connection module is controlled to perform testing based on the second output signal.

[0023] In some embodiments, when the first signal and the fourth signal have a second logic level, a second output signal is generated to prevent the connection module from being tested. When the first signal has a second logic level and the fourth signal has a first logic level, a second output signal is generated to prevent the connection module from being tested. When the first signal, the fourth signal, and the fourth input signal all have a first logic level, a second output signal is generated to prevent the connection module from being tested. When the first signal and the fourth signal both have a first logic level, and the fourth input signal has a second logic level, a second output signal is generated to prevent the connection module from being tested.

[0024] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0025] When referring to the drawings in conjunction with the embodiments and claims, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

[0026] Figure 1 A schematic diagram illustrating a dynamic random access memory (DRAM) according to some embodiments of the present disclosure is shown.

[0027] Figure 2 A schematic diagram illustrating a connection module of the dynamic random access memory according to some embodiments of the present disclosure is shown.

[0028] Figure 3 A schematic diagram illustrating a determination circuit of the connection module of the dynamic random access memory according to some embodiments of the present disclosure.

[0029] Figure 4 A schematic diagram illustrating a determination circuit of the connection module of the dynamic random access memory according to various embodiments of the present disclosure.

[0030] Figure 5 A schematic diagram illustrating a determination unit of the determination circuit according to some embodiments of the present disclosure is shown.

[0031] Figure 6 A schematic diagram illustrating a determination unit of the determination circuit according to some embodiments of the present disclosure is shown.

[0032] Figure 7 A schematic diagram illustrating the determination circuit of some embodiments of this disclosure is shown.

[0033] Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 as well as Figure 15 This illustration shows the operation of the judgment unit of the judgment circuit of the connection module of the dynamic random access memory according to some embodiments of the present disclosure.

[0034] Figure 16 This diagram illustrates the operation of the judgment circuit of the connection module of the dynamic random access memory in some embodiments of the present disclosure.

[0035] Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 as well as Figure 22 This illustration shows the operation of the judgment unit of the judgment circuit of the connection module of the dynamic random access memory according to some embodiments of the present disclosure.

[0036] Figure 23 This diagram illustrates the operation of the judgment circuit of the connection module of the dynamic random access memory in some embodiments of the present disclosure.

[0037] Figure 24 , Figure 25 , Figure 26 , Figure 27 , Figure 28 as well as Figure 29 A flowchart illustrating the control method of the dynamic random access memory according to some embodiments of this disclosure is shown.

[0038] The reference numerals in the attached figures are explained as follows:

[0039] 1: Dynamic Random Access Memory

[0040] 10: Connection Module

[0041] 11: Input / Output Pads

[0042] 12: Determine the circuit

[0043] 20: Memory Array

[0044] 24: Control Methods

[0045] 30: Control Module

[0046] 120: Detector

[0047] 121: Receiver

[0048] 122: Judgment Unit

[0049] 123: Judgment Unit

[0050] IN1: Input signal

[0051] IN2: Input signal

[0052] IN3: Input signal

[0053] IN4: Input signal

[0054] INV1: Inverter

[0055] INV2: Inverter

[0056] INV3: Inverter

[0057] INV4: Inverter

[0058] NG1: Reverse and gate

[0059] NG2: Reverse and gate

[0060] NG3: Reverse and gate

[0061] NG3: Reverse and gate

[0062] NG4: Reverse and gate

[0063] OC1: Operation Diagram

[0064] OC2: Operation Diagram

[0065] OUT1: Output signal

[0066] OUT2: Output signal

[0067] S1: Signal

[0068] S2: Signal

[0069] S3: Signal

[0070] S4: Signal

[0071] S5: Signal

[0072] S6: Signal

[0073] S7: Signal

[0074] S8: Signal

[0075] S241: Steps

[0076] S242: Steps

[0077] S2421: Steps

[0078] S2422: Steps

[0079] S2423: Steps

[0080] S243: Steps

[0081] S2431: Steps

[0082] S2432: Steps

[0083] S2433: Steps

[0084] S2434: Steps

[0085] S2435: Steps

[0086] S244: Steps

[0087] S2441: Steps

[0088] S2442: Steps

[0089] S2443: Steps

[0090] S2444: Steps

[0091] S281: Steps

[0092] S282: Steps

[0093] S283: Steps

[0094] S284: Steps

[0095] S291: Steps

[0096] S292: Steps

[0097] S293: Steps

[0098] S294: Steps

[0099] SREF: Reference Signal

[0100] VDD: Voltage

[0101] VSS: Voltage

[0102] VTM: Voltage Detailed Implementation

[0103] The following description of this disclosure, accompanied by drawings incorporated in and forming part of this specification, illustrates embodiments of the disclosure; however, the disclosure is not limited to these embodiments. Furthermore, the following embodiments may be appropriately integrated to complete another embodiment.

[0104] The terms "an embodiment," "an embodiment," "an illustrative embodiment," "an other embodiment," and "another embodiment" refer to embodiments described in this disclosure that may include specific features, structures, or characteristics; however, not every embodiment must include that specific feature, structure, or characteristic. Furthermore, repeated use of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but may refer to the same embodiment.

[0105] To enable a full understanding of this disclosure, the following description provides detailed steps and structures. It is obvious that implementation of this disclosure does not limit the specific details known to those skilled in the art. Furthermore, known structures and steps are not detailed further to avoid unnecessarily limiting this disclosure. Preferred embodiments of this disclosure are detailed below. However, in addition to the detailed description, this disclosure can also be widely implemented in other embodiments. The scope of this disclosure is not limited to the detailed description, but is defined by the claims.

[0106] It should be understood that the following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the dimensions of elements are not limited to the disclosed range or values, but may depend on process conditions and / or the desired properties of the apparatus. Furthermore, the description of a first feature being formed "on" or "on" a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby potentially preventing direct contact between the first and second features. For simplicity and clarity, various features may be drawn at any scale. In the drawings, some layers / features may be omitted for simplicity.

[0107] Furthermore, for ease of explanation, this document may use spatial relative terms such as "beneath," "below," "lower," "above," and "upper" to describe the relationship between one element or feature shown in the figures and another (other) element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0108] Figure 1A schematic diagram illustrating a Dynamic Random Access Memory (DRAM) 1 according to some embodiments of the present disclosure is shown. DRAM 1 includes a connection module 10, a memory array 20, and a control module 30. The connection module 10 is configured to connect signals and supply power to DRAM 1. The memory array 20 is configured to store data and is controlled and powered by the control module 30 based on these signals.

[0109] In some embodiments, DRAM 1 is a Double Data Rate (DDR) Synchronous DRAM (SDRAM) and connects to module 10, memory array 20, and control module 30. DRAM 1 is designed to conform to DDR DRAM specifications. For example, DRAM 1 is a Double Data Rate Generation 5 (DDR5) SDRAM.

[0110] In some embodiments, DRAM 1 can operate in a first operating mode and a second operating mode, such as the 1N mode and 2N mode defined in the DDR5 SDRAM specification. Instructions in DRAM 1 operate at different speeds in different modes. Furthermore, instructions sent in the first operating mode differ from those sent in the second operating mode.

[0111] Typically, when an operating DRAM is in a switching mode, it must receive a multi-purpose command (MPC) and be controlled to switch from one operating mode to another. When testing DRAM, it is typically performed in a preset operating mode; for example, DDR5 SDRAM's preset operating mode is 2N mode. However, the efficiency of commands operating in a preset mode may be lower than in other modes. In this case, DRAM testing is time-consuming and may waste unnecessary time.

[0112] Compared to existing methods, the DRAM 1 provided in this disclosure can easily switch modes and is more efficient in testing.

[0113] refer to Figure 2 , Figure 2 A schematic diagram illustrating a connection module 10 according to some embodiments of the present disclosure is shown. The connection module 10 includes input / output (I / O) pads 11 and a determination circuit 12. The I / O pads 11 are configured to receive or transmit signals and / or provide power via a location disposed at the edge of the DRAM 1, while the determination circuit 12 is coupled to the I / O pads 11.

[0114] refer to Figure 2I / O pad 11 is configured to receive input signal IN1 and transmit input signal IN1 to determination circuit 12. In some embodiments, I / O pad 11 is a metal pad, such as a copper pad. Determination circuit 12 is configured to receive input signal IN1 and generate output signal OUT1 and output signal OUT2 based on input signal IN1.

[0115] In some embodiments, the input signal IN1 has a power supply voltage. This power supply voltage can be provided as voltage VSS, voltage VDD, and / or voltage VTM. In some embodiments, voltage VSS is grounded, voltage VDD is approximately 1.1 volts (V), and voltage VTM is approximately 3.3 volts.

[0116] In some embodiments, the output signal OUT1 is generated to control the DRAM 1 to operate in either the first operating mode or the second operating mode. When the output signal OUT1 has a logic low level (i.e., logic 0), the DRAM 1 will operate in the first operating mode. When the output signal OUT1 has a logic high level (i.e., logic 1), the DRAM 1 will operate in the second operating mode.

[0117] In some embodiments, the output signal OUT2 is generated to control whether the connection module 10 performs a connectivity test. When the output signal OUT2 is at a logic high level, the connectivity test is performed on the connection module 10. When the output signal OUT2 is at a logic low level, the connectivity test is not performed on the connection module 10.

[0118] refer to Figure 3 , Figure 3 A schematic diagram illustrating a determination circuit 12 according to some embodiments of the present disclosure is shown. The determination circuit 12 includes a detector 120, a receiver 121, a determination unit 122, and a determination unit 123. The detector 120 and receiver 121 are configured to receive an input signal IN1 and generate signals S1 and S2, respectively. The determination unit 122 is coupled to the detector 120. The determination unit 123 is coupled to both the detector 120 and the receiver 121.

[0119] Detector 120 generates signal S1 based on input signal IN1. When input signal IN1 has a voltage VSS or a voltage VDD, signal S1 is generated to have that logic low level. When input signal IN1 has a voltage VTM, signal S1 is generated to have that logic high level. In some embodiments, detector 120 is implemented using a comparator. Detector 120 compares the received input signal IN1 with a reference signal SREF. When the voltage level of input signal IN1 is not greater than the voltage level of reference signal SREF, signal S1 is generated to have that logic low level. When the voltage level of input signal IN1 is greater than the voltage level of reference signal SREF, signal S1 is generated to have that logic high level. In some embodiments, reference signal SREF has a voltage VDD.

[0120] The determination unit 122 is configured to receive signal S1 and generate output signal OUT1 based on signal S1. DRAM 1 operates in the second operating mode under the control of the output signal OUT1 having the logic high level. Conversely, DRAM 1 operates in the first operating mode under the control of the output signal OUT1 having the logic low level.

[0121] Receiver 121 generates signal S2 based on input signal IN1. When input signal IN1 has a voltage VSS, signal S2 is generated to have a logic low level. In some embodiments, receiver 121 includes a buffer and a comparator.

[0122] The judgment unit 123 is configured to receive signals S1 and S2, and generates an output signal OUT2 based on signals S1 and S2. When signals S1 and S2 are at a logic low level (i.e., input signal IN1 has a voltage VSS), the output signal OUT2 is generated to have a logic low level. The connection module 10 does not perform this connectivity test. Conversely, when signal S1 is at a logic low level and signal S2 is at a logic high level (i.e., input signal IN1 has a voltage VDD), the output signal OUT2 is generated to have a logic high level. The connection module 10 performs this connectivity test.

[0123] The above configuration of the determination circuit 12 is provided for illustrative purposes. Various configurations of the determination circuit 12 are within the expected range. For example, in various embodiments, the determination circuit 12 also receives further information such as... Figure 4 Example input signal.

[0124] refer to Figure 4 , Figure 4Schematic diagrams illustrating various embodiments of the judgment circuit 12 of this disclosure are provided. For ease of understanding, similar elements are designated with the same numbers. The judgment circuit 12 includes a detector 120, a receiver 121, a judgment unit 122, and a judgment unit 123. Figure 4 For example, the judgment unit 122 is further configured to receive input signals IN2 and IN3, and the judgment unit 123 is further configured to receive input signal IN4. Therefore, the judgment unit 122 is configured to generate output signal OUT1 based on input signals IN1, IN2, and IN3, and the judgment unit 123 is configured to generate output signal OUT2 based on input signals IN1 and IN4. The operation of the judgment circuit 12 corresponding to input signals IN1, IN2, IN3, and IN4 will be referred to below. Figures 5 to 16 Describe it.

[0125] refer to Figure 5 , Figure 5 A schematic diagram illustrating a determination unit 122 according to some embodiments of this disclosure is provided. The determination unit 122 includes an inverting NAND gate NG1, an inverting NAND gate NG2, an inverter INV1, and an inverter INV2. For example... Figure 5 For example, a first input terminal of the inverter NG1 is configured to receive signal S1, a second input terminal of the inverter NG1 is coupled to an output terminal of the inverter INV1, an output terminal of the inverter NG1 is coupled to a first input terminal of the inverter NG2, an input terminal of the inverter INV1 is configured to receive input signal IN2, a second input terminal of the inverter NG2 is configured to receive input signal IN3, an output terminal of the inverter NG2 is coupled to an input terminal of the inverter INV2, and an output terminal of the inverter INV2 is configured to output output signal OUT1.

[0126] refer to Figure 6 , Figure 6 A schematic diagram illustrating a determination unit 123 according to some embodiments of this disclosure is provided. The determination unit 123 includes an inverter NG3, an inverter NG4, an inverter INV3, and an inverter INV4. For example... Figure 6 For example, the first input terminal of the inverter NG3 is configured to receive signal S1, the second input terminal of the inverter NG3 is coupled to an output terminal of the inverter INV3, an output terminal of the inverter NG3 is configured to be coupled to a second input terminal of the inverter NG4, an input terminal of the inverter INV3 is configured to receive input signal IN4, the first input terminal of the inverter NG4 is configured to receive signal S2, an output terminal of the inverter NG4 is coupled to an input terminal of the inverter INV4, and an output terminal of the inverter INV4 is configured to output output signal OUT2.

[0127] refer to Figure 7 , Figure 7 A schematic diagram of a judgment circuit 12 is shown, illustrating some embodiments of this disclosure. Figure 7 For ease of discussion, signals S1, S2, S3, S4, S5, S6, S7, and S8 are shown in the example.

[0128] In some embodiments, signals S1, S2, S3, S4, S5, S6, S7, and S8 are digital signals and have either a logic high level or a logic low level. In other words, the level of signals S1, S2, S3, S4, S5, S6, S7, and S8 is only 0 or 1.

[0129] The descriptions of signals S1 and S2 are as follows: Figure 3 The same applies as discussed in the examples. For example... Figure 7 For example, in the judgment unit 122, signal S3 is inverted with input signal IN2, signal S4 is the result of performing an inverse (not-and, NAND) operation on signals S1 and S3, signal S5 is the result of performing an inverse (not-and, NAND) operation on input signals IN3 and S4, and output signal OUT1 is inverted with signal S5.

[0130] In the judgment unit 123, signal S6 is inverted with input signal IN4, signal S7 is the result of the inverse operation of signal S1 and signal S6, signal S8 is the result of the inverse operation of signal S2 and signal S7, and output signal OUT2 is inverted with signal S8.

[0131] refer to Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 as well as Figure 15 , Figures 8 to 15 The following is a schematic diagram illustrating the operation of the judgment unit 122 in some embodiments of this disclosure. For ease of understanding, the input signals IN2, IN3, S1, S2, S3, S4, S5, and OUT1 are represented by logic levels 0 or 1.

[0132] like Figure 8 For example, input signal IN1 has a voltage VSS or VDD, input signal IN2 has this logic low level, and input signal IN3 has this logic high level. At this time, signal S1 has this logic low level, signal S3 has this logic high level, signal S4 has this logic high level, and signal S5 has this logic low level. Therefore, output signal OUT1 has this logic high level to enable DRAM 1 to operate in this second operating mode.

[0133] In some embodiments, input signals IN2 and IN3 have preset levels, wherein the preset level of input signal IN2 is the logic low level and the preset level of input signal IN3 is the logic high level. In other words, when input signals IN2 and IN3 are not controlled, input signals IN2 and IN3 generally have the logic low level and the logic high level, respectively.

[0134] Figure 9 In this context, the input signal IN2 is controlled to have this logic high level. For example... Figure 9 For example, input signal IN1 remains a voltage VSS or VDD, and input signal IN3 remains at the same logic high level. At this time, signal S1 has the same logic low level, signal S3 has the same logic low level, signal S4 has the same logic high level, and signal S5 has the same logic low level. Therefore, output signal OUT1 has the same logic high level to enable DRAM 1 to operate in this second operating mode.

[0135] Figure 10 In this context, input signals IN2 and IN3 are controlled to have the logic high level and logic low level, respectively. For example... Figure 10 For example, the input signal IN1 still has a voltage VSS or VDD. At this time, signal S1 has this logic low level, signal S3 has this logic low level, signal S4 has this logic high level, and signal S5 has this logic high level. Therefore, the output signal OUT1 has this logic low level to enable DRAM 1 to operate in this first operating mode.

[0136] exist Figure 11 In this context, input signals IN2 and IN3 are controlled to have this logic low level. For example... Figure 11 For example, the input signal IN1 still has a voltage VSS or VDD. At this time, signal S1 has this logic low level, signal S3 has this logic high level, signal S4 has this logic high level, and signal S5 has this logic high level. Therefore, the output signal OUT1 has this logic low level to enable DRAM 1 to operate in this first operating mode.

[0137] exist Figure 12 In this first operating mode, input signal IN1 has the voltage VTM, and input signals IN2 and IN3 have the logic low level. At this time, signal S1 has the logic high level, signal S3 has the logic high level, signal S4 has the logic low level, and signal S5 has the logic high level. Therefore, output signal OUT1 has the logic low level to enable DRAM 1 to operate in this first operating mode.

[0138] Figure 13In this context, the input signal IN3 is controlled to have this logic high level. For example... Figure 13 For example, input signal IN1 still has voltage VTM, while input signal IN2 still has this logic low level. At this time, signal S1 has this logic high level, signal S3 has this logic high level, signal S4 has this logic low level, and signal S5 has this logic high level. Therefore, output signal OUT1 has this logic low level to enable DRAM 1 to operate in this first operating mode.

[0139] Figure 14 In this context, input signals IN2 and IN3 are controlled to have the logic high level and logic low level, respectively. For example... Figure 14 For example, the input signal IN1 still has a voltage VTM. At this time, signal S1 has this logic high level, signal S3 has this logic low level, signal S4 has this logic high level, and signal S5 has this logic high level. Therefore, the output signal OUT1 has this logic low level to enable DRAM 1 to operate in this first operating mode.

[0140] exist Figure 15 In this context, input signals IN2 and IN3 are controlled to have this logic high level. For example... Figure 15 For example, the input signal IN1 still has a voltage VTM. At this time, signal S1 has this logic high level, signal S3 has this logic low level, signal S4 has this logic high level, and signal S5 has this logic low level. Therefore, the output signal OUT1 has this logic high level to enable DRAM 1 to operate in this second operating mode.

[0141] according to Figures 8 to 15 As a result, the logical operation results of judgment unit 122 can be summarized as follows: Figure 15 The operation diagram OC1 is shown.

[0142] refer to Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 as well as Figure 22 . Figures 17 to 22 The following is a schematic diagram illustrating the operation of the judgment unit 123 in some embodiments of this disclosure. For ease of understanding, the input signals IN4, S6, S7, and S8, and the output signal OUT2 are represented by logic levels 0 or 1.

[0143] exist Figure 17In this configuration, input signal IN1 has the voltage VSS and input signal IN4 has the logic low level. At this time, signals S1 and S2 have the logic low level, signal S6 has the logic high level, signal S7 has the logic high level, and signal S8 has the logic high level. Therefore, output signal OUT2 has the logic low level to prevent connection module 10 from performing the connectivity test.

[0144] In some embodiments, the input signal IN4 has a preset level, wherein the preset level of the input signal IN4 is the logic low level. In other words, when the input signal IN4 is not controlled, the input signal IN4 generally has the logic low level.

[0145] Figure 18 In this context, the input signal IN4 is controlled to have this logic high level. For example... Figure 18 For example, the input signal IN1 still has a voltage VSS. At this time, signals S1 and S2 have this logic low level, signal S6 has this logic low level, signal S7 has this logic high level, and signal S8 has this logic high level. Therefore, the output signal OUT2 has this logic low level to prevent the connection module 10 from performing the connectivity test.

[0146] exist Figure 19 In this configuration, input signal IN1 has a voltage VDD, and input signal IN4 has a logic low level. At this time, signal S1 is a logic low level, signal S2 is a logic high level, signal S6 is a logic high level, signal S7 is a logic high level, and signal S8 is a logic low level. Therefore, output signal OUT2 has this logic high level to enable connection module 10 to perform the connectivity test.

[0147] exist Figure 20 In this configuration, input signal IN1 has a voltage VDD, and input signal IN4 has this logic high level. At this time, signals S1, S2, S6, S7, and S8 have this logic low level. Therefore, output signal OUT2 has this logic high level to enable connection module 10 to perform the connectivity test.

[0148] exist Figure 21 In this configuration, input signal IN1 has a voltage VTM, and input signal IN4 has this logic low level. At this time, signals S1 and S2 have this logic high level, signal S6 has this logic high level, signal S7 has this logic low level, and signal S8 has this logic high level. Therefore, output signal OUT2 has this logic low level to prevent connection module 10 from performing the connectivity test.

[0149] exist Figure 22In this configuration, input signal IN1 has a voltage VTM, and input signal IN4 has this logic high level. At this time, signals S1 and S2 have this logic high level, signal S6 has this logic low level, signal S7 has this logic high level, and signal S8 has this logic low level. Therefore, output signal OUT2 has this logic high level to enable connection module 10 to perform the connectivity test.

[0150] according to Figures 17 to 22 As a result, the logical operation results of judgment unit 123 can be summarized as follows: Figure 23 The operation diagram OC2 is shown.

[0151] refer to Figure 24 , Figure 25 , Figure 26 , Figure 27 , Figure 28 ,as well as Figure 29 . Figure 24 , Figure 25 , Figure 26 , Figure 27 , Figure 28 as well as Figure 29 A flowchart illustrating a control method for DRAM1 according to some embodiments of this disclosure is provided. Control method 24 is executed to switch the operating mode of DRAM1. Specifically, when testing DRAM1, the operating mode of DRAM1 can be changed by executing control method 24 to achieve better testing efficiency. For example, when performing a functional test on DDR5 SDRAM, control method 24 changes the preset 2N mode of DDR5 SDRAM to 1N mode. Therefore, DDR5 SDRAM can operate in 1N mode to obtain better testing efficiency. The operation of control method 24 will be described in detail below; please refer to [reference needed]. Figures 1 to 23 .

[0152] exist Figure 24 In the control method 24, steps S241, S242, S243, and S244 are included. First, the input signal IN1 is received by the I / O pad 11 of DRAM 1. The corresponding steps are illustrated in... Figure 24 Step S241 of the control method 24 shown. The input signal IN1 is transmitted to the judgment circuit 12, and the detector 120 and receiver 121 of the judgment circuit 12 receive the input signal IN1. Then, the detector 120 generates signal S1 based on a voltage level of the input signal IN1 and a voltage level of the reference signal SREF. The corresponding steps are illustrated in... Figure 24The control method 24 shown includes step S242. Then, the judgment unit 122 of the judgment circuit 12 generates an output signal OUT1 based on signal S1, and the output signal OUT1 is generated to control DRAM 1 to operate in a first operating mode or a second operating mode. The corresponding steps are illustrated in... Figure 24 The control method 24 shown includes step S243. Finally, the judgment unit 123 of the judgment circuit 12 generates the output signal OUT2 based on the first input signal IN1. The corresponding steps are illustrated in... Figure 24 Step S244 of the control method 24 shown. In some embodiments, when the output signal OUT1 has the logic high level, DRAM 1 is controlled to operate in the second operating mode. When the output signal OUT1 has the logic low level, DRAM 1 is controlled to operate in the first operating mode. In some embodiments, when the output signal OUT2 has the logic high level, the output signal OUT2 is generated to control the connectivity module 10 of DRAM 1 to perform the connectivity test.

[0153] In some embodiments, step S242 includes, for example, Figure 25 The steps S2421, S2422, and S2423 are shown below. First, the detector 120 compares the voltage level of the input signal IN1 with the voltage level of the reference signal SREF. The corresponding steps are illustrated in the diagram below. Figure 25 Step S2421 in the control method 24 shown. Next, when the voltage level of the input signal IN1 is lower than the voltage level of the reference signal SREF, the signal S1 generated by the detector 120 has a logic low level. The corresponding steps are illustrated in... Figure 25 Step S2422 in the control method 24 shown. Then, when the voltage level of the input signal IN1 is greater than the voltage level of the reference signal SREF, the signal S1 generated by the detector 120 has that logic high level. The corresponding steps are illustrated in... Figure 25 Step S2423 in the control method 24 shown.

[0154] In some embodiments, step S243 includes, for example: Figure 26 The steps S2431, S2432, S2433, S2434, and S2435 are shown. First, the judgment unit 122 receives the input signal IN2. The corresponding steps are illustrated in... Figure 26 The control method 24 shown includes step S2431. Next, signal S4 is generated based on signal S1 and input signal IN2. The corresponding steps are illustrated in... Figure 26 The control method 24 shown includes step S2432. Then, the judgment unit 122 receives the input signal IN3. The corresponding steps are illustrated in... Figure 26The control method 24 shown includes step S2433. Next, signal S5 is generated based on signal S4 and input signal IN3. The corresponding steps are illustrated in... Figure 26 The control method 24 shown includes steps S2434. Finally, the output signal OUT1 is generated based on signal S5. The corresponding steps are illustrated in... Figure 26 Step S2435 in the control method 24 shown. In some embodiments, when signal S5 has the logic high level, the generated output signal OUT1 has the logic low level. In some embodiments, when signal S1 has the logic high level, and input signals IN2 and / or IN3 reach the logic low level, the generated output signal OUT1 has the logic low level.

[0155] In some embodiments, signal S3 is the inverse of input signal IN2. Signal S4 is generated by performing an inverse AND operation on signals S1 and S3. Signal S5 is generated by performing an inverse AND operation on signals S4 and input signal IN3. Output signal OUT1 is the inverse of signal S5.

[0156] In some embodiments, step S244 includes, for example, Figure 27 The steps S2441, S2442, S2443, and S2444 are shown below. First, signal S2 is generated based on input signal IN1. The corresponding steps are illustrated in the diagram below. Figure 27 Step S2441 in the control method 24 shown. Next, the judgment unit 123 receives the input signal IN4. The corresponding steps are illustrated in... Figure 27 The control method 24 shown includes step S2442. Then, signal S8 is generated based on signals S1, S2, and input signal IN4. The corresponding steps are illustrated in... Figure 27 The control method 24 shown includes step S2443. Finally, the output signal OUT2 is generated based on signal S8. The corresponding steps are illustrated in... Figure 27 Step S2444 in the control method 24 shown.

[0157] In some embodiments, signal S6 is the inverse of input signal IN4. Signal S7 is generated by performing an inverse AND operation on signals S1 and S6. Signal S8 is generated by performing an inverse AND operation on signals S2 and S7. Output signal OUT2 is the inverse of signal S8.

[0158] In some embodiments, the control method 24 further includes, for example, Figure 28 The steps S281, S282, S283, and S284 are shown below. First, the control module 30 receives the output signal OUT1. The corresponding steps are illustrated in the diagram below. Figure 28Step S281 in control method 24 is shown. Next, the voltage level of the output signal OUT1 is determined. The corresponding steps are illustrated in... Figure 28 Step S282 in control method 24 is shown. Then, when the output signal OUT1 has the logic high level, DRAM 1 is controlled to operate in the second operating mode. The corresponding steps are illustrated in... Figure 28 Step S283 in the control method 24 shown. In some embodiments, the second operating mode can be the 2N mode of DDR5 SDRAM. Finally, when the output signal OUT1 has this logic low level, DRAM 1 is controlled to operate in the first operating mode. The corresponding steps are illustrated in... Figure 28 Step S284 in the control method 24 shown. In some embodiments, the first operating mode can be the 1N mode of DDR5 SDRAM.

[0159] In some embodiments, the control method 24 further includes, for example, Figure 29 The steps S291, S292, S293, and S294 are shown. The control module 30 receives the output signal OUT2. The corresponding steps are illustrated in... Figure 29 Step S291 in control method 24 shown: Determine the voltage level of the output signal OUT2. The corresponding step is illustrated in... Figure 29 Step S292 in control method 24 is shown. When the output signal OUT2 has this logic high level, the connectivity test is performed on the connection module 10 of DRAM 1. The corresponding steps are illustrated in... Figure 29 The control method 24 shown includes step S293. When the output signal OUT2 has this logic low level, the connectivity test stops. The corresponding step is illustrated in... Figure 29 Step S294 in the control method 24 shown.

[0160] This disclosure provides a DRAM having a first operating mode and a second operating mode, including a control module and a connection module. The connection module includes I / O pads and a judgment circuit. The I / O pads are configured to receive a first input signal. The judgment circuit includes a detector and a first judgment unit. The detector is configured to compare the first input signal with a reference signal to generate a first signal. The first judgment unit is configured to receive the first signal and generate a first output signal based on the first signal. The control module is configured to control the DRAM to operate in the first operating mode or the second operating mode based on the first output signal.

[0161] This disclosure also provides a DRAM control method, comprising: receiving a first input signal through I / O pads of a DRAM connection module; generating a first signal based on a voltage level of the first input signal and a voltage level of a reference signal; and generating a first output signal based on the first signal to control the DRAM to operate in a first operating mode or a second operating mode. When the first output signal has a first logic level, the DRAM is controlled to operate in the second operating mode, and when the first output signal has a second logic level, the DRAM is controlled to operate in the first operating mode.

[0162] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0163] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A dynamic random access memory, having a first operating mode and a second operating mode, comprising: One control module; as well as A connection module includes an input / output pad and a judgment circuit, wherein the input / output pad is configured to receive a first input signal, and the judgment circuit includes: A detector is configured to compare the first input signal with a reference signal to generate a first signal; as well as A first determination unit is configured to receive the first signal and generate a first output signal based on the first signal. The control module is configured to control the dynamic random access memory to operate in the first operating mode or the second operating mode according to the first output signal. When a voltage level of the first input signal is lower than a voltage level of the reference signal, the detector generates a first signal with a first logic level; and when the voltage level of the first input signal is higher than the voltage level of the reference signal, the detector generates a first signal with a second logic level. The first operating mode is a 1N mode of a double data rate fifth generation synchronous dynamic random access memory, and the second operating mode is a 2N mode of the double data rate fifth generation synchronous dynamic random access memory.

2. The dynamic random access memory as claimed in claim 1, wherein when the first output signal has a first logic level, the control module controls the dynamic random access memory to operate in the first operation mode, and when the first output signal has a second logic level, the control module controls the dynamic random access memory to operate in the second operation mode.

3. The dynamic random access memory as claimed in claim 1, wherein the first determination unit is further configured to receive a second input signal and generate the first output signal based on the first signal and the second input signal.

4. The dynamic random access memory as claimed in claim 3, wherein when the first signal has a second logic level and the second input signal has a first logic level, the first determination unit generates the first output signal to enable the dynamic random access memory to operate in the first operating mode.

5. The dynamic random access memory of claim 4, wherein the first determination unit is further configured to receive a third input signal and generate the first output signal based on the first signal, the second input signal and the third input signal.

6. The dynamic random access memory as claimed in claim 5, wherein when the first input signal has the second logic level and the third input signal has the first logic level, the first determination unit generates the first output signal to enable the dynamic random access memory to operate in the first operation mode.

7. The dynamic random access memory as claimed in claim 5, wherein when the first input signal, the second input signal, and the third input signal have the second logic level, the first determination unit generates the first output signal to enable the dynamic random access memory to operate in the second operating mode.

8. The dynamic random access memory as claimed in claim 5, wherein the first determination unit comprises: A first reverse gate has a first input terminal, a second input terminal, and an output terminal; A second reverse gate has a first input terminal, a second input terminal, and an output terminal; A first inverter has an input terminal and an output terminal; as well as A second inverter has an input terminal and an output terminal. The first input terminal of the first inverter is coupled to the detector and configured to receive the first signal; the second input terminal of the first inverter is coupled to the output terminal of the first inverter; the output terminal of the first inverter is coupled to the first input terminal of the second inverter; the input terminal of the first inverter is configured to receive the second input signal; the second input terminal of the second inverter is configured to receive the third input signal; the output terminal of the second inverter is coupled to the input terminal of the second inverter; and the output terminal of the second inverter is configured to output the first output signal.

9. The dynamic random access memory as claimed in claim 1, wherein the determining circuit further comprises: A receiver configured to receive the first input signal and generate a second signal based on the first input signal; as well as A second determination unit is configured to receive the first signal and the second signal, and is configured to generate a second output signal based on the first signal and the second signal. The control module is configured to control the testing of the connection module according to the second output signal.

10. The dynamic random access memory of claim 9, wherein when a voltage level of the first input signal is lower than a voltage level of the reference signal, the receiver generates the second signal having a first logic level, and when the voltage level of the first input signal is equal to the voltage level of the reference signal, the receiver generates the second signal having a second logic level.

11. The dynamic random access memory of claim 10, wherein the second determination unit is further configured to receive a fourth input signal, and to generate the second output signal based on the first signal, the second signal, and the fourth input signal, and in When the first signal and the second signal have the first logic level, the second determination unit generates the second output signal to prevent the connection module from being tested. When the first signal has the first logic level and the second signal has the second logic level, the second determination unit generates the second output signal to test the connection module. When the first signal and the second signal have the second logic level, and the fourth input signal has the first logic level, the second determination unit generates the second output signal to prevent the connection module from being tested. When the first signal, the second signal, and the fourth input signal have the second logic level, the second judgment unit generates the second output signal to test the connection module.

12. The dynamic random access memory as claimed in claim 9, wherein the second determination unit comprises: A third reverse gate has a first input terminal, a second input terminal, and an output terminal; A fourth reverse gate has a first input terminal, a second input terminal, and an output terminal; A third inverter, having an input terminal and an output terminal; as well as A fourth inverter, having one input and one output. The first input terminal of the third inverter is coupled to the detector and configured to receive the first signal; the second input terminal of the third inverter is coupled to the output terminal of the third inverter; the output terminal of the third inverter is coupled to the second input terminal of the fourth inverter; the input terminal of the third inverter is configured to receive a fourth input signal; the first input terminal of the fourth inverter is coupled to the receiver and configured to receive the second signal; the output terminal of the fourth inverter is coupled to the input terminal of the fourth inverter; and the output terminal of the fourth inverter is configured to output the second output signal.

13. A control method for a dynamic random access memory, comprising: A first input signal is received through an input / output pad of a connection module of a dynamic random access memory; A first signal is generated based on a voltage level of the first input signal and a voltage level of a reference signal; as well as A first output signal is generated based on the first signal to control the dynamic random access memory to operate in a first operating mode or a second operating mode. When the first output signal has a first logic level, the dynamic random access memory is controlled to operate in the second operating mode; and when the first output signal has a second logic level, the dynamic random access memory is controlled to operate in the first operating mode. Generating the first signal based on the voltage level of the first input signal and the voltage level of the reference signal includes: The voltage level of the first input signal is compared with the voltage level of the reference signal; When the voltage level of the first input signal is lower than the voltage level of the reference signal, the first signal having the second logic level is generated; and When the voltage level of the first input signal is greater than the voltage level of the reference signal, a first signal with the first logic level is generated. The first operating mode is a 1N mode of a double data rate fifth generation synchronous dynamic random access memory, and the second operating mode is a 2N mode of the double data rate fifth generation synchronous dynamic random access memory.

14. The control method of claim 13, wherein generating the first output signal comprises: Receive a second input signal; as well as A second signal is generated based on the first signal and the second input signal.

15. The control method of claim 14, wherein generating the first output signal further comprises: Receive a third input signal; A third signal is generated based on the second signal and the third input signal; as well as The first output signal is generated based on the third signal. When the first input signal, the second input signal, and the third input signal have the first logic level, the dynamic random access memory is controlled to operate in the second operating mode. When the first input signal has the first logic level, the second input signal has the second logic level, and the third input signal has the second logic level, the dynamic random access memory is controlled to operate in the first operating mode. When the first signal has the first logic level, the second input signal has the first logic level, and the third input signal has the second logic level, the dynamic random access memory is controlled to operate in the first operating mode. When the first signal has the first logic level, the second input signal has the second logic level, and the third input signal has the first logic level, the dynamic random access memory is controlled to operate in the first operating mode.

16. The control method as described in claim 13, further comprising: A second output signal is generated based on the first input signal, including: A fourth signal is generated based on the first input signal; Receive a fourth input signal; A fifth signal is generated based on the first signal, the fourth signal, and the fourth input signal; and The second output signal is generated based on the fifth signal. The connection module is controlled to perform tests based on the second output signal.

17. The control method as described in claim 16, wherein When the first signal and the fourth signal have the second logic level, the second output signal is generated to prevent the connection module from being tested. When the first signal has the second logic level and the fourth signal has the first logic level, the second output signal is generated to test the connection module. When the first signal, the fourth signal, and the fourth input signal have the first logic level, the second output signal is generated to test the connection module. When the first signal and the fourth signal have the first logic level, and the fourth input signal has the second logic level, the second output signal is generated so that the connection module is not tested.

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