Storage arithmetic circuit

Abstract

The present application provides a storage operation circuit, which includes a first chip, a second chip, and multiple data pins. Among them, the first chip and the second chip are three-dimensionally stacked, and the multiple data pins are the data pins of the first chip, which are arranged in a two-dimensional array form. The first chip includes multiple memory blocks, and each memory block includes multiple memory cells. The second chip includes multiple operation blocks corresponding to the memory blocks one by one, and each operation block includes a read / write circuit and an in-block operation circuit connected to the read / write circuit. In the storage operation circuit of the present application, the first chip and the second chip are three-dimensionally stacked, so that the data pins can be arranged in a two-dimensional array form, and the number is no longer limited by the side length of the memory. Therefore, within one read / write cycle, more data than one row in the existing memory can be read, written, and transmitted for operation, improving the bandwidth and thus the operation speed.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to a storage operation circuit. Background Art

[0002] The storage operation circuit is a basic component circuit in a computer and is used to execute arithmetic tasks in the computer.

[0003] Currently, a common storage operation circuit includes two circuit modules located in the same chip, and multiple data pins for data communication. Among them, a memory is provided in the first circuit module, including multiple memory cells arranged in a two-dimensional array and a read / write circuit. An arithmetic circuit is provided in the second circuit module, and the data pins are located on one side or multiple sides of the first circuit module and are arranged in the form of a one-dimensional vector. In one read / write cycle, at most one row of data in the memory can be read, written, and transmitted for arithmetic operations.

[0004] However, for the above-mentioned storage operation circuit located in the same chip, the row and column selection mechanism is used to read and write the data stored in the memory, the bandwidth is limited, and the operation speed is slow, which cannot be applied to high-parallel arithmetic tasks such as neural networks. Summary of the Invention

[0005] This application provides a storage operation circuit to improve the operation speed.

[0006] In a first aspect, this application provides a storage operation circuit, including: a first chip, a second chip, and multiple data pins; wherein, the first chip and the second chip are three-dimensionally stacked; the multiple data pins are the data pins of the first chip and are arranged in a two-dimensional array;

[0007] The first chip includes multiple storage blocks; each storage block includes multiple storage cells;

[0008] The second chip includes multiple arithmetic blocks corresponding to the storage blocks one by one; each arithmetic block includes a read / write circuit and an in-block arithmetic circuit connected to the read / write circuit.

[0009] Further, for each storage block in the storage operation circuit as described above, one or more storage cells in the storage block are correspondingly connected to a bit line; wherein, the bit lines and the data pins are in one-to-one correspondence; the bit lines corresponding to all the storage cells in one storage block form a group of bit lines; the group of bit lines corresponds to a group of data pins;

[0010] The read / write circuit is communicatively connected to the multiple storage cells in the storage block through a group of bit lines in the storage block corresponding to the arithmetic block where it is located, and a group of data pins corresponding to the group of bit lines.

[0011] Furthermore, for the storage and arithmetic circuit described above, the storage unit is used to store data required for arithmetic operations; among them, one storage unit is used to store one or more bits of data;

[0012] The read / write circuit is used to read the data stored in the storage unit via the data pin corresponding to the storage block corresponding to the arithmetic block where it is located, through the bit line connected to the storage unit in the storage block corresponding to the arithmetic block where it is located, and transmit the read data to the in-block arithmetic circuit connected thereto; among them, within one read / write cycle, the read / write circuit is used to read the data stored in one or more target storage units in the storage block corresponding to the arithmetic block where it is located;

[0013] The in-block arithmetic circuit is used to receive the data transmitted by the read / write circuit connected thereto and perform arithmetic operations on the received data to obtain a first arithmetic result; among them, the first arithmetic result includes an intermediate arithmetic result or a final arithmetic result.

[0014] Furthermore, for the storage and arithmetic circuit described above, when the first arithmetic result obtained by the in-block arithmetic circuit is the final arithmetic result, the read / write circuit is further used to obtain the first arithmetic result of the in-block arithmetic circuit connected thereto, and write the first arithmetic result into the storage unit via the data pin corresponding to the storage block corresponding to the arithmetic block where it is located, through the bit line connected to the storage unit in the storage block corresponding to the arithmetic block where it is located; among them, within one read / write cycle, the read / write circuit is used to write the first arithmetic result into one or more target storage units in the storage block corresponding to the arithmetic block where it is located.

[0015] Furthermore, for the storage and arithmetic circuit described above, the arithmetic block further includes: a register;

[0016] The register is connected to the read / write circuit and the in-block arithmetic circuit, and is used to store the first arithmetic result obtained by the in-block arithmetic circuit; when the first arithmetic result obtained by the in-block arithmetic circuit is the final arithmetic result, to enable the read / write circuit connected thereto to write the stored first arithmetic result into the storage unit in the storage block corresponding to the arithmetic block where it is located;

[0017] The register is further used to store the data read by the read / write circuit from one or more target storage units in the storage block corresponding to the arithmetic block where it is located, and transmit the data to the in-block arithmetic circuit.

[0018] Furthermore, for the storage and arithmetic circuit described above, the arithmetic block further includes: an in-block control circuit; the in-block control circuit is connected to the read / write circuit, and the read / write circuit is connected to the storage unit in the storage block corresponding to the arithmetic block where it is located through a strobe line;

[0019] The in-block control circuit is used to generate a strobe signal; the strobe signal is used to select one or more memory cells from the memory block corresponding to the operation block where it is located in each read-write cycle as the target memory cells for data reading or data writing.

[0020] Furthermore, for the storage operation circuit as described above, the in-block control circuit is also connected to the in-block operation circuit and the register;

[0021] The in-block control circuit is further used to generate an in-block control signal; the in-block control signal is used to control the read-write circuit to read the data stored in the target memory cells of the memory block corresponding to the operation block where it is located in the read-write cycle and transmit the read data to the register connected thereto;

[0022] The in-block control signal is further used to control the in-block operation circuit to receive the data transmitted by the register connected thereto, perform an operation on the received data, and transmit the obtained first operation result to the register connected thereto, so that the register stores the first operation result under the control of the in-block control signal.

[0023] Furthermore, for the storage operation circuit as described above, when the first operation result obtained by the in-block operation circuit is the final operation result, the in-block control signal is further used to control the read-write circuit to obtain the first operation result from the register connected thereto and write the first operation result into the target memory cells of the memory block corresponding to the operation block where it is located in the read-write cycle.

[0024] Furthermore, for the storage operation circuit as described above, the storage operation circuit further includes: a top-level operation circuit;

[0025] The top-level operation circuit is respectively connected to the registers in each operation block, and is used to obtain the intermediate operation results stored in the registers and perform a top-level operation based on the obtained multiple intermediate operation results to obtain the final operation result.

[0026] Furthermore, for the storage operation circuit as described above, the storage operation circuit further includes: a top-level control circuit;

[0027] The top-level control circuit is connected to the top-level operation circuit and is used to generate a top-level control signal; the top-level control signal is used to control the top-level operation circuit to obtain the intermediate operation results stored in the registers in each read-write cycle and perform a top-level operation based on the multiple intermediate operation results obtained in all read-write cycles to obtain the final operation result.

[0028] The present application provides a storage and computing circuit, including a first chip, a second chip, and multiple data pins. Among them, the first chip and the second chip are three-dimensionally stacked, and the multiple data pins are the data pins of the first chip, arranged in a two-dimensional array. The first chip includes multiple memory blocks, and each memory block includes multiple memory cells. The second chip includes multiple computing blocks corresponding to the memory blocks one by one, and each computing block includes a read / write circuit and an in-block computing circuit. That is to say, in the storage and computing circuit provided by the present application, the first chip and the second chip are three-dimensionally stacked, so that the data pins can be arranged in a two-dimensional array, and the number of data pins is no longer limited by the side length of the memory. In one read / write cycle, more data than one row in the existing memory can be read, written, and transmitted for computing, improving the bandwidth and thus the computing speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0030] Figure 1 FIG. 9 is a schematic structural diagram of a storage and computing circuit provided by the prior art of the present application;

[0031] Figure 2 FIG. 13 is a schematic structural diagram of a storage and computing circuit provided by an embodiment of the present application;

[0032] Figure 3 FIG. 17 is a first schematic structural diagram of a memory block and its corresponding computing block provided by an embodiment of the present application;

[0033] Figure 4 FIG. 21 is a second schematic structural diagram of a memory block and its corresponding computing block provided by an embodiment of the present application;

[0034] Figure 5 FIG. 25 is a third schematic structural diagram of a memory block and its corresponding computing block provided by an embodiment of the present application;

[0035] Figure 6 FIG. 29 is a fourth schematic structural diagram of a memory block and its corresponding computing block provided by an embodiment of the present application.

[0036] Through the above accompanying drawings, specific embodiments of the present application have been shown, and there will be more detailed descriptions hereinafter. These drawings and text descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] Exemplary embodiments will be described in detail herein, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of a storage operation circuit consistent with some aspects of the present application.

[0038] The storage operation circuit is a basic component circuit in a computer and is used to perform arithmetic tasks in the computer. Currently, common storage operation circuits include two circuit modules located within the same chip and multiple data pins for data communication. Among them, a memory is provided in the first circuit module, including multiple memory cells arranged in a two-dimensional array and a read / write circuit. An arithmetic circuit is provided in the second circuit module, and the data pins are arranged on one side or multiple sides of the first circuit module in the form of a one-dimensional vector. In one read / write cycle, at most one row of data in the memory can be read, written, and transmitted for arithmetic operations.

[0039] In one example, Figure 1 is a schematic structural diagram of a storage operation circuit provided by the prior art of the present application. As Figure 1 shown, p rows and q columns are provided in the first circuit module 1, with a total of p×q memory cells 11 and a read / write circuit 12. Each memory cell 11 stores n-bit data. An arithmetic circuit 21, a control circuit 22, and a register 23 are provided in the second circuit module 2. The data pins 3 are provided corresponding to each column of the memory cells 11, and the number is q. In one read / write cycle (set as T 2D ), at most one row, that is, q×n bits of data, can be read, written, and transmitted for arithmetic operations.

[0040] For example, if 64 rows and 16 columns, a total of 64×16 = 1024 memory cells 11 are provided in the first circuit module 1, and the data pins 3 are provided corresponding to each column of the memory cells 11, and the number is 16. That is, in one read / write cycle, at most 16×n bits of data can be read, written, and transmitted for arithmetic operations. Assuming that 1024 bits of data are required to complete one arithmetic operation, the number of read / write cycles T 2D required to transmit the data required for each arithmetic operation is 1024 / (16×n) = 64 / n, and the bandwidth is 16×n / T 2D .

[0041] However, for the above storage operation circuit located within the same chip, the row and column selection mechanism is used to read and write the data stored in the memory, and the bandwidth (q×n / T 2D ) is limited, and the arithmetic speed is slow, which cannot be applied to high-parallel arithmetic tasks such as neural networks.

[0042] The storage operation circuit provided by the present application aims to solve the above technical problems of the prior art.

[0043] The technical solution of the present application and how the technical solution of the present application solves the above technical problems will be described in detail below with specific embodiments. The following several specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below with reference to the accompanying drawings.

[0044] Figure 2 As shown in the structural schematic diagram of a storage operation circuit provided by an embodiment of the present application, Figure 2 as shown, the storage operation circuit provided in this embodiment includes: a first chip 100, a second chip 200, and a plurality of data pins 300. Among them, the first chip 100 and the second chip 200 are three-dimensionally stacked. The plurality of data pins 300 are data pins of the first chip 100 and are arranged in a two-dimensional array.

[0045] In this embodiment, the first chip 100 includes a plurality of storage blocks 110. Each storage block 110 includes a plurality of storage units 111. The second chip 200 includes a plurality of operation blocks 210 corresponding one-to-one to the storage blocks 110. Each operation block 210 includes a read-write circuit 211 and an in-block operation circuit 212 connected to the read-write circuit 211.

[0046] Based on the above embodiment, in an optional implementation manner, for each storage block 110, one or more storage units 111 in the storage block 110 are correspondingly connected to a bit line. Figure 3 As shown in the first structural schematic diagram of the storage block and its corresponding operation block provided by an embodiment of the present application, Figure 3 as shown, in the storage block 110 and its corresponding operation block 210 provided by an embodiment of the present application, a plurality of storage units 111 in the storage block 110 are correspondingly connected to a bit line 400. Among them, the bit line 400 corresponds one-to-one to Figure 2 the data pins 300 shown in, and the bit lines 400 correspondingly connected to all the storage units 111 in one storage block 110 form a group of bit lines 40. A group of bit lines 40 corresponds to a group of data pins 30.

[0047] In this embodiment, the read-write circuit 211 is communicatively connected to a plurality of storage units 111 in the storage block 110 through a group of bit lines 40 in the storage block 110 corresponding to the operation block 210 where it is located, and a group of data pins 30 corresponding to the group of bit lines 40.

[0048] Based on the above embodiment, in an optional implementation manner, the storage unit 111 can be used to store data required for operations. Among them, one storage unit 111 is used to store one or more bits of data.

[0049] The read / write circuit 211 can be used to read the data stored in the storage unit 111 via the data pin 300 corresponding to the storage block 110 corresponding to the operation block 210 where it is located, through the bit line 400 connected to the storage unit 111 in the storage block 110 corresponding to the operation block 210 where it is located, and transmit the read data to the in-block operation circuit 212 connected thereto. Among them, within one read / write cycle, the read / write circuit 211 can read the data stored in one or more target storage units in the storage block 110 corresponding to the operation block 210 where it is located.

[0050] The in-block operation circuit 212 can be used to receive the data transmitted by the read / write circuit 211 connected thereto and perform operations on the received data to obtain a first operation result.

[0051] Among them, the first operation result can be the final operation result of the storage operation circuit or an intermediate operation result, and this embodiment does not limit this.

[0052] Based on the above embodiment, in another alternative embodiment, when the first operation result obtained by the in-block operation circuit is the final operation result, the read / write circuit 211 can also be used to obtain the first operation result of the in-block operation circuit 212 connected thereto, and write the first operation result into the storage unit 111 via the data pin 300 corresponding to the storage block 110 corresponding to the operation block 210 where it is located, through the bit line 400 connected to the storage unit 111 in the storage block 110 corresponding to the operation block 210 where it is located, so as to store the final operation result. Among them, within one read / write cycle, the read / write circuit 211 can write the first operation result into one or more target storage units in the storage block 110 corresponding to the operation block 210 where it is located.

[0053] In one example, the first chip 100 includes 64 storage blocks 110. Among them, each storage block 110 includes 16 storage units 111, and each storage unit 111 stores n-bit data. Correspondingly, 64 groups of data pins 30 are provided on the first chip 100, and each group of data pins 30 includes 4 data pins 300. That is, within one read / write cycle, at most 64×4×n bits of data can be read, written, and transmitted for operation. Assuming that one operation requires 1024 bits of data, it takes 1024 / (64×4×n) = 4 / n read / write cycles (denoted as T 3D ) to transmit the data required for each operation, and the bandwidth is 256×n / T 3D .

[0054] The storage and operation circuit provided in this embodiment includes a first chip, a second chip, and multiple data pins. Among them, the first chip and the second chip are three-dimensionally stacked, and the multiple data pins are the data pins of the first chip, arranged in a two-dimensional array. The first chip includes multiple storage blocks, and each storage block includes multiple storage units. The second chip includes multiple operation blocks corresponding to the storage blocks one by one, and each operation block includes a read / write circuit and an in-block operation circuit connected to the read / write circuit. That is to say, in the embodiment of the present application, the first chip and the second chip are three-dimensionally stacked, so that the data pins can be arranged in a two-dimensional array, and the number of data pins is no longer limited by the side length of the memory. In one read / write cycle, more data than one row in the existing memory can be read, written, and transmitted for operation, improving the bandwidth and thus the operation speed.

[0055] Based on the above embodiment, Figure 4 This is the second structural schematic diagram of the storage block and its corresponding operation block provided in the embodiment of the present application. As Figure 4 shown, in the storage block and its corresponding operation block provided in this embodiment, the operation block 210 further includes: a register 213.

[0056] In this embodiment, the register 213 is connected to the read / write circuit 211 and the in-block operation circuit 212, and is used to store the first operation result obtained by the in-block operation circuit 212. When the first operation result obtained by the in-block operation circuit 212 is the final operation result, the connected read / write circuit 211 writes the stored first operation result into the storage unit 111 in the storage block 110 corresponding to the operation block 210 where it is located.

[0057] In addition, the register 213 is also used to store the data read by the read / write circuit 211 from one or more target storage units in the storage block 110 corresponding to the operation block 210 where it is located, and transmit the data to the in-block operation circuit 212.

[0058] In practical applications, the register 213 can be used to store the first operation result obtained by the in-block operation circuit 212, so as to perform different subsequent processes for different types of first operation results. In one example, when the first operation result obtained by the in-block operation circuit 212 is the final operation result, the connected read / write circuit 211 can write the stored first operation result into the storage unit 111 in the storage block 110 corresponding to the operation block 210 where it is located to achieve the storage of the final operation result.

[0059] In another example, when the first operation result obtained by the in-block operation circuit 212 is an intermediate operation result, it indicates that the obtained intermediate result needs to be further operated to obtain the final operation result.

[0060] Based on the above embodiments, in an alternative embodiment, the storage and operation circuit further includes: a top-level operation circuit.

[0061] In this embodiment, the top-level operation circuit is respectively connected to the registers 213 in each operation block, and can obtain the intermediate operation results stored in each register 213, and perform a top-level operation based on the obtained multiple intermediate operation results to obtain the final operation result.

[0062] Based on the above embodiments, in another alternative embodiment, the storage and operation circuit further includes: a top-level control circuit.

[0063] In this embodiment, the top-level control circuit is connected to the top-level operation circuit and is used to generate a top-level control signal. The top-level control signal can be used to control the top-level operation circuit to obtain the intermediate operation results stored in different registers 213 in different read / write cycles, and perform a top-level operation based on the multiple intermediate operation results obtained in all read / write cycles to obtain the final operation result.

[0064] In practical applications, after the top-level operation circuit calculates and obtains the final operation result, the obtained final operation result can be transmitted to the registers 213 in one or more operation blocks, so that the read / write circuit 211 connected to the register 213 writes the final operation result obtained by the register 213 into the storage unit 111 in the storage block 110 corresponding to the operation block 210 where it is located, realizing the storage of the final operation result.

[0065] Based on the above embodiments, Figure 5 is the third structural schematic diagram of the storage block and its corresponding operation block provided by the embodiment of the present application. As Figure 5 shown, in the storage block and its corresponding operation block provided by this embodiment, the operation block 210 further includes: an in-block control circuit 214. The in-block control circuit 214 is connected to the read / write circuit 211, and the read / write circuit 211 is connected to the storage unit 111 in the storage block 110 corresponding to the operation block 210 where it is located through a selection line 500.

[0066] In this embodiment, the in-block control circuit 214 can be used to generate a selection signal. The selection signal can select one or more storage units 111 from the storage block 110 corresponding to the operation block 210 where it is located in each read / write cycle as the target storage unit 1110 for data reading or data writing. Among them, the target storage unit 1110 selected in different read / write cycles can be the same target storage unit 1110 or different target storage units 1110, and this embodiment does not limit this.

[0067] In practical applications, the selection signal can be a high-level signal or a low-level signal.

[0068] In one example, if the storage unit 111 is turned on when the level is low, within one read / write cycle, the in-block control circuit 214 can generate a low-level signal corresponding to one storage unit 111, generate a high-level signal corresponding to other storage units 111, and transmit them to each storage unit 111 through the strobe line 500. Among them, the storage unit 111 that receives the low-level signal is the target storage unit 1110 that can perform data reading or data writing in this read / write cycle.

[0069] Correspondingly, in another example, if the storage unit 111 is turned on when the level is high, within one read / write cycle, the in-block control circuit 214 can generate a high-level signal corresponding to one storage unit 111, generate a low-level signal corresponding to other storage units 111, and transmit them to each storage unit 111 through the strobe line 500. Among them, the storage unit 111 that receives the high-level signal is the target storage unit 1110 that can perform data reading or data writing in this read / write cycle.

[0070] Based on the above embodiments, Figure 6 This is the fourth structural schematic diagram of the storage block and its corresponding arithmetic block provided by the embodiments of the present application. As Figure 6 shown, in the storage block and its corresponding arithmetic block provided in this embodiment, the in-block control circuit 214 is further connected to the in-block arithmetic circuit 212 and the register 213.

[0071] In this embodiment, the in-block control circuit is further configured to generate an in-block control signal. This in-block control signal can be used to control the read / write circuit 211 to read the data stored in the target storage unit 1110 of the storage block 110 corresponding to the current arithmetic block within the read / write cycle, and transmit the read data to the register 213 connected thereto.

[0072] In addition, the in-block control signal can also be used to control the in-block arithmetic circuit 212 to receive the data transmitted by the register 213 connected thereto, perform arithmetic operations on the received data, and transmit the obtained first arithmetic result to the register 213 connected thereto, so that the register 213 stores the first arithmetic result under the control of the in-block control signal.

[0073] Based on the above embodiments, in an alternative embodiment, when the first arithmetic result obtained by the in-block arithmetic circuit 212 is the final arithmetic result, the in-block control signal can also be used to control the read / write circuit 211 to obtain the first arithmetic result from the register 213 connected thereto, and within the read / write cycle, write the first arithmetic result into the target storage unit 1110 of the storage block 110 corresponding to the current arithmetic block 210, so as to store the final arithmetic result.

[0074] The storage operation circuit provided in this embodiment controls the storage unit through a gating signal, so as to ensure that only the selected target storage unit in a storage block can perform data reading or writing in each read-write cycle, ensuring the smooth progress of the operation.

[0075] In several embodiments provided by the present application, it should be understood that the disclosed storage operation circuit can be implemented in other ways. For example, the storage operation circuit embodiments described above are merely illustrative. For example, the division of modules is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces. The indirect coupling or communication connection of the storage operation circuit or module can be in electrical, mechanical or other forms.

[0076] The modules described as separate components may or may not be physically separated. The components shown as modules may or may not be physical modules, that is, they may be located in one place, or may be distributed to multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0077] In addition, in each embodiment of the present application, the various functional modules can be integrated in a processing module, or each module can exist physically alone, or two or more modules can be integrated in one module. The above-mentioned integrated modules can be implemented in the form of hardware, or in the form of hardware plus software functional modules.

[0078] In addition, although the operations are depicted in a specific order, this should be understood as requiring such operations to be performed in the specific order shown or in sequential order, or requiring that all illustrated operations should be performed to achieve the desired result. In certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the present application. Certain features described in the context of separate embodiments can also be implemented combinatorially in a single implementation. Conversely, the various features described in the context of a single implementation can also be implemented separately or in any suitable sub-combination in multiple implementations.

[0079] Other embodiments of the present application will be readily apparent to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include known common knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and examples are only illustrative, and the true scope and spirit of the present application are pointed out by the following claims.

[0080] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. A storage operation circuit, characterized in that, Comprising: A first chip, a second chip, and a plurality of data pins; wherein, the first chip and the second chip are three-dimensionally stacked; The plurality of data pins are data pins of the first chip and are arranged in a two-dimensional array; The first chip includes a plurality of memory blocks; each memory block includes a plurality of memory cells; The second chip includes a plurality of arithmetic blocks corresponding one-to-one to the memory blocks; each arithmetic block includes a read-write circuit and an intra-block arithmetic circuit connected to the read-write circuit.

2. The storage operation circuit according to claim 1, wherein For each memory block, one or more memory cells in the memory block are correspondingly connected to a bit line; wherein, the bit lines and the data pins are in one-to-one correspondence; the bit lines correspondingly connected to all the memory cells in a memory block form a group of bit lines; the group of bit lines corresponds to a group of data pins; The read-write circuit is communicatively connected to the plurality of memory cells in the memory block through a group of bit lines in the memory block corresponding to the arithmetic block where it is located, and a group of data pins corresponding to the group of bit lines.

3. The memory arithmetic circuit according to claim 2, wherein The memory cell is used to store data required for arithmetic; wherein, one memory cell is used to store one or more bits of data; The read-write circuit is used to read out the data stored in the memory cell via the data pins corresponding to the memory block corresponding to the arithmetic block where it is located, through the bit lines connected to the memory cells in the memory block corresponding to the arithmetic block where it is located, and transmit the read-out data to the intra-block arithmetic circuit connected thereto; wherein, within one read-write cycle, the read-write circuit is used to read out the data stored in one or more target memory cells in the memory block corresponding to the arithmetic block where it is located; The intra-block arithmetic circuit is used to receive the data transmitted by the read-write circuit connected thereto and perform arithmetic on the received data to obtain a first arithmetic result; wherein, the first arithmetic result includes an intermediate arithmetic result or a final arithmetic result.

4. The memory arithmetic circuit according to claim 3, wherein When the first arithmetic result obtained by the intra-block arithmetic circuit is a final arithmetic result, the read-write circuit is further used to obtain the first arithmetic result of the intra-block arithmetic circuit connected thereto, and write the first arithmetic result into the memory cell via the data pins corresponding to the memory block corresponding to the arithmetic block where it is located, through the bit lines connected to the memory cells in the memory block corresponding to the arithmetic block where it is located; wherein, within one read-write cycle, the read-write circuit is used to write the first arithmetic result into one or more target memory cells in the memory block corresponding to the arithmetic block where it is located.

5. The storage operation circuit according to claim 4, wherein The arithmetic block further includes: a register; The register is connected to the read-write circuit and the intra-block arithmetic circuit, and is used to store the first arithmetic result obtained by the intra-block arithmetic circuit; when the first arithmetic result obtained by the intra-block arithmetic circuit is a final arithmetic result, to enable the read-write circuit connected thereto to write the stored first arithmetic result into the memory cells in the memory block corresponding to the arithmetic block where it is located; The register is further configured to store data read by the read / write circuit from one or more target storage units in the storage block corresponding to the operation block where the register is located, and transmit the data to the intra-block operation circuit.

6. The storage operation circuit according to claim 5, wherein The operation block further includes: an intra-block control circuit; the intra-block control circuit is connected to the read / write circuit, and the read / write circuit is connected to the storage units in the storage block corresponding to the operation block where the read / write circuit is located through a strobe line; The intra-block control circuit is configured to generate a strobe signal; the strobe signal is used to select one or more storage units from the storage block corresponding to the operation block where the intra-block control circuit is located in each read / write cycle as the target storage units for data reading or data writing.

7. The storage operation circuit according to claim 6, wherein The intra-block control circuit is further connected to the intra-block operation circuit and the register; The intra-block control circuit is further configured to generate an intra-block control signal; the intra-block control signal is used to control the read / write circuit to read the data stored in the target storage units in the storage block corresponding to the operation block where the read / write circuit is located in a read / write cycle, and transmit the read data to the register connected thereto; The intra-block control signal is further used to control the intra-block operation circuit to receive the data transmitted by the register connected thereto, perform an operation on the received data, and transmit the obtained first operation result to the register connected thereto, so that the register stores the first operation result under the control of the intra-block control signal.

8. The storage operation circuit according to claim 7, wherein when the first operation result obtained by the intra-block operation circuit is the final operation result, the intra-block control signal is further used to control the read / write circuit to obtain the first operation result from the register connected thereto, and write the first operation result into the target storage units in the storage block corresponding to the operation block where the read / write circuit is located in a read / write cycle.

9. The storage operation circuit according to claim 8, wherein The storage operation circuit further includes: a top-level operation circuit; The top-level operation circuit is respectively connected to the registers in each operation block, and is configured to obtain the intermediate operation results stored in the registers, and perform a top-level operation based on the obtained multiple intermediate operation results to obtain a final operation result.

10. The storage operation circuit according to claim 9, wherein The storage operation circuit further includes: a top-level control circuit; The top-level control circuit is connected to the top-level operation circuit, and is configured to generate a top-level control signal; the top-level control signal is used to control the top-level operation circuit to obtain the intermediate operation results stored in the registers in each read / write cycle, and perform a top-level operation based on the multiple intermediate operation results obtained in all read / write cycles to obtain a final operation result.

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