Memory device and method of operation thereof

Abstract

Embodiments of the present disclosure relate to a memory device and an operating method thereof. A memory device is provided. The memory device can include a voltage code controller configured to generate a voltage code based on a number of times a program loop is executed, the voltage code generating a program voltage and a pass voltage; and a voltage generator configured to generate the program voltage and the pass voltage in response to the voltage code, to transmit the program voltage to a selected word line and to transmit the pass voltage to an unselected word line, wherein the voltage generator is configured to sequentially increase the pass voltage applied to the unselected word line in an order of proximity to the selected word line as the number of times the program loop is executed increases.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0126705, filed on September 29, 2020, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The disclosure relates to a memory device and a method of operating a memory device, and more particularly to a memory device capable of performing a program operation. BACKGROUND

[0004] Memory devices can include a volatile memory device in which stored data is lost when power supply is interrupted, and a non-volatile memory device in which stored data is retained even when power supply is interrupted.

[0005] Examples of the volatile memory device can include a dynamic random access memory (DRAM) and a static random access memory (SRAM). Examples of the non-volatile memory device can include a read only memory (ROM), a programmable read only memory (PROM), an erasable PROM (EPROM), an electrically EPROM (EEPROM), a NAND flash, etc.

[0006] The memory device can include a memory cell array, a peripheral circuit, and a logic circuit.

[0007] The memory cell array can include a plurality of memory cells, each of which can store data. A scheme in which one bit of data is stored in one memory cell is referred to as a single level cell (SLC) scheme, and a scheme in which two or more bits of data are stored in one memory cell is referred to as a multi-level cell (MLC) scheme. The MLC scheme can be classified into a triple level cell (TLC) scheme and a quad level cell (QLC) scheme based on the number of bits stored in each memory cell. In the TLC scheme, three bits of data can be stored in one memory cell, and in the QLC scheme, four bits of data can be stored in one memory cell. SUMMARY

[0008] One embodiment of the present disclosure can provide a memory device. The memory device can include a voltage code controller configured to generate a voltage code based on a number of program loops performed, the voltage code generating a program voltage and a pass voltage; and a voltage generator configured to generate the program voltage and the pass voltage in response to the voltage code, transmit the program voltage to a selected word line, and transmit the pass voltage to unselected word lines, wherein the voltage generator is configured to sequentially increase the pass voltage applied to the unselected word lines in an order of proximity to the selected word line as the number of program loops performed increases.

[0009] One embodiment of the present disclosure can provide a method of operating a memory device. The method can include setting a first step voltage for increasing a program voltage and a second step voltage for increasing a pass voltage; performing a program loop with an operation of applying the program voltage to a selected word line and a verify operation of verifying a memory cell coupled with the selected word line; increasing the program voltage by the first step voltage as a number of program loops performed increases; and increasing the pass voltage applied to unselected word lines by the second step voltage in an order of proximity to the selected word line as the number of program loops performed increases.

[0010] One embodiment of the present disclosure can provide a method of operating a memory device. The method can include incrementally increasing a program voltage applied to a selected word line as a number of program loops performed increases; incrementally increasing a pass voltage applied to an unselected word line adjacent to the selected word line as the number of program loops performed increases; and increasing a number of unselected word lines to which the incrementally increased pass voltage is applied as the number of program loops performed increases. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 FIG. 1 is a diagram illustrating a memory system according to one embodiment of the present disclosure.

[0012] Figure 2 FIG. 2 is a diagram illustrating a memory device according to one embodiment of the present disclosure.

[0013] Figure 3 FIG. 3 is a diagram illustrating a memory block according to one embodiment of the present disclosure.

[0014] Figure 4 FIG. 4 is a diagram illustrating a voltage code controller according to one embodiment of the present disclosure.

[0015] Figure 5 FIG. 5 is a diagram illustrating a first voltage generator according to one embodiment of the present disclosure.

[0016] Figure 6is a graph illustrating a threshold voltage distribution of memory cells.

[0017] Figure 7 is a graph illustrating threshold voltages of memory cells changed by a loop in a program operation.

[0018] Figure 8 is a graph illustrating a program operation based on incremental step pulse programming (ISPP).

[0019] Figure 9 is a graph illustrating a voltage applied to a word line coupled with a selected memory block.

[0020] Figure 10 is a flowchart illustrating a method of operating a memory device according to an embodiment of the present disclosure.

[0021] Figure 11A and Figure 11B is a graph illustrating a program operation according to a first embodiment of the present disclosure.

[0022] Figure 12A and Figure 12B is a graph illustrating a program operation according to a second embodiment of the present disclosure.

[0023] Figure 13A and Figure 13B is a graph illustrating a program operation according to a third embodiment of the present disclosure.

[0024] Figure 14 and Figure 15 is a graph illustrating a program operation according to a fourth embodiment of the present disclosure.

[0025] Figure 16 and Figure 17 is a graph illustrating a program operation according to a fifth embodiment of the present disclosure.

[0026] Figure 18 is a graph illustrating a memory card system applying a memory device according to an embodiment of the present disclosure.

[0027] Figure 19 is a graph illustrating a solid state drive (SSD) system applying a memory device according to the present disclosure. DETAILED DESCRIPTION

[0028] The specific configurations or functional descriptions disclosed herein are merely for the purpose of exemplifying embodiments according to the concept of the present disclosure. Embodiments according to the concept of the present disclosure can be implemented in various forms, and should not be interpreted as being limited to the embodiments set forth herein.

[0029] It should be understood that, although the terms “first,” “second,” “third,” etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present disclosure.

[0030] Furthermore, it should be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

[0031] Various embodiments of the present disclosure are directed to a memory device, and a method of operating a memory device, the memory device having enhanced reliability by controlling a pass voltage applied to an unselected word line in a program operation.

[0032] Figure 1 FIG. 1 is a diagram illustrating a memory system according to one embodiment of the present disclosure.

[0033] Referring to Figure 1 The memory system 1000 can include a storage device 1100 and a memory controller 1200. The storage device 1100 can include a plurality of memory devices MD, which can be coupled to the memory controller 1200 via input / output lines.

[0034] The memory controller 1200 can communicate between a host 1500 and the memory devices MD. The memory controller 1200 can create a command CMD to control the memory devices MD at a request RQ of the host 1500, and can perform a background operation for performance enhancement of the memory system 1000 even without the request RQ.

[0035] The host 1500 can create a request RQ for various operations, and can output the request RQ to the memory system 1000. For example, the request RQ can include a program request to control a program operation, a read request to control a read operation, an erase request to control an erase operation.

[0036] The host 1500 can communicate with the memory system 1000 by means of various interfaces such as Peripheral Component Interconnect Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA (PATA), Serial Attached Small Computer System Interface (SAS), Non-Volatile Memory Express (NVMe), Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Disk Interface (ESDI), or Integrated Drive Electronics (IDE).

[0037] Figure 2 is a diagram illustrating a memory device according to one embodiment of the disclosure.

[0038] Referring to Figure 2 , the memory device MD can include an array 110 of memory cells storing data, peripheral circuits 120a to 150 performing a program, read, or erase operation, and a logic circuit 160 controlling the peripheral circuits 120a to 150.

[0039] The array 110 of memory cells can include a plurality of memory blocks BLK1 to BLKI storing data. Each of the memory blocks can include a plurality of memory cells, and the memory cells can be implemented in a two-dimensional (2D) structure in which the memory cells are arranged in parallel with a substrate, or in a three-dimensional (3D) structure in which the memory cells are stacked in a direction perpendicular to the substrate.

[0040] The peripheral circuits 120a to 150 can include a first voltage generator 120a, a first row decoder 130a, a first page buffer group 140a, and an input / output circuit 150.

[0041] The first voltage generator 120a can generate and output an operating voltage VOP required for various operations in response to a voltage code VCD. For example, the first voltage generator 120a can generate and output a program voltage, a verify voltage, a read voltage, a pass voltage, an erase voltage, etc. having various levels.

[0042] The first row decoder 130a can select one of the memory blocks BLK1 to BLKI included in the array 110 of memory cells based on a row address (RADD), and can transfer the operating voltage VOP to the selected memory block.

[0043] The first page buffer group 140a can be coupled to the array 110 of memory cells with bit lines. For example, the first page buffer group 140a can include page buffers coupled to respective bit lines. The page buffers can operate simultaneously in response to a buffer control signal PBSIG and can temporarily store data in a program or read operation. A verify operation performed in a program operation and a verify operation performed in an erase operation can be performed in the same manner as a read operation. The page buffers can sense a bit line voltage that varies based on a threshold voltage of the memory cells in a read operation or a verify operation. In other words, it can be determined whether the threshold voltage of the memory cell is lower or higher than a read voltage or a verify voltage based on a result of a sensing operation performed by the page buffer.

[0044] The input / output circuit 150 can be coupled toFigure 1 The input / output circuit 150 can input or output the command CMD, the address ADD, and the data DATA by means of the input / output line. For example, the input / output circuit 150 can transmit the received command CMD and the address ADD to the logic circuit 160 by means of the input / output line, and can transfer the data DATA received from the first page buffer group 140a to the memory controller 1200 by means of the input / output line.

[0045] The logic circuit 160 can output the voltage code VCD, the row address RADD, the page buffer control signal PBSIG, and the column address (CADD) in response to the command CMD and the address ADD. For example, the logic circuit 160 can include software that performs an algorithm in response to the command CMD, and hardware configured to output various signals based on the algorithm. The logic circuit 160 can further include a voltage code controller 200 for changing the program voltage and the pass voltage based on a loop in a program operation.

[0046] The voltage code controller 200 can be configured to output the voltage code VCD, the loop count (count value, LC#), and the word line address WL_ADD for changing the program voltage and the pass voltage. For example, the program operation can be performed on the basis of an incremental step pulse programming (ISPP) that gradually increases the program voltage in increments. The ISPP-based program operation can perform a plurality of loops. In each loop, an operation of applying the program voltage to a selected word line and an operation of verifying the threshold voltage of the memory cell can be performed. The voltage code controller 200 can output the voltage code VCD so that the program voltage and the pass voltage increase as the loop count LC# (the loop count LC# is the number of times the loop is performed) increases, and allocate and apply the program voltage and the pass voltage to the selected word line and the unselected word line based on the word line address (WL_ADD).

[0047] The program voltage can be a voltage for increasing the threshold voltage of a memory cell selected from among memory cells coupled with a selected word line. The pass voltage can be a voltage applied to an unselected word line to form a channel for a string by turning on memory cells coupled with the unselected word line.

[0048] The pass voltage can be applied to an unselected word line coupled with a selected memory block when the program voltage is applied to a selected word line coupled with the selected memory block. The voltage code controller 200 can be configured to output the voltage code VCD to change the program voltage and the pass voltage as the loop count LC# increases.

[0049] Figure 3 is a diagram illustrating a memory block, e.g., a memory block BLKi of a plurality of memory blocks BLK1 to BLKi shown in Figure 1

[0050] Referring to Figure 3 , the i-th memory block BLKi can include a plurality of strings ST1 to ST4. Although a first string to a fourth string ST1 to ST4 are illustrated in Figure 3 , more strings can be included in the memory block.

[0051] The first to fourth strings ST1 to ST4 can be coupled between bit lines BL1 to BL4 and a source line SL. For example, the first string ST1 can be coupled between the first bit line BL1 and the source line SL, and the second string ST2 can be coupled between the second bit line BL2 and the source line SL.

[0052] Each of the first to fourth strings ST1 to ST4 can include a source select transistor SST, a plurality of memory cells C1 to C16, and a drain select transistor DST, and although not shown, dummy cells can also be included between the memory cells C1 to C16 and the source or drain select transistor SST or DST. Although a first to a sixteenth memory cell C1 to C16 are illustrated in Figure 3 for ease of illustration, the strings ST1 to ST4 can include more memory cells. The string configuration of, e.g., the fourth string ST4 can now be described in detail hereinafter.

[0053] The source select transistor SST included in the fourth string ST4 can electrically couple or electrically decouple the source line SL and the first memory cell C1 from each other based on a voltage applied to a source select line SSL. The gates of the first to sixteenth memory cells C1 to C16 can be coupled to first to sixteenth word lines WL1 to WL16, respectively. The drain select transistor DST can electrically couple or electrically decouple the fourth bit line BL4 and the sixteenth memory cell C16 from each other based on a voltage applied to a drain select line DSL. The gates of the source select transistors SST included in the different strings ST1 to ST4 can be commonly coupled to the source select line SSL; the gates of the first to sixteenth memory cells C1 to C16 can be coupled to the first to sixteenth word lines WL1 to WL16; and the gates of the drain select transistors DST can be commonly coupled to the drain select line DSL. A group of memory cells coupled to the same word line is referred to as a page PG, and a program operation and a read operation can be performed in the page PG.

[0054] ​For example, for a program operation, a program voltage can be applied to a selected word line coupled with a selected page PG, and a pass voltage can be applied to the remaining word lines, i.e., unselected word lines. The program voltage is a voltage for increasing a threshold voltage of a selected memory cell, and the pass voltage is a voltage for forming a channel for a string by turning on unselected memory cells included in the string. For example, assuming that the sixth word line WL6 is a selected word line, the other first to fifth word lines WL1 to WL5 and the seventh to sixteenth word lines WL7 to WL16 can be unselected word lines. The program operation can be performed in a direction from a source select line SSL to a drain select line DSL or in a direction from the drain select line DSL to the source select line SSL.

[0055] Figure 4 is a diagram illustrating a voltage code controller according to one embodiment of the disclosure.

[0056] Referring to Figure 4 The voltage code controller 200 can include an offset table 210, a loop counter 220, a code generator 230, and a word line (WL) address manager 240.

[0057] The offset table 210 can include various offset values OFS# for each of the program voltage VPGM and the pass voltage VPASS. For example, the offset table 210 can include program offset values PGM_OFS1 to n for determining step voltages of the program voltage Vpgm and pass offset values PASS_OFS1 to m for determining step voltages of the pass voltage Vpass. The offset values selected from among the plurality of offset values stored in the offset table 210 can be pre-set based on electrical characteristics of the memory device.

[0058] The loop counter 220 can count the number of times that a program loop is performed in a program operation for a selected page. For example, when a verify operation for the selected page fails, the loop counter 220 can increase a loop count value LC# by 1, and when the verify operation for the selected page has passed, the loop count value LC#1 can be reset. Figure 2 The logic circuit 160 of the first page buffer set 140a can determine whether a verify operation has passed or failed based on data sensed by Figure 2 The logic circuit 160 of the first page buffer set 140a can determine whether a verify operation has passed or failed based on data sensed by

[0059] The code generator 230 can receive the selected offset value OFS# from the offset table 210, and can output a voltage code VCD to which the offset value OFS# is applied, based on the offset loop count LC#. The voltage code VCD can include a program voltage code Vpgm_CD, a program offset code OFS_Vpgm_CD, a pass voltage code Vpass_CD, a pass offset code OFS_Vpass_CD, and the loop count LC#. The program voltage code Vpgm_CD can be a code to generate a program voltage applied to the selected word line. The program offset code OFS_Vpgm_CD can be a code indicating a change level of the program voltage when the loop is changed. The pass voltage code Vpass_CD can be a code to generate a pass voltage applied to the unselected word line. The pass offset code OFS_Vpass_CD can be a code indicating a change level of the pass voltage when the loop is changed.

[0060] When the loop count LC# is increased by 1, the code generator 230 can output the voltage code VCD, and when the loop count LC# is reset to 0, the code generator 230 can not output the voltage code VCD.

[0061] The word line address manager 240 can output a word line address WL_ADD having an address of the selected word line and the unselected word line. For example, when a program operation for the selected memory block starts, the word line address manager 240 can set a default address of the selected word line to "1", and can set the unselected word line to the remaining address. As a program loop for the selected word line increases, the loop count LC# increases, and when the loop count LC# is input, the word line address WL_ADD is output, and when the loop count LC# is reset, the address of the selected word line can be changed to the next address. In other words, when the loop count LC# increases, the word line address manager 240 can output the same word line address WL_ADD, and when the loop count LC# is reset, the word line address manager 240 can change the word line address WL_ADD. For example, when a program operation for a memory cell coupled with a first word line is completed and the loop count LC# is reset, the word line address manager 240 can change the selected word line to a second word line and can change the addresses of the other word lines to the addresses of the unselected word lines.

[0062] Figure 5 is a diagram illustrating a first voltage generator according to one embodiment of the disclosure.

[0063] Reference Figure 5The first voltage generator 120a can generate and output operation voltages Vop required for various operations in response to the voltage code VCD, the loop count LC#, and the word line address WL_ADD. For example, the first voltage generator 120a can include a program voltage generator 51, a first level changer 52, a pass voltage generator 53, a second level changer 54, and a voltage distributor 55.

[0064] The program voltage generator 51 can generate a first program voltage 1Vpgm in response to a program voltage code Vpgm_CD included in the voltage code VCD. Figure 4 The first program voltage 1Vpgm is the lowest program voltage applied to the selected word line, and the lowest program voltage can be a starting program voltage.

[0065] The first level changer 52 can receive the first program voltage 1Vpgm and can output a program voltage #Vpgm in response to a program offset code OFS_Vpgm_CD and the loop count LC#. For example, the first level changer 52 can output the first program voltage 1Vpgm or a second program voltage obtained by adding a step voltage to the first program voltage 1Vpgm in response to the loop count LC# and the program offset code OFS_Vpgm_CD. In this way, the first level changer 52 can output the program voltage #Vpgm that increases the step voltage from the previous program voltage as the loop count increases.

[0066] The pass voltage generator 53 can output a first pass voltage 1Vpass in response to a pass voltage code Vpass_CD. The first pass voltage 1Vpass can be the lowest pass voltage applied to the unselected word line.

[0067] The second level changer 54 can receive the first pass voltage 1Vpass and can selectively output the first to nth pass voltages 1Vpass to nVpass in response to the pass offset code OFS Vpgm CD and the loop count LC#. The number of pass voltages with different levels output from the second level changer 54 can be determined based on the loop count LC#. For example, when the loop count LC# is 1, the second level changer 54 can output only the first pass voltage 1Vpass. When the loop count LC# is 2, the second level changer 54 can output the first pass voltage 1Vpass and the second pass voltage 2Vpass. The second pass voltage 2Vpass can be a voltage generated based on the pass offset code OFS Pass CD and can be one step voltage higher than the first pass voltage 1Vpass. The step voltage for the pass voltage is different from the step voltage for the program voltage. When the loop count LC# is 3, the second level changer 54 can output the first to third pass voltages 1Vpass to 3Vpass. The third pass voltage 3Vpass is a voltage generated based on the pass offset code OFS Pass CD and can be higher than the second pass voltage 2Vpass.

[0068] In one embodiment of the disclosure, the second level changer 54 can increase the number of pass voltages based on a segment to which the loop count LC# belongs. For example, when the loop count LC# belongs to a first segment, the second level changer 54 can output only the first pass voltage 1Vpass; when the loop count LC# belongs to a second segment, the second level changer 54 can output the first pass voltage 1Vpass and the second pass voltage 2Vpass; and when the loop count LC# belongs to a third segment, the second level changer 54 can output the first to third pass voltages 1Vpass to 3Vpass. The first to third segments can each refer to an interval of a certain number of loop counts LC#.

[0069] The voltage distributor 55 can be configured to apply the program voltage Vpgm and the first to nth pass voltages 1Vpass to nVpass as operation voltages Vop to respective word lines in response to the word line address WL_ADD. Specifically, the operation voltages Vop output from the voltage distributor 55 can be applied to a global word line, and the operation voltages Vop applied to the global word line can be transferred to local word lines coupled with memory blocks selected by the first row decoder 130a of the first row of Figure 2 The operation voltages Vop output from the voltage distributor 55 can be applied to a global word line, and the operation voltages Vop applied to the global word line can be transferred to local word lines coupled with memory blocks selected by the first row decoder 130a of the first row of

[0070] The voltage distributor 55 can apply a program voltage #Vpgm to a selected word line based on a word line address WL_ADD, and can apply pass voltages to unselected word lines, in which case a relatively high pass voltage can be applied to an unselected word line that is more adjacent to the selected word line. For example, the voltage distributor 55 can apply a high pass voltage to an unselected word line that is close to the selected word line, and can sequentially apply relatively low pass voltages to unselected word lines that are farther from the selected word line.

[0071] For example, when a program voltage #Vpgm and a first pass voltage 1Vpass are applied to the voltage distributor 55, the voltage distributor 55 can apply the program voltage #Vpgm to a selected word line, and apply the first pass voltage 1Vpass to all unselected word lines. When a program voltage #Vpgm and first and second pass voltages 1Vpass and 2Vpass are applied to the voltage distributor 55, the voltage distributor 55 can apply the program voltage #Vpgm to a selected word line, apply the second pass voltage 2Vpass to an unselected word line that is closest to the selected word line, and apply the first pass voltage 1V to the remaining unselected word lines. When a program voltage #Vpgm and first to third pass voltages 1Vpass to 3Vpass are applied to the voltage distributor 55, the voltage distributor 55 can apply the program voltage #Vpgm to a selected word line, apply the third pass voltage 3Vpass to an unselected word line that is closest to the selected word line, apply the second pass voltage 2Vpass to an unselected word line that is next closest to the selected word line, and apply the first pass voltage 1V to the remaining unselected word lines.

[0072] The first pass voltage 1Vpass is the lowest pass voltage, the second pass voltage 2Vpass is higher than the first pass voltage 1Vpass, and the third pass voltage 3Vpass is higher than the second pass voltage 2Vpass.

[0073] Figure 6 is a graph illustrating a threshold voltage distribution of a memory cell.

[0074] Referring to Figure 6 A program operation can be classified into various methods based on the number of bits stored in a memory cell. For example, a method in which three bits of data are stored in a memory cell is referred to as a triple-level cell (TLC) method, and a method in which four bits of data are stored in a memory cell is referred to as a quad-level cell (QLC) method.

[0075] In the TLC method, the state of the memory cell can be classified as one of an erased state ER or seven program states P1 to P7. In the QLC method, the state of the memory cell can be classified as one of an erased state ER or fifteen program states P1 to P15.

[0076] In an embodiment of the disclosure, the number of bits that can be stored in the memory cell can be 5 or more, and there can be no limit to the number of bits stored in the memory cell.

[0077] Figure 7 is a graph for explaining that the threshold voltage of the memory cell is changed by a loop in a program operation.

[0078] Referring to Figure 7 In the program operation for the selected page, a plurality of loops LP1 to LPn can be performed until the threshold voltage of the selected memory cell reaches the target level PV. For example, when the program operation starts, the selected memory cell can be in the erased state ER. When the first loop LP1 is performed by using a first program voltage, the threshold voltage of the selected memory cell can increase based on the first program voltage. Subsequently, when the second loop LP2 is performed, in which a second program voltage higher than the first program voltage is applied to the selected word line, the threshold voltage of the selected memory cell can increase based on the second program voltage. In this way, the nth loop LPn can be performed.

[0079] Since the plurality of memory cells included in the selected page can have different electrical characteristics and target levels PV, the number of loops performed from the erased state ER to the target level PV can differ for the memory cells.

[0080] The first to nth loops LP1 to LPn will now be described in more detail.

[0081] Figure 8 is a graph illustrating an ISPP-based program operation.

[0082] Referring to Figure 8 In the ISPP-based program operation, the first to nth loops LP1 to LPn can be performed to increase the threshold voltage of the selected memory cell to the target level.

[0083] Assuming that the entire program operation in which the first to nth loops LP1 to LPn are performed is a main program operation, a sub-program operation and a verify operation can be performed in each loop.

[0084] For example, the first to nth loops LP1 to LPn can be sequentially performed when a main programming operation for the selected page starts. Here, n denotes a positive integer, which can be changed based on a result of a verification operation performed in each loop. A maximum value of n is set in advance, and when the verification operation fails until n reaches the maximum value, the selected memory block can be regarded as a bad block.

[0085] The sub-programming operation performed in each of the first to nth loops LP1 to LPn can be an operation in which a program voltage is applied to the selected word line, and the verification operation can be an operation of determining whether the threshold voltage of the memory cell has increased to a target voltage.

[0086] In Figure 8 In the TLC-based main programming operation, the memory cell can be programmed using seven program states. Accordingly, at least seven verification voltages can be used in the verification operation. For example, in the sub-programming operation of the first loop LP1, a first program voltage 1Vpgm can be applied to the selected word line. The first program voltage 1Vpgm can correspond to a starting program voltage of the main programming. The first program voltage 1Vpgm is a positive voltage greater than 0V, and the threshold voltage of the selected memory cell can be increased based on the first program voltage 1Vpgm. In the sub-programming operation, the selected memory cell can be a memory cell coupled with a bit line to which a program enable voltage is applied, and the unselected memory cell can be a memory cell coupled with a bit line to which a program inhibit voltage is applied. The program enable voltage can be 0V, and the program inhibit voltage can be a power supply voltage. In the verification operation of the first loop LP1, a first verification voltage V1 can be applied to the selected word line. The first verification voltage V1 can be a positive voltage greater than 0V to determine whether the selected memory cell has been programmed to the first program state. When the verification operation of the first loop LP1 fails, the second loop LP2 can be performed.

[0087] In the second loop LP2, the sub-programming operation can be performed by using a second program voltage 2Vpgm greater than the first program voltage 1Vpgm, and the verification operations for the first and second program states can be sequentially performed. For example, in the verification operation of the second loop LP2, the verification operation for the first program state and the verification operation for the second program state can be sequentially performed. In the verification operation for the first program state, the first verification voltage V1 can be used, and in the verification operation for the second program state, a second verification voltage V2 greater than the first verification voltage V1 can be used.

[0088] In the third loop LP3, the sub-programming operation can be performed by using a third programming voltage 3Vpgm which is greater than the second programming voltage 2Vpgm, and the verify operations for the first to third program states can be sequentially performed. In the verify operation for the first program state, the first verify voltage V1 can be used. In the verify operation for the second program state, the second verify voltage V2 which is greater than the first verify voltage V1 can be used; and in the verify operation for the third program state, the third verify voltage V3 which is greater than the second verify voltage V2 can be used. When the verify operation performed for the first program state passes in the third loop LP3, the verify operation by using the first verify voltage V1 is not performed in the fourth loop LP4.

[0089] In the fourth loop LP4, the sub-programming operation can be performed by using a fourth programming voltage 4Vpgm which is greater than the third programming voltage 3Vpgm, and the verify operations for the second to fourth program states can be sequentially performed. In the verify operation for the fourth program state, the fourth verify voltage V4 which is greater than the third verify voltage V3 can be used.

[0090] The remaining loops can be performed in this way, when the verify operation performed in the nth loop LPn passes, the main programming operation for the selected page can end.

[0091] Figure 9 is a graph illustrating voltages applied to word lines coupled with a selected memory block.

[0092] Referring to Figure 9 The selected memory block can include a plurality of strings, and among the memory cells included in the selected page, the memory cells included in a selected string Sel_ST are programmed. A program enable voltage can be applied to a bit line coupled with the selected string Sel_ST, and a program inhibit voltage can be applied to a bit line coupled with an unselected string Unsel_ST. For example, assuming that one string coupled with a first bit line BL1 among four strings is the selected string Sel_ST, and the strings coupled with second to fourth bit lines BL2 to BL4 are the unselected strings Unsel_ST, in the programming operation, the program enable voltage can be applied to the first bit line BL1, and the program inhibit voltage can be applied to the second to fourth bit lines BL2 to BL4.

[0093] Assuming that among the word lines in the first through sixteenth word lines WL1 through WL16, the ninth word line WL9 is a selected word line Sel WL, the first through eighth word lines WL1 through WL8 and the tenth through sixteenth word lines WL10 through WL16 can be unselected word lines Unsel WL. In a program operation, a program voltage Vpgm can be applied to the selected word line Sel WL, and a pass voltage #Vpass can be applied to the unselected word lines Unsel WL.

[0094] The pass voltage #Vpass applied to the unselected word lines Unsel WL can be changed by a cycle count of the selected page coupled with the selected word line Sel WL. For example, as the cycle count increases, the pass voltage applied to the unselected word lines Unsel WL can be incremented in an order of proximity to the selected word line Sel WL.

[0095] In embodiments of the present disclosure, how the pass voltage is applied to the unselected word lines will now be described in detail.

[0096] Figure 10 is a flowchart illustrating a method of operating a memory device according to one embodiment of the present disclosure.

[0097] Referring to Figure 10 At step S101, one of the plurality of word lines included in the selected memory block is selected. A program operation sequence corresponding to the selected word line Sel WL can be defined as N. Thus, N can be a positive integer. For example, N is 1 for the selected word line Sel WL coupled with the page to be programmed first, and N is 2 for the selected word line Sel WL coupled with the page to be programmed second.

[0098] At step S102, a starting number of cycle counts LC for the selected word line Sel WL can be set to 1.

[0099] At step S103, a level of a program voltage Vpgm to be applied to the selected word line Sel WL is set based on a program voltage code. The program voltage Vpgm set with the cycle count LC of 1 can be a starting program voltage.

[0100] At step S104, a first pass voltage 1Vpass can be set based on a pass voltage code. The first pass voltage 1Vpass can be the lowest value among the pass voltages to be applied to the unselected word lines. Subsequently, at step S105, an offset of the pass voltage can be set based on a pass offset code. The offset of the pass voltage can define a difference between the pass voltages to be applied to different unselected word lines, and can be changed by the cycle count LC.

[0101] The pass voltage for the unselected word line adjacent to the selected word line Sel WL in the first direction is then set. At step S106, the pass voltage #Vpass to be applied to the (N-l)th unselected word line Unsel WL(N-l) can be set. The (N-l)th unselected word line Unsel WL(N-l) can be the line that is most proximate to the selected word line Sel WL in the first direction. When the pass voltage #Vpass to be applied to the (N-l)th unselected word line Unsel WL(N-l) is set, at step S107, it is determined whether the (N-l)th unselected word line Unsel WL(N-l) is the last word line arranged in the first direction from the selected word line Sel WL. When the (N-l)th unselected word line Unsel WL(N-l) is not the last word line (in the case of "No"), at step S108, the next unselected word line arranged in the first direction is selected. For example, N-l can be used in place of N to select the next unselected word line to the (N-l)th unselected word line Unsel WL(N-l). Steps S106 to S108 can be repeated until all the pass voltages #Vpass to be applied to the unselected word lines arranged in the first direction are set.

[0102] When all the pass voltages #Vpass to be applied to the unselected word lines arranged in the first direction are set (in the case of "Yes") at step S107, at step S109, N is reset to the value of the selected word line Sel WL.

[0103] The pass voltage for the unselected word line adjacent to the selected word line Sel WL in the second direction is then set. The second direction can be opposite to the first direction. At step S110, the pass voltage #Vpass to be applied to the (N+l)th unselected word line Unsel WL(N+1) can be set. The (N+l)th unselected word line Unsel WL(N+1) can be the line closest to the selected word line Sel WL in the second direction. When the pass voltage #Vpass to be applied to the (N+l)th unselected word line Unsel WL(N+1) is set, at step S111, it is determined whether the (N+l)th unselected word line Unsel WL(N+1) is the last word line arranged in the second direction from the selected word line Sel WL. When the (N+l)th unselected word line Unsel WL(N+1) is not the last word line (in the case of "No"), at step S112, the next unselected word line arranged in the second direction is selected. For example, N+l can be used to select the next unselected word line to the (N+l)th unselected word line Unsel WL(N+1) using N instead. Steps S110 to S112 can be repeated until all the pass voltages #Vpass to be applied to the unselected word lines arranged in the second direction are set.

[0104] When at step S111, the pass voltages #Vpass to be applied to the unselected word lines arranged in the second direction are all set (in the case of "Yes"), at step S113, a programming operation using the established program voltage Vpgm and pass voltages #Vpass can be performed.

[0105] Subsequently, at step S114, a verify operation for the programming operation performed at step S113 can be performed. When the verify operation has passed (PASS), the programming operation for the selected memory cell can end. When the verify operation has failed (FAIL), at step S115, an operation of determining whether the loop count LC reaches a maximum value (MAX) can be performed. The maximum value MAX of the loop count LC can be set in advance. When it is determined that the loop count LC reaches the maximum value MAX, the selected memory block can be treated as a bad block.

[0106] When at step S115, it is determined that the loop count LC has not reached the maximum value MAX (in the case of "No"), at step S117, the loop count LC is increased by 1, and the next loop can be performed from step S103.

[0107] The programming operation can be based on Figure 10 The flowchart shown is performed in various methods, now referring to Figures 11A to 13Bwill be described.

[0108] Figure 11A and Figure 11B is a diagram illustrating a program operation according to the first embodiment of the present disclosure.

[0109] Referring to Figure 11A , the following will describe voltages applied to the selected word line Sel_WL and the unselected word line Unsel_WL for each loop count LC in the program operation for the selected page.

[0110] It is assumed that the nth word line WLn is the selected word line Sel_WL, and the other word lines WL(n±1)... are the unselected word lines Unsel_WL.

[0111] In the first embodiment of the present disclosure, as the loop count LC increases, the program voltage can increase by a first program offset value, and the pass voltage to be applied to the unselected word line Unsel_WL can sequentially increase by a first pass offset value.

[0112] In the first program loop where the loop count LC is 1, a first program voltage 1Vpgm can be applied to the selected word line Sel_WL, and a first pass voltage 1Vpass can be applied to the unselected word line Unsel_WL.

[0113] When the loop count LC is 2, a second program voltage 2Vpgm higher than the first program voltage 1Vpgm can be applied to the selected nth word line WLn, a second pass voltage 2Vpass higher than the first pass 1Vpass can be applied to the unselected (n±1)th word line WL(n±1), and the first pass voltage 1Vpass can be applied to the remaining unselected word lines Unsel_WL.

[0114] When the loop count LC is 3, a third program voltage 3Vpgm higher than the second program voltage 2Vpgm can be applied to the selected nth word line WLn, a third pass voltage 3Vpass higher than the second pass voltage 2Vpass can be applied to the unselected (n±1)th word line WL(n±1), the second pass voltage 2Vpass can be applied to the unselected (n±2)th word line WL(n±2), and the first pass voltage 1Vpss can be applied to the remaining unselected word lines Unsel_WL.

[0115] When the cycle count LC is 4, a fourth program voltage 4Vpgm higher than the third program voltage 3Vpgm can be applied to the selected nth word line WLn, a fourth pass voltage 4Vpass higher than the third pass voltage 3Vpass can be applied to the unselected (n±1)th word line WL(n±1), the third pass voltage 3Vpass can be applied to the unselected (n±2)th word line WL(n±2), the second pass voltage 2Vpass can be applied to the unselected (n±3)th word line WL(n±3), and the first pass voltage 1Vpss can be applied to the remaining unselected word lines Unsel_WL.

[0116] Referring to Figure 11B , the horizontal axis of the graph indicates that the cycle count LC increases to the right, and the vertical axis indicates that the voltage V increases upward.

[0117] In the program operation in the first embodiment of the present disclosure, as the cycle count LC increases, the program voltages 1Vpgm, 2Vpgm, 3Vpgm... can increase at a first slope 1DE.

[0118] When the cycle count LC reaches 2 or more, an incremental pass voltage Vpass can be applied to the (n±1)th word line WL(n±1) among the unselected word lines Unsl_WL that is closest to the selected word line Sel_wl.

[0119] When the cycle count LC reaches 3 or more, an incremental pass voltage Vpass can be applied to the unselected (n±2)th word line WL(n±2), and when the cycle count LC reaches 4 or more, an incremental pass voltage Vpass can be applied to the unselected (n±3)th word line WL(n±3).

[0120] In the first embodiment of the present disclosure, the pass voltage Vpass applied to the unselected (n±1)th word line WL(n±1) increases in proportion to the cycle count LC at a second slope 2DE, and the pass voltage Vpass applied to the remaining unselected word lines can also increase in proportion to the cycle count LC at the second slope 2DE. The second slope 2DE can be smaller than the first slope 1DE.

[0121] As described above, the pass voltage applied to the (n±1)th word line WL(n±1) adjacent to the selected word line Sel_WL can be set to be higher than the pass voltage applied to the remaining unselected word lines, thereby reducing the difference in channel voltage between the unselected word line WL(n±1) adjacent to the selected word line Sel_WL. This can suppress an increase in the threshold voltage of the unselected memory cell adjacent to the selected memory cell.

[0122] Furthermore, as the higher the loop count LC, the higher the program voltage Vpgm, an incremental pass voltage can be applied to unselected word lines with respect to the selected word line Sel_WL, thereby reducing the difference in channel voltage between unselected memory cells and thus suppressing the phenomenon of hot electron occurrence.

[0123] Figure 12A and Figure 12B is a diagram illustrating a program operation according to a second embodiment of the present disclosure.

[0124] Referring to Figure 12A , the following will describe the voltage applied to the selected word line Sel_WL and the unselected word line Unsel_WL for each loop count LC in the program operation for the selected page.

[0125] It can be assumed that the nth word line WLn is the selected word line Sel_WL, and the other word lines WL(n±1),... are the unselected word lines Unsel_WL.

[0126] In the first program loop with the loop count LC of 1, a first program voltage 1Vpgm can be applied to the selected word line Sel_WL, and a first pass voltage 1Vpass can be applied to the unselected word line Unsel_WL.

[0127] When the loop count LC is 2, a second program voltage 2Vpgm higher than the first program voltage 1Vpgm can be applied to the selected nth word line WLn, a pass voltage 1Vpass+Δa higher than the first pass voltage 1Vpass by Δa can be applied to the unselected (n±1)th word line WL(n±1), and the first pass voltage 1Vpass can be applied to the remaining unselected word lines Unsel_WL. Here, "a" can be a positive integer.

[0128] When the loop count LC is 3, a third program voltage 3Vpgm higher than the second program voltage 2Vpgm can be applied to the selected nth word line WLn, a pass voltage 1Vpass+Δ2a higher than the first pass voltage 1Vpass by Δ2a can be applied to the unselected (n±1)th word line WL(n±1), a pass voltage 1Vpass+Δb higher than the first pass voltage 1Vpass by Δb can be applied to the unselected (n±2)th word line WL(n±2), and the first pass voltage 1Vpss can be applied to the remaining unselected word lines Unsel_WL. Here, "b" can be a positive integer smaller than "a".

[0129] When the loop count LC is 4, a fourth program voltage 4Vpgm higher than the third program voltage 3Vpgm can be applied to the selected nth word line WLn, a pass voltage 1Vpass+Δ3a higher than the first pass voltage 1Vpass by Δ3a can be applied to the unselected (n±1)th word line WL(n±1), a pass voltage 1Vpass+Δ2b higher than the first pass voltage 1Vpass by Δ2b can be applied to the unselected (n±2)th word line WL(n±2), a pass voltage 1Vpass+Δb higher than the first pass voltage 1Vpass by Δb can be applied to the unselected (n±3)th word line WL(n±3), and the first pass voltage 1Vpss can be applied to the remaining unselected word lines Unsel_WL. In this way, as the loop count LC increases, an increasing pass voltage can be applied to the unselected word lines further away from the selected word line Sel_WL.

[0130] Referring to Figure 12B , the horizontal axis of the graph represents the loop count LC increasing to the right, and the vertical axis represents the voltage V increasing upwards.

[0131] In the program operation in the second embodiment of the disclosure, as the loop count LC increases, an increasing portion of the pass voltage applied to the (n±1)th word line WL(n±1) adjacent to the selected word line Sel_WL can be greater than an increasing portion of the pass voltage applied to the remaining unselected word lines. For example, when the pass voltage applied to the (n±1)th word line WL(n±1) increases at a second slope 2DE, the pass voltage applied to the remaining unselected word lines can increase at a third slope 3DE, which is less than the second slope 2DE. The pass voltage applied to the (n±1)th word line WL(n±1) adjacent to the selected word line Sel_WL is set to be higher than the pass voltage applied to the remaining unselected word lines, thereby reducing the difference in channel voltage between the unselected word line WL(n±1) adjacent to the selected word line Sel_WL. Having a high slope means having a large offset value, which means the more the loop count LC increases, the higher the voltage becomes.

[0132] This can suppress an increase in threshold voltage of the unselected memory cell adjacent to the selected memory cell.

[0133] Figure 13A and Figure 13B is a graph illustrating a program operation according to a third embodiment of the disclosure.

[0134] Referring to Figure 13AThe following will describe voltages applied to the selected word line Sel_WL and the unselected word lines Unsel_WL for each loop count LC in the programming operation for the selected page.

[0135] Assume that the nth word line WLn is the selected word line Sel_WL, and the other word lines WL(n±1),... are the unselected word lines Unsel_WL.

[0136] In the first programming loop with the loop count LC being 1, a first programming voltage 1Vpgm can be applied to the selected word line Sel_WL, and a first pass voltage 1Vpass can be applied to the unselected word lines Unsel_WL.

[0137] When the loop count LC is 2, a second programming voltage 2Vpgm higher than the first programming voltage 1Vpgm can be applied to the selected nth word line WLn, a pass voltage 1Vpass+Da higher than the first pass voltage 1Vpass by Da can be applied to the unselected (n±1)th word line WL(n±1), and the first pass voltage 1Vpass can be applied to the remaining unselected word lines Unsel_WL. Here, a can be a positive integer.

[0138] When the loop count LC is 3, a third programming voltage 3Vpgm higher than the second programming voltage 2Vpgm can be applied to the selected nth word line WLn, a pass voltage 1Vpass+Da2 higher than the first pass voltage 1Vpass by Da2 can be applied to the unselected (n±1)th word line WL(n±1), a pass voltage 1Vpass+Db higher than the first pass voltage 1Vpass by Db can be applied to the unselected (n±2)th word line WL(n±2), and the first pass voltage 1Vpass can be applied to the remaining unselected word lines Unsel_WL. Here, “b” can be a positive integer smaller than “a”.

[0139] When the loop count LC is 4, a fourth program voltage 4Vpgm higher than the third program voltage 3Vpgm can be applied to the selected nth word line WLn, a pass voltage 1Vpass+Δ3a higher than the first pass voltage 1Vpass by Δ3a can be applied to the unselected (n±1)th word line WL(n±1), a pass voltage 1Vpass+Δ2b higher than the first pass voltage 1Vpass by Δ2b can be applied to the unselected (n±2)th word line WL(n±2), a pass voltage 1Vpass+Δc higher than the first pass voltage 1Vpass by Δc can be applied to the unselected (n±3)th word line WL(n±3), and the first pass voltage 1Vpass can be applied to the remaining unselected word lines Unsel_WL. In this way, as the loop count LC increases, an increasing pass voltage can be sequentially applied to the unselected word lines farther away from the selected word line Sel_WL. Here, “a”, “b”, and “c” are positive integers, b is smaller than “a”, and “c” is smaller than “b”. In this way, the farther away from the word line Sel_WL, the lower the increasing portion of the pass voltage to be applied to the selected word line.

[0140] Reference Figure 13B , the horizontal axis of the graph indicates the loop count LC increasing to the right, and the vertical axis indicates the voltage V increasing upward.

[0141] In the programming operation in the third embodiment of the present disclosure, as the loop count LC increases, the pass voltage applied to the unselected word lines increases, but the farther away from the selected word line Sel_WL, the unselected word line can have a decreasing portion of the pass voltage. For example, when the pass voltage applied to the (n±1)th word line WL(n±1) increases at a second slope 2DE, the pass voltage applied to the (n±2)th word line WL(n±2) can increase at a third slope 3DE, which is lower than the second slope 2DE, and the pass voltage applied to the (n±3)th word line WL(n±3) can increase at a fourth slope 3DE, which is lower than the third slope 3DE.

[0142] The pass voltage applied to the (n±1)th word line WL(n±1) adjacent to the selected word line Sel_WL can be set to be higher than the pass voltage applied to the remaining unselected word lines, thereby reducing the difference in channel voltage between the unselected word line WL(n±1) adjacent to the selected word line Sel_WL. This can suppress the threshold voltage increase of the unselected memory cell adjacent to the selected memory cell.

[0143] Figure 14 and Figure 15 is a graph illustrating a programming operation according to the fourth embodiment of the present disclosure.

[0144] Reference Figure 14 Embodiments of the present disclosure can also be applied to a memory device MD having a multi-plane structure. Figure 14 The illustrated memory device MD has the same parts as the memory device MD illustrated in Figure 2 The illustrated memory device MD has the same parts as the memory device MD illustrated in Figure 2 and thus the description will now be focused on parts different from the memory device MD illustrated in

[0145] A memory device MD having a multi-plane structure can include a plurality of planes PL1 to PL4 each having a plurality of memory blocks BLK1 to BLKi. For example, the memory device MD can include first to fourth planes PL1 to PL4. The first to fourth planes PL1 to PL4 can be coupled to different row decoders 130a to 130d and page buffer groups 140a to 140d, respectively. The first plane PL1 can be coupled to the first row decoder 130a and the first page buffer group 140a, the second plane PL2 can be coupled to the second row decoder 130b and the second page buffer group 140b, the third plane PL3 can be coupled to the third row decoder 130c and the third page buffer group 140c, and the fourth plane PL4 can be coupled to the fourth row decoder 130d and the fourth page buffer group 140d.

[0146] The first operating voltage Vopl output from the first voltage generator 120a can be transmitted to the first decoder 130a and the second decoder 130b, and the second operating voltage Vop2 output from the second voltage generator 120b can be transmitted to the third decoder 130c and the fourth decoder 130d. The first to fourth page buffers 140a to 140d can operate simultaneously in response to a page buffer control signal PBSIG output from the logic circuit 160.

[0147] In the memory device MD having a multi-plane structure, the distances at which the operating voltages Vopl and Vop2 are to be transmitted to the first to fourth planes PL1 to PL4 are longer than in the single-plane structure, and thus there can be different electrical characteristics compared to the single-plane structure illustrated in Figure 2 Thus, in the fourth embodiment of the present disclosure, the offset of the pass voltage applied to the unselected word line can be adjusted by further taking into account information related to the number of selected planes.

[0148] Reference Figure 15In the memory device MD having a multi-plane structure, the offset table 210 can include the program offset values 1PGM_OFS1 to 4, 2PGM_OFS1 to 4, 3PGM_OFS1 to 4, and 4PGM_OFS1 to 4 separated by the number of planes, and the pass offset values 1PASS_OFS1 to 4, 2PASS_OFS1 to 4, 3PASS_OFS1 to 4, and 4PASS_OFS1 to 4. For example, when one plane PL(1) is included in the memory device MD, one of the first program offset values 1PGM_OFS1 to 4 and one or more of the first pass offset values 1PASS_OFS1 to 4 can be used.

[0149] Figure 16 and Figure 17 is a diagram illustrating a program operation according to the fifth embodiment of the present disclosure.

[0150] Referring to Figure 16 , the memory device MD in the fifth embodiment of the present disclosure has a similar structure to the memory device MD as shown in Figure 2 , and thus overlapping parts can not be described.

[0151] Figure 16 The memory device MD of

[0152] Referring to Figure 17 , in the memory device MD having the temperature sensor 300, the offset table 210 can include the program offset values 1PGM_OFS1 to 4, 2PGM_OFS1 to 4, 3PGM_OFS1 to 4, and 4PGM_OFS1 to 4 separated by temperature, and the pass offset values 1PASS_OFS1 to 4, 2PASS_OFS1 to 4, 3PASS_OFS1 to 4, and 4PASS_OFS1 to 4. For example, when the temperature in the memory device MD belongs to the first temperature range 1C-2C, one of the first program offset values 1PGM_OFS1 to 4 and one or more of the first pass offset values 1PASS_OFS1 to 4 can be used.

[0153] The aforementioned first to fifth embodiments of the present disclosure can be used individually or in combination.

[0154] Figure 18 is a diagram illustrating a memory card system to which a memory device according to one embodiment of the present disclosure is applied.

[0155] Referring to Figure 18 , the memory card system 2000 can include a memory controller 2100, a memory device 2200, and a connector 2300.

[0156] The memory controller 2100 can be coupled to the memory device 2200. The memory controller 2100 can access the memory device 2200. For example, the memory controller 2100 can control programming, reading, or erasing operations of the memory device 2200, or can control background operations of the memory device 2200. The memory controller 2100 can provide an interface between the memory device 2200 and a host. The memory controller 2100 can run firmware that controls the memory device 2200. The memory device 2200 can operate in the same manner as the memory device MD described above with reference to Figure 2 、 Figure 14 and Figure 16 .

[0157] The memory controller 2100 can communicate with an external device by means of the connector 2300. The memory controller 2100 can communicate with an external device (e.g., a host) based on a specific communication protocol. In one embodiment, the memory controller 2100 can communicate with an external device by means of at least one of various interface protocols, such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), a PCI-express (PCI-E), an advanced technology attachment (ATA) protocol, a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a firewire, a universal flash storage (UFS), WIFI, Bluetooth, and a non-volatile memory express (NVMe) protocol. In one embodiment, the connector 2300 can be defined by at least one of the various communication protocols described above.

[0158] In one embodiment, the memory device 2200 can be implemented as any one of various non-volatile memory devices, such as an electrically erasable programmable ROM (EEPROM), a NAND flash, a NOR flash, a phase-change RAM (PRAM), a resistive RAM (ReRAM), a ferroelectric RAM (FRAM), and a spin-transfer torque magnetic RAM (STT-MRAM).

[0159] The memory controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and the memory device 2200 can be integrated into a single semiconductor device to form a memory card such as a Personal Computer Memory Card International Association (PCMCIA), a CompactFlash card (CF), a Smart Media card (SM or SMC), a Memory Stick MultiMediaCard (MMC, RS-MMC, MMCmicro, or eMMC), an SD card (SD, miniSD, microSD, or SDHC), a Universal Flash Storage (UFS), etc.

[0160] Figure 19 is a diagram illustrating a solid state drive (SSD) system to which a memory device according to the disclosure is applied.

[0161] Referring to Figure 19 , the SSD system 3000 can include a host 3100 and an SSD 3200. The SSD 3200 can exchange signals with the host 3100 by means of a signal connector 3001, and can receive a power voltage by means of a power connector 3002. The SSD 3200 can include an SSD controller 3210, a plurality of flash memories 3221 through 322N, an auxiliary power supply 3230, and a buffer memory 3240.

[0162] According to one embodiment of the disclosure, the flash memories 3221 through 322n can be configured in the same manner as the memory device MD described above with reference to Figure 2 , Figure 14 and Figure 16 .

[0163] The SSD controller 3210 can control the plurality of flash memories 3221 through 322n in response to a signal received from the host 3100. In one embodiment, the signal can be a signal based on an interface of the host 3100 and the SSD 3200. For example, such a signal can be a signal defined by at least one of various interfaces such as a Universal Serial Bus (USB), a Multimedia Card (MMC), an Embedded MMC (eMMC), a Peripheral Component Interconnect (PCI), a PCI-express (PCI-E), an Advanced Technology Attachment (ATA), a Serial ATA (SATA), a Parallel ATA (PATA), a Small Computer System Interface (SCSI), an Enhanced Small Disk Interface (ESDI), an Integrated Drive Electronics (IDE), a firewire, a Universal Flash Storage (UFS), WIFI, Bluetooth, and a Non-Volatile Memory Express (NVMe) interface.

[0164] The auxiliary power supply 3230 can be coupled to the host 3100 by means of the power connector 3002. The auxiliary power supply 3230 can be powered from the host 3100 and can be charged. The auxiliary power supply 3230 can provide power for the SSD 3200 when the power supply from the host 3100 does not perform smoothly. In one embodiment, the auxiliary power supply 3230 can be located inside the SSD 3200 or outside the SSD 3200. For example, the auxiliary power supply 3230 can be located in a motherboard and can also provide auxiliary power to the SSD 3200.

[0165] The buffer memory 3240 can be used as a buffer memory of the SSD 3200. For example, the buffer memory 3240 can temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 through 322n, or can temporarily store metadata (e.g., a mapping table) of the plurality of flash memories 3221 through 322n. The buffer memory 3240 can include a volatile memory such as DRAM, SDRAM, DDR SDRAM, and LPDDR SDRAM or a non-volatile memory such as FRAM, RERAM, STT-MRAM, and PRAM.

[0166] The present disclosure can enhance the reliability of a memory device capable of performing a programming operation.

Claims

1. A memory device, comprising: A voltage code controller generates a voltage code based on the number of times a programming loop is executed, the voltage code generating a programming voltage and a pass voltage; as well as A voltage generator, in response to the voltage code, generates the programming voltage and the pass voltage, transmits the programming voltage to the selected word line, and transmits the pass voltage to the unselected word line. As the number of times the programming loop is executed increases, the voltage generator sequentially increases the through voltage applied to the unselected word lines in order of proximity to the selected word lines.

2. The memory device according to claim 1, wherein the voltage code controller comprises: An offset table has multiple different programming offset values ​​and multiple different pass offset values, wherein the multiple different programming offset values ​​are used to gradually increase the programming voltage, and the multiple different pass offset values ​​are used to gradually increase the pass voltage; A loop counter outputs a loop count by counting the number of times a programmed loop is executed. A code generator, in response to the loop count, receives the programming offset value and the pass offset value selected from the offset table, and outputs the voltage code based on the programming offset value and the pass offset value; as well as The word line address manager outputs the addresses of the selected word lines and the unselected word lines.

3. The memory device of claim 2, wherein the programming offset value selected from the offset table and the pass offset value are preset based on the characteristics of the memory device.

4. The memory device of claim 2, wherein when a verification operation performed in a programming loop is determined to have failed, the loop counter is incremented and the loop count is output; and when the verification operation is determined to have passed, the loop count is reset.

5. The memory device of claim 4, wherein when the cycle count is reset, the word line address manager changes the address of the selected word line.

6. The memory device of claim 2, wherein the code generator: In response to the cycle count, a programming voltage code for generating the programming voltage and a pass voltage code for generating the pass voltage are generated. Based on the programming offset value and the pass offset value, a programming offset code and a pass offset code are generated, and The output is the voltage code having the programmed voltage code, the pass voltage code, the programmed offset code, and the pass offset code.

7. The memory device of claim 1, wherein the voltage generator comprises: A programming voltage generator produces the first programming voltage. A first level changer receives the first programming voltage and outputs the programming voltage by changing the level of the first programming voltage based on a programming offset value. The first through voltage is generated by a voltage generator; A second level changer receives the first pass voltage and outputs a pass voltage with a different level by changing the level of the first pass voltage based on a pass offset value; as well as a voltage distributor to transmit the program voltage and the pass voltage to respective word lines based on a word line address.

8. The memory device of claim 7, wherein the program voltage generator generates the first program voltage in response to a program voltage code output from the voltage code controller.

9. The memory device of claim 7, wherein the first level modifier generates a program voltage higher than the first program voltage in response to a loop count and a program offset code output from the voltage code controller.

10. The memory device of claim 7, wherein the pass voltage generator generates the first pass voltage in response to a pass voltage code output from the voltage code controller.

11. The memory device of claim 7, wherein the second level modifier generates a pass voltage higher than the first pass voltage in response to a loop count and a pass offset code output from the voltage code controller.

12. The memory device of claim 7, wherein the voltage distributor transmits the program voltage to the selected word line and transmits the pass voltage to the unselected word lines in order of proximity to the selected word line in response to the word line address.

13. A method of operating a memory device, comprising: setting a first step voltage for increasing a program voltage and a second step voltage for increasing a pass voltage; performing a program loop with an operation to apply the program voltage to a selected word line and a verify operation to verify memory cells coupled to the selected word line; increasing the program voltage by the first step voltage as a number of times the program loop is performed increases; and increasing the pass voltage applied to unselected word lines by the second step voltage in order of proximity to the selected word line as the number of times the program loop is performed increases.

14. The method of claim 13, wherein increasing the pass voltage by the second step voltage comprises: in a first program loop, applying a first pass voltage to the unselected word lines; in a second program loop, applying a second pass voltage higher than the first pass voltage based on the second step voltage to a first unselected word line adjacent to the selected word line and applying the first pass voltage to the remaining unselected word lines; and in a third program loop, applying a third pass voltage higher than the second pass voltage by the second step voltage to the first unselected word line, applying the second pass voltage higher than the first pass voltage by the second step voltage to a second unselected word line adjacent to the first unselected word line, and applying the first pass voltage to the remaining unselected word lines.

15. The method of claim 13, wherein the second step voltage is set lower than the first step voltage.

16. A method of operating a memory device, comprising: ​ increasing the pass voltage applied to unselected word lines adjacent to the selected word line as the number of program cycles performed increases; and increasing the number of unselected word lines to which the pass voltage is applied as the number of program cycles performed increases.

17. The method of claim 16, wherein the pass voltage that is increased stepwise is applied to the unselected word lines in order of proximity to the selected word line as the number of program cycles performed increases.

18. The method of claim 17, wherein the pass voltage applied to the unselected word line closest to the selected word line is increased stepwise by a first step voltage, and wherein the pass voltage applied to the remaining unselected word lines is increased stepwise by a second step voltage that is lower than the first step voltage.

19. The method of claim 17, wherein the pass voltage applied to the unselected word line closest to the selected word line is increased stepwise by a first step voltage, and wherein the pass voltage applied to the remaining unselected word lines is increased stepwise by a second step voltage that is lower as the unselected word line is farther from the selected word line. ​ ​

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