Package and method of forming the same

Abstract

The method includes: attaching interconnect structures to a carrier substrate, wherein each interconnect structure includes: a redistribution structure; a first sealant located on the redistribution structure; and a via extending through the sealant for physical and electrical connection to the redistribution structure; depositing a second sealant on the interconnect structure, wherein adjacent interconnect structures are laterally separated by the second sealant; after depositing the second sealant, attaching a first core substrate to the redistribution structure of at least one interconnect structure, wherein the core substrate is electrically connected to the redistribution structure; and attaching a semiconductor device to the interconnect structure, wherein the semiconductor device is electrically connected to the via of the interconnect structure. Embodiments of this application also relate to packages and methods of forming the same.

Description

Technical Field

[0001] Embodiments of this application relate to packages and methods of forming the same. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, improvements in integration density come from iterative reductions in the smallest component size, allowing more components to be integrated into a given area. With the growing demand for miniaturized electronics, there has been a need for smaller and more innovative semiconductor die packaging technologies. An example of such packaging systems is stacked package (PoP) technology. In PoP devices, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology typically allows for the production of semiconductor devices with enhanced functionality and small coverage areas on printed circuit boards (PCBs). Summary of the Invention

[0003] Some embodiments of this application provide a method for forming a package, comprising: attaching a plurality of interconnect structures to a carrier substrate, wherein each interconnect structure of the plurality of interconnect structures includes: a redistribution structure; a first sealant located on the redistribution structure; and a via extending through the sealant to be physically and electrically connected to the redistribution structure; depositing a second sealant on the plurality of interconnect structures, wherein adjacent interconnect structures of the plurality of interconnect structures are laterally separated by the second sealant; after depositing the second sealant, attaching a first core substrate to the redistribution structure of at least one of the plurality of interconnect structures, wherein the core substrate is electrically connected to the redistribution structure; and attaching a plurality of semiconductor devices to the plurality of interconnect structures, wherein the plurality of semiconductor devices are electrically connected to the vias of the plurality of interconnect structures.

[0004] Other embodiments of this application provide a method for forming a package, comprising: forming a first interconnect structure, including: forming a first via on a first carrier; depositing a first molding material over the first via; forming a redistribution structure on a first side of the first via and the first molding material, wherein the redistribution structure is electrically connected to the first via; and forming a second via on a second side of the first via and the first molding material opposite to the first side, wherein the second via is electrically connected to the first via; forming a connection structure, including: placing the first interconnect structure and a second interconnect structure on a second carrier, and depositing a second molding material between the first interconnect structure and the second interconnect structure; connecting a first core substrate to the connection structure, wherein the first core substrate is connected to the redistribution structure of the first interconnect structure; and connecting a first semiconductor device to the connection structure, wherein the first semiconductor device is connected to the second via of the first interconnect structure.

[0005] Further embodiments of this application provide a package comprising: a substrate electrically connected to a respective first side of an interconnect structure of a plurality of interconnect structures, wherein each interconnect structure of the plurality of interconnect structures is at least partially surrounded by a sealant, wherein each interconnect structure of the plurality of interconnect structures comprises: a redistribution structure; a via located on the redistribution structure; and an integrated device; and a plurality of semiconductor devices electrically connected to a respective second side of an interconnect structure of the plurality of interconnect structures, wherein the second side is opposite to the first side. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0007] Figure 1 A cross-sectional view of an interconnect component according to some embodiments is shown.

[0008] Figures 2 to 9 A cross-sectional view is shown during an intermediate step in a process for forming interconnect components, according to some embodiments.

[0009] Figures 10 to 16 A cross-sectional view is shown during an intermediate step in a process for forming a package having multiple interconnect components, according to some embodiments.

[0010] Figures 17 to 21 A cross-sectional view is shown during an intermediate step in a process for forming a package having multiple interconnect components and multiple core substrates, according to some embodiments.

[0011] Figure 22 A cross-sectional view of an interconnect component according to some embodiments is shown.

[0012] Figures 23 to 28 A cross-sectional view is shown during an intermediate step in a process for forming a package having multiple interconnect components, according to some embodiments.

[0013] Figure 29 A cross-sectional view of a package having multiple interconnect components according to some embodiments is shown.

[0014] Figure 30 A cross-sectional view of a package having multiple interconnect components and multiple core substrates according to some embodiments is shown.

[0015] Figures 31 to 39 A cross-sectional view is shown during an intermediate step in a process for forming a package having multiple interconnect components, according to some embodiments.

[0016] Figure 40A , Figure 40B , Figure 40C and Figure 40D A plan view is shown of an intermediate step in the formation of a package according to some embodiments.

[0017] Figure 41A and Figure 41B A plan view is shown of an intermediate step in the formation of a package according to some embodiments.

[0018] Figure 42A and Figure 42B A plan view is shown of an intermediate step in the formation of a package according to some embodiments. Detailed Implementation

[0019] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0020] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0021] The embodiments discussed herein can be discussed in the specific context of a package having one or more interconnect structures. In some embodiments, the package is a system-on-integrated substrate (SoIS) package, etc. The package includes two or more interconnect components attached to one or more core substrates. The interconnect components may include electrical wiring, vias, integrated devices such as IPDs or local wiring structures, etc. Semiconductor devices may be attached to two or more interconnect components. In some cases, by using multiple interconnect components as described herein, yield can be improved and the number of cells per wafer can be increased. For example, the interconnect structure may have a relatively small size that allows more interconnect structures to be formed on a single wafer. Furthermore, forming multiple interconnects allows known good interconnect structures to be tested prior to use within the package manufacturing process. In this way, the cost of forming the package can be reduced. Different types of interconnect structures can be used within the same package, which can allow for design flexibility and improved performance.

[0022] Figure 1 A cross-sectional view of an interconnect component 50 according to some embodiments is shown. The interconnect component 50 may be incorporated into an interconnect structure, such as those described below. Figure 9 The described interconnect structure 100. In some embodiments, the interconnect component 50 is used to form local interconnects within the package, such as... Figure 16 The package 200 shown herein or other packages described herein. In some cases, the interconnect component 50 may be considered an integrated device or a local wiring structure.

[0023] Interconnect components 50 can be formed in a wafer, which may include different device regions that are diced in subsequent steps to form multiple interconnect components 50. Interconnect components 50 can be processed according to applicable manufacturing processes, such as those used to form dies or semiconductor devices. For example, interconnect components 50 may include a substrate 52, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. Substrate 52 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; etc.; or combinations thereof. In some embodiments, substrate 52 may include ceramic materials, polymer films, magnetic materials, etc., or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, substrate 52 has an active surface (e.g., Figure 1 The surface facing upwards (sometimes called the front side), and non-active surfaces (e.g., Figure 1 The surface facing downwards (the middle side), sometimes referred to as the dorsal side.

[0024] In some embodiments, interconnect component 50 may include active or passive devices. In some embodiments, interconnect component 50 may not have active or passive devices and may be used solely for wiring electrical signals. In embodiments including active or passive devices, device 54 (made of...) can be formed on the front side of substrate 52. Figure 1 (Transistor representation in the image). Device 54 may include active devices (e.g., transistors, diodes, etc.), capacitors, resistors, inductors, etc., or combinations thereof. An interlayer dielectric (ILD) 56 is located above the front side of substrate 52. ILD 56 surrounds and may cover device 54. ILD 56 may include one or more dielectric layers formed of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0025] Conductive plug 58 extends through ILD 56 to electrically and physically couple device 54. For example, when device 54 is a transistor, conductive plug 58 may couple the gate and source / drain regions of the transistor. Conductive plug 58 may be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, or combinations thereof. Interconnect structure 60 is located above ILD 56 and conductive plug 58. Interconnect structure 60 interconnects device 54 and / or provides electrical wiring and connections between die connector 66. Interconnect structure 60 may include, for example, a metallization pattern in a dielectric layer on ILD 56. The metallization pattern may include wires and conductive vias formed in one or more low-k dielectric layers. The metallization pattern may be formed using a suitable process, such as a damascene process. In embodiments including device 54, the metallization pattern of interconnect structure 60 is electrically coupled to device 54 via conductive plug 58. Although interconnect structure 60 is shown as having only two layers of conductive vias and two layers of wires, in other embodiments, it may include more or fewer layers of conductive vias or wires.

[0026] Interconnect component 50 also includes pads 62, such as aluminum pads, formed to external connections. Pads 62 are located on the active side of interconnect component 50, such as within and / or on interconnect structure 60. One or more passivation films 64 are located on interconnect component 50, such as on portions of interconnect structure 60 and pads 62. Openings extend through passivation films 64 to pads 62. Die connectors 66, such as conductive pillars (e.g., formed of a metal such as copper), extend through openings in passivation films 64 and are physically and electrically coupled to corresponding pads 62. Die connectors 66 can be formed, for example, by plating. Die connectors 66 are electrically coupled to corresponding integrated circuits of interconnect component 50.

[0027] Optionally, solder areas (e.g., solder balls or solder bumps) can be provided on pad 62. Solder balls can be used to perform chip probe (CP) testing on interconnect components 50. CP testing can be performed on interconnect components 50 to determine if interconnect components 50 are known good dies (KGD). Therefore, only KGD interconnect components 50 that undergo subsequent processing are packaged, while interconnect components 50 that fail the CP test are not packaged. After testing, the solder areas can be removed in subsequent processing steps.

[0028] In other embodiments, a dielectric layer may be formed on the active side of the interconnect component 50, such as on the passivation film 64 and the die connector 66. Figure 1The embodiments shown do not include the dielectric layer. The dielectric layer may laterally seal the die connector 66. The dielectric layer may be: a polymer, such as PBO, polyimide, BCB, etc.; a nitride, such as silicon nitride, etc.; an oxide, such as silicon oxide, PSG, BSG, BPSG, etc.; or combinations thereof. For example, the dielectric layer may be formed by spin coating, lamination, chemical vapor deposition (CVD), etc. In some embodiments, the die connector 66 is exposed through the dielectric layer during the formation of the interconnect assembly 50. In some embodiments, the die connector 66 remains buried and is exposed during subsequent processes for packaging the interconnect assembly 50. Exposing the die connector 66 may remove any solder areas that may be present on the die connector 66.

[0029] Figures 2 to 9 The diagram illustrates an example of a method for forming an interconnect structure 100 according to some embodiments (see...). Figure 9 A cross-sectional view of an intermediate step during the process of [the technology]. Interconnect structure 100 includes one or more interconnect components 50 (see [the diagram]). Figure 1 ) and / or one or more integrated passive devices (IPDs) 80 (see Figure 5 ).exist Figures 2 to 8 The diagram illustrates a first region 101A and a second region 101B, and an interconnect structure 100 can be formed in each of regions 101A and 101B. A partitioning process can be implemented to partition the individual interconnect structures 100, such as... Figure 9 As shown in the image.

[0030] exist Figure 2 In this embodiment, a first carrier substrate 102 is provided, and a release layer 104 is formed on the first carrier substrate 102. The first carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, etc. The first carrier substrate 102 may be a wafer, thereby allowing multiple packages to be formed simultaneously on the first carrier substrate 102. The release layer 104 may be formed of a polymer-based material, which may be removed from the above structure along with the first carrier substrate 102 in subsequent steps. In some embodiments, the release layer 104 is a thermally release epoxy resin-based material that loses its adhesiveness upon heating, such as a photothermal conversion (LTHC) release coating. In other embodiments, the release layer 104 may be a UV adhesive that loses its adhesiveness upon exposure to UV light. The release layer 104 may be dispensed and cured as a liquid, and may be a laminated film laminated onto the first carrier substrate 102, or the like. The top surface of the release layer 104 may be flush and may have a high degree of planarity.

[0031] exist Figure 3 In this process, a wire 110 is formed on the release layer 104. The wire 110 can then be exposed via a carrier stripping process (see...). Figure 8As an example of forming the conductive line 110, a seed layer (not shown) is formed above the release layer 104. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer comprising multiple sublayers formed of different materials. The seed layer can be, for example, a titanium layer and a copper layer located above the titanium layer. The seed layer can be formed using, for example, physical vapor deposition (PVD). Photoresist is then formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. Patterning forms openings through the photoresist to expose the seed layer, wherein the openings in the photoresist correspond to the conductive line 110. A conductive material is then formed in the openings of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating (such as electroplating or electroless plating). The conductive material can include metals such as copper, titanium, tungsten, aluminum, etc. The combination of the conductive material and the lower portion of the seed layer forms the conductive line 110. The portions of the photoresist and the seed layer on which the conductive material is not formed are removed. Photoresist can be removed using acceptable ashing or stripping processes, such as using oxygen plasma. Once the photoresist is removed, the exposed portion of the seed layer is removed, for example by using acceptable etching processes, such as wet etching or dry etching.

[0032] exist Figure 4 In some embodiments, a via 116 is formed on the conductor 110. As an example of forming the via 116, a seed layer (not shown) is formed over the conductor 110 and the release layer 104. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer comprising multiple sublayers formed of different materials. In a particular embodiment, the seed layer includes a titanium layer and a copper layer located above the titanium layer. The seed layer can be formed using, for example, PVD. A photoresist is formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to the via 116. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating (such as electroplating or electroless plating). The conductive material can include metals such as copper, titanium, tungsten, aluminum, etc. The portions of the photoresist and seed layer on which no conductive material is formed are removed. The photoresist can be removed using an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist is removed, the exposed portion of the seed layer is removed, for example by using an acceptable etching process, such as wet etching or dry etching. The remaining portion of the seed layer and conductive material forms the via 116. In other embodiments, a seed layer is not used.

[0033] exist Figure 5 In some embodiments, interconnect components 50 and / or integrated passive devices 80 (IPDs) are attached to wires 110. Figure 5An interconnect component 50 and an IPD 80 attached within each region 101A-101B are shown, but in other embodiments, more or fewer interconnect components 50 or IPD 80 may be attached within each region 101A-101B. The interconnect component 50 may be similar to that used for... Figure 1 Interconnect component 50 is described. IPD 80 may be a device, for example, including one or more passive devices (such as capacitors, resistors, inductors, etc.). In some embodiments, other types of components, such as integrated voltage regulators (IVRs), may be incorporated into interconnect structure 100. In this way, interconnect structure 100 may be configured to include various components, such as interconnect component 50 and / or IPD 80, which can provide desired functional and performance advantages. In some cases, incorporating interconnect component 50 or IPD 80 into interconnect structure 100 may reduce the chance of connector failure of interconnect component 50 or IPD 80 compared to attaching interconnect component 50 and / or IPD 80 to other parts of the package.

[0034] In some embodiments, interconnect components 50 or IPD 80 may be attached using conductive connectors 114. Conductive connectors 114 may be, for example, ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed using electroless nickel-palladium immersion gold (ENEPIG) technology, etc. Conductive connectors 114 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, conductive connectors 114 are initially formed by evaporation, electroplating, printing, solder transfer, ball placement, etc., to form a solder layer. Once the solder layer has been structurally formed, reflow may be performed to shape the material into the desired bump shape. Conductive connectors 114 may be formed on die connectors 66 of interconnect components 50, die connectors of IPD 80, and / or conductors 110.

[0035] In one embodiment, interconnect components 50 and IPD 80 are positioned to physically contact wire 110 using, for example, pick-and-place processes. Interconnect components 50 and IPD 80 may be positioned such that areas of wire 110 are aligned with corresponding conductive connectors 114 of interconnect components 50 and IPD 80. In some embodiments, once the conductive connectors 114 are in physical contact with wire 110, a reflow process may be performed to bond the conductive connectors 114 to wire 110 and thus attach interconnect components 50 and IPD 80 to wire 110. In other embodiments, other bonding techniques, such as direct bonding, hybrid bonding, etc., may be used to attach interconnect components 50 and IPD 80 to wire 110.

[0036] exist Figure 6In this process, a sealant 118 is formed on and around the various components. The sealant 118 seals the through-hole 116, the interconnect component 50, and the IPD 80. The sealant 118 can be a molding compound, epoxy resin, etc. The sealant 118 can be applied by compression molding, transfer molding, etc., and can be formed over the first carrier substrate 102, thereby burying or covering the through-hole 116, the interconnect component 50, and / or the IPD 80. The sealant 118 can be applied in liquid or semi-liquid form and then subsequently cured.

[0037] In some embodiments, an underfill 117 is formed prior to sealing with sealant 118. The underfill 117 may surround the conductive connector 114 of the interconnect assembly 50 or IPD 80. The underfill 117 may reduce stress and protect the joints created by backflow of the conductive connector 114. The underfill 117 may be formed by a capillary process after the interconnect assembly 50 or IPD 80 is attached, and may be formed by a suitable deposition method. In some embodiments, a single layer of underfill 117 is formed beneath a plurality of adjacent devices.

[0038] In some embodiments, a planarization process is performed on the sealant 118 to expose the via 116. In some embodiments, the surfaces of one or more interconnect components 50 or IPD 80 are also exposed by a planarization process. The planarization process may also remove material from the via 116. After the planarization process, the top surfaces of the via 116 and the sealant 118 are substantially coplanar within a range of process variations. The planarization process may be, for example, chemical mechanical polishing (CMP), grinding, etc. In some embodiments, planarization may be omitted, for example, if the via 116 has already been exposed.

[0039] exist Figure 7 In some embodiments, a redistribution structure 120 is formed over the sealant 118 and the via 116. The redistribution structure 120 includes dielectric layers 124, 128, and 132; and metallization patterns 122, 126, 130, and 134. The metallization patterns may also be referred to as redistribution layers or redistribution lines. The redistribution structure 120 is shown as an example with four layers of metallization patterns. More or fewer dielectric layers and metallization patterns can be formed in the redistribution structure 120. If fewer dielectric layers and metallization patterns are to be formed, the steps and processes discussed below can be omitted. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed below can be repeated.

[0040] As an example of forming the redistribution structure 120, a metallization pattern 122 is formed over the sealant 118 and the via 116. The metallization pattern 122 includes conductive elements extending along the main surface of the sealant 118 and over the via 116 to be physically and electrically coupled to the via 116. As an example of forming the metallization pattern 122, a seed layer is formed over the sealant 118 and the via 116. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer located above the titanium layer. The seed layer can be formed using, for example, PVD. A photoresist is then formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 122. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. Conductive materials can be formed by plating (such as electroplating or electroless plating). Conductive materials can include metals such as copper, titanium, tungsten, aluminum, etc. The combination of the conductive material and the lower portion of the seed layer forms a metallization pattern 122. The photoresist and the portion of the seed layer above which no conductive material is formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet etching or dry etching. In other embodiments, the metallization pattern 122 is not formed on the sealant 118 and the via 116 prior to the formation of the dielectric layer 124.

[0041] A dielectric layer 124 is deposited on a sealant 118 and a metallization pattern 122. In some embodiments, the dielectric layer 124 is formed of a photosensitive material that can be patterned using a photolithographic mask, such as PBO, polyimide, BCB, etc. The dielectric layer 124 can be formed by spin coating, lamination, CVD, or combinations thereof. The dielectric layer 124 is then patterned. The patterning forms openings that expose portions of the metallization pattern 122. The patterning can be performed by acceptable processes, such as exposing the dielectric layer 124 to light and developing it when the dielectric layer 124 is a photosensitive material, or by etching, for example, anisotropic etching.

[0042] Then, a metallization pattern 126 is formed. The metallization pattern 126 includes portions located on and extending along the main surface of the dielectric layer 124. The metallization pattern 126 also includes portions extending through the dielectric layer 124 to physically and electrically couple the metallization pattern 122. The metallization pattern 126 may be formed in a similar manner to the metallization pattern 122 and from a similar material. In some embodiments, the metallization pattern 126 has different dimensions than the metallization pattern 122. For example, the conductors of the metallization pattern 126 may be wider or thicker than the conductors of the metallization pattern 122. Furthermore, the metallization pattern 126 may be formed with a larger pitch than the metallization pattern 122.

[0043] Then, a dielectric layer 128 is deposited on the metallization pattern 126 and the dielectric layer 124. The dielectric layer 128 can be formed in a manner similar to that of the dielectric layer 124, and can be formed from a material similar to that of the dielectric layer 124.

[0044] Metallization pattern 130 is then formed. Metallization pattern 130 includes portions located on and extending along the main surface of dielectric layer 128. Metallization pattern 130 also includes portions extending through dielectric layer 128 to physically and electrically couple metallization pattern 126. Metallization pattern 130 may be formed in a similar manner to metallization pattern 122 and from a similar material. In some embodiments, metallization pattern 130 has different dimensions than metallization pattern 126. For example, the conductors and / or vias of metallization pattern 130 may be wider or thicker than the conductors and / or vias of metallization pattern 126. Furthermore, metallization pattern 130 may be formed with a larger pitch than metallization pattern 126.

[0045] A dielectric layer 132 is then deposited on the metallization pattern 130 and the dielectric layer 128. The dielectric layer 132 can be formed in a manner similar to that of the dielectric layer 124 and can be formed from a material similar to that of the dielectric layer 124. The dielectric layer 132 is the topmost dielectric layer of the redistribution structure 120. For example, all intermediate dielectric layers of the redistribution structure 120 (e.g., dielectric layers 124 and 128) are disposed between the dielectric layer 132 and the sealant 118.

[0046] Metallization pattern 134 is then formed. Metallization pattern 134 includes portions located on and extending along the main surface of dielectric layer 132. Metallization pattern 134 also includes portions extending through dielectric layer 132 to physically and electrically couple metallization pattern 130. Metallization pattern 134 may be formed in a similar manner to metallization pattern 122 and from a similar material. Metallization pattern 134 is the topmost metallization pattern of redistribution structure 120. Therefore, all intermediate metallization patterns of redistribution structure 120 (e.g., metallization patterns 126 and 130) are disposed between metallization pattern 134 and sealant 118. In some embodiments, metallization pattern 134 has different dimensions than metallization patterns 122, 126, and 130. For example, the conductors and / or vias of metallization pattern 134 may be wider or thicker than the conductors and / or vias of metallization patterns 122, 126, and 130. Furthermore, the metallized pattern 134 can be formed with a larger spacing than the metallized pattern 130.

[0047] exist Figure 8 In some embodiments, a structure is peeled off and a conductive via 136 is formed. Peeling is performed to separate (or “peel off”) the first carrier substrate 102 from the structure. According to some embodiments, peeling includes projecting light, such as laser or UV light, onto a release layer 104, causing the release layer 104 to decompose under the heat of the light, and the first carrier substrate 102 can be removed. The structure is then flipped and attached to a second carrier substrate 142. The second carrier substrate 142 may be similar to the first carrier substrate 102 or may be, for example, a strip. A release layer 144 may be formed on the second carrier substrate 142 to facilitate attachment of the structure to the second carrier substrate 142. The release layer 144 may be similar to the release layer 104 or may be, for example, an adhesive layer.

[0048] According to some embodiments, after attachment to the second carrier substrate 142, a conductive via 136 can be formed on the wire 110. The conductive via 136 is electrically connected to the via 116, the interconnect component 50, and the IPD 80. In some embodiments, the conductive via 136 may include under-bump metal (UBM). As an example of forming the conductive via 136, a seed layer (not shown) is formed over the sealant 118 and the wire 110. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. The seed layer may be, for example, a titanium layer and a copper layer located above the titanium layer. The seed layer can be formed using, for example, physical vapor deposition (PVD). A photoresist is then formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The patterning forms openings through the photoresist to expose the seed layer, wherein the openings in the photoresist correspond to the conductive via 136. A conductive material is then formed in the openings of the photoresist and on the exposed portion of the seed layer. Conductive materials can be formed by plating (such as electroplating or electroless plating). Conductive materials can include metals such as copper, titanium, tungsten, and aluminum. The combination of the conductive material and the lower portion of the seed layer forms the conductive via 136. The photoresist and the portion of the seed layer above which no conductive material is formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist is removed, the exposed portion of the seed layer is removed, for example by using an acceptable etching process, such as wet etching or dry etching.

[0049] According to some embodiments, a dielectric layer 138 is formed on and around the conductive via 136. After formation, the dielectric layer 138 surrounds the conductive via 136. The dielectric layer 138 can provide electrical isolation and environmental protection. The dielectric layer 138 can be a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc.; a nitride, such as silicon nitride; an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.; a sealant, molding compound, epoxy resin, etc.; or a combination thereof. The dielectric layer 138 can be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. In some embodiments, after the dielectric layer 138 is formed, a planarization process (e.g., CMP or polishing process) can be performed to expose the conductive via 136.

[0050] In other embodiments, the dielectric layer 138 may be formed prior to the conductive via 136. In such embodiments, an opening is formed through the dielectric layer 138 to expose portions of the wire 110. For example, the opening may be formed using, for example, laser drilling, etching, etc. The conductive via 136 is then formed in the opening to make physical and electrical contact with the wire 110. In some embodiments, a planarization process (e.g., CMP or polishing process) may be performed after the conductive via 136 is formed.

[0051] exist Figure 9 In some embodiments, the structure is peeled off from the second carrier substrate 142 and divided to form individual interconnect structures 100. Figure 9 A partitioned interconnect structure 100 is illustrated according to some embodiments. The partitioning process is performed along a scribing region (e.g., in...). Figures 2 to 8 This is implemented by sawing between the first region 101A and the second packaging region 101B shown. The sawing divides the first region 101A from an adjacent region (e.g., the second region 101B) to form a plurality of segmented interconnect structures 100. Figure 9 As shown, the interconnect structure 100 may have conductive vias 136 and metallization patterns 134 that allow for subsequent electrical connection with the interconnect structure 100.

[0052] Figures 10 to 16 A package 200 comprising multiple interconnect structures 100A-100B according to some embodiments is shown (see Figure 16 The interconnection structure 100A-100B of the package 200 can be similar to the formation of the package. Figure 9 The interconnect structure 100 is shown. By using multiple interconnect structures 100 within the package 200 instead of a single, larger interconnect structure, manufacturing costs can be reduced and yield can be improved. The following section addresses... Figures 40A to 42B The advantages of using multiple interconnect structures 100 in a package are described in more detail below. The package 200 may include a different number of interconnect structures 100 than those shown, and the interconnect structures 100 within the package 200 may be similar or different.

[0053] Figure 10 The diagram illustrates the placement of interconnect structures 100A-100B on a carrier substrate 202 according to some embodiments. The carrier substrate 202 may be similar to the first carrier substrate 102 previously described. Figure 10 As shown, interconnect structures 100A-100B can be positioned such that the redistribution structure 120 of each interconnect structure 100A-100B faces the carrier substrate 202. Interconnect structures 100A-100B can be attached to the carrier substrate 202 using, for example, an adhesive layer 204. In some embodiments, the adhesive layer 204 can be similar to the release layer 104 previously described. Figure 10The placement of two interconnect structures 100A-100B is shown, but in other embodiments, more than two interconnect structures may be placed.

[0054] exist Figure 11 In some embodiments, a sealant 206 is formed on interconnect structures 100A-100B. The sealant 206 can be a molding compound, epoxy resin, etc., and can be similar to the sealant 118 previously described. The sealant 206 can be applied by compression molding, transfer molding, etc., and can be formed above the carrier substrate 202, thereby burying or covering the interconnect structures 100A-100B. The sealant 206 can be applied in liquid or semi-liquid form and then subsequently cured.

[0055] exist Figure 12 In some embodiments, a planarization process is performed to remove excess sealant 206 and form conductive interconnects 208. The planarization process removes the sealant 206, thereby exposing the conductive vias 136 and dielectric layers 138 of each interconnect structure 100A-100B. After the planarization process, the surfaces of the sealant 206 and the interconnect structures 100A-100B can be coplanar. The planarization process may include CMP processes, polishing processes, etching processes, or combinations thereof.

[0056] Still referencing Figure 12 Conductive connectors 208 are formed on conductive vias 136. Conductive connectors 208 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed by electroless nickel-palladium immersion gold (ENEPIG) technology, etc. Conductive connectors 208 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, conductive connectors 208 are initially formed by evaporation, electroplating, printing, solder transfer, ball placement, etc., to form a solder layer. Once the solder layer has been structurally formed, reflow can be performed to shape the material into the desired bump shape. In another embodiment, conductive connectors 208 include metal pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The metal pillars may be solderless and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on the top of the metal pillar. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or combinations thereof, and may be formed by a plating process.

[0057] exist Figure 13In some embodiments, the structure is peeled off from the carrier substrate 202, and conductive connectors 210 are formed on the interconnect structures 100A-100B. A previously deposited sealant 206 fixes the plurality of interconnect structures 100A-100B, forming a generally rigid structure comprising the plurality of interconnect structures 100A-100B, which may be referred to herein as a “connection structure.” The conductive connectors 210 may be formed on the metallization pattern 134 of the redistribution structure 120 of each interconnect structure 100A-100B. In some embodiments, the conductive connectors 210 comprise flux and are formed in a flux impregnation process. In some embodiments, the conductive connectors 210 comprise conductive paste such as solder paste, silver paste, etc., and are dispensed in a printing process. In some embodiments, the conductive connectors 210 are formed in a manner similar to conductive connector 208 and may be formed from a material similar to conductive connector 208.

[0058] Transfer to Figure 14 A core substrate 250 is shown according to some embodiments. The core substrate 250 is then bonded to a conductive connector 210 of the connection structure (see...). Figure 15 The core substrate 250 has the advantage of being manufactured in different processes, which allows for different testing, thus enabling the use of a known good core substrate 250. For example, in some embodiments, the core substrate 250 can be tested, verified, and / or validated individually or in batches before being bonded to the conductive connector 210. The core substrate 250 may include active and passive devices (not shown), or may have no active devices, passive devices, or both. A wide variety of devices can be used, such as transistors, capacitors, resistors, inductors, combinations thereof, etc. The devices can be formed using any suitable method.

[0059] The core substrate 250 can be processed according to applicable manufacturing processes to form a redistributed structure within it. For example, the core substrate 250 includes a core material 252. The core material 252 includes one or more layers of glass fiber, resin, filler, prepreg, epoxy resin, silica filler, Ajinomoto polymer film (ABF), polyimide, molding compound, other materials, and / or combinations thereof. The core material 252 may be formed from organic and / or inorganic materials. In some embodiments, for example, the core material 252 may include two or more layers of material. In some embodiments, the core material 252 includes one or more passive components (not shown) embedded within it. The core material 252 may include other materials or components.

[0060] A conductive via 256 is formed extending through the core material 252. In some embodiments, the conductive via 256 may include a conductive material such as copper, a copper alloy, or other conductors, and may include a barrier layer (not shown), a pad (not shown), a seed layer (not shown), and / or a filler material 251. The conductive via 256 provides a vertical electrical connection from one side of the core material 252 to the other side of the core material 252. For example, some conductive components on one side of the core material 252 and conductive components on the opposite side of the core material 252 are coupled together. In some embodiments, openings for the conductive via 256 may be formed in the core material 252 using drilling, photolithography, laser processing, or other suitable techniques. The openings for the conductive via 256 are then filled or plated with a conductive material. In some embodiments, the conductive via 256 is a hollow via having a center filled with an insulating filler material 251.

[0061] A redistribution structure 253 is formed on opposite sides of the core material 252. The redistribution structures 253 are electrically coupled via conductive vias 256. Each redistribution structure 253 includes a dielectric layer 257 (formed from ABF, prepreg, etc.) and a metallization pattern 255. Each corresponding metallization pattern 255 has a line portion located on and extending along the main surface of the corresponding dielectric layer 257, and a via portion extending through the corresponding dielectric layer 257. Each redistribution structure 253 may include under-bump metallization (UBM) 254 for external connection and solder resist 258 protecting the components of the redistribution structure 253. Each redistribution structure 253 of the core substrate 250 may have a higher density than... Figure 14 The dielectric layer 257 and metallization pattern 255 shown are more or less.

[0062] Transfer to Figure 15 According to some embodiments, the core substrate 250 is attached to the interconnect structures 100A-100B. The core substrate 250 can be similar to... Figure 14 The core substrate 250 shown. Attaching the core substrate 250 may include... Figure 13 The structure is placed on the core substrate 250, such that the conductive connector 210 physically contacts one side of the core substrate 250, UBM 254. The conductive connector 210 can then be subjected to a reflow process to physically and electrically couple the core substrate 250 and the interconnect structures 100A-100B.

[0063] In some embodiments, an underfill 212 may be formed around the conductive connector 210 between the interconnect structures 100A-100B and the core substrate 250. The underfill 212 may be formed by a capillary flow process after attaching the core substrate 250, or by a suitable deposition method before attaching the core substrate 250. The underfill 212 may be a molding compound, epoxy resin, underfill, molded underfill (MUF), resin, etc., and may be similar to the sealant 206 or sealant 118 previously described.

[0064] In some embodiments, conductive connectors 214 may be formed on the core substrate 250. For example, conductive connectors 214 may be formed on a UBM 254 of the core substrate 250. Conductive connectors 214 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed by electroless nickel-palladium-ion immersion gold (ENEPIG) technology, etc. Conductive connectors 214 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, conductive connectors 214 are initially formed by evaporation, electroplating, printing, solder transfer, ball placement, etc., to form a solder layer. Once the solder layer has been structurally formed, reflow may be performed to shape the material into the desired bump shape. In another embodiment, conductive connectors 214 include metal pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The metal pillars may be solderless and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillar. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or combinations thereof, and may be formed by a plating process.

[0065] Figure 16 The attachment of semiconductor devices 260A-260C according to some embodiments is shown to form package 200. Semiconductor devices 260A-260C are physically and electrically connected to conductive connectors 208 to form an electrical connection between semiconductor devices 260A-260C and interconnect structures 100A-100B.

[0066] Figure 16 The attachment of three semiconductor devices 260A-260C is shown, but in other embodiments, one, two, or more than three semiconductor devices 260 may be attached to the conductive connector 208. In some embodiments, the semiconductor devices 260 attached to the conductive connector 208 may include one or more semiconductor devices 260 of the same type or may include two or more semiconductor devices 260 of different types. Semiconductor devices 260A-260C may be attached in an arrangement or configuration different from that shown. For example, Figure 16A semiconductor device 260B is shown that is electrically connected to interconnect structures 100A and 100B, but in other embodiments, each semiconductor device 260 may be electrically connected to a single interconnect structure 100.

[0067] Semiconductor devices 260A-260C can be placed on conductive connectors 208 using suitable processes such as pick-and-place processes. Semiconductor devices 260A-260C can be positioned such that conductive areas of semiconductor devices 260A-260C (e.g., contact pads, conductive connectors, solder bumps, etc.) are aligned with corresponding conductive connectors 208 on interconnect structures 100A-100B. Once physical contact is established, a reflow process can be used to bond the conductive connectors 208 to the semiconductor devices 260A-260C, forming package 200. Figures 10 to 16 The process shown is a "post-chip" process, in which semiconductor devices 260A-260C are attached after the attachment core substrate 250. In other embodiments, semiconductor devices 260A-260C may be attached before the attachment core substrate 250.

[0068] like Figure 16 As shown, an underfill 215 can be deposited between semiconductor devices 260A-260C and interconnect structures 100A-100B. The underfill 215 may also at least partially surround the conductive interconnect 208. The underfill 215 may be a material such as molding compound, epoxy resin, underfill, molded underfill (MUF), resin, etc., and may be similar to the previously described underfill 117 or sealant 118. In some embodiments, the sidewalls of interconnect structure 100, the sidewalls of underfill 212, and the sidewalls of core substrate 250 may be substantially coplanar. In other embodiments, two of the sidewalls of interconnect structure 100, underfill 212, and core substrate 250 may be substantially coplanar, or no sidewalls may be substantially coplanar.

[0069] like Figure 16As shown, one or more of the semiconductor devices 260A-260C are electrically connected to the interconnect component 50 of the interconnect structure 100. In some cases, two or more semiconductor devices 260A-260C can be at least partially connected to each other through the interconnect component 50. As described herein, by forming the interconnect component 50 in a layer of the interconnect structure 100 near the semiconductor devices 260A-260C, the wiring distance of the connection between the semiconductor devices 260A-260C can be reduced, which can increase the bandwidth or speed of the electrical signals communicating between the semiconductor devices 260A-260C, improving high-speed operation. In this way, the interconnect component 50 can increase the communication bandwidth between the semiconductor devices 260A-260C while maintaining low contact resistance and high reliability. Furthermore, the greater wiring density available in the interconnect component 50 can provide more efficient wiring between the semiconductor devices 260A-260C, and in some cases, can reduce the number of metallization patterns used in the interconnect structures 100A-100B or the number of metallization patterns used in the core substrate 250. In some cases, forming an interconnect structure 100 with IPD 80 can reduce the wiring distance between the semiconductor device 260 and the IPD 80, which can improve high-speed operation.

[0070] Each of the semiconductor devices 260A-260C may include one or more integrated fan-out (InFO) structures, semiconductor packages, integrated circuit dies, such as logic dies (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-chip (SoC), component-on-wafer (CoW), application processor (AP), microcontroller, etc.), memory dies (e.g., dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, etc.), power management dies (e.g., power management integrated circuit (PMIC) dies), radio frequency (RF) dies, sensor chips, microelectromechanical systems (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end (AFE) dies), input-output (I / O) dies, etc., or combinations thereof. The integrated circuit die may include memory devices, such as hybrid memory dataset (HMC) modules, high-bandwidth memory (HBM) modules, etc., which include multiple memory dies. In some embodiments, one or more of the semiconductor devices 260A-260C may include integrated circuit devices, such as transistors, capacitors, inductors, resistors, metallization layers, external connectors, etc., as required for a specific function.

[0071] Figures 17 to 21 A package 300 comprising multiple interconnect structures 100A-100B and multiple core substrates 250A-250B according to some embodiments is shown (see Figure 21The interconnect structure 100A-100B of the package 300 can be similar to the formation of the package. Figure 9 The interconnect structures 100A-100B are shown. The core substrates 250A-250B of the package 300 can be similar to... Figure 14 The core substrate 250 shown, except that core substrates 250A-250B can have a higher density than... Figure 14 The core substrate 250 shown is relatively small in size. Therefore, the package 300 can be similar to... Figure 16 The package 200 shown uses multiple core substrates 250A-250B instead of a single core substrate 250. By using multiple core substrates 250A-250B within the package 300 instead of a single, larger core substrate 250, manufacturing costs can be reduced and yield can be improved. The package 300 may include interconnect structures 100 or core substrates 250 in different numbers or configurations as shown.

[0072] exist Figure 17 In some embodiments, a structure including multiple interconnect structures 100A-100B is shown. Figure 17 The structure shown is similar to the previous one. Figure 13 The connection structure shown, except Figure 17 The structure has been attached to the carrier 302. For example, Figure 17 The structure shown includes a plurality of interconnect structures 100A-100B fixed by a sealant 206, which may be similar to the sealant 206 previously described. Conductive connectors 208 and 210, similar to the conductive connectors 208 and 210 previously described, have been formed on the interconnect structures 100A-100B. Figure 17 The structure shown can be similar to that for Figure 13 The structure shown is formed in the manner described. The carrier 302 may be similar to the first carrier substrate 102 or may be, for example, a strip.

[0073] exist Figure 18 In some embodiments, core substrates 250A-250B are attached to interconnect structures 100A-100B. Core substrates 250A-250B can be similar to... Figure 14 The core substrate 250 is shown. The lateral dimensions of core substrates 250A-250B are shown as larger than the lateral dimensions of interconnect structures 100A-100B, but in other embodiments, core substrates 250A-250B may have one or more lateral dimensions smaller than the interconnect structures 100A / B. Attaching core substrates 250A-250B may include placing core substrates 250A-250B on... Figure 17 Structurally, this allows the conductive connector 210 to physically contact the UBM 254 of the core substrate 250A-250B. For example, Figure 18 Core substrate 250A is shown placed on interconnect structure 100A and core substrate 250B is placed on interconnect structure 100B. A reflow process can then be performed on conductive connector 210 to physically and electrically couple core substrates 250A-250B and interconnect structures 100A-100B. Figure 18 A single core substrate 250 is shown attached to each interconnect structure 100, but in other embodiments, more than one core substrate 250 may be attached to a single interconnect structure 100 or a single core substrate 250 may be attached to more than one interconnect structure 100.

[0074] exist Figure 19 In some embodiments, an underfill 312 is formed between interconnect structures 100A-100B and core substrates 250A-250B. The underfill 312 may surround and protect the conductive connectors 210. The underfill 312 may be formed after attachment of the core substrates 250A-250B via a capillary flow process or before attachment of the core substrates 250A-250B via a suitable deposition method. The underfill 312 may be a molding compound, epoxy resin, underfill, molded underfill (MUF), resin, etc., and may be similar to the previously described sealant 206 or sealant 118.

[0075] exist Figure 20 In some embodiments, a planarization process is performed to remove excess underfill 312 and form conductive interconnects 214. The planarization process removes the underfill 312, thereby exposing the UBM 254 of the core substrates 250A-250B. After the planarization process, the surfaces of the underfill 312 and the core substrates 250A-250B can be coplanar. The planarization process may include CMP processes, polishing processes, etching processes, or combinations thereof. The conductive interconnects 214 can then be formed on the UBM 254 of the core substrates 250A-250B. The conductive interconnects 214 can be similar to those for... Figure 15 The conductive connector 214 is described, and can be formed in a similar manner.

[0076] Figure 21 The attachment of semiconductor devices 260A-260C according to some embodiments is shown to form package 300. After removing carrier 302 from the structure, semiconductor devices 260A-260C can be attached to conductive connector 208. Semiconductor devices 260A-260C are physically and electrically connected to conductive connector 208 to form an electrical connection between semiconductor devices 260A-260C and interconnect structures 100A-100B. Semiconductor devices 260A-260C can be similar to those previously described for... Figure 16 The semiconductor devices described are 260A-260C. Figure 21 The attachment of three semiconductor devices 260A-260C is shown, but in other embodiments, one, two, or more than three semiconductor devices 260 may be attached to the conductive connector 208. Semiconductor devices 260A-260C may be attached in a different arrangement or configuration than shown.

[0077] Semiconductor devices 260A-260C can use similar technologies to those designed for... Figure 16 The described process is attached to the conductive connector 208. For example, semiconductor devices 260A-260C can be placed on the conductive connector 208 and a reflow process can be used to bond the conductive connector 208 to the semiconductor devices 260A-260C to form a package 300. Figures 17 to 21 The process shown is a "post-chip" process, in which semiconductor devices 260A-260C are attached after the attachment core substrates 250A-250B. In other embodiments, semiconductor devices 260A-260C may be attached before the attachment core substrates 250A-250B. Figure 21 As shown, an underfill 215 can be deposited between semiconductor devices 260A-260C and interconnect structures 100A-100B. The underfill 215 can be similar to that used for... Figure 16 The bottom filler 215 is described, and can be formed in a similar manner.

[0078] Figures 22 to 28 A package 400 comprising a plurality of interconnect structures 100A-100B and one or more through-hole structures 450 is shown according to some embodiments (see Figure 28 The interconnect structure 100A-100B of the package 400 can be similar to the formation of the package. Figure 9 The interconnect structures 100A-100B are shown. Package 400 includes a core substrate 250, which can be similar to... Figure 14 The core substrate 250 is shown below. In other embodiments, multiple core substrates 250 may be used, and the following describes the process for determining the core substrate 250. Figure 30 Describe an exemplary embodiment. Package 400 may be similar to Figure 16The package 200 shown, in addition to the interconnect structures 100A-100B, includes one or more through-hole structures 450 (described in more detail below). In some embodiments, the through-hole structures 450 can be used to transmit electrical signals and / or electrical power to one or more semiconductor devices 260 of the package 400. The through-hole structures 450 can also be configured for power applications or to safely provide relatively large voltages or currents. By using the through-hole structures 450, which are formed separately from the interconnect structures 100, different processes can be used to form components more suitable for high-power applications, such as conductive components with larger dimensions, in the through-hole structures 450. Furthermore, the manufacturing cost of the package can be reduced and the yield of the package can be improved. The package 400 may include different numbers or configurations of interconnect structures 100, through-hole structures 450, or core substrates 250 as shown.

[0079] Transfer to Figure 22 According to some embodiments, a through-hole structure 450 is shown. The through-hole structure 450 is similar to... Figure 9 The interconnect structure 100 shown does not include interconnect component 50 or IPD 80, except for the through-hole structure 450. In other embodiments, the through-hole structure 450 may include interconnect component 50 or IPD 80. In some embodiments, the through-hole structure 450 may be configured with... Figures 2 to 9 The via structure 450 is formed in a manner similar to that described for interconnect structure 100. The via structure 450 includes a redistribution structure 420, which may be similar to the redistribution structure 120 previously described for interconnect structure 100 and can be formed using similar techniques. The via structure 450 includes a conductive via 436, which may be similar to the conductive via 136 previously described for interconnect structure 100 and can be formed using similar techniques. In some embodiments, the redistribution structure 420 or the conductive via 436 may have conductive components that are larger (e.g., thicker, with a larger linewidth, a larger diameter, etc.) than the corresponding conductive components of the redistribution structure 120 or the conductive via 136. The via structure 450 also includes a via 456 connecting the redistribution structure 420 and the conductive via 436. The via 456 may be similar to the via 116 previously described for interconnect structure 100 and can be formed using similar techniques. In some embodiments, the via 456 may have a larger dimension than the via 116. In some embodiments, via 456 may have a width ranging from about 20% to about 200% of the width of via 116. In some cases, forming a conductive component with a larger size can reduce resistance and improve performance when using relatively large currents or voltages. Via structure 450 may have a size greater than, less than, or approximately the same as interconnect structure 100.

[0080] Figure 23The via structure 450 and interconnect structures 100A-100B according to some embodiments are shown placed on a carrier substrate 402. The carrier substrate 402 may be similar to the first carrier substrate 102 previously described. The via structure 450 and interconnect structures 100A-100B may be attached to the carrier substrate 402 using, for example, an adhesive layer 404. In some embodiments, the adhesive layer 404 may be similar to the release layer 104 previously described. Figure 23 The illustration shows the placement of a through-hole structure 450 and two interconnect structures 100A-100B, but in other embodiments, more through-hole structures 450 or interconnect structures 100 may be placed. Figure 23 A via structure 450 is shown placed between interconnect structures 100A-100B, but in other embodiments, the via structure 450 and interconnect structures 100A-100B may have different arrangements.

[0081] exist Figure 24 In some embodiments, a sealant 206 is formed on the through-hole structure 450 and the interconnect structures 100A-100B. The sealant 206 can be a molding compound, epoxy resin, etc., and can be similar to the sealant 206 previously described. The sealant 206 can be applied by compression molding, transfer molding, etc., and can be formed above the carrier substrate 402, thereby burying or covering the through-hole structure 450 and the interconnect structures 100A-100B. The sealant 206 can be applied in liquid or semi-liquid form and then subsequently cured.

[0082] exist Figure 25 In some embodiments, a planarization process is performed to remove excess sealant 206 and form conductive connectors 208. The planarization process removes the sealant 206, thereby exposing the conductive vias 436 of the via structure 450 and the conductive vias 136 of the interconnect structures 100A-100B. After the planarization process, the surfaces of the sealant 206, the via structure 450, and the interconnect structures 100A-100B can be coplanar. The planarization process may include CMP processes, polishing processes, etching processes, or combinations thereof.

[0083] Still referencing Figure 25 Conductive connectors 208 are formed on the conductive vias 436 of the via structure 450 and the conductive vias 136 of the interconnect structures 100A-100B. The conductive connectors 208 can be similar to those previously used for... Figure 12 The conductive connector 208 is described, and can be formed in a similar manner.

[0084] exist Figure 26In some embodiments, the structure is peeled off from the carrier substrate 402, and conductive connectors 210 are formed on the via structure 450 and the interconnect structures 100A-100B. A previously deposited sealant 206 secures the via structure 450 and the plurality of interconnect structures 100A-100B, forming a substantially rigid structure, which may be referred to herein as the “connection structure”. The conductive connectors 210 may be formed on the redistribution structure 420 of the via structure 450 and the redistribution structure 120 of the interconnect structures 100A-100B. The conductive connectors 210 may be similar to those for… Figure 13 The described conductive connector can be formed in a similar manner.

[0085] Transfer to Figure 27 According to some embodiments, the core substrate 250 is attached to the via structure 450 and the interconnect structures 100A-100B. The core substrate 250 can be similar to... Figure 14 The core substrate 250 shown. Attaching the core substrate 250 may include... Figure 26 The connection structure is placed on the core substrate 250, so that the conductive connector 210 is in physical contact with UBM254 on one side of the core substrate 250. Then, a reflow process can be performed on the conductive connector 210 to physically and electrically couple the core substrate 250 to the via structure 450 and the interconnect structures 100A-100B.

[0086] In some embodiments, an underfill 212 may be formed between the via structure 450 and the core substrate 250, and between the interconnect structures 100A-100B and the core substrate 250. The underfill 212 may surround the conductive connector 210. The underfill 212 may be formed by a capillary flow process after attaching the core substrate 250, or by a suitable deposition method before attaching the core substrate 250. The underfill 212 may be similar to that previously described for... Figure 15 The bottom filler 212 is described.

[0087] Still referencing Figure 27 In some embodiments, conductive connectors 214 may be formed on the core substrate 250. For example, conductive connectors 214 may be formed on the UBM 254 of the core substrate 250. Conductive connectors 214 may be similar to those for... Figure 15 The conductive connector 214 is described, and can be formed in a similar manner.

[0088] Figure 28 The attachment of semiconductor devices 260A-260C according to some embodiments is shown to form package 400. Semiconductor devices 260A-260C are physically and electrically connected to conductive connector 208 to form an electrical connection between semiconductor devices 260A-260C, through-hole structure 450 and interconnect structures 100A-100B. Figure 28 Only semiconductor device 260B directly coupled to via structure 450 is shown; however, in other embodiments, via structure 450 may be directly coupled to different semiconductor devices 260 or multiple semiconductor devices 260. Semiconductor devices 260A-260C may be similar to those previously shown for... Figure 16 The semiconductor devices described are 260A-260C. Figure 28 The attachment of three semiconductor devices 260A-260C is shown, but in other embodiments, one, two, or more than three semiconductor devices 260 may be attached to the conductive connector 208. Semiconductor devices 260A-260C may be attached in a different arrangement or configuration than shown.

[0089] Semiconductor devices 260A-260C can use similar technologies to those designed for... Figure 16 The described process is attached to the conductive connector 208. For example, semiconductor devices 260A-260C can be placed on the conductive connector 208 and a reflow process can be used to bond the conductive connector 208 to the semiconductor devices 260A-260C to form a package 400. Figures 23 to 28 The process shown is a "post-chip" process, in which semiconductor devices 260A-260C are attached after the attachment core substrate 250. In other embodiments, semiconductor devices 260A-260C may be attached before the attachment core substrate 250. Figure 28 As shown, an underfill 215 can be deposited beneath semiconductor devices 260A-260C. The underfill 215 can be similar to that used for... Figure 16 The bottom filler 215 is described, and can be formed in a similar manner.

[0090] Figure 29 A package 460, comprising a through-hole structure 450 and interconnect structures 100A-100B according to some embodiments, is shown. Package 460 is similar to... Figure 28 The package 400 shown, except Figure 29 The core substrate 250 has a higher density than Figure 28 The core substrate 250 shown has a large size. In some embodiments, the package 460 may be formed in a similar manner to the package 400. For example, similar to Figure 26 The structure shown can be formed using a similar process. Then the structure can be formed using a process similar to that used for... Figure 27 The techniques described are attached to the core substrate 250. For example, conductive connectors 210 of the structure can be placed on the core substrate 250, and a reflow process can then be performed. Figure 29 As shown, the structure can have a size D1 smaller than the size D2 of the core substrate 250. An underfill 212 can be deposited between the structure and the core substrate 250, which can be similar to that previously used for... Figure 15 The bottom filler 212 is described.

[0091] Then semiconductor devices 260A-260C can use similar technologies to those for… Figure 16 The described process attaches to conductive connector 208. For example, semiconductor devices 260A-260C can be placed on conductive connector 208 and the conductive connector 208 can be bonded to semiconductor devices 260A-260C using a reflow process to form package 460. This process is a "post-chip" process, wherein semiconductor devices 260A-260C are attached after attaching the core substrate 250. In other embodiments, semiconductor devices 260A-260C can be attached before attaching the core substrate 250. Figure 29 As shown, an underfill 215 can be deposited beneath semiconductor devices 260A-260C. The underfill 215 can be similar to that used for... Figure 16 The bottom filler 215 is described, and can be formed in a similar manner.

[0092] Figure 30 A package 470, according to some embodiments, includes a through-hole structure 450, interconnect structures 100A-100B, and multiple core substrates 250A-250C. Package 470 is similar to... Figure 29 The package 460 shown, except that package 470 has multiple core substrates 250A-250C. The core substrates 250A-250C of package 470 can be similar to Figure 14 The core substrate 250 shown, except that core substrates 250A-250C can have a higher density than... Figure 14 The core substrate 250 shown is relatively small in size. The core substrates 250A-250C of package 470 can be similar to... Figure 21 The core substrates 250A-250B of the package 300 shown are illustrated. By using multiple core substrates 250A-250C within the package 470 instead of a single, larger core substrate 250, manufacturing costs can be reduced and yields can be improved. The package 470 may include via structures 450, interconnect structures 100, or core substrates 250 in different numbers or configurations as shown. For example, multiple core substrates 250 may be attached to a single via structure 450 or interconnect structure 100, or multiple via structures 450 and / or interconnect structures 100 may be attached to the same core substrate 250.

[0093] In some embodiments, the package 470 can use a similar design to that for... Figures 17 to 21 Package 300 or for Figures 22 to 28 The technology described in package 400 is used to form those components. For example, similar processes can be used to form components similar to those described in the package. Figure 26The structure shown is then used. Multiple core substrates 250A-250C can then be used in a manner similar to... Figure 18 The techniques described are attached to the structure. For example, core substrates 250A-250C can be placed on the conductive interconnects 210 of the structure, and a reflow process can then be performed. An underfill 212 can be deposited between the structure and the core substrates 250A-250C, which can be similar to those previously used for... Figure 15 The bottom filler 212 is described.

[0094] Then semiconductor devices 260A-260C can use similar technologies to those for… Figure 16 The described process attaches to conductive connector 208. For example, semiconductor devices 260A-260C can be placed on conductive connector 208 and a reflow process can be used to bond conductive connector 208 to semiconductor devices 260A-260C to form package 470. This process is a "post-chip" process, wherein semiconductor devices 260A-260C are attached after attaching core substrates 250A-250C. In other embodiments, semiconductor devices 260A-260C can be attached before attaching core substrates 250A-250C. Figure 30 As shown, an underfill 215 can be deposited beneath semiconductor devices 260A-260C. The underfill 215 can be similar to that used for... Figure 16 The bottom filler 215 is described, and can be formed in a similar manner.

[0095] Figures 31 to 39 A package 500 comprising multiple interconnect structures 512A-512B and a through-hole 510 according to some embodiments is shown (see Figure 39 The formation of the package 500. Figure 16 The package 200 shown includes one or more through-holes 510 in addition to the interconnect structures 512A-512B. The interconnect structures 512A-512B of the package 500 can be similar to... Figure 9 The interconnect structures 100A-100B shown, except that the dielectric layer 138 and the conductive via 136 are not formed above the conductor 110 before attachment (see... Figure 34 Package 500 includes a core substrate 250, which may be similar to... Figure 14The core substrate 250 is shown. In other embodiments, multiple core substrates 250 may be used. In some embodiments, vias 510 may be used to transmit electrical signals and / or electrical power to one or more semiconductor devices 260 of the package 500. Vias 510 may also be configured for power applications or to safely provide relatively large voltages or currents. By using vias 510 formed separately from interconnect structures 512, vias 510 can be formed to have a larger size than conductive parts of interconnect structures 512 (such as via 116). Furthermore, the manufacturing cost of the package can be reduced and the yield of the package can be improved. The package 500 may include interconnect structures 512 or vias 510 in different numbers or configurations as shown.

[0096] exist Figures 31 to 33 In some embodiments, vias 510 are formed on a carrier substrate 502. The carrier substrate 502 may be similar to the first carrier substrate 102 previously described. A release layer 504, which may be similar to the release layer 104 previously described, may be formed on the carrier substrate 502. Figures 31 to 33 An example for forming a through-hole 510 is shown, but other techniques may be used in other embodiments. In some embodiments, the through-hole 510 uses techniques similar to those used for forming... Figure 4 The techniques described for forming the through-hole 116.

[0097] Transfer to Figure 31 A seed layer 505 can be formed over the carrier substrate 502. For example, the seed layer 505 can be formed over the release layer 504 (if present). In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer comprising multiple sublayers formed of different materials. In a particular embodiment, the seed layer includes a titanium layer and a copper layer located above the titanium layer. The seed layer can be formed using, for example, PVD. In some embodiments, the seed layer 505 can be similar to that used for... Figure 3 or Figure 4 The described seed layer can also be formed in a similar manner. In other embodiments, the seed layer 505 is not used.

[0098] Still referencing Figure 31 A photoresist 506 is formed and patterned on the seed layer 505. The photoresist 506 can be formed and patterned using a suitable photolithography technique. For example, the photoresist 506 can be formed by spin coating or the like and can be exposed to light for patterning. The pattern formed in the photoresist 506 corresponds to a via 510. For example, patterning can form an opening 508 through the photoresist 506 that exposes the seed layer 505.

[0099] exist Figure 32In this process, a conductive material 509 is formed in the opening 508 of the photoresist 506 and on the exposed portion of the seed layer 505. The conductive material 509 can be formed by plating (such as electroplating or chemical plating). The conductive material can include metals such as copper, titanium, tungsten, aluminum, etc., and can be similar to those used for... Figure 4 The conductive material of the through hole 116 is described.

[0100] exist Figure 33 In this process, the portion of photoresist 506 and seed layer 505 on which the non-conductive material 509 is formed is removed to form a via 510. The photoresist 506 can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist 506 is removed, the exposed portion of the seed layer 505 is removed, for example by using an acceptable etching process, such as by wet etching or dry etching. The remaining portion of the seed layer 505 and conductive material 509 forms the via 510. In some embodiments, the via 510 can be formed to have a size larger than the via 116 of the interconnect structure 100. In some embodiments, the via 510 can have a width ranging from about 20% to about 200% of the width of the via 116. In some cases, forming a via with a larger size can reduce resistance and improve performance when using relatively large currents or voltages.

[0101] Figure 34 The placement of interconnect structures 512A-512B on a carrier substrate 502 according to some embodiments is shown. Figure 34 As shown, interconnect structures 512A-512B can be positioned such that the redistribution structure 120 of each interconnect structure 512A-512B faces the carrier substrate 502. Figure 34 The placement of two interconnect structures 512A-512B is shown, but in other embodiments more than two interconnect structures 512 may be placed. Figure 34 A through-hole 510 is shown as being located between interconnect structures 512A-512B, but the through-hole 510 and interconnect structures 512A-512B can have any suitable arrangement.

[0102] Still referencing Figure 34 According to some embodiments, a sealant 206 is formed on the through-hole 510 and the interconnect structures 512A-512B. The sealant 206 can be a molding compound, epoxy resin, resin, etc., and can be similar to those previously used for... Figure 11The sealant 206 is described. The sealant 206 can be applied by compression molding, transfer molding, etc., and can be formed over the carrier substrate 502, thereby burying or covering the via 510 and / or the interconnect structures 512A-512B. The sealant 206 can be applied in liquid or semi-liquid form and then subsequently cured. The sealant 206 can surround the via 510, separating and insulating the via 510 from the interconnect structures 512A-512B.

[0103] exist Figure 35 In some embodiments, a planarization process is performed to remove excess sealant 206. The planarization process removes the sealant 206, thereby exposing the conductors 110 of the via 510 and the interconnect structures 512A-512B. In some embodiments, the planarization process may remove a portion of the via 510. After the planarization process is performed, the surfaces of the sealant 206, the via 510, and the interconnect structures 512A-512B may be coplanar. The planarization process may include CMP processes, polishing processes, etching processes, or combinations thereof.

[0104] exist Figure 36 In some embodiments, a conductive via 536 and a conductive connector 208 are formed. The conductive via 536 is formed on the conductor 110 of the interconnect structure 512A-512B and on the via 510. In this way, the conductive via 536 is electrically connected to the via 510 and via 116, the interconnect assembly 50, and the IPD 80 of the interconnect structure 512A-512B. In some embodiments, the conductive via 536 may include under-bump metallization (UBM). The conductive via 536 may be similar to that used for... Figure 8 The conductive via 136 is described, and can be formed in a similar manner. For example, a seed layer (not shown) can be deposited, and then photoresist can be formed and patterned on the seed layer. The patterning forms openings through the photoresist to expose the seed layer, wherein the openings in the photoresist correspond to the conductive via 536. A conductive material is then formed in the openings of the photoresist and on the exposed portion of the seed layer. The combination of the conductive material and the lower portion of the seed layer forms the conductive via 536. The portions of the photoresist and seed layer on which no conductive material is formed are removed.

[0105] Still referencing Figure 36 According to some embodiments, a dielectric layer 538 may be formed on and around the conductive via 536. The dielectric layer 538 may be similar to that used for... Figure 8The dielectric layer 138 is described and can be formed in a similar manner. After formation, the dielectric layer 538 surrounds the conductive via 536 and can extend over the sealant 206, the via 510, and the interconnect structures 512A-512B. The dielectric layer 538 can provide electrical isolation and environmental protection for the conductive via 536. The dielectric layer 538 can be a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc.; a nitride, such as silicon nitride; an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.; a sealant, molding compound, epoxy resin, etc.; or a combination thereof. The dielectric layer 538 can be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. In some embodiments, after the formation of the dielectric layer 538, a planarization process (e.g., CMP or polishing process) can be performed to expose the conductive via 536.

[0106] In other embodiments, the dielectric layer 538 may be formed prior to the conductive via 536. In such embodiments, an opening is formed through the dielectric layer 538 to expose portions of the via 510 and the wire 110. For example, the opening may be formed using laser drilling, etching, or the like. The conductive via 536 is then formed in the opening to make physical and electrical contact with the wire 110. In some embodiments, a planarization process (e.g., CMP or polishing process) may be performed after the conductive via 536 is formed.

[0107] exist Figure 37 In some embodiments, a structure is peeled off and a conductive connector 210 is formed. Peeling is performed to separate the carrier substrate 502 from the structure. The structure is then flipped and attached to a different carrier substrate 552. The carrier substrate 552 may be similar to the carrier substrate 502 or may be, for example, a strip. A release layer 554 may be formed on the carrier substrate 502 to facilitate attachment of the structure to the carrier substrate 502. The release layer 554 may be similar to the release layer 104 or may be, for example, an adhesive layer. A previously deposited sealant 206 secures the via 510 and the plurality of interconnect structures 512A-512B, forming a substantially rigid structure, which may be referred to herein as a “connection structure.” The conductive connector 210 may be formed on the via 510 and on the redistribution structure 120 of the interconnect structures 512A-512B. The conductive connector 210 may be similar to that for… Figure 13 The described conductive connector can be formed in a similar manner.

[0108] exist Figure 38 In some embodiments, the core substrate 250 is attached to the via 510 and the interconnect structures 512A-512B. The core substrate 250 can be similar to... Figure 14The core substrate 250 is shown. In some embodiments, more than one core substrate 250 may be attached. Attaching a core substrate 250 may include placing the core substrate 250 on... Figure 37 Structurally, this allows the conductive connector 210 to physically contact the UBM 254 of the core substrate 250. A reflow process can then be performed on the conductive connector 210 to physically and electrically couple the core substrate 250 to the via 510 and the interconnect structures 100A-100B.

[0109] Still referencing Figure 38 According to some embodiments, an underfill 212 can be formed under the core substrate 250. The underfill 212 can surround and protect the conductive connector 210. The underfill 212 can be formed after attachment of the core substrate 250 by a capillary flow process, or it can be formed before attachment of the core substrate 250 by a suitable deposition method. The underfill 212 can be a molding compound, epoxy resin, underfill, molded underfill (MUF), resin, etc., and can be similar to those previously used for... Figure 15 The bottom filler 212 is described.

[0110] Figure 39 The attachment of semiconductor devices 260A-260C according to some embodiments is shown to form package 500. Semiconductor devices 260A-260C are physically and electrically connected to conductive connector 208 to form an electrical connection between semiconductor devices 260A-260C, through-hole 510, and interconnect structures 512A-512B. Figure 39 Only semiconductor device 260B directly coupled to via 510 is shown; however, in other embodiments, via 510 may be directly coupled to different or multiple semiconductor devices 260. Semiconductor devices 260A-260C may be similar to those previously described for... Figure 16 The semiconductor devices described are 260A-260C. Figure 39 The attachment of three semiconductor devices 260A-260C is shown, but in other embodiments, one, two, or more than three semiconductor devices 260 may be attached to the conductive connector 208. Semiconductor devices 260A-260C may be attached in a different arrangement or configuration than shown.

[0111] Semiconductor devices 260A-260C can use similar technologies to those designed for... Figure 16 The described process is attached to the conductive connector 208. For example, semiconductor devices 260A-260C can be placed on the conductive connector 208 and a reflow process can be used to bond the conductive connector 208 to the semiconductor devices 260A-260C to form a package 500. Figures 31 to 39The process shown is a "post-chip" process, in which semiconductor devices 260A-260C are attached after the attachment core substrate 250. In other embodiments, semiconductor devices 260A-260C may be attached before the attachment core substrate 250. Figure 39 As shown, an underfill 215 can be deposited beneath semiconductor devices 260A-260C. The underfill 215 can be similar to that used for... Figure 16 The bottom filler 215 is described, and can be formed in a similar manner.

[0112] In some cases, forming a package with multiple smaller interconnect structures (e.g., interconnect structure 100) instead of a single larger redistributed structure can improve yield and reduce process costs. As described herein, a package with multiple smaller interconnect structures can be formed that together provide the same functionality, such as electrical wiring, as a single larger redistributed structure. In some embodiments, the interconnect structure may include interconnect components 50 or IPD 80 that provide additional functionality.

[0113] In some cases, processing defects such as falling particles, contamination, and embedded defects can lead to open circuits or short circuits in conductors or vias. In other cases, the relatively larger area of ​​a single redistributed structure increases the chance of defects occurring during processing, potentially causing the entire package to fail. By forming multiple smaller interconnect structures as described herein, a single occurrence of a localized defect can cause the failure of a single interconnect structure rather than the entire package. Each interconnect structure can be tested with known good cells before being incorporated into the package, reducing the chance of package failure due to defects within the interconnect structure. This improves package manufacturing yield. Furthermore, in some cases, using smaller interconnect structures can reduce warpage or problems caused by misalignment. In some cases, using multiple interconnect structures can allow yields greater than approximately 80%, but other yields are also possible.

[0114] Forming packages that include multiple interconnect structures instead of a single redistributed structure can improve the overall yield of the package, which can reduce manufacturing costs. For example, in some cases, a greater number of undivided interconnect structures can be formed per wafer compared to the number of single redistributed structures that can be formed per wafer. This is in Figures 40A to 40D and Figures 41A to 41B The diagrams show exemplary layouts of the package, wafer, and structures formed thereon, illustrating schematic plan views. Figures 40A to 40D and Figures 41A to 41B The layouts shown are for illustrative purposes only, and the embodiments described herein may be formed using other layouts, arrangements, or configurations different from those shown in these examples.

[0115] Transfer to Figures 40A to 40D , Figure 40A An exemplary layout of a wafer 602 according to some embodiments is shown, on which a redistribution structure 610 has been formed as a package 600 (see...). Figure 40B This is part of the fabrication process. Wafer 602 can be similar to the first carrier substrate 102 previously described, such as a silicon wafer. For illustrative purposes, each of the redistribution structures 610 is shown with four functional regions labeled "A", "B", "C", and "D", representing regions of the redistribution structure 610 that have specific functions. Functional regions AD may include, for example, electrical wiring. Figure 40A As shown, for the exemplary dimensions of the illustrated wafer 602 and redistribution structure 610, two redistribution structures 610 can be formed simultaneously on a single wafer 602. For example, each redistribution structure 610 can have a diameter of approximately 130 mm. 2 The area and wafer 602 can be a 12-inch wafer, but other sizes are also possible.

[0116] Figure 40A The two redistribution structures 610 shown can subsequently be divided as part of forming package 600. Figure 40B A plan view of an exemplary package 600 is shown, which includes a redistribution structure 610 attached to a core substrate 650. The core substrate 650 may be similar to that for... Figure 14 The core substrate 250 is described. In this example, processing one wafer 602 produces two packages 600, corresponding to a total of two packages 600 per wafer.

[0117] Figure 40C An exemplary layout of wafers 702A-702D according to some embodiments is shown, on which interconnect structures 710A-710D have been formed as packages 700 (see...). Figure 40D This is part of the fabrication of the interconnect structure 610A-702D. Wafers 702A-702D can be similar to the first carrier substrate 102 previously described, such as a silicon wafer, and can have dimensions similar to wafer 602. For illustrative purposes, each interconnect structure 710A-710D is associated with a different functional region AD of the redistribution structure 610. For example, interconnect structure 710A corresponds to the function of functional region A of the redistribution structure 610. In this way, the four types of interconnect structures 710A-710D together can have the same function as a single redistribution structure 610. Figure 40CAs shown, for the exemplary dimensions of the illustrated wafers 702A-702D and interconnect structures 710A-710D, twelve of each interconnect structure 710A-710D can be formed simultaneously on each corresponding single wafer 702A-702D. For example, each interconnect structure 710A-710D can have approximately 32mm². 2 The area and wafers 702A-702D can be 12-inch wafers, but other sizes are also possible.

[0118] Figure 40C The interconnect structures 710A-710D shown can subsequently be segmented as part of forming package 700. Figure 40D A plan view of an exemplary package 700 is shown, which includes one of each interconnect structure 710A-710D attached to a core substrate 750. The core substrate 750 may be similar to that for... Figure 14 The described core substrate 250. In this example, processing four wafers 702A-702D produces twelve packages 700, corresponding to a total of three packages 700 per wafer. Therefore, in this example, for wafers of the same size, forming multiple interconnect structures 710A-710D instead of a single redistribution structure 610 can increase the total unit yield per wafer by 50%. As described above, forming multiple interconnect structures 710A-710D instead of a single redistribution structure 610 can improve yield. For example, a single defect on wafer 602 during processing can reduce the yield of one of two possible packages 600 (e.g., a 50% yield reduction), but a single defect on each of wafers 702A-702D only reduces the yield of one of the twelve possible packages 700 (e.g., approximately an 8% yield reduction).

[0119] The redistribution structure 610 and interconnection structures 710A-710D are illustrative examples, and the function (e.g., partitions A, B, C, and D), size, shape, arrangement, or quantity of the redistribution structure 610 or interconnection structure 710 may differ in other cases. For example, Figure 40D The package 700 shown may be larger than, smaller than, or approximately the same size as... Figure 40A The package shown is the same size as the 600 shown.

[0120] Figures 41A to 41B and Figures 42A to 42B Additional exemplary layouts for redistributed structures and interconnect structures of other sizes are shown according to some embodiments. Figures 41A to 41BWafers 602 and 702A-702D are shown, on which redistribution structures 612 and interconnect structures 712A-712D have been formed as part of the fabrication of a package (not shown separately). Wafers 602 and 702A-702D can be similar to those for... Figures 40A to 40D Those described. The redistribution structure 612 and the interconnection structures 712A-712D can be similar to those for... Figures 40A to 40D The redistribution structure 610 and interconnection structures 710A-710D described have smaller dimensions, except that redistribution structure 612 and interconnection structures 712A-712D have smaller dimensions. For example, redistribution structure 612 can have a size of approximately 110 mm. 2 The area and interconnect structure of the 712A-712D can each have approximately 27.5mm². 2 The area is [area], but other sizes are also possible. For example... Figure 41A As shown, three redistribution structures 612 can be formed simultaneously on a single wafer 602, corresponding to a total of three packages per wafer. Figure 41B As shown, sixteen of each interconnect structure 712A-712D can be formed simultaneously on each corresponding individual wafer 702A-702D, corresponding to a total of four packages per wafer. Therefore, in this example, for wafers of the same size, forming multiple interconnect structures 712A-712D instead of a single redistribution structure 612 can increase the total unit size per wafer by 33%.

[0121] Figures 42A to 42B Wafers 602 and 702A-702D are shown, on which redistribution structures 614 and interconnect structures 714A-714D have been formed as part of the fabrication of a package (not shown separately). Wafers 602 and 702A-702D can be similar to those for... Figures 40A to 40D Those described. The redistribution structure 614 and the interconnection structures 714A-714D can be similar to those for... Figures 40A to 40D The redistribution structure 610 and interconnection structures 710A-710D described have smaller dimensions, except that redistribution structure 614 and interconnection structures 714A-714D have smaller dimensions. For example, redistribution structure 614 can have a size of approximately 91 mm. 2 The area and interconnect structure of the 714A-714D can each have approximately 23mm². 2 The area is [specific size], but other sizes are also possible. For example... Figure 42A As shown, five redistribution structures 614 can be formed simultaneously on a single wafer 602, corresponding to a total of five packages per wafer. Figure 42BAs shown, 26 of each interconnect structure 714A-714D can be formed simultaneously on each corresponding individual wafer 702A-702D, corresponding to a total of six and a half packages per wafer. Therefore, in this example, for wafers of the same size, forming multiple interconnect structures 714A-714D instead of a single redistribution structure 614 can increase the total unit size per wafer by 30%.

[0122] Other components and processes may also be included. For example, test structures may be included to aid in the verification testing of 3D packaged or 3DIC devices. Test structures may include, for example, test pads formed in the redistribution layer or on the substrate, which allow testing of the 3D package or 3DIC using probes and / or probe cards, etc. Verification testing can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be used in conjunction with test methods that incorporate intermediate verification of known good dies to increase yield and reduce cost.

[0123] The embodiments can achieve advantages. By forming a package including multiple interconnect structures attached to one or more core substrates, as described herein, yield can be improved and the number of cells per wafer can be increased, which can reduce process costs. The processes described herein also allow the formation of interconnect structures in packages smaller than the core substrate of the package. Interconnect structures can include components, such as interconnect components having electrical wiring, IPDs, vias, etc., which can allow for design flexibility and performance improvements. The use of interconnect structures also allows for the attachment of semiconductor devices before or after the core substrate (e.g., "post-chip"). The use of interconnect structures allows for the formation of larger vias in or adjacent to the interconnect structures, which can provide benefits for higher power operation of the package.

[0124] According to some embodiments of the present invention, the method includes: attaching interconnect structures to a carrier substrate, wherein each interconnect structure includes: a redistribution structure; a first sealant located on the redistribution structure; and a via extending through the sealant for physical and electrical connection to the redistribution structure; depositing a second sealant on the interconnect structure, wherein adjacent interconnect structures are laterally separated by the second sealant; after depositing the second sealant, attaching a first core substrate to the redistribution structure of at least one interconnect structure, wherein the core substrate is electrically connected to the redistribution structure; and attaching a semiconductor device to the interconnect structure, wherein the semiconductor device is electrically connected to the via of the interconnect structure. In embodiments, at least one interconnect structure further includes an interconnect assembly, wherein the interconnect assembly is surrounded by the first sealant, wherein the interconnect assembly includes electrical wiring. In embodiments, the semiconductor device is electrically connected to the interconnect assembly of the interconnect structure. In embodiments, at least one interconnect structure further includes an integrated passive device (IPD). In embodiments, the semiconductor device is attached after attaching the first core substrate. In embodiments, the method includes: attaching a second core substrate to the redistribution structure of at least one interconnect structure, wherein the core substrate is electrically connected to the redistribution structure. In one embodiment, the method includes depositing an underfill material between a first core substrate and an interconnect structure. In another embodiment, the method includes forming a plurality of vias on a carrier substrate, wherein a second sealant is deposited on the plurality of vias. In another embodiment, the vias of the first interconnect structure have a wider width than the vias of the second interconnect structure.

[0125] According to some embodiments of the present invention, the method includes: forming a first interconnect structure, which includes: forming a first via on a first carrier; depositing a first molding material over the first via; forming a redistribution structure on a first side of the first via and the first molding material, wherein the redistribution structure is electrically connected to the first via; and forming a second via on a second side of the first via and the first molding material opposite to the first side, wherein the second via is electrically connected to the first via; forming a connection structure, which includes: placing a first interconnect structure and a second interconnect structure on a second carrier, and depositing a second molding material between the first interconnect structure and the second interconnect structure; connecting a first core substrate to the connection structure, wherein the first core substrate is connected to the redistribution structure of the first interconnect structure; and connecting a first semiconductor device to the connection structure, wherein the first semiconductor device is connected to the second via of the first interconnect structure. In an embodiment, the method includes: performing a planarization process on the second molding material, the first interconnect structure, and the second interconnect structure, wherein after performing the planarization process, the second molding material and the second via of the first interconnect structure are coplanar. In an embodiment, the second interconnect structure includes a redistribution structure, and wherein the first core substrate is connected to the redistribution structure of the second interconnect structure. In one embodiment, forming the first interconnect structure further includes placing an integrated passive device (IPD) on a first carrier and depositing a first molding material over the IPD, wherein a second via is formed over the IPD and electrically connected to the IPD. In another embodiment, the method includes connecting a second core substrate to a connection structure, wherein the second core substrate is not connected to a redistribution structure of the first interconnect structure. In another embodiment, the sidewalls of the first core substrate protrude beyond the sidewalls of the connection structure. In yet another embodiment, connecting the first core substrate to the connection structure includes bonding the first core substrate to the connection structure using solder bumps.

[0126] According to some embodiments of the present invention, a package includes: a substrate electrically connected to respective first sides of a plurality of interconnect structures, wherein each interconnect structure is at least partially surrounded by a sealant, wherein each interconnect structure includes: a redistribution structure; a via located on the redistribution structure; and an integrated device; and a semiconductor device electrically connected to a respective second side of the interconnect structure, wherein the second side is opposite to the first side. In embodiments, the integrated device is a local wiring structure. In embodiments, the integrated device is isolated from the via and the redistribution structure by a molding material. In embodiments, at least one semiconductor device is electrically connected to at least two of the interconnect structures.

[0127] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A method of forming a package, comprising: Multiple interconnect structures are attached to a carrier substrate, wherein the interconnect structures of the multiple interconnect structures each include: First redistribution structure; A first sealant, located on the first redistribution structure; and An interconnect component, wherein the interconnect component is surrounded by a first sealant, wherein the interconnect component includes electrical wiring, and the interconnect component is perpendicularly spaced from the first redistribution structure by the first sealant; A first through-hole extends through the sealant to be physically and electrically connected to the first redistribution structure; A via structure is attached to the carrier substrate and the via structure is located between adjacent interconnect structures of the plurality of interconnect structures, wherein the via structure includes: Second redistribution structure; A third sealant is located on the second redistribution structure; and A second through-hole extends through the third sealant to be physically and electrically connected to the second redistribution structure, wherein the conductive components in the second through-hole and the second redistribution structure are larger than the conductive components in the first through-hole and the first redistribution structure. A second sealant is deposited on the plurality of interconnect structures and the through-hole structure, wherein adjacent interconnect structures of the plurality of interconnect structures and the through-hole structure are laterally separated from adjacent interconnect structures by the second sealant; After depositing the second sealant, a first core substrate is attached to the first redistribution structure of at least one of the plurality of interconnect structures and / or the second redistribution structure of the via structure, wherein the first core substrate is electrically connected to the first redistribution structure and / or the second redistribution structure; and Multiple semiconductor devices are attached to the multiple interconnect structures and the via structures, wherein the multiple semiconductor devices are electrically connected to the first via of the multiple interconnect structures and the second via of the via structures.

2. The method according to claim 1, wherein, The first sealant is a molding compound.

3. The method according to claim 1, wherein, The plurality of semiconductor devices are electrically connected to the interconnect components of the plurality of interconnect structures.

4. The method according to claim 1, wherein, At least one of the plurality of interconnect structures further includes an integrated passive device.

5. The method according to claim 1, wherein, The plurality of semiconductor devices are attached after the first core substrate is attached.

6. The method according to claim 1, further comprising: The second core substrate is attached to the first redistribution structure of at least one of the plurality of interconnect structures, wherein the second core substrate is electrically connected to the first redistribution structure.

7. The method according to claim 6, further comprising: An underfill is deposited between the first core substrate and the plurality of interconnect structures.

8. The method according to claim 1, further comprising: A plurality of through holes are formed on the carrier substrate, wherein the second sealant is deposited on the plurality of through holes.

9. The method according to claim 1, wherein, The via of the first interconnect structure of the plurality of interconnect structures has a wider width than the via of the second interconnect structure of the plurality of interconnect structures.

10. A method of forming a package, comprising: Forming a first interconnect structure includes: forming a first through-hole on a first carrier; depositing a first molding material over the first through-hole; forming a first redistribution structure on a first side of the first through-hole and the first molding material, wherein the first redistribution structure is electrically connected to the first through-hole; and forming a second through-hole on the first through-hole and a second side of the first molding material opposite to the first side, wherein the second through-hole is electrically connected to the first through-hole. A through-hole structure is formed, the through-hole structure comprising: a second redistribution structure; a third molding material located on the second redistribution structure; and a third through-hole extending through the third molding material to be physically and electrically connected to the second redistribution structure, wherein the conductive components in the third through-hole and the second redistribution structure are larger than the conductive components in the first through-hole and the first redistribution structure; Forming an interconnect structure includes: placing a first interconnect structure and a second interconnect structure on a second carrier; attaching a via structure to the second carrier with the via structure located between the first interconnect structure and the second interconnect structure; depositing a second molding material between the first interconnect structure, the second interconnect structure, and the via structure; and performing a planarization process on the second molding material, the via structure, the first interconnect structure, and the second interconnect structure, wherein, after performing the planarization process, the second molding material is coplanar with the second via of the first interconnect structure; Connecting a first core substrate to the interconnect structure, wherein the first core substrate is connected to the first redistribution structure of the first interconnect structure; and A first semiconductor device is connected to the connection structure, wherein the first semiconductor device is connected to the second via of the first interconnect structure.

11. The method of claim 10, wherein, The first core substrate includes a core material comprising one or more layers of glass fiber, resin, filler, prepreg, epoxy resin, silica filler, Ajinomoto polymer film (ABF), polyimide, molding compound, and / or combinations thereof.

12. The method according to claim 10, wherein, The second interconnect structure includes a third redistribution structure, wherein the first core substrate is connected to the third redistribution structure of the second interconnect structure.

13. The method according to claim 10, wherein, Forming the first interconnect structure further includes placing an integrated passive device on the first carrier and depositing the first molding material over the integrated passive device, wherein the second via is formed over the integrated passive device and electrically connected to the integrated passive device.

14. The method of claim 10, further comprising: The second core substrate is connected to the connection structure, wherein the second core substrate is not connected to the first redistribution structure of the first interconnect structure.

15. The method according to claim 10, wherein, The sidewall of the first core substrate protrudes beyond the sidewall of the connection structure.

16. The method of claim 10, wherein, Connecting the first core substrate to the connection structure includes using solder bumps to bond the first core substrate to the connection structure.

17. A package comprising: A substrate electrically connected to a respective first side of the interconnect structure and the via structure of the plurality of interconnect structures, wherein the interconnect structure and the via structure of the plurality of interconnect structures are at least partially surrounded by a sealant, wherein each interconnect structure of the plurality of interconnect structures includes: a first redistribution structure; a first via located on the first redistribution structure; and an integrated device; and Multiple semiconductor devices are electrically connected to corresponding second sides of the interconnect structures and the via structures of the multiple interconnect structures, wherein the second sides are opposite to the first sides; The integrated device and the first redistributed structure are perpendicularly spaced apart by molding material surrounding the integrated device. The through-hole structure includes: a second redistribution structure; and a second through-hole located on and electrically connected to the second redistribution structure, wherein the conductive components in the second through-hole and the second redistribution structure are larger than the conductive components in the first through-hole and the first redistribution structure.

18. The package according to claim 17, wherein, The integrated device has a local wiring structure.

19. The package according to claim 17, wherein, The integrated device is isolated from the first through-hole by the molding material.

20. The package according to claim 17, wherein, At least one of the plurality of semiconductor devices is electrically connected to at least two interconnect structures of the plurality of interconnect structures.

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