Semiconductor device testing methods, semiconductor devices and three-dimensional memory
By setting test blocks and test holes in semiconductor devices and using voltage contrast to detect the extension depth of channel holes, the problem of abnormal extension depth during channel hole etching is solved, achieving efficient non-destructive testing and cost savings.
Patent Information
- Application Number
- CN202111642823.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-12-29
- Publication Date
- 2025-10-31
- Estimated Expiration
- 2041-12-29
AI Technical Summary
In semiconductor devices, abnormal extension depths are prone to occur during the etching process of vias, especially etching through defects, which are difficult to detect effectively and avoid destructive testing with existing technologies.
A test block is set in a semiconductor device. The test block includes a test substrate and test holes. The test substrate has multiple test semiconductor layers spaced longitudinally. The sidewalls of the test holes have test conductive layers. By applying an electric field to the device, the voltage contrast of the test holes is detected to determine whether the extension depth of the channel holes is abnormal.
It enables non-destructive testing of the extended depth of the channel hole, improves testing efficiency, avoids unnecessary subsequent process steps, and saves costs.
Smart Images
Figure CN114334694B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device testing method, a semiconductor device, and a three-dimensional memory. Background Technology
[0002] In semiconductor devices, the etching of channel holes (CH) is the most critical process step, so it is necessary to monitor the specific situation of channel hole etching during the fabrication process.
[0003] In actual production, the extension depth of the channel hole is prone to abnormalities, such as the presence of punch-through defects. Summary of the Invention
[0004] This invention provides a semiconductor device testing method, a semiconductor device, and a three-dimensional memory, which can avoid the use of destructive testing methods to detect the extension depth of the channel hole and improve testing efficiency.
[0005] This invention provides a method for testing a semiconductor device. The semiconductor device includes a memory array region and a non-memory array region. The memory array region includes a substrate and multiple vias. The vias extend longitudinally from the top surface of the semiconductor device away from the substrate to the substrate. A test block is disposed within the non-memory array region. The test block includes a test substrate that is longitudinally identical to the substrate and a test hole extending longitudinally from the top surface to the test substrate. The test substrate includes multiple test semiconductor layers spaced longitudinally, each test semiconductor layer having a different volume. A test conductive layer is provided on the sidewall of the test hole. The test conductive layer is conductive to the test semiconductor layer that the bottom of the test hole passes through or falls into. The longitudinal direction refers to the direction perpendicular to the top surface.
[0006] The method includes:
[0007] An electric field is applied to the semiconductor device to detect the voltage contrast of the test aperture; the direction of the electric field is from the top to the bottom of the semiconductor device.
[0008] Based on the voltage contrast, determine whether the extension depth of the channel hole is abnormal.
[0009] Further, the step of detecting the voltage contrast of the test hole includes:
[0010] Obtain a voltage contrast image of the top of the test hole;
[0011] The brightness of the voltage contrast image is detected.
[0012] Further, the step of determining whether the channel orifice is abnormal based on the voltage contrast includes:
[0013] If the brightness of the voltage contrast image is within a first preset range, then the extension depth of the channel hole is determined to be normal.
[0014] If the brightness of the voltage contrast image is outside the first preset range, then the extension depth of the channel hole is determined to be abnormal.
[0015] Furthermore, the number of test blocks is multiple;
[0016] The step of determining whether the channel orifice is abnormal based on the voltage contrast includes:
[0017] If the brightness difference of the voltage contrast images of any two test holes is within the second preset range, then the extension depth of the channel hole is determined to be normal.
[0018] If the brightness difference between the voltage contrast images of any two test holes is outside the second preset range, then the extension depth of the channel hole is determined to be abnormal.
[0019] Furthermore, the non-memory array region also includes a film layer stacking structure, and the plurality of test semiconductor layers include a first test semiconductor layer and a second test semiconductor layer, wherein the volume of the second test semiconductor layer is smaller than the volume of the first test semiconductor layer;
[0020] The film stack structure is located on the substrate, and the second test semiconductor layer is located on the side of the first test semiconductor layer close to the film stack structure;
[0021] The test hole penetrates the film stack structure and extends longitudinally into the second test semiconductor layer, or the test hole penetrates the film stack structure and the second test semiconductor layer and extends longitudinally into the first test semiconductor layer.
[0022] Furthermore, the second test semiconductor layer includes a plurality of sub-semiconductor layers arranged laterally at intervals, wherein "lateral" refers to a direction parallel to the top surface; each sub-semiconductor layer corresponds to one test hole, and the volume of each sub-semiconductor layer is smaller than the volume of the first test semiconductor layer;
[0023] The test hole penetrates the film stack structure and extends longitudinally into the corresponding sub-semiconductor layer, or the test hole penetrates the film stack structure and the corresponding sub-semiconductor layer and extends into the first test semiconductor layer.
[0024] Furthermore, the test hole and the channel hole have a channel structure, the channel structure including a channel layer and a storage medium layer disposed around the channel layer, and the channel layer in the test hole is the test conductive layer.
[0025] Furthermore, the non-storage array area includes a free area surrounding the storage array area and a slicing channel surrounding the free area;
[0026] The test block is located within at least one of the free area and the cutting channel.
[0027] Accordingly, the present invention also provides a semiconductor device, the semiconductor device including a memory array region and a non-memory array region, the memory array region including a substrate and a plurality of channel vias, the channel vias extending longitudinally from the top surface of the semiconductor device away from the substrate to the substrate; a test block is disposed in the non-memory array region, the test block including a test substrate that is longitudinally identical to the substrate, and test vias extending longitudinally from the top surface to the test substrate, the test substrate including a plurality of test semiconductor layers arranged longitudinally at intervals, each of the test semiconductor layers having a different volume; the longitudinal direction refers to the direction perpendicular to the top surface;
[0028] The test hole has a test conductive layer on its sidewall, and the test conductive layer is connected to the test semiconductor layer that passes through or falls into the bottom of the test hole.
[0029] Furthermore, the non-memory array region also includes a film layer stacking structure, and the plurality of test semiconductor layers include a first test semiconductor layer and a second test semiconductor layer, wherein the volume of the second test semiconductor layer is smaller than the volume of the first test semiconductor layer;
[0030] The film stack structure is located on the substrate, and the second test semiconductor layer is located on the side of the first test semiconductor layer close to the film stack structure;
[0031] The test hole penetrates the film stack structure and extends longitudinally into the second test semiconductor layer, or the test hole penetrates the film stack structure and the second test semiconductor layer and extends longitudinally into the first test semiconductor layer.
[0032] Furthermore, the second test semiconductor layer includes a plurality of sub-semiconductor layers arranged laterally at intervals, wherein "lateral" refers to a direction parallel to the top surface; each sub-semiconductor layer corresponds to one test hole, and the volume of each sub-semiconductor layer is smaller than the volume of the first test semiconductor layer;
[0033] The test hole penetrates the film stack structure and extends longitudinally into the corresponding sub-semiconductor layer, or the test hole penetrates the film stack structure and the corresponding sub-semiconductor layer and extends into the first test semiconductor layer.
[0034] Furthermore, the test hole and the channel hole have a channel structure, the channel structure including a channel layer and a storage medium layer disposed around the channel layer, and the channel layer in the test hole is the test conductive layer.
[0035] Furthermore, the non-storage array area includes a free area surrounding the storage array area and a slicing channel surrounding the free area;
[0036] The test block is located within at least one of the free area and the cutting channel.
[0037] Accordingly, embodiments of the present invention also provide a three-dimensional memory, including a memory array area and a free area disposed around the memory array area;
[0038] The three-dimensional memory includes a common source layer, and the memory array region includes multiple channel holes that extend longitudinally from the top surface of the three-dimensional memory away from the common source layer to the common source layer; the free area includes a test hole that extends longitudinally from the top surface to the common source layer; the sidewall of the test hole has a test conductive layer.
[0039] Furthermore, the storage array region also includes a stack layer and a first stop layer, the first stop layer being located between the stack layer and the common source layer; the channel via extends longitudinally through the stack layer and the first stop layer, and extends into the common source layer;
[0040] The free area further includes a film stack structure and a second stop layer, the second stop layer being located between the film stack structure and the common source layer; the test hole extends longitudinally through the film stack structure and the second stop layer, and extends into the common source layer.
[0041] Furthermore, the test hole and the channel hole have a channel structure, the channel structure including a channel layer and a storage medium layer disposed around the channel layer, and the channel layer in the test hole is the test conductive layer.
[0042] The beneficial effects of this invention are as follows: a test block is provided in the non-memory array area. The test block includes a test substrate and test holes. The test substrate includes multiple test semiconductor layers arranged longitudinally at intervals. Each test semiconductor layer has a different volume. The sidewall of the test hole has a test conductive layer. The test conductive layer is connected to the test semiconductor layer through which the bottom of the test hole passes or falls, so as to apply an electric field to the semiconductor device, detect the voltage contrast of the test hole, and determine whether the extension depth of the channel hole is abnormal based on the voltage contrast. This avoids the use of destructive detection methods to detect the extension depth of the channel hole and effectively improves the detection efficiency. Attached Figure Description
[0043] To more clearly illustrate the technical solutions in the embodiments or prior art, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0044] Figure 1 A top view of a semiconductor device provided in an embodiment of the present invention;
[0045] Figure 2 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;
[0046] Figure 3 This is a schematic flowchart of a semiconductor device detection method provided in an embodiment of the present invention;
[0047] Figure 4 This is a schematic diagram of a voltage contrast image in a semiconductor device detection method provided in an embodiment of the present invention;
[0048] Figure 5 Another schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;
[0049] Figure 6 This is another schematic diagram of the voltage contrast image in the semiconductor device detection method provided in the embodiments of the present invention;
[0050] Figure 7 A schematic diagram of a three-dimensional memory provided in an embodiment of the present invention. Detailed Implementation
[0051] The specific structural and functional details disclosed herein are merely representative and are intended to describe exemplary embodiments of the invention. However, the invention can be embodied in many alternative forms and should not be construed as being limited solely to the embodiments set forth herein.
[0052] In the description of this invention, it should be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more. Additionally, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion.
[0053] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0054] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms “a” and “an” as used herein are also intended to include the plural. It should also be understood that the terms “comprising” and / or “including” as used herein specify the presence of the stated features, integers, steps, operations, units, and / or components, without excluding the presence or addition of one or more other features, integers, steps, operations, units, components, and / or combinations thereof.
[0055] See Figure 1 This is a top view of a semiconductor device provided in an embodiment of the present invention. The semiconductor device may include at least one memory array region 101 and a non-memory array region 102 located outside the memory array region 101. The memory array region 101 includes a core region (not shown) and a stepped region (not shown), and the non-memory array region 102 includes a free area 103 surrounding the memory array region 101 and a dicing channel 104 surrounding the free area 103.
[0056] Figure 2 for Figure 1 A schematic diagram of the cross-section at the dashed line A1A2. (See diagram below.) Figure 2As shown, the semiconductor device provided in this embodiment of the invention includes a memory array region 101 and a non-memory array region 102. A test block 10 is disposed within the non-memory array region 102. The test block 10 can be disposed on a free area 103 or a dicing track 104 of the non-memory array region 102, or it can be disposed simultaneously on both the free area 103 and the dicing track 104 of the non-memory array region 102. Figure 1 As shown. The test block 10 includes a test substrate 1, which may include multiple test semiconductor layers 11, and the multiple test semiconductor layers 11 are arranged longitudinally at intervals, where longitudinal refers to the direction perpendicular to the top surface of the substrate 1. The multiple test semiconductor layers 11 may be spaced apart by a first insulating layer 12. The first insulating layer 12 may be silicon oxide, etc.
[0057] The bottommost test semiconductor layer among the multiple test semiconductor layers 11 is the first test semiconductor layer 11a. The first test semiconductor layer 11a can be a substrate, such as a silicon substrate, or a substrate including other element semiconductors or compound semiconductors. The other test semiconductor layers among the multiple test semiconductor layers 11 besides the first test semiconductor layer 11a can be polysilicon, etc.
[0058] The memory array region 101 includes a substrate 4, which may include multiple semiconductor layers 41, which are arranged vertically at intervals. The bottom semiconductor layer among the multiple semiconductor layers 41 is the first semiconductor layer 41a. The first semiconductor layer 41a can be a substrate, and the other semiconductor layers 41 besides the first semiconductor layer 41a can be polysilicon, etc. The test substrate 1 in the non-memory array region 102 is vertically identical to the substrate 4 in the memory array region 101, that is, the number of semiconductor layers 41 in the memory array region 101 is the same as the number of test semiconductor layers 11 in the non-memory array region 102, and they correspond one-to-one. The first test semiconductor layer 11a and the first semiconductor layer 41a are integrally formed. The other test semiconductor layers 11 and their corresponding semiconductor layers 41 are formed using the same process steps, but the other test semiconductor layers 11 and their corresponding semiconductor layers 41 are arranged laterally at intervals, where "lateral" refers to the direction parallel to the top surface of the substrate 1.
[0059] like Figure 2 As shown, the plurality of test semiconductor layers 11 in the non-memory array region 102 may include a first test semiconductor layer 11a, a second test semiconductor layer 11b, and a third test semiconductor layer 11c arranged vertically in sequence, and the first test semiconductor layer 11a, the second test semiconductor layer 11b, and the third test semiconductor layer 11c are separated by a first insulating layer 12. The first test semiconductor layer 11a may be a substrate, and the second test semiconductor layer 11b and the third test semiconductor layer 11c may be polysilicon.
[0060] The multiple semiconductor layers 41 in the memory array region 101 may include a first semiconductor layer 41a, a second semiconductor layer 41b, and a third semiconductor layer 41c. The first test semiconductor layer 11a and the first semiconductor layer 41a may be the same film layer, the second test semiconductor layer 11b and the second semiconductor layer 41b are on the same layer but spaced apart, and the third test semiconductor layer 11c and the third semiconductor layer 41c are on the same layer but spaced apart.
[0061] like Figure 2 As shown, the non-memory array region 102 may further include a film stack structure 3, which is located on the test substrate 1. The film stack structure 3 may include multiple longitudinally alternating sacrificial layers 31 and second insulating layers 32. The sacrificial layer 31 may be silicon nitride, etc., and the second insulating layer 32 may be silicon oxide, etc.
[0062] The storage array region 101 may further include a stack layer 5, which may include multiple vertically alternating interlayer sacrificial layers 51 and interlayer insulating layers 52. The interlayer sacrificial layer 51 may be silicon nitride, etc., and the interlayer insulating layer 52 may be silicon oxide, etc. The film layer stacking structure 3 and the stack layer 5 have the same number of stacked layers and correspond one-to-one. The sacrificial layer 31 and the corresponding interlayer sacrificial layer 51 may be integrally formed, that is, formed using the same process steps, and the second insulating layer 32 and the corresponding interlayer insulating layer 52 may be integrally formed, that is, formed using the same process steps.
[0063] The storage array region 101 also includes a channel hole 60, which extends longitudinally from the top surface of the semiconductor device away from the substrate 4 to the substrate 4. Specifically, the channel hole 60 extends longitudinally through the stack layer 5 and into the substrate 4.
[0064] The non-memory array region 102 also includes a test hole 2, which extends longitudinally from the top surface facing away from the test substrate 1 into the test substrate 1. Specifically, the test hole 2 extends longitudinally through the film stack structure 3 and into the test substrate 1. It should be noted that the test hole 2 and the channel via 60 are formed using the same process steps.
[0065] During the fabrication of the via 60, due to defects in the fabrication process, the via 60 may penetrate the stack layer 5 and extend longitudinally to any semiconductor layer 41 in the substrate 4. That is, the via 60 may extend into the first semiconductor layer 41a, the second semiconductor layer 41b, or the third semiconductor layer 41c. However, among the multiple semiconductor layers 41, there is only one target semiconductor layer. This target semiconductor layer refers to the semiconductor layer where the bottom of the via 60 is normally located in the actual manufacturing process. If the via 60 extends to other semiconductor layers (non-target semiconductor layers), the extension depth of the via 60 is abnormal, for example, there is an etch-through defect.
[0066] For example, when the first semiconductor layer 41a is the substrate, the second semiconductor layer 41b is the sacrificial layer, and the third semiconductor layer 41c is the stop layer, the normal via 60 needs to extend longitudinally into the interior of the second semiconductor layer 41b, i.e., the second semiconductor layer 41b is the target semiconductor layer. If the via 60 extends longitudinally into the first semiconductor layer 41a or the third semiconductor layer 41c, the extension depth of the via 60 is abnormal.
[0067] Based on this, in this embodiment of the invention, a test block 10 is provided in the non-memory array area 102, such that the test block 10 includes a test substrate 1 and a test hole 2. The test substrate 1 has multiple test semiconductor layers 11 with different volumes, and a test conductive layer 24 is provided on the sidewall of the test hole 2, so as to determine whether the extension depth of the channel hole 60 is abnormal by detecting the extension depth of the test hole 2.
[0068] In some embodiments, a test conductive layer 24 is provided on the sidewall of the test hole 2, and the test conductive layer 24 is conductive to the test semiconductor layer 11 that passes through or falls into the bottom of the test hole 2. It should be noted that after forming the channel hole 60 and the test hole 2, and before filling the channel hole 60, the test conductive layer 24 can be formed on the sidewall of the test hole 2 to detect whether the extension depth of the channel hole 60 is abnormal. If the extension depth of the channel hole 60 is abnormal, subsequent processes are not performed to save costs; if the extension depth of the channel hole 60 is normal, a channel structure is formed in the channel hole 60. Figure 2 (Not shown in the image).
[0069] In other embodiments, the structure of the test hole 2 is the same as that in the channel hole 60, that is, after the channel hole 60 and the test hole 2 are formed, a channel structure is formed in both the test hole 2 and the channel hole 60. For example... Figure 5As shown, the channel structure in the via 60 may include a longitudinally extending channel layer 21 and a storage medium layer 22 disposed around the channel layer 21. The storage medium layer 22 includes a tunneling layer (not shown in the figure) disposed around the channel layer 21, a storage layer (not shown in the figure) disposed around the tunneling layer, and a barrier layer (not shown in the figure) disposed around the storage layer. The channel structure in the via 60 may also include an isolation layer 23, with the channel layer 21 disposed around the isolation layer 23. The channel structure in the test via 2 may include a longitudinally extending channel layer (which constitutes the test conductive layer 24) and a storage medium layer 25 disposed around the channel layer (i.e., the test conductive layer 24). The structure of the storage medium layer 25 is the same as that of the storage medium layer 22 in the via 60, and will not be described in detail here. The channel structure in the test via 2 may also include an isolation layer 26, with the channel layer (i.e., the test conductive layer 24) disposed around the isolation layer 26. It should be noted that although a storage dielectric layer 25 is disposed around the channel layer (i.e., the test conductive layer 24), the channel layer (i.e., the test conductive layer 24) can be connected to the test semiconductor layer 11 that passes through or falls into at the bottom of the test hole 2 through the tunneling effect. In this embodiment, it is not necessary to form a separate test conductive layer in the test hole 2, but to use the channel layer in the test hole 2 as the test conductive layer 24, which simplifies the manufacturing process.
[0070] Accordingly, embodiments of the present invention provide a semiconductor device detection method.
[0071] like Figure 3 As shown, the semiconductor device detection method provided in this embodiment of the invention may include steps 101 to 102, as detailed below:
[0072] Step 101: Apply an electric field to the semiconductor device to detect the voltage contrast of the test hole; the direction of the electric field is from the top to the bottom of the semiconductor device.
[0073] In this embodiment of the invention, since it is uncertain which test semiconductor layer in the test substrate 1 the test hole 2 extends into longitudinally, the semiconductor device is placed in an electric field, and the direction B of the electric field points from the top to the bottom of the semiconductor device. Regardless of which test semiconductor layer the test hole 2 extends into longitudinally, the electric field can cause electrons e in the test semiconductor layer to... - The electrons move along the test conductive layer 24 in test hole 2 to the top of test hole 2, thereby detecting the voltage contrast of test hole 2. Due to the different volumes of different test semiconductor layers, the amount of electrons moving to the top of test hole 2 in different test semiconductor layers is different, that is, the voltage contrast at the top of test hole 2 is different.
[0074] Specifically, the step 101 of detecting the voltage contrast of the test hole includes:
[0075] Obtain a voltage contrast image of the top of the test hole;
[0076] The brightness of the voltage contrast image is detected.
[0077] In electronic e - When the electron scanning lens moves to the top of test hole 2, a voltage contrast image of the top of test hole 2 can be obtained. If the volume of the test semiconductor layer is large, there are more electrons in the test semiconductor layer, and more electrons move to the top of test hole 2, resulting in a brighter voltage contrast image at the top of test hole 2; if the volume of the test semiconductor layer is small, there are fewer electrons in the test semiconductor layer, and fewer electrons move to the top of test hole 2, resulting in a darker voltage contrast image at the top of test hole 2.
[0078] like Figure 2 As shown, after applying an electric field to the semiconductor device, a voltage contrast image of the top of test hole 2 is acquired, as follows. Figure 4 As shown, the brightness of the voltage contrast image at the top of test hole 2 is detected.
[0079] Step 102: Determine whether the extension depth of the channel hole is abnormal based on the voltage contrast.
[0080] In this embodiment of the invention, due to the different extension depths of the test hole 2, the volume of the test semiconductor layer 11 that the bottom of the test hole 2 passes through or falls into is different, resulting in different voltage contrasts of the test hole 2. Therefore, based on the voltage contrast of the test hole 2, it can be determined whether the extension depth of the test hole 2 is abnormal, and thus whether the extension depth of the channel hole 60 is abnormal.
[0081] In one embodiment, step 102, determining whether the channel orifice is abnormal based on the voltage contrast, includes:
[0082] If the brightness of the voltage contrast image is within a first preset range, then the extension depth of the channel hole is determined to be normal.
[0083] If the brightness of the voltage contrast image is outside the first preset range, then the extension depth of the channel hole is determined to be abnormal.
[0084] Based on the volume of the target test semiconductor layer (the test semiconductor layer corresponding to the target semiconductor layer), the amount of electrons in the target test semiconductor layer is determined, and then the brightness of the voltage contrast image extending to the top of the test hole within the target test semiconductor layer is determined. Since the extension depth of the test hole within the target test semiconductor layer varies, the volume of the target test semiconductor layer will slightly differ, resulting in slight differences in the brightness of the voltage contrast image at the top of the test hole. Furthermore, since there are errors in the detection of the volume of the target test semiconductor layer and the brightness of the voltage contrast image, a brightness range is set for the top of the voltage contrast image extending to the target test semiconductor layer, and this brightness range is used as the first preset range. During semiconductor device testing, after detecting the brightness of the voltage contrast image for each test hole, the detected brightness is compared with the first preset range. If all detected brightness values are within the first preset range, it is determined that all test holes extend into the target test semiconductor layer, and the extension depth of the test holes and the extension depth of the channel holes are normal. If any detected brightness value is outside the first preset range, it is determined that some test holes extend into other test semiconductor layers (non-target test hole semiconductor layers), and the extension depth of the test holes and the extension depth of the channel holes are abnormal.
[0085] For example, Figure 2 The target semiconductor layer is the second semiconductor layer 41b, and the brightness range of the voltage contrast image extending to the top of the test hole in the second test semiconductor layer 11b is a first preset range. Figure 4 If the voltage contrast image is relatively dark, but its brightness is within the first preset range, then it indicates... Figure 2 The test hole 2 extends into the second test semiconductor layer 11b, i.e. Figure 2 The extension depth of test hole 2 is normal. Figure 2 The extension depth of the channel hole 60 in the middle is normal.
[0086] In another embodiment, the number of test blocks is multiple; step 102, determining whether the channel orifice is abnormal based on the voltage contrast, includes:
[0087] If the brightness difference of the voltage contrast images of any two test holes is within the second preset range, then the extension depth of the channel hole is determined to be normal.
[0088] If the brightness difference between the voltage contrast images of any two test holes is outside the second preset range, then the extension depth of the channel hole is determined to be abnormal.
[0089] Because the test holes extend to different depths within the target semiconductor layer, the volume of the target semiconductor layer will vary slightly, resulting in slight differences in the brightness of the voltage contrast image at the top of the test holes. Therefore, a brightness difference range is set as the second preset range. The difference between the brightness of the voltage contrast image at the top of the test hole extending to the top of the target semiconductor layer and the brightness of the voltage contrast image at the top of the test hole extending to the bottom of the target semiconductor layer is the maximum value of the brightness difference range, and 0 is the minimum value of the brightness difference range.
[0090] The volume difference between different test semiconductor layers is much greater than the volume difference of the target test semiconductor layer caused by the different extension depths of the test holes within the target test semiconductor layer. If two test holes extend to different test semiconductor layers, the brightness difference of the voltage contrast image at the top of the two test holes is much greater than the brightness difference range. Therefore, the brightness difference range is used as a second preset range to determine whether the extension depth of the test holes is abnormal.
[0091] After acquiring the brightness of the voltage contrast image at the top of each test hole, the brightness of the voltage contrast images at the top of any two test holes is compared. If the brightness difference between the voltage contrast images at the top of any two test holes is within the second preset range, it is determined that the test holes extend into the target test semiconductor layer, and the extension depth of the test holes and the extension depth of the channel holes are normal. If the brightness difference between the voltage contrast images at the top of any two test holes is outside the second preset range, it is determined that there are test holes extending into other test semiconductor layers (non-target test semiconductor layers), and the extension depth of the test holes and the extension depth of the channel holes are abnormal.
[0092] In some embodiments, the non-memory array region includes multiple test vias. To increase the volume difference between different test semiconductor layers, each test semiconductor layer other than the first test semiconductor layer may include multiple sub-semiconductor layers arranged laterally at intervals. Each of the multiple sub-semiconductor layers in each of the other test semiconductor layers is configured to correspond one-to-one with the multiple test vias. The volumes of the sub-semiconductor layers in different test semiconductor layers may be different.
[0093] like Figure 5As shown, there are two test holes: a first test hole 2a and a second test hole 2b. The second test semiconductor layer 11b includes two sub-semiconductor layers arranged laterally, namely sub-semiconductor layer 11b-1 and sub-semiconductor layer 11b-2. The third test semiconductor layer 11c includes two sub-semiconductor layers arranged laterally, namely sub-semiconductor layer 11c-1 and sub-semiconductor layer 11c-2. The first test hole 2a corresponds to sub-semiconductor layers 11b-1 and 11c-1, and the second test hole 2b corresponds to sub-semiconductor layers 11b-2 and 11c-2. The volumes of sub-semiconductor layers 11b-1 and 11b-2 are both smaller than the volume of the first test semiconductor layer 11a, the volume of sub-semiconductor layer 11c-1 is smaller than the volume of sub-semiconductor layer 11b-1, and the volume of sub-semiconductor layer 11c-2 is smaller than the volume of sub-semiconductor layer 11b-2. The second test semiconductor layer 11b is the target test semiconductor layer.
[0094] An electric field is applied to the semiconductor device, causing electrons e passing through or falling into the test semiconductor layer at the bottom of the first test hole 2a and the second test hole 2b. - It can move to the top of the first test hole 2a and the second test hole 2b respectively through the test conductive layer 24 in the first test hole 2a and the second test hole 2b.
[0095] Then, voltage contrast images of the tops of the first test hole 2a and the second test hole 2b are obtained, such as... Figure 6 As shown, the voltage contrast image at the top of the first test hole 2a is darker (DVC, Dark Voltage Contrast), while the voltage contrast image at the top of the second test hole 2b is brighter (BVC, Bright Voltage Contrast). In one embodiment, the brightness of the voltage contrast images at the top of the first test hole 2a and the second test hole 2b is compared with a first preset range. If the brightness of the voltage contrast image at the top of the first test hole 2a is within the first preset range, it indicates that the first test hole 2a extends into the interior of the first sub-semiconductor layer 11b-1 (i.e., into the interior of the target test semiconductor layer), meaning the extension depth of the first test hole 2a is normal. If the brightness of the voltage contrast image at the top of the second test hole 2b is outside the first preset range, it indicates that the second test hole 2b extends into the interior of a non-target test semiconductor layer, meaning the extension depth of the second test hole 2b is abnormal. Because the extension depth of the second test hole 2b is abnormal, the extension depth of the channel via 60 is determined to be abnormal.
[0096] In another embodiment, the brightness of the voltage contrast images at the top of the first test hole 2a and the second test hole 2b is compared. If the brightness difference between the voltage contrast images at the top of the first test hole 2a and the second test hole 2b is within a second preset range, it indicates that the extension depth of the first test hole 2a and the second test hole 2b is normal, and the extension depth of the channel hole 60 is normal. If the brightness difference between the voltage contrast images at the top of the first test hole 2a and the second test hole 2b is outside the second preset range, it indicates that the extension depth of the first test hole 2a or the second test hole 2b is abnormal, and the extension depth of the channel hole 60 is abnormal.
[0097] As described above, the embodiments of the present invention provide a test block in the non-memory array area. The test block includes a test substrate and test holes. The test substrate includes multiple test semiconductor layers arranged longitudinally at intervals. Each test semiconductor layer has a different volume. The sidewall of the test hole has a test conductive layer. The test conductive layer is connected to the test semiconductor layer through which the bottom of the test hole passes or falls, so as to apply an electric field to the semiconductor device, detect the voltage contrast of the test hole, and determine whether the extension depth of the channel hole is abnormal based on the voltage contrast. This avoids the use of destructive detection methods to detect the extension depth of the channel hole and effectively improves the detection efficiency.
[0098] Accordingly, embodiments of the present invention also provide a three-dimensional memory.
[0099] See Figure 7 This is a schematic diagram of the structure of the three-dimensional memory provided in an embodiment of the present invention.
[0100] After the semiconductor device is tested, if the channel hole extension depth is normal (i.e., the channel hole extends into the target semiconductor layer), subsequent processes are performed on the semiconductor device to form a three-dimensional memory. If the test block 10 in the semiconductor device is only located on the dicing track 104, the dicing track 104 is cut after the three-dimensional memory is fabricated to remove the dicing track 104 and the test block 10 on it; that is, the three-dimensional memory no longer contains the test block 10. If the test block 10 in the semiconductor device is located in the free area 103, the test block 10 is retained in the three-dimensional memory.
[0101] like Figure 7As shown, the three-dimensional memory may include a memory array region 101 and a free space region 103 surrounding the memory array region 101. The memory array region 101 may include a plurality of vias 60, in which a channel structure is formed. The channel structure may include a longitudinally extending channel layer 21 and a memory medium layer 22 surrounding the channel layer 21. The memory medium layer 22 includes a tunneling layer (not shown) surrounding the channel layer 21, a memory layer (not shown) surrounding the tunneling layer, and a barrier layer (not shown) surrounding the memory layer. The channel structure may also include an isolation layer 23, around which the channel layer 21 is disposed.
[0102] The free space 103 may include a test hole 2, the sidewall of which has a test conductive layer 24, or the test hole 2 may have the same structure as the channel hole 60, that is, the test hole 2 has a channel layer (i.e., test conductive layer 24) and a storage medium layer 25 disposed around the channel layer (i.e., test conductive layer 24). The test hole 2 may also have an isolation layer 26, with the channel layer (i.e., test conductive layer 24) disposed around the isolation layer 26.
[0103] The memory array region 101 may further include a stacked layer 5, which may include multiple vertically alternating interlayer gate layers 53 and interlayer insulating layers 52. A channel via 60 extends vertically through the stacked layer 5. The idle region 103 may further include a film stack structure 3, which may include multiple vertically alternating gate layers 33 and a second insulating layer 32. A test via 2 extends vertically through the film stack structure 3. The film stack structure 3 has the same number of stacked layers as the stacked layer 5, and they correspond one-to-one. The gate layer 33 and the corresponding interlayer gate layer 53 can be integrally formed, i.e., formed using the same process steps; similarly, the second insulating layer 32 and the corresponding interlayer insulating layer 52 can be integrally formed, i.e., formed using the same process steps.
[0104] After the semiconductor device testing is completed, and during the formation of the three-dimensional memory, the substrate 4 in the storage array region 101 and the test substrate 1 in the idle region 103 of the semiconductor device are etched, leaving only the top semiconductor layer in the substrate 4 (e.g., Figure 2 The third semiconductor layer 41c in the test substrate 1 and the test semiconductor layer on top of the test substrate 1 (such as the test semiconductor layer 41c in the test substrate 1) Figure 2The third test semiconductor layer 11c) in the test hole 2 has a top semiconductor layer that can serve as a first stop layer 71 and a top test semiconductor layer that can serve as a second stop layer 72. When there is a channel structure in the channel hole 60 and the test hole 2, the storage dielectric layer 22 in the channel hole 60 and the storage dielectric layer 25 in the test hole 2 are also etched to remove the storage dielectric layer 22 on the side of the first stop layer 71 facing away from the stack layer 4, and to remove the storage dielectric layer 25 on the side of the second stop layer 72 facing away from the film stack structure 3. Then, a common source layer 8 is formed at the bottom of the first stop layer 71 and the second stop layer 72.
[0105] Therefore, the three-dimensional memory may further include a common source layer 8 located in the memory array region 101 and the free region 103, a first stop layer 71 located in the memory array region 101, and a second stop layer 72 located in the free region 103. The first stop layer 71 is located between the stack layer 4 and the common source layer 8, and the second stop layer 72 is located between the film stack structure 3 and the common source layer 8. The channel layer 21 in the channel via 60 penetrates the stack layer 5 and the first stop layer 71 and extends into the common source layer 8, and the channel layer (i.e., the conductive test layer 24) in the test via 2 penetrates the film stack structure 3 and the second stop layer 72 and extends into the common source layer 8. The common source layer 8 may be a semiconductor layer such as polysilicon.
[0106] In summary, although the present invention has been disclosed above with reference to preferred embodiments, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.
Claims
1. A method for testing semiconductor devices, characterized in that, The semiconductor device includes a memory array region and a non-memory array region. The memory array region includes a substrate and multiple channel vias. The channel vias extend longitudinally from the top surface of the semiconductor device away from the substrate to the substrate. A test block is disposed in the non-memory array region. The test block includes a test substrate that is longitudinally identical to the substrate and test vias extending longitudinally from the top surface to the test substrate. The test substrate includes multiple test semiconductor layers that are longitudinally spaced apart, and each test semiconductor layer has a different volume. The test hole has a test conductive layer on its sidewall, and the test conductive layer is in communication with the test semiconductor layer that passes through or falls into the bottom of the test hole; The longitudinal direction refers to the direction perpendicular to the top surface; The method includes: An electric field is applied to the semiconductor device to detect the voltage contrast of the test aperture; the direction of the electric field is from the top to the bottom of the semiconductor device. Based on the voltage contrast, determine whether the extension depth of the channel hole is abnormal.
2. The semiconductor device testing method according to claim 1, characterized in that, The step of detecting the voltage contrast of the test hole includes: Obtain a voltage contrast image of the top of the test hole; The brightness of the voltage contrast image is detected.
3. The semiconductor device testing method according to claim 2, characterized in that, The step of determining whether the channel orifice is abnormal based on the voltage contrast includes: If the brightness of the voltage contrast image is within a first preset range, then the extension depth of the channel hole is determined to be normal. If the brightness of the voltage contrast image is outside the first preset range, then the extension depth of the channel hole is determined to be abnormal.
4. The semiconductor device testing method according to claim 2, characterized in that, The number of test blocks is multiple; The step of determining whether the channel orifice is abnormal based on the voltage contrast includes: If the brightness difference of the voltage contrast images of any two test holes is within the second preset range, then the extension depth of the channel hole is determined to be normal. If the brightness difference between the voltage contrast images of any two test holes is outside the second preset range, then the extension depth of the channel hole is determined to be abnormal.
5. The semiconductor device testing method according to claim 1, characterized in that, The non-memory array region also includes a film layer stacking structure, and the plurality of test semiconductor layers include a first test semiconductor layer and a second test semiconductor layer, wherein the volume of the second test semiconductor layer is smaller than the volume of the first test semiconductor layer; The film stack structure is located on the substrate, and the second test semiconductor layer is located on the side of the first test semiconductor layer close to the film stack structure; The test hole penetrates the film stack structure and extends longitudinally into the second test semiconductor layer, or the test hole penetrates the film stack structure and the second test semiconductor layer and extends longitudinally into the first test semiconductor layer.
6. The semiconductor device testing method according to claim 5, characterized in that, The second test semiconductor layer includes a plurality of sub-semiconductor layers arranged laterally at intervals, wherein "lateral" refers to a direction parallel to the top surface; each sub-semiconductor layer corresponds to one test hole, and the volume of each sub-semiconductor layer is smaller than the volume of the first test semiconductor layer; The test hole penetrates the film stack structure and extends longitudinally into the corresponding sub-semiconductor layer, or the test hole penetrates the film stack structure and the corresponding sub-semiconductor layer and extends into the first test semiconductor layer.
7. The semiconductor device testing method according to claim 1, characterized in that, The test hole and the channel hole have a channel structure, the channel structure includes a channel layer and a storage medium layer disposed around the channel layer, and the channel layer in the test hole is the test conductive layer.
8. The semiconductor device testing method according to claim 1, characterized in that, The non-memory array region includes a free area surrounding the memory array region and a slicing channel surrounding the free area; The test block is located within at least one of the free area and the cutting channel.
9. A semiconductor device, characterized in that, The semiconductor device includes a memory array region and a non-memory array region. The memory array region includes a substrate and multiple vias. The vias extend longitudinally from the top surface of the semiconductor device away from the substrate to the substrate. A test block is disposed within the non-memory array region. The test block includes a test substrate that is longitudinally identical to the substrate and test vias extending longitudinally from the top surface to the test substrate. The test substrate includes multiple test semiconductor layers spaced longitudinally, each test semiconductor layer having a different volume. The longitudinal direction refers to the direction perpendicular to the top surface. The test hole has a test conductive layer on its sidewall, and the test conductive layer is connected to the test semiconductor layer that passes through or falls into the bottom of the test hole.
10. The semiconductor device according to claim 9, characterized in that, The non-memory array region also includes a film layer stack structure, and the plurality of test semiconductor layers include a first test semiconductor layer and a second test semiconductor layer, wherein the volume of the second test semiconductor layer is smaller than the volume of the first test semiconductor layer; The film stack structure is located on the substrate, and the second test semiconductor layer is located on the side of the first test semiconductor layer close to the film stack structure; The test hole penetrates the film stack structure and extends longitudinally into the second test semiconductor layer, or the test hole penetrates the film stack structure and the second test semiconductor layer and extends longitudinally into the first test semiconductor layer.
11. The semiconductor device according to claim 10, characterized in that, The second test semiconductor layer includes a plurality of sub-semiconductor layers arranged laterally at intervals, wherein "lateral" refers to a direction parallel to the top surface; each sub-semiconductor layer corresponds to one test hole, and the volume of each sub-semiconductor layer is smaller than the volume of the first test semiconductor layer; The test hole penetrates the film stack structure and extends longitudinally into the corresponding sub-semiconductor layer, or the test hole penetrates the film stack structure and the corresponding sub-semiconductor layer and extends into the first test semiconductor layer.
12. The semiconductor device according to claim 9, characterized in that, The test hole and the channel hole have a channel structure, the channel structure includes a channel layer and a storage medium layer disposed around the channel layer, and the channel layer in the test hole is the test conductive layer.
13. The semiconductor device according to claim 9, characterized in that, The non-memory array region includes a free area surrounding the memory array region and a slicing channel surrounding the free area; The test block is located within at least one of the free area and the cutting channel.
14. A three-dimensional memory, characterized in that, Formed by the semiconductor device according to any one of claims 9 to 13, and comprising a memory array region and a free area disposed around the memory array region; The three-dimensional memory includes a common source layer, and the memory array region includes multiple channel holes. The channel holes extend longitudinally from the top surface of the three-dimensional memory away from the common source layer to the common source layer. The free area includes a test hole extending longitudinally from the top surface to the common source layer. The sidewall of the test hole has a test conductive layer.
15. The three-dimensional memory according to claim 14, characterized in that, The storage array region further includes a stack layer and a first stop layer, the first stop layer being located between the stack layer and the common source layer; the channel via extends longitudinally through the stack layer and the first stop layer, and extends into the common source layer; The free area further includes a film stack structure and a second stop layer, the second stop layer being located between the film stack structure and the common source layer; the test hole extends longitudinally through the film stack structure and the second stop layer, and extends into the common source layer.
16. The three-dimensional memory according to claim 14, characterized in that, The test hole and the channel hole have a channel structure, the channel structure includes a channel layer and a storage medium layer disposed around the channel layer, and the channel layer in the test hole is the test conductive layer.
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