Method of forming a semiconductor device

Abstract

The present invention provides a method for forming a semiconductor device, including providing a substrate, on which there is a dielectric layer with a through hole inside, and the bottom of the through hole exposes the top surface of a conductive layer inside the substrate; etching the exposed top surface of the conductive layer by a sputter etching process to form a concave groove in the conductive layer; forming a sacrificial layer on the sidewalls and bottom of the concave groove and on the sidewalls of the through hole; after forming the sacrificial layer, removing the sacrificial layer; on the one hand, using the sputter etching process to etch the concave groove to ensure the etched shape of the concave groove; on the other hand, forming a sacrificial layer, and the sacrificial layer serves as a buffer layer. During the process of removing the sacrificial layer, part of the conductive layer will be removed while part of the conductive layer at the bottom of the sacrificial layer will be oxidized. This kind of loss and oxidation can be well controlled to ensure a consistent contact resistance at the bottom of the through hole, which is convenient for improving the performance of the finally formed semiconductor device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular, to a method for forming a semiconductor device. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher element density and higher integration. As the most basic semiconductor devices, devices are currently widely used. The ability of traditional planar devices to control channel current becomes weak, resulting in short-channel effects and leakage current, ultimately affecting the electrical performance of semiconductor devices.

[0003] During the manufacturing process of semiconductor devices, contact holes need to be formed on the source region, drain region, or gate structure of transistors, etc. Then, a conductive material is filled in the contact holes to form a conductive layer. After forming the conductive layer, a metal layer needs to be formed on the conductive layer as a connection layer with metal layer 1 (M1), so as to achieve the electrical connection between the transistor and the outside. However, during the process of forming the metal layer on the conductive layer, the conductive layer will be damaged, resulting in the absence of the conductive layer, making the interface connection between the conductive layer and the metal layer very different, resulting in a large difference in contact resistance, and thus resulting in a large electrical difference in the performance of the formed semiconductor device, affecting the yield of the formed semiconductor device, and limiting the use of semiconductor devices.

[0004] Therefore, how to ensure the quality of the formed conductive layer, ensure a small difference in the interface connection between the conductive layer and the metal layer, ensure the consistency of the electrical performance of the formed semiconductor device, and thus improve the performance of the finally formed semiconductor device is an urgent problem to be solved at present. Summary of the Invention

[0005] The problem solved by the present invention is to provide a method for forming a semiconductor device, which ensures that the formed semiconductor device has high quality.

[0006] To solve the above problems, the present invention provides a method for forming a semiconductor device, including providing a substrate, a dielectric layer is provided on the substrate, through holes are provided in the dielectric layer, and the top surface of the conductive layer in the substrate is exposed at the bottom of the through holes; etching the exposed top surface of the conductive layer by a sputtering etching process to form a concave groove in the conductive layer; forming a sacrificial layer on the side walls and bottom of the concave groove and the side walls of the through holes; after forming the sacrificial layer, removing the sacrificial layer.

[0007] Optionally, the parameters of the sputtering etching process include using argon, wherein the flow rate of argon is 0 - 50 sccm, the source radio frequency power is 200W - 1000W, and the bias power is 200W - 1000W.

[0008] Optionally, after removing the sacrificial layer, the method further includes: forming a metal layer in the through hole and the concave groove.

[0009] Optionally, after removing the sacrificial layer and before forming the metal layer, the method further includes: performing a reduction treatment on the surface of the conductive layer at the bottom of the concave groove.

[0010] Optionally, the parameters of the reduction treatment include: a mixed gas of argon and hydrogen, wherein the flow rate of the mixed gas is 0 - 1000 sccm, the source radio frequency power is 200W - 1000W, and the bias power is 200W - 1000W.

[0011] Optionally, the material of the sacrificial layer is titanium nitride, tantalum nitride, or amorphous silicon.

[0012] Optionally, the step of forming the metal layer includes: forming an initial metal layer in the through hole, the concave groove, and on the dielectric layer; planarizing the initial metal layer until the surface of the dielectric layer is exposed to form the metal layer.

[0013] Optionally, the process of forming the initial metal layer is chemical vapor deposition process, selective growth process, or physical vapor deposition process.

[0014] Optionally, the thickness of the sacrificial layer is less than or equal to

[0015] Optionally, the concave groove has a "U" - shaped groove structure.

[0016] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0017] After exposing the conductive layer in the substrate, a sputter etching process is used to etch the top surface of the exposed conductive layer to form a concave groove; a sacrificial layer is formed on the sidewalls and bottom of the concave groove and on the sidewalls of the through hole; then the sacrificial layer is removed, and a metal layer is formed in the through hole and the concave groove; on the one hand, the sputter etching process is used to etch the concave groove to ensure the etching shape of the concave groove; on the other hand, a sacrificial layer is formed, and the sacrificial layer serves as a buffer layer. During the process of removing the sacrificial layer, part of the conductive layer will be taken away while part of the conductive layer at the bottom of the sacrificial layer will be oxidized. This kind of loss and oxidation can be well controlled. Since part of the conductive layer is taken away during the process of removing the sacrificial layer, the size of the concave groove in the horizontal direction becomes larger. In this way, during the subsequent process of forming the metal layer, the damage caused by the etching solution to the bottom conductive layer during the planarization of the metal layer is reduced. This is because the size of the concave groove in the horizontal direction becomes larger, increasing the flow path of the etching solution, and at the same time, the capillary effect is reduced, thereby reducing the damage caused by the etching solution to the conductive layer at the bottom of the metal layer, reducing the difference in the connection between the metal layer and the conductive layer, ensuring a consistent contact resistance, and facilitating the improvement of the performance of the finally formed semiconductor device. Description of the Drawings

[0018] Figures 1 to 3 is a schematic structural diagram of the formation process of a semiconductor device in an embodiment;

[0019] Figures 4 to 9 is a schematic structural diagram of the formation process of a semiconductor device in an embodiment of the present invention. Detailed Embodiments

[0020] During the formation process of a semiconductor device, after forming a conductive layer, it is necessary to form a through hole in the conductive layer and form a metal layer in the through hole to form a connection with the upper metal layer 1 (M1). In this way, when in use, the connection between the transistor and the external circuit can be realized. For a transistor, a lot of conductive layers need to be formed, and correspondingly, metal layers in the through holes are required. However, currently, during the process of forming the metal layer, not only is the difference in the interface connection between the conductive layer and the metal layer in the through hole large, but also the difference in the connection between the conductive layers and the metal layers in different through holes is large, resulting in inconsistent contact resistances at the bottoms of the through holes, and thus the performance of the formed semiconductor device is consistently poor, affecting the use of the semiconductor device.

[0021] For the convenience of description, only one conductive layer is shown in the drawings.

[0022] First, refer to Figure 1 , a substrate 100 is provided, a dielectric layer 101 is provided on the substrate 100, a through hole 102 is provided in the dielectric layer 101, and the top surface of the conductive layer 103 in the substrate 100 is exposed at the bottom of the through hole 102.

[0023] Please refer toFigure 2 Wet-etch the top surface of the conductive layer 103 at the bottom of the through hole 102 to form a concave groove 104.

[0024] Please refer to Figure 3 A metal layer 105 is formed in the concave groove 104 and in the through hole 102.

[0025] The step of forming the metal layer 105 includes: forming an initial metal layer (not shown in the figure) in the concave groove 104, in the through hole 102, and on the surface of the dielectric layer 101, and planarizing the initial metal layer until the surface of the dielectric layer 101 is exposed to form the metal layer 105.

[0026] The inventors found that when wet-etching the top surface of the conductive layer 103 at the bottom of the through hole 102 to form the concave groove 104, the shape of the concave groove 104 is uncontrollable, resulting in a large difference in the contact interface between the metal layer 105 and the conductive layer 103, and a large difference in the contact resistance within the through hole 102; at the same time, during the process of forming the metal layer 105, during the planarization process, the etching solution will penetrate along the gap between the metal layer 105 and the dielectric layer 101 to the surface of the conductive layer 103, causing damage to the conductive layer 103, resulting in the loss of the conductive layer 103, reducing the performance of the formed semiconductor device, and limiting the use of the semiconductor device.

[0027] The inventors' research found that after exposing the conductive layer in the substrate, the sputter etching process is used to etch the top surface of the exposed conductive layer to form a concave groove; a sacrificial layer is formed on the side wall and bottom of the concave groove and on the side wall of the through hole; then the sacrificial layer is removed, and a metal layer is formed in the through hole and the concave groove; on the one hand, the sputter etching process is used to etch the concave groove to ensure the etched shape of the concave groove; on the other hand, a sacrificial layer is formed, and the sacrificial layer serves as a buffer layer. During the process of removing the sacrificial layer, part of the conductive layer will be removed while part of the conductive layer at the bottom of the sacrificial layer will be oxidized. This loss and oxidation can be well controlled. Since part of the conductive layer is removed during the process of removing the sacrificial layer, the size of the concave groove in the transverse direction becomes larger. In this way, during the subsequent process of forming the metal layer, the damage caused by the etching solution to the bottom conductive layer during the planarization of the metal layer is reduced. This is because the size of the concave groove in the transverse direction becomes larger, increasing the flow path of the etching solution, and at the same time the capillary effect is reduced, thereby reducing the damage caused by the etching solution to the conductive layer at the bottom of the metal layer, reducing the difference in the connection between the metal layer and the conductive layer, ensuring a consistent contact resistance, and facilitating the improvement of the performance of the finally formed semiconductor device.

[0028] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following will describe in detail the specific embodiments of the present invention with reference to the accompanying drawings.

[0029] Figures 4 to 9 It is a schematic structural diagram of the process of forming a semiconductor device in an embodiment of the present invention.

[0030] First, referring to Figure 4 , a substrate 200 is provided. A dielectric layer 201 is provided on the substrate 200. A via hole 202 is provided in the dielectric layer 201. The bottom of the via hole 202 exposes the top surface of a conductive layer 203 in the substrate 200.

[0031] In this embodiment, the bottom of the via hole 202 exposes a partial top surface of the conductive layer 203.

[0032] In this embodiment, the substrate 200 further includes a substrate. The conductive layer 203 is located on the substrate, and includes storage devices and logic devices on the substrate, etc.

[0033] In this embodiment, the conductive layer 203 is a metal layer, formed above the source-drain doping layer, for realizing the electrical connection between the source-drain doping layer and the outside.

[0034] In this embodiment, the material of the conductive layer 203 is cobalt (Co); in other embodiments, the material of the conductive layer 203 can also be metal materials such as copper and aluminum.

[0035] In this embodiment, only one conductive layer 203 in the substrate 200 is schematically shown.

[0036] In this embodiment, the material of the dielectric layer 201 is silicon oxide.

[0037] In other embodiments, the material of the dielectric layer 201 can also be silicon nitride, silicon boron nitride, silicon carbon oxynitride, or silicon oxynitride, etc.

[0038] In this embodiment, the dielectric layer 201 is formed by chemical vapor deposition. The process parameters of the chemical vapor deposition process include that the gases used include oxygen, ammonia (NH3), and N(SiH3)3 gas. The flow rate of oxygen is 20 sccm to 10000 sccm, the flow rate of ammonia (NH3) gas is 20 sccm to 10000 sccm, the flow rate of N(SiH3)3 gas is 20 sccm to 10000 sccm, the chamber pressure is 0.01 to 10 Torr, and the temperature is 30°C to 90°C.

[0039] In this embodiment, the process of forming the via hole 202 is a dry etching process; in other embodiments, a wet etching process can also be used to form the via hole 202.

[0040] In this embodiment, the parameters of the dry etching process include: the gases used include CF4 and CH3F, the flow rate of CF4 is 20 sccm to 200 sccm, the flow rate of CH3F is 20 sccm to 50 sccm, the source radio frequency power is 200 watts to 500 watts, and the chamber pressure is 1 torr to 10 torr.

[0041] In this embodiment, the reason for using the dry etching process is that during the dry etching process, the longitudinal etching rate is greater than the lateral etching rate. In this way, during the formation of the through hole 202, the influence on the cross section of the through hole 202 in the lateral direction can be reduced.

[0042] In this embodiment, the purpose of forming the through hole 202 is to provide space for forming a metal layer on the surface of the conductive layer 203 subsequently.

[0043] Please refer to Figure 5 , and the top surface of the exposed conductive layer 203 is etched by a sputter etching process to form a concave groove 204 in the conductive layer 203.

[0044] In this embodiment, the concave groove 204 has a "U" - shaped groove structure.

[0045] In this embodiment, the advantage of setting the concave groove 204 as a "U" - shaped groove structure is that during the subsequent process of removing the sacrificial layer, the concave groove 204 is likely to expand laterally (in the X direction). In this way, the length of the concave groove 204 in the lateral direction increases, so that during the formation of the metal layer, the flow path of the etching solution is increased, the etching solution reaching the surface of the conductive layer 203 is reduced, and thus the damage and loss caused to the conductive layer 203 by the etching solution are reduced, which helps to improve the quality of the conductive layer 203.

[0046] In this embodiment, the parameters of the sputter etching process include using argon gas, where the flow rate of argon (Ar) is 0 to 50 sccm, the source radio frequency power is 200 W to 1000 W, and the bias power is 200 W to 1000 W.

[0047] In this embodiment, the concave groove 204 is formed by a sputter etching process. The purpose is that the sputter etching process can well control the shape of the formed concave groove 204, and at the same time can control the surface quality of the concave groove 204, ensuring that the concave groove 204 has uniform flatness everywhere. On the one hand, this can ensure that when the metal layer is formed subsequently, the interface difference between the metal layer and the concave groove 204 is reduced; on the other hand, when the metal layer is formed in the concave groove 204 at the bottom of different through holes, due to the small difference in the shape of different concave grooves 204, it is ensured that the interface difference between the metal layers in different through holes and the conductive layer 203 is small, thereby ensuring that the contact resistance difference in different through holes is small, and improving the uniformity of the electrical performance of the formed semiconductor device.

[0048] Please refer to Figure 6 , and a sacrificial layer 205 is formed on the side wall and bottom of the concave groove 204 and the side wall of the through hole 202.

[0049] In this embodiment, the material of the sacrificial layer 205 is titanium nitride (TiN);

[0050] In other embodiments, the material of the sacrificial layer 205 can also be tantalum nitride (TaN) or amorphous silicon (α-Si).

[0051] In this embodiment, the sacrificial layer 205 plays a buffering role, so that the conductive layer 203 at the bottom of the concave groove 204 will not be lost too much in the subsequent process, and the loss of the conductive layer 203 can be well controlled.

[0052] In this embodiment, the reason why the sacrificial layer 205 can play a buffering role is as follows: It replaces the traditional method of directly wet etching to expand the concave groove 204 in the transverse direction (X-axis direction). By removing the sacrificial layer 205, part of the conductive layer 203 at the bottom is taken away. On the one hand, this makes the concave groove 204 expand in the transverse direction, increasing the length of the concave groove 204 in the transverse direction. On the other hand, it helps to control the missing amount of the conductive layer 203, thereby playing a buffering role.

[0053] In this embodiment, the process for forming the sacrificial layer 205 is an atomic layer deposition process; in other embodiments, the process for forming the sacrificial layer 205 can also be a chemical vapor deposition process, a physical vapor deposition process, etc.

[0054] In this embodiment, the reason for using the atomic layer deposition process to form the sacrificial layer 205 is that it can ensure that the formed sacrificial layer 205 has good uniformity and coverage gradient.

[0055] In this embodiment, the thickness of the sacrificial layer 205 is less than or equal to When the thickness of the sacrificial layer 205 is greater than At this time, the formed sacrificial layer 205 is too thick, and the time required to remove the sacrificial layer 205 will be longer; and because it is too thick, it is not easy to remove it completely; at the same time, because the time required to remove the sacrificial layer 205 is longer, the amount of the conductive layer 203 oxidized at the bottom is more, so the subsequent reduction time will be longer, and it is easy to have the phenomenon that the reduction is not complete, thus affecting the performance of the finally formed semiconductor device.

[0056] Please refer to Figure 7 , after forming the sacrificial layer 205, remove the sacrificial layer 205.

[0057] In this embodiment, during the process of removing the sacrificial layer 205, part of the conductive layer 203 will be removed at the same time, and due to the action of the etching solution, the surface of the conductive layer 203 in contact with the sacrificial layer 205 will be oxidized to form an oxide 207, which makes the size of the concave groove 204 in the transverse direction (X-axis) larger. In this way, when the etching solution used in the planarization process does not reach the surface of the conductive layer 203 in time during the planarization process, the planarization process has ended and the metal layer has been formed, reducing the damage to the conductive layer 203.

[0058] In this embodiment, the process for removing the sacrificial layer 205 is to use a mixed solution of hydrogen peroxide with a concentration of 1% - 10% and ammonia water with a concentration of 1% - 10%, and the temperature is 50°C - 70°C.

[0059] Please refer to Figure 8 , perform a reduction treatment on the surface of the conductive layer 203 at the bottom of the concave groove 204.

[0060] In this embodiment, since the conductive layer 203 in contact with the bottom of the sacrificial layer 205 will be oxidized to form an oxide during the process of removing the sacrificial layer 205, if the oxide is not reduced to a metal substance at this time, it will cause the contact resistance at the bottom of the through hole 202 to increase, resulting in the phenomenon of easy heating during the formation of the semiconductor device, restricting the use of the semiconductor device.

[0061] In this embodiment, the parameters of the reduction treatment include: a mixed gas of argon and hydrogen, where the flow rate of the mixed gas is 0 - 1000 sccm, the source radio frequency power is 200W - 1000W, the bias power is 200W - 1000W, and the temperature is room temperature.

[0062] Please refer to Figure 9 , form a metal layer 206 in the through hole 202 and the concave groove 204.

[0063] The steps of forming the metal layer 206 include: forming an initial metal layer (not shown in the figure) in the through holes 202, the concave grooves 204 and on the dielectric layer 201; planarizing the initial metal layer until the surface of the dielectric layer 201 is exposed to form the metal layer 206.

[0064] In this embodiment, during the process of removing the sacrificial layer 205, part of the conductive layer 203 is removed, which makes the size of the concave groove 204 increase in the lateral direction. In this way, during the process of planarizing the initial metal layer, the flow path for the etching solution to reach the surface of the conductive layer 203 becomes larger, and at the same time, the capillary effect is reduced. As a result, the damage to the conductive layer at the bottom of the metal layer caused by the etching solution during the planarizing process is reduced, the difference in the connection between the metal layer and the conductive layer is reduced, a consistent contact resistance is ensured, and it is convenient to improve the performance of the finally formed semiconductor device.

[0065] In this embodiment, the process of forming the initial metal layer is a selective growth process.

[0066] In other embodiments, the process of forming the initial metal layer can also be a chemical vapor deposition process or a physical vapor deposition process.

[0067] In this embodiment, the material of the initial metal layer is tungsten.

[0068] In other embodiments, the material of the initial metal layer can also be Ru, cobalt (Co), or titanium (Ti).

[0069] In this embodiment, the reason for using the selective growth process to form the initial metal layer is that the selectively grown initial metal layer grows from the bottom upwards, which can ensure that the formed initial metal layer is dense inside and there are no hole defects inside, thus ensuring the performance of the formed semiconductor device.

[0070] In this embodiment, the process parameters for forming the initial metal layer include: the reaction gases include WF6 gas and H2, where the gas flow rate of the WF6 gas is 50 - 1000 sccm and the gas flow rate of the H2 gas is 500 - 20000 sccm; the reaction temperature is 100 - 400 °C; the chamber pressure is 2 - 100 Torr.

[0071] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor device, characterized in that, Including: Providing a substrate, on which there is a dielectric layer, and there are through holes in the dielectric layer, and the bottom of the through holes exposes the top surface of the conductive layer in the substrate; Etching the exposed top surface of the conductive layer by using a sputtering etching process to form a concave groove in the conductive layer; Forming a sacrificial layer on the side walls and the bottom of the concave groove and on the side walls of the through holes; After forming the sacrificial layer, removing the sacrificial layer to take away part of the bottom conductive layer so that the concave groove expands laterally; 2. The forming method according to claim 1, characterized in that, The parameters of the sputtering etching process include using argon gas, wherein the flow rate of argon gas is 0 - 50 sccm, the source radio frequency power is 200 W - 1000 W, and the bias power is 200 W - 1000 W; 3. The forming method according to claim 1, wherein After removing the sacrificial layer, it further includes: forming a metal layer in the through holes and the concave groove; 4. The forming method according to claim 3, characterized in that, After removing the sacrificial layer and before forming the metal layer, it further includes: performing a reduction treatment on the surface of the conductive layer at the bottom of the concave groove; 5. The forming method according to claim 4, wherein The parameters of the reduction treatment include: a mixed gas of argon gas and hydrogen gas, wherein the flow rate of the mixed gas is 0 - 1000 sccm, the source radio frequency power is 200 W - 1000 W, and the bias power is 200 W - 1000 W; 6. The forming method according to claim 1, wherein The material of the sacrificial layer is titanium nitride or tantalum nitride or amorphous silicon; 7. The forming method according to claim 3, characterized in that, The step of forming the metal layer includes: Forming an initial metal layer in the through holes, the concave groove and on the dielectric layer; Planarizing the initial metal layer until the surface of the dielectric layer is exposed to form the metal layer; 8. The forming method according to claim 7, wherein The process of forming the initial metal layer is chemical vapor deposition process, selective growth process or physical vapor deposition process; 9. The forming method according to claim 1, wherein The thickness of the sacrificial layer is less than or equal to 35 Å; 10. The forming method according to claim 1, wherein, The concave groove is a "U"-shaped groove structure.

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