Method for forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate having a first interconnect structure therein and exposing the surface of the first interconnect structure on the surface of the substrate; forming a plurality of overlapping composite dielectric structures on the surface of the substrate, each composite dielectric structure including a first dielectric layer and a second dielectric layer located on the surface of the first dielectric layer; forming an initial second interconnect structure on the surface of the first interconnect structure within the composite dielectric structure; after forming the initial second interconnect structure, performing a repair process on at least one layer of the first dielectric layer to release the stress in the first dielectric layer towards the initial second interconnect structure; after the repair process, planarizing the initial second interconnect structure until the surface of the composite dielectric structure with the smallest distance from the substrate surface is exposed, forming a second interconnect structure. Thus, the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and particularly to a method for forming a semiconductor structure. Background Art

[0002] Currently, in the process of semiconductor manufacturing, it is a widely used process to form an opening in an interlayer dielectric layer by an etching process, and then fill a conductive material in the opening to form an electrical connection structure for electrical connection between semiconductor devices.

[0003] However, the performance of the existing semiconductor structure is still poor. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.

[0005] To solve the above technical problem, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate having a first interconnect structure therein and exposing the surface of the first interconnect structure on the surface of the substrate; forming a plurality of overlapping composite dielectric structures on the surface of the substrate, each composite dielectric structure including a first dielectric layer and a second dielectric layer located on the surface of the first dielectric layer; forming an initial second interconnect structure on the surface of the first interconnect structure within the composite dielectric structure; after forming the initial second interconnect structure, performing a repair process on at least one layer of the first dielectric layer to release the stress in the first dielectric layer towards the initial second interconnect structure; after the repair process, planarizing the initial second interconnect structure until the surface of the composite dielectric structure with the smallest distance from the surface of the substrate is exposed, to form a second interconnect structure.

[0006] Optionally, the process of the repair process includes heat treatment.

[0007] Optionally, the temperature range of the heat treatment is from 300°C to 500°C.

[0008] Optionally, the thickness range of the first dielectric layer is from 2 nanometers to 10 nanometers, and the thickness range of the second dielectric layer is from 20 nanometers to 50 nanometers.

[0009] Optionally, the number of the composite dielectric structures is 2 layers, and the object of the repair process is the first dielectric layer with a larger distance between the bottom surface and the surface of the substrate in the direction perpendicular to the surface of the substrate among the 2 layers of composite dielectric structures.

[0010] Optionally, the number of the composite dielectric structures is more than 3 layers, and the object of the repair process is the first dielectric layer of multiple layers of composite dielectric structures among the 3 layers.

[0011] Optionally, the method of forming the initial second interconnect structure includes: after forming a plurality of the composite dielectric structures, forming second interconnect openings in the plurality of the composite dielectric structures, with the surface of the first interconnect structure exposed at the bottom of the second interconnect openings; and forming the initial second interconnect structure in the second interconnect openings by using a selective metal chemical vapor deposition process.

[0012] Optionally, when the number of the composite dielectric structures is more than two layers, the method of planarizing the initial second interconnect structure further includes: performing a first planarization process on the initial second interconnect structure until the surface of the first dielectric layer with the smallest distance from the substrate surface and having undergone the repair process is exposed; and after the first planarization process, performing a second planarization process on the initial second interconnect structure until the second interconnect structure is formed.

[0013] Optionally, it further includes: after performing the first planarization process and before performing the second planarization process, performing a cleaning process on the surface of the composite dielectric structure and the surface of the initial second interconnect structure.

[0014] Optionally, the material of the first interconnect structure includes cobalt.

[0015] Optionally, the material of the second interconnect structure includes tungsten.

[0016] Optionally, the material of the first dielectric layer includes silicon nitride.

[0017] Optionally, the material of the second dielectric layer includes silicon oxide.

[0018] Optionally, the substrate includes a substrate and a third dielectric layer on the surface of the substrate, and the first interconnect structure is located within the third dielectric layer.

[0019] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0020] In the method for forming a semiconductor structure provided by the technical solution of the present invention, each layer of the composite dielectric structure includes a first dielectric layer and a second dielectric layer located on the surface of the first dielectric layer. Moreover, after forming the initial second interconnect structure in the composite dielectric structure, at least one layer of the first dielectric layer is repaired to release the stress in the first dielectric layer towards the initial second interconnect structure. Therefore, through the stress towards the initial second interconnect structure, the side wall surface of the first dielectric layer can be extruded towards the initial second interconnect structure, so as to reduce the gap between the side wall surface of the initial second interconnect structure and the first dielectric layer. Thus, the risk of the polishing liquid used for planarizing the initial second interconnect structure penetrating into the first interconnect structure is reduced, the corrosion of the first interconnect structure by the polishing liquid is reduced, and the performance of the semiconductor structure is improved. Specifically, on the one hand, as the repair process is carried out, the stress (tensile stress) in at least one layer of the first dielectric layer material is released outwards. On the other hand, through the substrate or the second dielectric layer located on the bottom surface of the first dielectric layer and the second dielectric layer located on the top surface of the first dielectric layer, the fitting of the top surface and the bottom surface of the first dielectric layer reduces the space for the first dielectric layer to deform towards the surface and the bottom surface. Therefore, the direction of the tensile stress is restricted, and thus, a stress towards the side wall surface of the initial second interconnect structure is formed. The stress towards the side wall surface of the initial second interconnect structure causes the first dielectric layer to deform after the repair process and be extruded towards the side wall surface direction of the initial second interconnect structure, thereby reducing the gap between the initial second interconnect structure and the first dielectric layer.

[0021] Furthermore, through the heat treatment, the first dielectric layer and the second dielectric layer with different coefficients of thermal expansion can be extruded against each other, so that the stress in the first dielectric layer material can be released outwards.

[0022] Furthermore, since the number of the composite dielectric structures is two, and the object of the repair process is the first dielectric layer with a larger distance between the bottom surface and the substrate surface in the direction perpendicular to the substrate surface among the two composite dielectric structures, therefore, by repairing the first dielectric layer with a larger distance from the first interconnect structure, the penetration of the polishing liquid can be blocked earlier, thereby better protecting the first interconnect structure. At the same time, compared with forming a number of composite dielectric structures greater than two, it can also save materials and improve the efficiency of forming the semiconductor structure. Description of the Drawings

[0023] Figures 1 to 2 is a schematic cross-sectional structure diagram of each step of a method for forming a semiconductor structure;

[0024] Figures 3 to 9 is a schematic structural diagram of each step in the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Embodiment

[0025] As described in the background art, the performance of the semiconductor structure is poor, and the following will be described in detail with reference to the accompanying drawings.

[0026] Figures 1 to 2 It is a schematic cross-sectional structure diagram of each step of a method for forming a semiconductor structure.

[0027] Please refer to Figure 1 , a substrate 100 is provided. A first interconnect structure 110 is disposed within the substrate 100, and the surface of the first interconnect structure 110 is exposed on the surface of the substrate 100. A first dielectric layer 120 is formed on the surface of the substrate 100. The first dielectric layer 120 serves as an etch stop layer when forming a second interconnect opening subsequently. A second dielectric layer 130 is formed on the surface of the first dielectric layer 120. The second dielectric layer 130 provides support for forming a second interconnect structure subsequently. A second interconnect opening (not shown) is formed within the first dielectric layer 120 and the second dielectric layer 130, and the surface of the first interconnect structure 110 is exposed at the bottom of the second interconnect opening. An epitaxial growth process is employed to form an initial second interconnect structure 140 within the second interconnect opening.

[0028] Please refer to Figure 2 , the initial second interconnect structure 140 is planarized to form a second interconnect structure 141.

[0029] However, in the above embodiment, since the epitaxial growth process is used to form the initial second interconnect structure 140 within the second interconnect opening, due to the process limitations of the epitaxial growth process, a gap is likely to be generated between the initial second interconnect structure 140 and the sidewall surface of the second interconnect opening. Thus, during the process of planarizing the initial second interconnect structure 140, the acidic polishing liquid is likely to penetrate through the gap to the first interconnect structure 110 and corrode the first interconnect structure 110, resulting in damage to the first interconnect structure 110 and causing poor performance of the semiconductor structure.

[0030] To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure. By forming a plurality of overlapping composite dielectric structures on the surface of the substrate, each composite dielectric structure includes a first dielectric layer and a second dielectric layer located on the surface of the first dielectric layer, and before planarizing the initial second interconnect structure, at least one layer of the first dielectric layer is repaired. Thus, the performance of the semiconductor structure is improved.

[0031] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following will describe in detail the specific embodiments of the present invention with reference to the accompanying drawings.

[0032] Figures 3 to 9It is a schematic structural diagram of each step in the method for forming a semiconductor structure according to an embodiment of the present invention.

[0033] Please refer to Figure 3 , a substrate 200 is provided. The substrate 200 has a first interconnect structure 201 therein, and the surface of the first interconnect structure 201 is exposed on the surface of the substrate 200.

[0034] Specifically, in this embodiment, the substrate includes a substrate (not shown) and a third dielectric layer (not shown) located on the surface of the substrate, and the first interconnect structure 201 is located in the third dielectric layer.

[0035] The material of the substrate is a semiconductor material.

[0036] In this embodiment, the material of the substrate is silicon.

[0037] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI), etc. Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0038] In this embodiment, the substrate 100 further has a device layer (not labeled in the figure). The device layer may include device structures, for example, PMOS transistors or NMOS transistors. The device layer may also include interconnect structures electrically connected to the device structures, and insulating layers surrounding the device structures and the interconnect structures.

[0039] In this embodiment, the material of the first interconnect structure 201 includes cobalt.

[0040] In this embodiment, the material of the third dielectric layer includes silicon oxide.

[0041] Please refer to Figure 4 , a plurality of overlapping composite dielectric structures 210 are formed on the surface of the substrate 200. Each layer of the composite dielectric structure 210 includes a first dielectric layer 211 and a second dielectric layer 212 located on the surface of the first dielectric layer 211.

[0042] In this embodiment, the number of the composite dielectric structures is 2 layers.

[0043] In another embodiment, the number of the composite dielectric structures is more than 3 layers.

[0044] In other embodiments, the number of the composite dielectric structures is 1 layer.

[0045] In this embodiment, the method for forming the two-layer overlapping composite dielectric structure 210 includes: depositing a first dielectric layer 211 on the surface of the substrate 200 and the surface of the first interconnect structure 201; depositing a second dielectric layer 212 on the surface of the first dielectric layer 211 to form the first layer of the composite dielectric structure 210; depositing the second layer of the first dielectric layer 211 on the surface of the first layer of the composite dielectric structure 210; depositing the second layer of the second dielectric layer 212 on the surface of the second layer of the first dielectric layer 211 to form the second layer of the composite dielectric structure 210.

[0046] In this embodiment, the deposition process for forming the first dielectric layer 211 includes at least one of chemical vapor deposition process, physical vapor deposition process, or atomic layer deposition process.

[0047] In this embodiment, the deposition process for forming the second dielectric layer 212 includes at least one of chemical vapor deposition process, physical vapor deposition process, or atomic layer deposition process.

[0048] In this embodiment, the material of the first dielectric layer 211 is different from the material of the second dielectric layer 212.

[0049] In this embodiment, the material of the first dielectric layer 211 includes silicon nitride.

[0050] In this embodiment, the material of the second dielectric layer 212 includes silicon oxide.

[0051] In this embodiment, the thickness of the second dielectric layer 212 is greater than the thickness of the first dielectric layer 211. On the one hand, since the material of the second dielectric layer 212 has better fluidity, therefore, by forming a thicker second dielectric layer 212, the surface flatness of the semiconductor structure can be better improved. On the other hand, since the thickness of the second dielectric layer 212 is thinner, the time for the subsequent planarization process of the second dielectric layer 212 can be reduced, thereby reducing the polishing liquid and subsequent cleaning liquid that penetrate into the first interconnect structure 201 when planarizing the second dielectric layer 212.

[0052] In this embodiment, the thickness range of the first dielectric layer 211 is from 2 nanometers to 10 nanometers.

[0053] If the thickness of the first dielectric layer 211 is too large, the time required for subsequent planarization of the first dielectric layer 211 is relatively long, which is not conducive to reducing the abrasive liquid and subsequent cleaning liquid that penetrate into the first interconnect structure 201. Moreover, an overly thick first dielectric layer 211 will also cause the subsequent repair processing technology to only affect a part of the first dielectric layer 211, making it difficult to control the stress release of the first dielectric layer 211. If the thickness of the first dielectric layer 211 is too small, the barrier ability of the first dielectric layer 211 is reduced, which is not conducive to blocking the abrasive liquid and cleaning liquid during the planarization of the composite dielectric structure 210 and the initial second interconnect structure 220 on the second dielectric layer 212. Therefore, when selecting an appropriate thickness range, that is, when the thickness range of the first dielectric layer 211 is from 2 nanometers to 10 nanometers, on the one hand, when planarizing the first dielectric layer 211, the abrasive liquid and subsequent cleaning liquid that penetrate into the first interconnect structure 201 are reduced; on the other hand, the barrier ability against the abrasive liquid and cleaning liquid during the planarization of the composite dielectric structure 210 and the initial second interconnect structure 220 on the second dielectric layer 212 is increased, reducing the penetration of the abrasive liquid and cleaning liquid during the planarization of the composite dielectric structure 210 and the initial second interconnect structure 220 on the second dielectric layer 212 into the first interconnect structure 201. At the same time, during subsequent repair processing, the control accuracy of the stress release of the first dielectric layer 211 can also be improved.

[0054] In this embodiment, the thickness range of the second dielectric layer 212 is from 20 nanometers to 50 nanometers.

[0055] If the thickness of the second dielectric layer 212 is too large, it causes waste of materials. If the thickness of the second dielectric layer 212 is too small, it is not conducive to surface planarization. Therefore, when selecting an appropriate thickness range, that is, when selecting the second dielectric layer 212 with a thickness range of 20 nanometers to 50 nanometers, on the one hand, the waste of materials of the second dielectric layer 212 is reduced; on the other hand, it can effectively play a role in increasing the surface flatness.

[0056] Next, an initial second interconnect structure located on the surface of the first interconnect structure 201 is formed within the composite dielectric structure 210. For the specific process of forming the initial second interconnect structure, please refer to Figures 5 to 6 .

[0057] Please refer to Figure 5 , after forming a plurality of the composite dielectric structures 210, a second interconnect opening 203 is formed within the plurality of composite dielectric structures 210, and the surface of the first interconnect structure 201 is exposed at the bottom of the second interconnect opening 203.

[0058] In this embodiment, the method for forming the second interconnect opening 203 includes: forming a second opening mask layer (not shown) on the surfaces of several layers of the composite dielectric structure 210, where the second opening mask layer exposes the surface of the composite dielectric structure 210 on the first interconnect structure 201; using the second opening mask layer as a mask to etch several layers of the composite dielectric structure 210 until the surface of the first interconnect structure 201 is exposed, thereby forming the second interconnect opening 203.

[0059] In this embodiment, the method for etching several layers of the composite dielectric structure 210 includes at least one of a dry etching process or a wet etching process.

[0060] In this embodiment, after forming the second interconnect opening 203, the second opening mask layer is removed.

[0061] Please refer to Figure 6 , and an initial second interconnect structure 220 is formed in the second interconnect opening 203 by using a selective metal chemical vapor deposition process.

[0062] In this embodiment, the material of the initial second interconnect structure 220 includes tungsten.

[0063] Please refer to Figure 7 , after forming the initial second interconnect structure 220, a repair process is performed on at least one layer of the first dielectric layer 211 to release the stress F in the first dielectric layer 211 towards the initial second interconnect structure 220.

[0064] Since each layer of the composite dielectric structure 210 includes a first dielectric layer 211 and a second dielectric layer 212 located on the surface of the first dielectric layer 211, and after forming the initial second interconnect structure 220 in the composite dielectric structure 210, a repair process is performed on at least one layer of the first dielectric layer 211 to release the stress F in the first dielectric layer 211 towards the initial second interconnect structure 220. Therefore, through the stress F towards the initial second interconnect structure 220, the side wall surface of the first dielectric layer 211 can be extruded towards the initial second interconnect structure 220 to reduce the gap between the side wall surface of the initial second interconnect structure 220 and the first dielectric layer 211. Thus, the risk of the polishing liquid used for planarizing the initial second interconnect structure 220 penetrating into the first interconnect structure 201 is reduced, the corrosion of the first interconnect structure 201 by the polishing liquid is reduced, and the performance of the semiconductor structure is improved.

[0065] Specifically, on the one hand, as the repair process is carried out, stress F is released outward within the material of at least one layer of the first dielectric layer 211. On the other hand, through the substrate 200 or the second dielectric layer 212 located at the bottom surface of the first dielectric layer 211, and the second dielectric layer 212 located at the top surface of the first dielectric layer 211, the fitting of the top and bottom surfaces of the first dielectric layer 211 reduces the space for the first dielectric layer 211 to deform towards the surface and the bottom surface. Therefore, the direction of the tensile stress F is restricted, and thus, a stress F towards the side wall surface of the initial second interconnect structure 220 is formed. The stress F towards the side wall surface of the initial second interconnect structure 220 causes the first dielectric layer 211 to deform after the repair process and squeeze towards the side wall surface direction of the initial second interconnect structure 220, thereby reducing the gap between the initial second interconnect structure 220 and the first dielectric layer 211.

[0066] In this embodiment, the object of the repair process is the first dielectric layer 211 in the 2-layer composite dielectric structure 210 that has a larger distance between the bottom surface and the surface of the substrate 200 in the direction perpendicular to the surface of the substrate 200.

[0067] Since the number of the composite dielectric structures 210 is 2, and the object of the repair process is the first dielectric layer 211 in the 2 composite dielectric structures 210 that has a larger distance between the bottom surface and the surface of the substrate 200 in the direction perpendicular to the surface of the substrate 200, therefore, by repairing the first dielectric layer 211 with a larger distance from the first interconnect structure 201, the penetration of the polishing liquid and the cleaning liquid can be blocked earlier, thereby better protecting the first interconnect structure 201. At the same time, compared with forming a number of composite dielectric structures 210 greater than 2, materials can also be saved and the efficiency of forming the semiconductor structure can be improved.

[0068] In another embodiment, when the number of the composite dielectric structures is more than 3, and the object of the repair process is the first dielectric layer of multiple composite dielectric structures among the 3 layers. Thereby, the blocking of the penetration of the polishing liquid and the cleaning liquid can be further strengthened.

[0069] In this embodiment, the process of the repair process includes heat treatment.

[0070] Through the heat treatment, the first dielectric layer and the second dielectric layer with different coefficients of thermal expansion can be mutually extruded, so that stress can be released outward within the material of the first dielectric layer.

[0071] The range of the heat treatment temperature is 300 °C to 500 °C.

[0072] If the temperature of the heat treatment is too low, the stress released in the material of the first dielectric layer 211 will be too small, which is not conducive to increasing the blocking ability of the first dielectric layer 211. If the temperature of the heat treatment is too high, it is likely to affect some other semiconductor devices in the semiconductor structure, resulting in deterioration of the performance and reliability of the electrical characteristics of the semiconductor structure. Therefore, by selecting an appropriate temperature range, that is, when the temperature range of the heat treatment is from 300°C to 500°C, sufficient stress can be released in the material of the first dielectric layer 211 while reducing the impact on the performance and reliability of the electrical characteristics of the semiconductor structure.

[0073] The process parameters of the heat treatment further include: the gas used includes at least one of nitrogen, hydrogen, and ammonia, and at least one of argon and helium.

[0074] Next, after the repair treatment, the initial second interconnect structure 220 is planarized until the surface of the composite dielectric structure 210 with the smallest distance from the surface of the substrate 200 is exposed (the first-layer composite dielectric structure 210), and a second interconnect structure is formed. For the specific process of forming the second interconnect structure, please refer to Figures 8 to 9 .

[0075] Please refer to Figure 8 , and the initial second interconnect structure 220 is subjected to a first planarization treatment until the surface of the first dielectric layer 211 with the smallest distance from the surface of the substrate 100 and that has undergone the repair treatment is exposed.

[0076] In this embodiment, the process of the first planarization treatment includes a chemical mechanical polishing process.

[0077] In the process of the first planarization treatment, the polishing liquid used is an acidic polishing liquid.

[0078] In this embodiment, after the first planarization treatment and before the subsequent second planarization treatment, the surface of the composite dielectric structure 210 and the surface of the initial second interconnect structure 220 are subjected to a cleaning treatment.

[0079] Due to the first planarization treatment and the subsequent second planarization treatment being carried out respectively, and the surface of the composite dielectric structure 210 and the surface of the initial second interconnect structure 220 being subjected to a cleaning treatment before the subsequent second planarization treatment, therefore, before the planarization treatment of the first dielectric layer 211, the first dielectric layer 211 that has undergone the repair treatment can greatly block the penetration of the polishing liquid of the first planarization treatment and the cleaning liquid of the cleaning treatment before the subsequent second planarization treatment.

[0080] The process of the cleaning treatment includes a wet cleaning process.

[0081] In the wet cleaning process, the cleaning solution is acidic or alkaline.

[0082] It should be noted that in this embodiment, since the number of composite dielectric structures 210 is more than 2 layers, therefore, the first planarization process and the subsequent second planarization process are respectively performed, so as to perform a cleaning process between the first planarization process and the second planarization process (before removing the repaired first dielectric layer 211) to reduce the penetration of the cleaning solution. In other embodiments, the number of composite dielectric structures is 1 layer, therefore, the repaired first dielectric layer 211 is not removed, and thus, only one planarization process is performed.

[0083] Please refer to Figure 9 , after the first planarization process, the initial second interconnect structure 220 is subjected to a second planarization process until the second interconnect structure 221 is formed.

[0084] In this embodiment, the process of the second planarization process includes a chemical mechanical polishing process.

[0085] In the second planarization process, the polishing liquid used is an acidic polishing liquid.

[0086] In this embodiment, after the second planarization process, the surface of the semiconductor structure is subjected to a cleaning process.

[0087] The process of the cleaning process includes a wet cleaning process.

[0088] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate having a first interconnect structure therein and exposing the surface of the first interconnect structure on the surface of the substrate; Forming a plurality of overlapping composite dielectric structures on the surface of the substrate, each composite dielectric structure including a first dielectric layer and a second dielectric layer located on the surface of the first dielectric layer; Forming an initial second interconnect structure on the surface of the first interconnect structure within the composite dielectric structure; After forming the initial second interconnect structure, performing a repair process on at least one layer of the first dielectric layer to release the stress in the first dielectric layer towards the initial second interconnect structure; After the repair process, planarizing the initial second interconnect structure until the surface of the composite dielectric structure with the smallest distance from the substrate surface is exposed, to form a second interconnect structure; Wherein, the process of the repair process includes heat treatment; The number of the composite dielectric structures is two layers, and the object of the repair process is the first dielectric layer with a larger distance between the bottom surface and the substrate surface in the direction perpendicular to the substrate surface among the two layers of composite dielectric structures; Or, the number of the composite dielectric structures is more than three layers, and the object of the repair process is the first dielectric layer of multiple layers among the three layers of composite dielectric structures.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The temperature range of the heat treatment is 300°C to 500°C.

3. The method for forming a semiconductor structure according to claim 1, characterized in that, The thickness range of the first dielectric layer is 2 nanometers to 10 nanometers, and the thickness range of the second dielectric layer is 20 nanometers to 50 nanometers.

4. The method for forming a semiconductor structure according to claim 1, characterized in that, The method of forming the initial second interconnect structure includes: after forming a plurality of the composite dielectric structures, forming a second interconnect opening in the plurality of composite dielectric structures, with the bottom of the second interconnect opening exposing the surface of the first interconnect structure; using a selective metal chemical vapor deposition process to form an initial second interconnect structure in the second interconnect opening.

5. The method for forming a semiconductor structure according to claim 1, characterized in that, When the number of the composite dielectric structures is more than two layers, the method of planarizing the initial second interconnect structure further includes: performing a first planarization process on the initial second interconnect structure until the surface of the first dielectric layer with the smallest distance from the substrate surface and that has undergone the repair process is exposed; after the first planarization process, performing a second planarization process on the initial second interconnect structure until the second interconnect structure is formed.

6. The method for forming a semiconductor structure according to claim 5, characterized in that, Further comprising: After performing the first planarization process and before performing the second planarization process, performing a cleaning process on the surface of the composite dielectric structure and the surface of the initial second interconnect structure.

7. The method for forming a semiconductor structure according to claim 1, characterized in that, The material of the first interconnect structure includes cobalt.

8. The method for forming a semiconductor structure according to claim 1, characterized in that, The material of the second interconnect structure includes tungsten.

9. The method for forming a semiconductor structure according to claim 1, characterized in that, The material of the first dielectric layer includes silicon nitride.

10. The method for forming a semiconductor structure according to claim 1, characterized in that, The material of the second dielectric layer includes silicon oxide.

11. The method for forming a semiconductor structure according to claim 1, characterized in that, The substrate includes a substrate and a third dielectric layer located on the surface of the substrate, and the first interconnect structure is located within the third dielectric layer.

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