IGBT Device Integrated with FRD and Its Manufacturing Method

Abstract

The present invention provides a method for manufacturing an IGBT device with an integrated FRD, comprising forming a guard ring on the front surface of a substrate; disposing an oxide layer on the front surface of the substrate; disposing multiple gates on a portion of the front surface of the substrate; disposing a P-type well layer between the gates; disposing an N-type emitter layer on the front surface of a portion of the P-type well layer; disposing a dielectric layer on the front surface of the N-type emitter layer, the gate, and the oxide layer; implanting N-type and P-type ions; performing a heavy metal doping process; disposing a metal emitter on the front surface of the dielectric layer, and disposing an FRD cathode on the front surface of the first N-type layer. This method eliminates the need for an external FRD device, reduces parasitic parameters during packaging, improves chip reliability, and saves packaging area, making the packaging more flexible. Furthermore, the introduction of heavy metal doping can reduce carrier lifetime and increase carrier recombination velocity, thereby improving switching speed.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to an IGBT device integrated with an FRD and a manufacturing method thereof. Background Art

[0002] Insulated-Gate Bipolar Transistor (IGBT) combines the advantages of power transistors and power field-effect transistors. It has the characteristics of low on-state voltage, large current capacity, high input impedance, fast response speed and simple control. It is widely used in industry, information, new energy, medicine, transportation, military and aviation fields.

[0003] However, because IGBTs lack reverse conduction capability, currently available IGBTs are packaged in anti-parallel with an FRD (Fast Recovery Diode) to achieve freewheeling capability. Structurally, this still involves two chips connected in parallel, resulting in higher parasitic parameters during packaging, lower chip reliability, and a larger package area.

[0004] Therefore, the main object of the present invention is to provide an IGBT device integrated with FRD and a manufacturing method thereof to solve the above problems. Summary of the Invention

[0005] The present invention provides a method for manufacturing an IGBT device integrated with an FRD, which includes the following steps: providing a substrate having a front side and a back side opposite to each other; forming a guard ring on the front side of the substrate; disposing an oxide layer on the front side of the substrate; disposing a plurality of gates on a portion of the front side of the substrate; disposing a P-type well layer between the plurality of gates; disposing an N-type emitter layer on the front side of a portion of the P-type well layer; disposing a dielectric layer on the front side of the N-type emitter layer, the gates, and the oxide layer; injecting N-conductivity type ions and P-conductivity type ions to form a first N-type layer and a first P-type layer; performing a heavy metal doping process; disposing a metal emitter on the front side of the dielectric layer, and disposing an FRD cathode on the front side of the first N-type layer.

[0006] In one embodiment, the heavy metal doping process includes the following steps: depositing a heavy metal film layer on the front side of the substrate; performing alloying treatment under inert gas protection to form an alloy layer at the contact interface between the heavy metal film layer and the substrate; and then performing heavy metal absorption annealing treatment on the alloy layer.

[0007] In one embodiment, the heavy metal is platinum.

[0008] In one embodiment, after the step of providing the metal emitter and the FRD cathode is completed, the following step is further included: providing a passivation layer on the front sides of the metal emitter and the FRD cathode.

[0009] In one embodiment, after completing the steps of setting the metal emitter and the FRD cathode, the following steps are also included: setting a cutoff layer on the back side of the substrate; setting a second P-type layer on the back side of the cutoff layer; and setting a collector on the back side of the second P-type layer.

[0010] In one embodiment, during the packaging of the IGBT device, the FRD cathode is short-circuited with the collector.

[0011] In one embodiment, the step of setting multiple gates includes the following steps: first, growing a hard mask, then photolithographically etching to form a gate channel, removing the hard mask after etching, then growing a gate oxide layer, and depositing polysilicon, and then photolithographically etching the polysilicon to the front position of the substrate to form a gate.

[0012] In one embodiment, in the step of implanting N conductive type ions and P conductive type ions, the concentration of the implanted N conductive type ions is higher than the concentration of the implanted P conductive type ions.

[0013] In one embodiment, the concentration of the N conductive type ions is greater than or equal to 20 times the concentration of the P conductive type ions.

[0014] The present invention further provides an IGBT device integrated with an FRD, which is manufactured using the method for manufacturing an IGBT device integrated with an FRD provided in any of the above embodiments.

[0015] One advantage of the present invention is that it provides an IGBT device with integrated FRD and a manufacturing method thereof. The FRD can be integrated into the IGBT device without the need for an additional FRD device. This can reduce parasitic parameters during packaging, improve chip reliability, and save packaging area, making the packaging more flexible. In addition, by introducing a heavy metal doping process, the carrier lifetime in the drift region can be reduced. When the FRD is changed from forward bias to reverse bias, the carrier recombination velocity when the IGBT switches from on to off becomes faster, thereby improving the switching speed. In addition, the current specification of the FRD can be adjusted according to demand, without being restricted by the specifications on the market.

[0016] Another advantage of the present invention is that it provides an IGBT device integrated with an FRD. During packaging, the packaging method of short-circuiting the cathode and collector of the FRD can greatly save the area required for packaging, making the packaging more flexible.

[0017] Other features and benefits of the present invention will be described in the following description and, in part, will become apparent from the description or be understood through practice of the present invention. The objectives and other benefits of the present invention can be achieved and obtained through the structures specifically pointed out in the description, claims, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work. The positional relationships described in the drawings in the following description are based on the directions of the components drawn in the diagrams, unless otherwise specified.

[0019] Figure 1 1 is a flow chart of a method for manufacturing an IGBT device integrated with an FRD according to an embodiment of the present invention;

[0020] Figures 2 to 4 1 is a schematic diagram of the structure of an IGBT device integrated with FRD provided by an embodiment of the present invention at various stages in the manufacturing process.

[0021] Reference numerals:

[0022] 10-IGBT device; 12-substrate; 122-front side of substrate; 124-back side of substrate; 14-guard ring; 16-oxide layer; 20-gate; 202-gate oxide layer; 22-P-type well layer; 24-N-type emitter layer; 26-dielectric layer; 28-first N-type layer; 30-first P-type layer; 32-metal emitter; 34-FRD cathode; 36-passivation layer; 38-cutoff layer; 40-second P-type layer; 42-collector; 46-cell region; 48-terminal region; 50-FRD region. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments; the technical features designed in different implementation modes of the present invention described below can be combined with each other as long as they do not conflict with each other; based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0024] In the description of the present invention, it should be understood that the terms "center", "lateral", "up", "down", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more. In addition, the term "including" and any variations thereof all mean "at least including".

[0025] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integrally formed connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0026] The terms used herein are intended only to describe specific embodiments and are not intended to limit exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms "a", "an", "an item" used herein are also intended to include the plural. It should also be understood that the terms "comprise" and / or "include" used herein specify the presence of stated features, integers, steps, operations, units and / or components, and do not preclude the presence or addition of one or more other features, integers, steps, operations, units, components and / or combinations thereof.

[0027] See also Figures 1 to 4 , Figure 1 FIG. 1 is a flow chart of a method for manufacturing an IGBT device 10 integrated with an FRD according to an embodiment of the present invention. Figures 2 to 4 Schematic diagrams of various stages of the manufacturing process of an IGBT device 10 with an integrated FRD according to one embodiment of the present invention are provided. To achieve at least one of the aforementioned advantages, or other advantages, one embodiment of the present invention provides a method for manufacturing an IGBT device 10 with an integrated FRD. As shown in the figure, the manufacturing method includes the following steps:

[0028] S10: providing a substrate;

[0029] S12: forming a guard ring on the front side of the substrate;

[0030] S14: providing an oxide layer on the front surface of the substrate;

[0031] S16: Disposing a plurality of gates on a front surface of a portion of the substrate;

[0032] S18: Disposing a P-type well layer between the plurality of gates;

[0033] S20: Disposing an N-type emitter layer on a front surface of a portion of the P-type well layer;

[0034] S22: Disposing a dielectric layer on the front surface of the N-type emitter layer, the gate, and the oxide layer;

[0035] S24: Implanting N-type conductive ions and P-type conductive ions to form a first N-type layer and a first P-type layer;

[0036] S26: performing heavy metal doping process;

[0037] S28: Disposing a metal emitter on the front surface of the dielectric layer, and disposing an FRD cathode on the front surface of the first N-type layer.

[0038] In the step S14 , preferably, an oxide layer 16 may be further provided on the front surface of the guard ring 14 .

[0039] The step of setting multiple gates 20 in step S16 may further include the following steps: first, grow a hard mask, then perform photolithography and etching to form a gate channel, remove the hard mask after etching, then grow a gate oxide layer 202, and deposit polysilicon, and then perform photolithography and etching of the polysilicon to the front side 122 of the substrate 12 to form the gate 20.

[0040] In the step S18 , preferably, a P-type well layer 22 may be further provided between the gate 20 and the guard ring 14 .

[0041] In step S24 of implanting N-conductivity type ions and P-conductivity type ions, the N-conductivity type ions are implanted first, followed by the P-conductivity type ions. The concentration of the implanted N-conductivity type ions is higher than the concentration of the P-conductivity type ions. Preferably, the concentration of the N-conductivity type ions is greater than or equal to 20 times the concentration of the P-conductivity type ions.

[0042] The heavy metal doping process of step S26 further includes the following steps: depositing a heavy metal film layer on the front surface 122 of the substrate 12; performing an alloying treatment under inert gas protection to form an alloy layer at the contact interface between the heavy metal film layer and the substrate 12; and then performing a heavy metal absorption annealing treatment on the alloy layer. The heavy metal refers to a metal with a density greater than 4.5 g / cm3, such as platinum. It should be noted that after completing step S24, there is still an exposed blank area on the front surface 122 of the substrate 12, that is, the substrate 12 is exposed to perform the heavy metal doping process of step S26.

[0043] After completing step S28, the following steps may also be included:

[0044] S30: providing a passivation layer on the front side of the metal emitter and the FRD cathode;

[0045] S32: providing a cutoff layer on the back side of the substrate;

[0046] S34: Disposing a second P-type layer on the back side of the cut-off layer;

[0047] S36: Disposing a collector electrode on the back side of the second P-type layer.

[0048] In this embodiment, the front side 122 and the back side 124 of the substrate 12 are the upper surface and the lower surface of the substrate 12 in the figure, respectively, and the front side of each structure is a surface in the same direction, for example, the front side of the oxide layer 16 is the upper surface of the oxide layer 16.

[0049] The following will be combined Figures 2 to 4 , the specific process of the manufacturing method of the IGBT device 10 integrated with the FRD is described as an example, but the present invention is not limited to this. The specific process of the manufacturing method is as follows:

[0050] First, the morphology of the guard ring 14 (Guard Ring) is formed on the front surface 122 of the silicon substrate 12 (FZ-wafer) by photolithography. B11 / 130Kev / 2E14 (P-conductivity type ions) is then implanted and a high-temperature annealing process (1150°C / 110 minutes) is performed to form the guard ring 14. In other words, the guard ring 14 is integral with the silicon substrate 12. The morphology of the guard ring 14 is first formed by photolithography of the silicon substrate 12, and then P-conductivity type ions are implanted to form the guard ring 14. At this point, the doping ions of the guard ring 14 and the silicon substrate 12 are different. B11 / 130Kev / 2E14 refers to the implantation of boron ions at an energy of 130Kev and a concentration of 2E14. Boron ions are P-conductivity type ions. For similar ion descriptions below, please refer to this paragraph for understanding.

[0051] Secondly, after removing the photoresist, an oxide layer 16 (Field Oxide) with a thickness of 1.5 μm is grown on the front surface 122 of the guard ring 14 and the silicon substrate 12; the required portion of the oxide layer 16 is obtained by photolithography and etching, that is, the oxide layer 16 is set on part of the surface of the guard ring 14 and the silicon substrate 12. The oxide layer 16 portion on the silicon substrate 12 is used for the subsequent production of FRD.

[0052] Next, a hard mask is grown and a gate trench is formed by photolithography and etching. After etching, the remaining hard mask is removed. Then, a gate oxide layer 202 (thickness is 1000mm) is grown. ), and deposit polysilicon, and perform photolithography and etching of the polysilicon to the surface of the silicon substrate 12 to serve as the gate 20. That is, a plurality of gates 20 are provided on the front side 122 of the silicon substrate 12.

[0053] Next, B11 / 120Kev / 1.05E13, B11 / 90Kev / 8.6E12, and B11 / 40Kev / 1.05E13 (P conductivity type ions) are implanted and annealed at 1175°C for 80 minutes to form a P-type well layer 22 (PW region). This forms a PN junction and withstands voltage. Specifically, a P-type well layer 22 is provided between two adjacent gates 20 and between a gate 20 and the guard ring 14.

[0054] Next, the N-type emitter layer 24 is formed by photolithography and etching. As75 / 60Kev / 8E15 (N conductive type ions) is injected into the region and then annealed at high temperature (950°C / 30min) to form the N-type emitter layer 24. The structure at this time is as follows: Figure 2 shown.

[0055] Subsequently, a dielectric layer 26 (Inter Level Dielectric, ILD) is deposited with a thickness of 1.1 μm, and then photolithography and etching are performed to remove the dielectric layer 26 in the predetermined contact area and FRD area 50. Then, photoresist is applied to protect the contact, and the location of the FRD area 50 is etched out by development.

[0056] Next, As75 / 115Kev / 1E15 and As75 / 100Kev / 4E16 (N conductive type ions) are injected, and then the photoresist is removed. Then, B11 / 35Kev / 5E13 and B11 / 20Kev / 2E15 (P conductive type ions) are fully injected, and high temperature annealing (1000°C / 0.25min) is performed to form the first P type layer 30 and the first N type layer 28. It should be noted that because the concentration of the injected N conductive type ions is much higher than the concentration of the P conductive type ions, for example, at least 20 times higher, the first N type layer 28 is below the FRD region 30. The structure at this time is as follows: Figure 3 shown.

[0057] Then, a platinum thin film layer with a thickness of more than 0.001 μm is deposited on the front surface 122 of the silicon substrate 12 by a metal thin film deposition method. A platinum-silicon alloying treatment is performed under inert gas protection to form a platinum-silicon alloy layer at the contact interface between silicon and platinum. The remaining platinum thin film layer is then removed, leaving the platinum-silicon alloy layer. A platinum absorption annealing treatment is performed at a temperature of 670°C to 750°C for 20 to 790 minutes to allow platinum atoms to be doped into the silicon substrate 12. It should be noted that although at this time Figure 3 The front side 122 of the silicon substrate 12 in the figure does not have an exposed area, but it is a cross-sectional schematic diagram. If viewed from a top view, the front side 122 of the silicon substrate 12 does have an exposed blank area, that is, the substrate 12 is exposed to facilitate the heavy metal doping process.

[0058] Next, after completing the heavy metal doping process, a Ti / TiN layer is plated, tungsten is deposited, and the layer is etched to the surface of the dielectric layer 26. Then, metal is deposited and photoetched to form a metal emitter 32 (Emitter) and an FRD cathode 34 (Cathode). Finally, a passivation layer 36 is deposited and photoetched to form a passivation layer 36 to expose the metal emitter 32 and the FRD cathode 34, completing the front-side process.

[0059] After the front surface process is completed, the back surface 124 of the silicon substrate 12 is ground to a suitable thickness, and ion implantation and laser annealing are performed to form a cut-off layer 38 and a second P-type layer 40. After that, it is polished, cleaned, evaporated, and alloyed to form a back surface metal to form a collector electrode 42. The structure at this time is as follows: Figure 4 As shown in the figure, the resulting IGBT device 10 with integrated FRDs comprises a cell region 46, a terminal region 48, and an FRD region 50. The cell region 46 allows for current flow when on and withstands voltage when off. The terminal region 48 can be used to divide and smooth the electric field, improving the device's high-voltage resistance. The FRD region 50 enables the IGBT device 10 to conduct in the reverse direction. The withstand voltage test result of the IGBT device 10 was greater than 1200V.

[0060] Through the above steps, platinum atoms are doped into the silicon substrate 12 to form recombination centers, which reduces the carrier lifetime in the drift region of the silicon substrate 12. When the FRD is changed from forward bias to reverse bias, the recombination speed of the carriers becomes faster when the IGBT is turned on and off, thereby improving the switching speed.

[0061] In addition, when packaging the IGBT device 10 , by short-circuiting the FRD cathode 34 and the collector 42 , the area required for packaging can be greatly saved, making the packaging more flexible.

[0062] This embodiment provides an IGBT device 10 integrated with an FRD. The IGBT device 10 integrated with an FRD is manufactured using the manufacturing method of the IGBT device 10 integrated with an FRD provided in any of the above embodiments, and its specific structure and technical effects are not described in detail.

[0063] In summary, one advantage of the present invention is that it provides an IGBT device 10 integrated with an FRD and a manufacturing method thereof, which can integrate the FRD into the IGBT device 10 without the need for additional FRD devices. This can reduce parasitic parameters during packaging, improve chip reliability, and save packaging area, making the packaging more flexible. In addition, by introducing a heavy metal doping process, the carrier lifetime in the drift region can be reduced, so that when the FRD is changed from forward bias to reverse bias, the carrier recombination velocity becomes faster when the IGBT switches from on to off, thereby increasing the switching speed. In addition, the current specifications of the FRD can be adjusted according to demand without being restricted by market specifications.

[0064] Another advantage of the present invention is that it provides an IGBT device 10 integrated with an FRD. During packaging, the packaging method of short-circuiting the FRD cathode 34 and the collector 42 can greatly save the area required for packaging, making the packaging more flexible.

[0065] In addition, those skilled in the art should understand that, although there are many problems in the prior art, each embodiment or technical solution of the present invention may be improved in only one or several aspects, without having to simultaneously solve all the technical problems listed in the prior art or background art. Those skilled in the art should understand that any content not mentioned in a claim should not be construed as limiting the claim.

[0066] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing an IGBT device integrated with an FRD, characterized by: The manufacturing method comprises the following steps: Providing a substrate having opposite front and back surfaces; forming a guard ring on the front surface of the substrate; providing an oxide layer on the front surface of the substrate; Disposing a plurality of gates on a front surface of a portion of the substrate; Disposing a P-type well layer between the plurality of gates; Disposing an N-type emitter layer on a front surface of a portion of the P-type well layer; Disposing a dielectric layer on the front surface of the N-type emitter layer, the gate and the oxide layer; Implanting N conductive type ions and P conductive type ions to form a first N type layer and a first P type layer; Perform heavy metal doping process; as well as Disposing a metal emitter on the front surface of the dielectric layer, and disposing an FRD cathode on the front surface of the first N-type layer; The heavy metal doping process includes the following steps: depositing a heavy metal film layer on the exposed front surface of the substrate; performing alloying treatment under inert gas protection to form an alloy layer at the contact interface between the heavy metal film layer and the substrate; then performing heavy metal absorption annealing treatment on the alloy layer; the heavy metal refers to a material with a density greater than 4.5g / cm 3 of metal; wherein, in the step of implanting N conductive type ions and P conductive type ions, the concentration of the implanted N conductive type ions is higher than the concentration of the P conductive type ions, and the concentration of the N conductive type ions is greater than or equal to 20 times the concentration of the P conductive type ions; The IGBT device has a cell region, a terminal region and an FRD region, the terminal region is located between the cell region and the FRD region, the gate is located in the cell region and the terminal region, the N-type emitter layer is located in the cell region, the first P-type layer is located in the cell region and the terminal region, the first P-type layer is connected to the P-type well layer, the guard ring is located in the terminal region, part of the P-type well layer is located between two adjacent gates, part of the P-type well layer is located between the gate and the guard ring, and the first N-type layer is located in the FRD region.

2. The manufacturing method according to claim 1, wherein: The heavy metal is platinum.

3. The manufacturing method according to claim 1, wherein: After the step of providing the metal emitter and the FRD cathode is completed, the method further includes providing a passivation layer on the front sides of the metal emitter and the FRD cathode.

4. The manufacturing method according to claim 1, wherein: After completing the steps of setting the metal emitter and the FRD cathode, the following steps are also included: setting a cutoff layer on the back of the substrate; setting a second P-type layer on the back of the cutoff layer; and setting a collector on the back of the second P-type layer.

5. The manufacturing method according to claim 4, characterized in that: During packaging of the IGBT device, the FRD cathode is short-circuited with the collector.

6. The manufacturing method according to claim 1, wherein: The steps of setting multiple gates include the following steps: first, growing a hard mask, then photolithographically etching to form a gate channel, removing the hard mask after etching, then growing a gate oxide layer, and depositing polysilicon, and then photolithographically etching the polysilicon to the front position of the substrate to form the gate.

7. An IGBT device integrated with an FRD, characterized in that: The IGBT device integrated with FRD is manufactured by using the manufacturing method according to any one of claims 1 to 6.

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