Semiconductor structure and method of forming the same

Abstract

The application provides a semiconductor structure and a forming method thereof. The semiconductor structure comprises a semiconductor substrate, a fin formed on the semiconductor substrate, and a metal gate formed on a part of a top surface and a sidewall of the fin. An SDB isolation structure is located between fins on which adjacent metal gates are located, and is used for isolating the fins on which the adjacent metal gates are located. The semiconductor structure and the forming method thereof can improve the position accuracy of the SDB isolation structure, reduce residues on the sidewall of the SDB isolation structure, improve the quality of the SDB isolation structure, and improve the reliability of a device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] With advancements in semiconductor technology, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs continues to grow. To meet these demands, the semiconductor industry continues to scale down the size of semiconductor devices, and the design of three-dimensional structures such as FinFETs has become a hot topic in the semiconductor field.

[0003] As devices continue to miniaturize, new technologies have emerged for fabricating isolation structures to create smaller, more densely distributed fins. One such technology is the manufacturing of single diffusion break isolation structures (SDB structures). These typically involve removing certain areas of the fin to form one or more isolation trenches. Filling these trenches with insulating materials such as silicon dioxide divides the fin into multiple smaller fins. This prevents leakage current between adjacent fin regions and between adjacent fins, and also avoids source-drain bridging between the source and drain regions within the fin. Therefore, the quality of the manufacturing process and the formed structure of the SDB isolation structure affects its isolation performance and can even cause defects in the surrounding fins and gate structure, thus impacting the performance of FinFET devices.

[0004] However, current manufacturing technology for SDB isolation structures still has shortcomings. Therefore, it is necessary to provide a more reliable and efficient technical solution. Summary of the Invention

[0005] This application provides a semiconductor structure and a method for forming the same, which can improve the positional accuracy of the SDB isolation structure, reduce the residue on the sidewalls of the SDB isolation structure, thereby improving the quality of the SDB isolation structure and increasing device reliability.

[0006] One aspect of this application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, on which a fin is formed, and a dummy gate material layer is formed on the top surface and sidewalls of the fin; forming a first mask layer covering a portion of the dummy gate material layer on the top surface of the dummy gate material layer, wherein a first portion of the first mask layer corresponds to the dummy gate layer of the semiconductor structure, and a second portion of the first mask layer corresponds to the SDB isolation structure of the semiconductor structure; etching away the second portion of the first mask layer and continuing to etch the dummy gate material layer to form a first trench in the dummy gate material layer; etching the dummy gate material layer using the first portion of the first mask layer as a mask to expose the surface of the fin, while simultaneously etching along the first trench to the bottom of the first trench being coplanar with the bottom of the fin, thereby forming a dummy gate layer; and filling the first trench with a dielectric material to form an SDB isolation structure.

[0007] In some embodiments of this application, the method of etching away a second portion of the first mask layer and continuing to etch the dummy gate material layer to form a first trench in the dummy gate material layer includes: forming a second mask layer on the surface of the dummy gate material layer and the sidewalls and top surface of the first mask layer; forming a photoresist layer including an opening on the surface of the second mask layer, the opening exposing the top surface of the second portion of the first mask layer; sequentially etching the second mask layer, the first mask layer, and the dummy gate material layer along the opening to form the first trench in the dummy gate material layer; and removing the photoresist layer and the second mask layer.

[0008] In some embodiments of this application, the method of sequentially etching the second mask layer, the first mask layer, and the dummy gate material layer along the opening to form the first trench in the dummy gate material layer includes: etching the second mask layer along the opening to form a second opening, the second opening exposing the first mask layer; etching the first mask layer along the second opening to expose the dummy gate material layer; and continuing to etch the dummy gate material layer along the second opening to form the first trench in the dummy gate material layer.

[0009] In some embodiments of this application, the height difference between the bottom of the first trench and the top surface of the dummy gate material layer is 5 nanometers to 50 nanometers.

[0010] In some embodiments of this application, the method of filling the first trench with dielectric material to form an SDB isolation structure includes: forming a first dielectric layer on the sidewall of the dummy gate layer and the sidewall and bottom of the first trench; forming a source and a drain in the fins on both sides of the dummy gate layer; forming a second dielectric layer with its top higher than the first mask layer and completely covering the fins and the first mask layer, the second dielectric layer filling the first trench; and removing the second dielectric layer and the first mask layer that are higher than the top surface of the dummy gate layer.

[0011] In some embodiments of this application, the method of forming a first dielectric layer on the sidewall of the dummy gate layer and the sidewall and bottom of the first trench includes: forming a first dielectric layer on the top surface and sidewall of the first mask layer, the top surface of the fin, and the sidewall and bottom of the first trench; and etching away the first dielectric layer on the top surface of the first mask layer and the top surface of the fin.

[0012] In some embodiments of this application, the method for forming the semiconductor structure further includes: removing the dummy gate layer to form a second trench; and forming a metal gate in the second trench.

[0013] In some embodiments of this application, a pad oxide layer is formed between the surface of the semiconductor substrate and the bottom of the fin.

[0014] Another aspect of this application provides a semiconductor structure, comprising: a semiconductor substrate on which fins are formed, wherein a portion of the top surface and sidewalls of the fins are formed with metal gates; and an SDB isolation structure located between adjacent fins containing metal gates for isolating adjacent fins containing metal gates.

[0015] In some embodiments of this application, a pad oxide layer is formed between the surface of the semiconductor substrate and the bottom of the fin.

[0016] In some embodiments of this application, the semiconductor structure further includes a first dielectric layer located on the sidewall of the metal gate.

[0017] In some embodiments of this application, the semiconductor structure further includes a source and a drain in the fins located on both sides of the metal gate.

[0018] In some embodiments of this application, the semiconductor structure further includes: a second dielectric layer that completely covers the fins, wherein the top surface of the second dielectric layer is coplanar with the top surface of the metal gate.

[0019] The semiconductor structure and its formation method described in this application use the first mask layer as a mask to etch and form a first trench, and form an SDB isolation structure in the first trench. This can improve the positional accuracy of the SDB isolation structure, reduce the residue on the sidewalls of the SDB isolation structure, thereby improving the quality of the SDB isolation structure and improving the reliability of the device. Attached Figure Description

[0020] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:

[0021] Figure 1 A three-dimensional structural diagram of a semiconductor structure;

[0022] Figure 2 This is a schematic cross-sectional view of a semiconductor structure;

[0023] Figures 3 to 18 This is a schematic diagram of each step in the method for forming a semiconductor structure according to the embodiments of this application. Detailed Implementation

[0024] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0025] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0026] Figure 1 A three-dimensional structural diagram of a semiconductor structure; Figure 2 This is a schematic cross-sectional view of a semiconductor structure. Figure 2 It is along Figure 1 The cross-sectional view of the plane containing the dashed box 150.

[0027] refer to Figure 1 and Figure 2As shown, a FinFET device generally includes: a semiconductor substrate 100 and a plurality of thin fins 110 extending vertically upward on the semiconductor substrate 100 (only one fin is shown in the figure for simplicity); an isolation structure 120 located on the semiconductor substrate 100, surrounding a portion of the sidewalls of the fins 110, for isolating adjacent fins 110; and a gate structure 130 located on a portion of the top surface and sidewalls of the fins 110.

[0028] As devices continue to miniaturize, new isolation technologies have emerged to fabricate smaller, more densely distributed fins 110, such as the manufacturing technology for SDB isolation structures. (Reference) Figure 1 and Figure 2 The SDB isolation structure is generally distributed along the length of the fin 110. By removing certain areas of the fin 110, one or more isolation trenches 140 are formed in the fin 110. After these isolation trenches 140 are filled with insulating materials such as silicon dioxide, a single fin 110 can be divided into multiple small fins. This can prevent leakage current between two adjacent areas of the fin 110 and between two adjacent fins 110, and can also avoid bridging between the source and drain regions formed in the fin 110. Therefore, the quality of the manufacturing process and the forming structure of the SDB isolation structure will affect the isolation performance of the SDB isolation structure, and may even cause defects in the surrounding fins and gate structure, thereby affecting the performance of the FinFET device.

[0029] To form a higher quality and more reliable SDB isolation structure, this application provides a semiconductor structure and a method for forming the same. A first trench is formed by etching a first mask layer as a mask, and an SDB isolation structure is formed in the first trench. This method can improve the positional accuracy of the SDB isolation structure, reduce residue on the sidewalls of the SDB isolation structure, thereby improving the quality of the SDB isolation structure and enhancing device reliability.

[0030] Figures 3 to 18 This is a schematic diagram of each step in the method for forming a semiconductor structure according to an embodiment of this application. It should be noted that, for the sake of brevity, Figures 3 to 18 These are all cross-sectional views, but they should be understood as... Figure 2 Compared to Figure 1 similar, Figures 3 to 18 These are all cross-sectional views taken along the length of the fins on the semiconductor structure. The method for forming the semiconductor structure described in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0031] Embodiments of this application provide a method for forming a semiconductor structure, including: referencing Figure 3A semiconductor substrate 200 is provided, on which fins 220 are formed, and dummy gate material layers 230a are formed on the top surface and sidewalls of the fins 220; Reference Figure 4 A first mask layer 240 is formed on the top surface of the dummy gate material layer 230a, covering a portion of the dummy gate material layer 230a. A first portion 241 of the first mask layer 240 corresponds to the dummy gate layer of the semiconductor structure, and a second portion 242 of the first mask layer 240 corresponds to the SDB isolation structure of the semiconductor structure. (Reference) Figures 5 to 10 The second portion 242 of the first mask layer 240 is etched away, and the dummy gate material layer 230a is etched further, forming a first trench 250 in the dummy gate material layer 230a; Reference Figure 11 Using the first portion 241 of the first mask layer 240 as a mask, the dummy gate material layer 230a is etched until the surface of the fin 220 is exposed. Simultaneously, etching is performed along the first trench 250 until the bottom of the first trench 250 is coplanar with the bottom of the fin 220. The dummy gate material layer 230a forms the dummy gate layer 230. (Refer to...) Figures 12 to 16 The first trench 250 is filled with a dielectric material to form an SDB isolation structure 280.

[0032] The semiconductor structure formation method described in this application uses the first mask layer 240 as a mask to etch and form a first trench 250, and forms an SDB isolation structure 280 in the first trench 250. This can improve the positional accuracy of the SDB isolation structure 280, reduce the residue on the sidewalls of the SDB isolation structure 280, thereby improving the quality of the SDB isolation structure 280 and improving the reliability of the device.

[0033] refer to Figure 3 A semiconductor substrate 200 is provided, on which fins 220 are formed, and a dummy gate material layer 230a is formed on the top surface and sidewalls of the fins 220.

[0034] In some embodiments of this application, a pad oxide layer 210 is formed between the surface of the semiconductor substrate 200 and the bottom of the fin 220. The pad oxide layer 210 can serve as an etching stop layer when the first trench is subsequently etched until the bottom of the first trench is coplanar with the bottom of the fin, thereby preventing excessive etching from damaging the semiconductor substrate.

[0035] In some embodiments of this application, the material of the pad oxide layer 210 includes silicon oxide and the like.

[0036] In some embodiments of this application, the semiconductor substrate 200 is made of (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide; or (iv) a combination of the above. Furthermore, the semiconductor substrate 200 may be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of this application, the semiconductor substrate 200 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).

[0037] In some embodiments of this application, the method of forming the fin 220 may include: forming a fin material layer on the pad oxide layer 210; forming a patterned mask layer on the fin material layer; and etching the fin material layer using the patterned mask layer as a mask to form the fin 220. For example, etching may be performed using a dry etching process, a wet etching process, or a combination thereof. In some embodiments of this application, the mask layer may be a thin film comprising silicon oxide formed using a thermal oxidation process. In other embodiments of this application, the mask layer may be a thin film comprising silicon nitride formed using a low-pressure chemical vapor deposition (LPCVD) process or a plasma-enhanced CVD (PECVD) process.

[0038] In some embodiments of this application, the material of the dummy gate material layer 230a includes polysilicon. The method for forming the dummy gate material layer 230a includes a chemical vapor deposition process.

[0039] refer to Figure 4 A first mask layer 240 is formed on the top surface of the dummy gate material layer 230a, covering a portion of the dummy gate material layer 230a. A first portion 241 of the first mask layer 240 corresponds to the dummy gate layer of the semiconductor structure, and a second portion 242 of the first mask layer 240 corresponds to the SDB isolation structure of the semiconductor structure.

[0040] In subsequent processes, the first portion 241 and the second portion 242 will be used as masks for etching to form a dummy gate layer and an SDB isolation structure. The term "corresponding" refers to the fact that the vertical projections of the first portion 241 and the second portion 242 coincide with the vertical projections of the dummy gate layer and the SDB isolation structure, respectively.

[0041] In some embodiments of this application, the material of the first mask layer 240 may be the material that forms the gate mandral.

[0042] refer to Figures 5 to 10The second portion 242 of the first mask layer 230 is etched away and the dummy gate material layer 230a is etched to form a first trench 250 in the dummy gate material layer 230a.

[0043] refer to Figure 5 A second mask layer 251 is formed on the surface of the dummy gate material layer 230a and on the sidewalls and top surface of the first mask layer 240. The second mask layer 251 can increase the process window for etching the first trench and improve the accuracy of etching to form the first trench. The specific process for achieving this effect will be described in detail below.

[0044] In some embodiments of this application, the material selection of the second mask layer 251 can satisfy the large difference in the etching selectivity of the second mask layer 251 and the first mask layer 240. When etching the second mask layer 251, the first mask layer 240 can be used as an etching stop layer.

[0045] refer to Figure 6 A photoresist layer 252 including an opening 253 is formed on the surface of the second mask layer 251, the opening 253 exposing the second mask layer 251 on the top surface of the second portion 242 of the first mask layer 240.

[0046] It should be noted that the accompanying drawings in this application are merely schematic and do not represent the actual size proportions of the semiconductor structure. In the actual structure, the width (horizontal dimension) of the second portion 242 is very small. Even the minimum width of the opening 253 formed by exposure in some current photolithography processes is difficult to achieve such a small size, making it difficult to directly etch the second portion 242 through the opening 253. Therefore, a second mask layer 251 can be added. The second mask layer 251 is etched first to form a second opening 254 with a width smaller than the opening 253, and then the second portion 242 is etched through the second opening 254.

[0047] In some other embodiments of this application, if the precision of the photolithography process is sufficient to ensure that the minimum width of the exposure-formed opening 253 can reach the width of the second portion 242, then the second mask layer 251 can be omitted, and the second portion 242 can be directly etched through the opening 253.

[0048] refer to Figures 7 to 9 The second mask layer 251, the first mask layer 240, and the dummy gate material layer 230a are sequentially etched along the opening 253, and the first trench 250 is formed in the dummy gate material layer 230a.

[0049] refer to Figure 7The second mask layer 251 is etched along the opening 253 to form a second opening 254, which exposes a second portion 242 of the first mask layer 240. Since the etching selectivity ratios of the second mask layer 251 and the first mask layer 240 are different, the first mask layer 240 can serve as an etching stop layer, causing the etching to stop on the surface of the first mask layer 240.

[0050] In some embodiments of this application, the method for etching the second mask layer 251 includes dry etching. The dry etching can form a second opening 254 with a width smaller than that of the opening 253. Etching the second portion 242 along the second opening 254 is thus more precise than directly etching the second portion 242 along the opening 253, thereby improving the etching process window.

[0051] refer to Figure 8 The second portion 242 of the first mask layer 240 is etched along the second opening 254 until the dummy gate material layer 230a is exposed. The material of the first mask layer 240 is different from that of the second mask layer 251; therefore, a suitable etching gas or etching solution needs to be used at this point. Using the second portion 242 as a tool for positioning the first trench 250 improves the positional accuracy of forming the SDB isolation structure.

[0052] In some embodiments of this application, the method of etching the first mask layer 240 includes dry etching or wet etching.

[0053] refer to Figure 9 The dummy gate material layer 230a is etched along the second opening 254, forming the first trench 250 in the dummy gate material layer 230a. The material of the first mask layer 240 is different from the material of the dummy gate material layer 230a; therefore, a suitable etching gas or etching solution needs to be replaced at this point.

[0054] In some embodiments of this application, the method of etching the dummy gate material layer 230a includes dry etching or wet etching.

[0055] It should be noted that, for the sake of brevity, the specific details of each etching process are not listed in the embodiments of this application. In actual process, appropriate etching gas or etching solution can be selected according to the materials of the first mask layer 240, the second mask layer 251 and the pseudo gate material layer 230a.

[0056] refer to Figure 10 Remove the photoresist layer 252 and the second mask layer 251.

[0057] In some embodiments of this application, the method for removing the photoresist layer 252 is, for example, an ashing process.

[0058] In some embodiments of this application, the method for removing the second mask layer 251 is, for example, an etching process.

[0059] In some embodiments of this application, the height difference between the bottom of the first trench 250 and the top surface of the dummy gate material layer 230a is 5 nanometers to 50 nanometers. This height difference represents the depth of the first trench 250. In subsequent processes, while etching the dummy gate material layer 230a to form the dummy gate layer, the first trench 250 is etched down to the bottom of the fin 220. Therefore, to conserve process materials and improve efficiency, it is best that the first trench 250 is also etched to approximately the bottom of the fin 220 when the dummy gate layer is formed. In this way, the optimal depth of the first trench 250 can be calculated based on the etching time of the fin 220 and the etching time of the dummy gate layer 230a.

[0060] In some embodiments of this application, the etching selectivity ratios of the dummy gate material layer 230a and the fin 220 are close. Therefore, the etching rates of the dummy gate material layer 230a and the fin 220 are close, and the optimal depth of the first trench 250 is the height of the fin 220. The distance from the bottom of the first trench 250 to the bottom of the fin 220 is exactly equal to the height of the dummy gate material layer 230a. Thus, the time for subsequent etching of the dummy gate material layer 230a is essentially equal to the time for etching the first trench 250 to the bottom of the fin 220.

[0061] refer to Figure 11 Using the first portion 241 of the first mask layer 240 as a mask, the pseudo gate material layer 230a is etched to expose the surface of the fin 220. At the same time, it is etched along the first trench 250 until the bottom of the first trench 250 is coplanar with the bottom of the fin 220, and the pseudo gate material layer 230a forms the pseudo gate layer 230.

[0062] In some embodiments of this application, the etching selectivity of the dummy gate material layer 230a is close to that of the fin 220, so the dummy gate material layer 230a and the fin 220 can be etched simultaneously in the same etching process.

[0063] In some embodiments of this application, the pad oxide layer 210 can serve as an etch stop layer to prevent excessive etching from damaging the semiconductor substrate 200.

[0064] In some embodiments of this application, the method of etching the dummy gate material layer 230a includes wet etching or dry etching.

[0065] refer to Figures 12 to 16 The first trench 250 is filled with a dielectric material to form an SDB isolation structure 280.

[0066] refer to Figures 12 to 13 A first dielectric layer 260 is formed on the sidewalls of the dummy gate layer 230 and on the sidewalls and bottom of the first trench 250. The first dielectric layer 260 located on the sidewalls of the dummy gate layer 230 can serve as a sidewall of the dummy gate layer 230; the first dielectric layer 260 located on the sidewalls and bottom of the first trench 250 can serve as part of the dielectric material of the SDB isolation structure.

[0067] refer to Figure 12 A first dielectric layer 260 is formed on the top surface and sidewall of the first portion 241 of the first mask layer 240, the top surface of the fin 220, and the sidewall and bottom of the first trench 250.

[0068] In some embodiments of this application, the method for forming the first dielectric layer 260 includes a chemical vapor deposition process.

[0069] In some embodiments of this application, the material of the first dielectric layer 260 includes silicon nitride, etc.

[0070] refer to Figure 13 The first dielectric layer 260 of the first portion 241 of the first mask layer 240 and the first dielectric layer 260 of the fin 220 are etched away, leaving only the first dielectric layer 260 located on the sidewall of the dummy gate layer 230 and the sidewall and bottom of the first trench 250.

[0071] In some embodiments of this application, the method for etching the first dielectric layer 260 includes wet etching or dry etching, etc.

[0072] refer to Figure 14 Source 270 and drain 271 are formed in the fins 220 on both sides of the pseudo gate layer 230.

[0073] In some embodiments of this application, the method for forming the source 270 and the drain 271 is, for example, etching trenches in the fins 220 on both sides of the dummy gate layer 230; and epitaxially growing the source 270 and the drain 271 in the trenches.

[0074] refer to Figure 15 A second dielectric layer 261 is formed, with its top higher than the first mask layer 240 and completely covering the fin 220 and the first mask layer 240. The second dielectric layer 261 fills the first trench 250. The second dielectric layer 261 located in the first trench 250 is part of the SDB isolation structure.

[0075] In some embodiments of this application, the method for forming the second dielectric layer 261 includes a chemical vapor deposition process.

[0076] In some embodiments of this application, the material of the second dielectric layer 261 includes silicon oxide, etc.

[0077] refer to Figure 16 The second dielectric layer 261 and the first mask layer 240 above the top surface of the dummy gate layer 230 are removed. The first dielectric layer 260 located on the sidewalls and bottom of the first trench 250 and the second dielectric layer 261 located in the first trench 250 together constitute the SDB isolation structure 280.

[0078] In some embodiments of this application, the methods for removing the second dielectric layer 261 and the first mask layer 240 above the top surface of the dummy gate layer 230 include chemical mechanical polishing and wet etching processes.

[0079] refer to Figure 17 The dummy gate layer 230 is removed to form a second trench 291; Reference Figure 18 A metal gate 290 is formed in the second trench 291.

[0080] In some embodiments of this application, the method for removing the dummy gate layer 230 includes wet etching or dry etching.

[0081] In some embodiments of this application, the method for forming the metal gate 290 includes chemical vapor deposition or physical vapor deposition processes, etc.

[0082] In some embodiments of this application, the material of the metal gate 290 includes aluminum and the like.

[0083] The semiconductor structure formation method described in this application uses the first mask layer as a mask to etch and form a first trench, and forms an SDB isolation structure in the first trench. This can improve the positional accuracy of the SDB isolation structure, reduce the residue on the sidewalls of the SDB isolation structure, thereby improving the quality of the SDB isolation structure and improving device reliability.

[0084] Embodiments of this application also provide a semiconductor structure, referencing Figure 18 The semiconductor structure includes: a semiconductor substrate 200, on which fins 220 are formed, and metal gates 290 are formed on a portion of the top surface and sidewalls of the fins 220; and an SDB isolation structure 280 located between adjacent fins 220 containing adjacent metal gates 290, for isolating adjacent fins 220 containing adjacent metal gates 290.

[0085] refer toFigure 18 In some embodiments of this application, a pad oxide layer 210 is formed between the surface of the semiconductor substrate 200 and the bottom of the fin 220.

[0086] In some embodiments of this application, the material of the pad oxide layer 210 includes silicon oxide and the like.

[0087] In some embodiments of this application, the semiconductor substrate 200 is made of (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide; or (iv) a combination of the above. Furthermore, the semiconductor substrate 200 may be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of this application, the semiconductor substrate 200 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).

[0088] In some embodiments of this application, the material of the metal gate 290 includes aluminum and the like.

[0089] Continue to refer to Figure 18 The SDB isolation structure 280 is composed of a portion of the first dielectric layer 260 and a portion of the second dielectric layer 261. The SDB isolation structure 280 is used to isolate adjacent fins 220.

[0090] Continue to refer to Figure 18 A first dielectric layer 260 is also formed on the sidewall of the metal gate 290. The first dielectric layer 260 located on the sidewall of the metal gate 290 can serve as a sidewall of the metal gate 290.

[0091] In some embodiments of this application, the material of the first dielectric layer 260 includes silicon nitride, etc.

[0092] Continue to refer to Figure 18 The semiconductor structure also includes a source 270 and a drain 271 located in the fins 220 on both sides of the metal gate 290.

[0093] Continue to refer to Figure 18 The semiconductor structure further includes a second dielectric layer 261 that completely covers the fin 220, the top surface of the second dielectric layer 261 being coplanar with the top surface of the metal gate 290.

[0094] In some embodiments of this application, the material of the second dielectric layer 261 includes silicon oxide, etc.

[0095] The semiconductor structure described in this application uses the first mask layer as a mask to etch and form a first trench, and forms an SDB isolation structure in the first trench. This can improve the positional accuracy of the SDB isolation structure, reduce the residue on the sidewalls of the SDB isolation structure, thereby improving the quality of the SDB isolation structure and improving the reliability of the device.

[0096] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0097] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0098] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," when used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0099] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0100] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, on which fins are formed, and a dummy gate material layer is formed on the top surface and sidewalls of the fins; A first mask layer is formed on the top surface of the dummy gate material layer, covering a portion of the dummy gate material layer. A first portion of the first mask layer corresponds to the dummy gate layer of the semiconductor structure, and a second portion of the first mask layer corresponds to the SDB isolation structure of the semiconductor structure. The second portion of the first mask layer is etched away and the dummy gate material layer is etched further to form a first trench in the dummy gate material layer; Using the first portion of the first mask layer as a mask, the dummy gate material layer is etched to expose the fin surface, and simultaneously etched along the first trench until the bottom of the first trench is coplanar with the bottom of the fin, thus forming a dummy gate layer; The first trench is filled with a dielectric material to form an SDB isolation structure.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method of etching away a second portion of the first mask layer and continuing to etch the dummy gate material layer to form a first trench in the dummy gate material layer includes: A second mask layer is formed on the surface of the dummy gate material layer and on the sidewalls and top surface of the first mask layer; A photoresist layer including an opening is formed on the surface of the second mask layer, the opening exposing a second portion of the top surface of the first mask layer; The second mask layer, the first mask layer, and the dummy gate material layer are sequentially etched along the opening, and the first trench is formed in the dummy gate material layer; Remove the photoresist layer and the second mask layer.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The method of sequentially etching the second mask layer, the first mask layer, and the dummy gate material layer along the opening, and forming the first trench in the dummy gate material layer includes: The second mask layer is etched along the opening to form a second opening, the second opening exposing the first mask layer; Etch the first mask layer along the second opening to expose the dummy gate material layer; The dummy gate material layer is etched along the second opening to form the first trench in the dummy gate material layer.

4. The method for forming a semiconductor structure as described in claim 2, characterized in that, The height difference between the bottom of the first trench and the top surface of the pseudo gate material layer is 5 nanometers to 50 nanometers.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, A method for forming an SDB isolation structure by filling the first trench with dielectric material includes: A first dielectric layer is formed on the sidewall of the dummy gate layer and on the sidewall and bottom of the first trench. Source and drain electrodes are formed in the fins on both sides of the dummy gate layer; A second dielectric layer is formed with its top higher than the first mask layer and completely covering the fins and the first mask layer, the second dielectric layer filling the first trench; Remove the second dielectric layer and the first mask layer that are above the top surface of the dummy gate layer.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The method of forming a first dielectric layer on the sidewall of the dummy gate layer and on the sidewall and bottom of the first trench includes: A first dielectric layer is formed on the top and sidewalls of the first mask layer, the top surface of the fin, and the sidewalls and bottom of the first trench. The first dielectric layer on the top surface of the first mask layer and the top surface of the fin is removed by etching.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: The dummy gate layer is removed to form a second trench; A metal gate is formed in the second trench.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, A pad oxide layer is formed between the surface of the semiconductor substrate and the bottom of the fin.

9. A semiconductor structure formed using the semiconductor structure formation method according to any one of claims 1 to 8, characterized in that, include: A semiconductor substrate on which fins are formed, wherein a metal gate is formed on a portion of the top surface and sidewalls of the fins; The SDB isolation structure is located between fins containing adjacent metal gates and is used to isolate the fins containing adjacent metal gates.

10. The semiconductor structure as described in claim 9, characterized in that, A pad oxide layer is formed between the surface of the semiconductor substrate and the bottom of the fin.

11. The semiconductor structure as described in claim 9, characterized in that, Also includes: The first dielectric layer located on the sidewall of the metal gate.

12. The semiconductor structure as claimed in claim 9, characterized in that, Also includes: The source and drain are located in the fins on both sides of the metal gate.

13. The semiconductor structure as described in claim 9, characterized in that, Also includes: A second dielectric layer completely covers the fins, and the top surface of the second dielectric layer is coplanar with the top surface of the metal gate.

Images