Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: providing a substrate comprising adjacent first and second regions, with a stacked structure formed on the first and second regions, the stacked structure of the first and second regions and the substrate forming a first opening; forming a first dielectric layer on the bottom surface and sidewalls of the first opening, with a second opening between the first dielectric layers; forming a second dielectric layer in the second opening; forming a source / drain doped layer; removing the first dielectric layer between the source / drain doped layer and the second dielectric layer to form a groove exposing the sidewalls of the source / drain doped layer near the second dielectric layer; and forming a contact plug in the groove. In this embodiment, the contact plug contacts the top surface of the source / drain doped layer, as well as the sidewalls of the source / drain doped layer near and away from the second dielectric layer. The contact resistance between the contact plug and the source / drain doped layer is low, resulting in good electrical performance of the semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits, the feature size of integrated circuits continues to shrink. In order to adapt to the smaller feature size, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also continuously shortened.

[0003] Therefore, to better adapt to the requirements of proportionally shrinking device dimensions, semiconductor technology has gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as nanowire transistors. In nanowire transistors, the gate surrounds the area where the channel is located. Compared with planar transistors, nanowire transistors have stronger control over the channel by the gate and can better suppress short-channel effects.

[0004] To further improve the integration of semiconductor structures, the Forksheet transistor was proposed, which is the alternative to FinFET and nanowire transistors. It is characterized by a complex double-sided fin structure separated by dielectric walls. Summary of the Invention

[0005] The problem addressed by the embodiments of this application is to provide a semiconductor structure and a method for forming the same, thereby reducing the contact resistance of the contact plugs and source / drain doped layers and optimizing the electrical performance of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of this application provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region and a second region spaced apart from each other, a stacked structure formed on the first region and the second region, a first opening formed between the stacked structure of the first region and the stacked structure of the second region; forming a first dielectric layer on the sidewall of the first opening, the first dielectric layers having a second opening between them; forming a second dielectric layer in the second opening; after forming the second dielectric layer, forming a source / drain doped layer and an interlayer dielectric layer covering the source / drain doped layer in the stacked structure; etching the interlayer dielectric layer to form a trench, the trench exposing the top surface of the source / drain doped layer and the sidewall away from the second dielectric layer; after forming the trench, removing the first dielectric layer between the source / drain doped layer and the second dielectric layer to form a groove; and forming contact plugs in the trench and the groove.

[0007] Accordingly, this application also provides a semiconductor structure, including: a substrate, the substrate including a first region and a second region spaced apart; a first dielectric wall located on the substrate between the first region and the second region; a source / drain doped layer disposed on the substrate of the first region and the second region along the extension direction of the first dielectric wall, and the source / drain doped layer being spaced apart from the first dielectric wall; and a contact plug located between the source / drain doped layer and the first dielectric wall, and covering the top surface of the source / drain doped layer and the sidewall of the source / drain doped layer away from the first dielectric wall.

[0008] Compared with the prior art, the technical solution of this application has the following advantages:

[0009] In the semiconductor structure formation method provided in this application embodiment, the stacked structure of the first region and the second region forms a first opening with the substrate. A first dielectric layer is formed on the sidewall of the first opening. A second opening is formed between the first dielectric layers. The second dielectric layer is formed in the second opening. Source / drain doped layers and an interlayer dielectric layer covering the source / drain doped layers are formed in the stacked structure. Correspondingly, the source / drain doped layers of the first region and the second region are separated by the first dielectric layer and the second dielectric layer. The interlayer dielectric layer is etched to form a trench, and the trench exposes the top of the source / drain doped layers. The first dielectric layer between the source / drain doped layer and the second dielectric layer is removed, forming a groove that exposes the sidewall of the source / drain doped layer near the second dielectric layer. During the formation of contact plugs in the trenches and recesses, the contact plugs contact the top surface of the source / drain doped layer, as well as the sidewalls of the source / drain doped layer near and away from the second dielectric layer. The contact area between the contact plugs and the source / drain doped layer is large, resulting in a small contact resistance, which is beneficial for improving the electrical performance of the semiconductor structure. Attached Figure Description

[0010] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0011] Figures 4 to 23 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure according to the present application;

[0012] Figure 24 and Figure 25 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0013] As the background technology shows, the devices currently being fabricated still suffer from poor performance. This paper analyzes the reasons for this poor performance by examining a semiconductor structure fabrication method.

[0014] refer to Figures 1 to 3 The diagram shows a schematic representation of each step in a method for forming a semiconductor structure.

[0015] like Figures 1 to 3 , Figure 2 for Figure 1 Cross-sectional view at point aa Figure 3 for Figure 1 In the cross-sectional view at bb, a substrate 10 is provided, the substrate 10 including a first region i and a second region ii; a channel structure 12, disposed in the first region i and the second region ii, and the channel structure 12 suspended on the substrate 10, the channel structure 12 including a plurality of channel layers 13 spaced apart in the normal direction of the surface of the substrate 10; a dielectric wall 11, located between the channel structure 12 in the first region i and the channel structure 12 in the second region ii; a gate structure 14, spanning the channel structure 12 and the dielectric wall 11, and covering the channel layers 13, with the extension direction of the gate structure 14 being transverse; a source / drain doped layer 15, located on both sides of the gate structure 14, the source / drain doped layer 15 contacting the two ends of the extension direction of the channel layer 13; and a contact plug 16 located on the top surface and sidewall of the source / drain doped layer 15.

[0016] The dielectric wall 11 is located between the source and drain doped layers 15 in the first region i and the second region ii. The contact plug 16 contacts the top surface of the source and drain doped layer 15 and the sidewall of the source and drain doped layer 15 away from the dielectric wall 11. The contact area between the contact plug 16 and the source and drain doped layer 15 is small. When the semiconductor structure is working, the on-resistance between the contact plug 16 and the source and drain doped layer 15 is large, resulting in poor electrical performance of the semiconductor structure.

[0017] To address the technical problem, this application provides a method for forming a semiconductor structure. The stacked structure of the first and second regions forms a first opening with a substrate. A first dielectric layer is formed on the sidewall of the first opening. A second opening is formed between the first dielectric layers, and a second dielectric layer is formed in the second opening. Source / drain doped layers and an interlayer dielectric layer covering the source / drain doped layers are formed in the stacked structure. The source / drain doped layers of the first and second regions are separated by the first and second dielectric layers. The interlayer dielectric layer is etched to form trenches, which expose the source / drain doped layers. The top surface of the doped layer and the sidewalls away from the second dielectric layer are used to remove the first dielectric layer between the source / drain doped layer and the second dielectric layer, forming a groove. The groove exposes the sidewalls of the source / drain doped layer near the second dielectric layer. During the formation of contact plugs in the trenches and grooves, the contact plugs contact the top surface of the source / drain doped layer, as well as the sidewalls of the source / drain doped layer near and away from the second dielectric layer. The contact area between the contact plugs and the source / drain doped layer is large, resulting in a small contact resistance between the contact plugs and the source / drain doped layer, which is beneficial for improving the electrical performance of the semiconductor structure.

[0018] To make the above-mentioned objectives, features and advantages of the embodiments of this application more apparent and understandable, the specific embodiments of the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0019] Figures 4 to 23 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure according to the application.

[0020] refer to Figure 4 and Figure 5 , Figure 4 This is a top view of the semiconductor structure. Figure 5 for Figure 4 In the cross-sectional view at AA, a substrate 100 is provided, the substrate 100 including a first region I and a second region II spaced apart, a stacked structure 102 formed on the first region I and the second region II, and a first opening 106 formed between the stacked structure 102 of the first region I and the stacked structure 102 of the second region II.

[0021] In this embodiment, the first region I is used to form a first-type transistor, and the second region II is used to form a second-type transistor. The first-type transistor and the second-type transistor have different conductivity types. Specifically, the first-type transistor is a PMOS (Positive Channel Metal Oxide Semiconductor), and the second-type transistor is an NMOS (Negative Channel Metal Oxide Semiconductor).

[0022] The substrate 100 is used to provide a process platform for the subsequent formation of fork-type gate transistors.

[0023] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0024] It should be noted that the substrate 100 includes a plurality of spaced device regions, with the first region I and the second region II located within the device regions. In this embodiment, adjacent regions within adjacent device regions may both be the first region I or both be the second region II. In other embodiments, adjacent regions within adjacent device regions may also have one region being the first region and the other the second region.

[0025] In the step of providing substrate 100, fins 105 are formed between the stacked structure 102 and the substrate 100.

[0026] In this embodiment, the material of the fin 105 is the same as the material of the substrate 100. In other embodiments, the material of the fin may be different from the material of the substrate.

[0027] The fins 105 are used to space the channel stack 101 and the substrate 100, and to provide process space for forming an isolation structure on the substrate 100 between the fins 105.

[0028] In the step of providing substrate 100, the stacked structure 102 includes: a plurality of channel stacks 101, the channel stacks 101 including a sacrificial layer 1011 and a channel layer 1012 located on the sacrificial layer 1011.

[0029] The channel stack 101 provides a process basis for the subsequent channel layer 1012 to be suspended. The sacrificial layer 1011 supports the channel layer 1012, provides process conditions for the subsequent channel layer 1012 to be suspended, and also occupies space for the gate structure to be formed later.

[0030] When the semiconductor structure is in operation, the channel layer 1012 serves as the channel region.

[0031] In this embodiment, the channel layer 1012 is more difficult to etch than the sacrificial layer 1011, so the channel layer 1012 is less likely to be damaged when the sacrificial layer 1011 is removed.

[0032] In this embodiment, the channel layer 1012 is made of silicon; the sacrificial layer 1011 is made of silicon germanide. In other embodiments, the channel layer may also be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ide, and the sacrificial layer may also be made of silicon.

[0033] It should be noted that the stacked structure 102 also includes a top sacrificial layer 127. The top sacrificial layer 127 and the sacrificial layer 1011 together occupy space for the subsequent formation of the gate structure. As a result, the gate structure formed on the top channel layer 1012 is thicker. When the semiconductor structure is working, the gate structure has a stronger control over the topmost channel layer 1012, which is beneficial to improving the electrical performance of the semiconductor structure.

[0034] In this embodiment, the first opening 106 provides process space for the subsequent formation of the first dielectric layer and the second dielectric layer.

[0035] It should be noted that, in the step of providing the substrate 100, a bottom sacrificial layer 104 is formed between the stacked structure 102 and the fin 105.

[0036] The bottom sacrificial layer 104 occupies space for the isolation layer that will be formed later.

[0037] The etch resistance of the bottom sacrificial layer 104 is less than that of the sacrificial layer 1011. In the subsequent step of removing the bottom sacrificial layer 104, the sacrificial layer 1011 is not easily damaged, making it difficult to reduce the formation area of ​​the gate structure.

[0038] Specifically, the material of the bottom sacrificial layer 104 includes silicon germanide, and the concentration of germanium ions in the bottom sacrificial layer 104 is greater than the concentration of germanium ions in the sacrificial layer 104.

[0039] In this embodiment, during the step of providing the substrate 100, a power track line 103 is also formed in the substrate 100. The power track line 103 is an elongated structure, and the extension direction of the power track line 103 is parallel to that of the stacked structure 102.

[0040] Power rails 103 are used to provide power to different components of the chip. In this embodiment, the power rails 103 are located in the substrate 100 and are buried power rails (BPR). This facilitates the freeing up of wiring resources for back-end interconnects and reduces the height of standard cells to meet the needs of continuous logic chip miniaturization. In addition, the buried power rails employ a technique of increasing back-end (BEOL) resistance through pitch miniaturization, which also helps to provide a lower resistance local current distribution.

[0041] The power track 103 is made of a conductive material. In this embodiment, the power track 103 is made of a metallic material, including one or more of Co, W, Ni, and Ru. The low resistivity of the power track 103 material is beneficial for improving RC delay and increasing the chip's processing speed.

[0042] In this embodiment, a cap layer 107 is formed on the top of the power track line 103.

[0043] During the formation of the semiconductor structure, the capping layer 107 is used to protect the power rail line 103 from damage.

[0044] Specifically, the material of the capping layer 107 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, boron silicon nitride, and boron silicon carbide. In this embodiment, the material of the capping layer 107 includes silicon nitride.

[0045] In this embodiment, an insulating layer 108 is also formed between the sidewall of the power track line 103 and the substrate 100. The insulating layer 108 is used to achieve insulation between the power track line 103 and the substrate 100. Therefore, the material of the insulating layer 108 is an insulating material, such as silicon oxide, silicon oxynitride, or silicon nitride.

[0046] In this embodiment, during the step of providing the substrate 100, an isolation structure 109 is formed on the substrate 100 between the fins 105, and the top surface of the isolation structure 109 is lower than or flush with the bottom surface of the bottom sacrificial layer 104.

[0047] The top of the isolation structure 109 is lower than or flush with the top surface of the fin 105, which makes the process window for removing the bottom sacrificial layer 104 larger.

[0048] The isolation structure 109 is used for electrical isolation of adjacent fins 105. In this embodiment, the material of the isolation structure 109 includes silicon oxide.

[0049] Specifically, the first opening 106 is formed by an isolation structure 109, a stacked structure 102, and a bottom sacrificial layer 104.

[0050] refer to Figure 6 A first dielectric layer 111 is formed on the sidewall of the first opening 106, and a second opening 110 is formed between the first dielectric layers 111.

[0051] The second opening 110 provides process space for the subsequent formation of the second dielectric layer. The first dielectric layer 111 occupies the area subsequently used to form the groove.

[0052] In this embodiment, the etching resistance of the first dielectric layer 111 is less than that of the second dielectric layer, so the second dielectric layer is less likely to be damaged in the subsequent step of removing the first dielectric layer 111.

[0053] Specifically, the material of the first dielectric layer 111 includes one or both of silicon oxide and silicon oxynitride. In this embodiment, the material of the first dielectric layer 111 includes silicon oxide. Silicon oxide has low stress, is a commonly used and low-cost dielectric material, and has high process compatibility, which helps to reduce the process difficulty and cost of forming the first dielectric layer 111.

[0054] It should be noted that the density of the first dielectric layer 111 is less than that of the isolation structure 109, so that the isolation structure 109 is less likely to be damaged during the subsequent removal of the first dielectric layer 111.

[0055] It should be noted that in the step of forming the first dielectric layer 111, the lateral dimension of the first dielectric layer 111, which is parallel to the surface of the substrate 100 and perpendicular to the extension direction of the stacked structure 102, should not be too large or too small. Subsequently, a second dielectric layer is formed in the second opening 110, and a source / drain doped layer and an interlayer dielectric layer covering the source / drain doped layer are formed in the stacked structure 102. The interlayer dielectric layer is etched to form a trench, which exposes the top surface of the source / drain doped layer and the sidewall away from the second dielectric layer. After forming the trench, the first dielectric layer between the source / drain doped layer and the second dielectric layer is removed to form a groove, which exposes the sidewall of the source / drain doped layer near the second dielectric layer. Contact plugs are formed in the trench and the groove. If the lateral dimension of the first dielectric layer 111 is too small, the first dielectric layer 111 between the source / drain doped layer and the second dielectric layer is not easily removed, and the corresponding groove is not easily formed. During the formation of the contact plug, the contact plug is not easily formed between the second dielectric layer and the source / drain doped layer, resulting in the contact plug only contacting the top surface of the source / drain doped layer and the sidewall of the source / drain doped layer away from the second dielectric layer. The contact area between the contact plug and the source / drain doped layer is small, the contact resistance between the contact plug and the source / drain doped layer is large, and the electrical performance of the semiconductor structure is poor. If the lateral dimension of the first dielectric layer 111 is too large, it will occupy too much of the lateral dimension of the first opening 106, resulting in the lateral dimension of the second opening 110 being too small. Correspondingly, the lateral dimension of the second dielectric layer subsequently formed in the second opening 110 is too small, and the effect of the second dielectric layer in electrically isolating the contact plug in the first region I and the contact plug in the second region II is poor. The contact plug in the first region I and the contact plug in the second region II are prone to bridging, resulting in poor electrical performance of the semiconductor structure. In this embodiment, in the step of forming the first dielectric layer 111, the lateral dimension of the first dielectric layer 111 is 3 nanometers to 20 nanometers.

[0056] In this embodiment, the first dielectric layer 111 is formed on the sidewall of the first opening 106, and the corresponding isolation structure 109 between the stacked structure 102 of the first region I and the stacked structure 102 of the second region II is exposed. Thus, the second dielectric layer subsequently formed in the second opening 111 contacts the isolation structure 109. During the subsequent removal of the first dielectric layer 111 between the source / drain doped layer and the second dielectric layer, it is not easy to form a channel connecting the source / drain doped layer of the first region I and the source / drain doped layer of the second region II at the bottom of the second dielectric layer. Correspondingly, during the formation of contact plugs in the trenches and recesses, the second dielectric layer makes it difficult for the contact plugs of the first region I and the contact plugs of the second region II to bridge, which is beneficial to improving the electrical performance of the semiconductor structure.

[0057] The step of forming the first dielectric layer 111 includes: forming a first dielectric material layer (not shown in the figure) that conformally covers the sidewall and bottom surface of the first opening 106; removing the first dielectric material layer on the bottom surface of the first opening 106, and the remaining first dielectric material layer located on the sidewall of the first opening 106 as the first dielectric layer 111.

[0058] In this embodiment, the first dielectric material layer is formed using atomic layer deposition (ALD). ALD involves multiple deposition cycles, which improves the thickness uniformity of the first dielectric material layer, allowing it to conformally cover the bottom and sidewalls of the first opening 106. Furthermore, ALD offers good gap-filling performance and step coverage. In other embodiments, chemical vapor deposition (CVD) can also be used to form the first dielectric material layer.

[0059] In this embodiment, a dry etching process is used to remove the first dielectric material layer on the bottom surface of the first opening 106. Specifically, a maskless dry etching process is used. The maskless dry etching process has anisotropic etching characteristics, which helps to ensure complete removal of the first dielectric material layer at the bottom of the first opening 106 while minimizing damage to other film structures. It also helps to avoid lateral etching of the first dielectric material layer, resulting in a larger lateral dimension of the first dielectric layer 111. This makes the first dielectric layer 111 easier to remove in subsequent processes, improving the formation quality of the groove. Consequently, the contact plugs formed in the groove have better formation quality, resulting in lower contact resistance between the source / drain doped layers and the contact plugs, which is beneficial for improving the electrical performance of the semiconductor structure. Furthermore, the maskless dry etching process eliminates the need for a photomask, reducing the process cost of forming the first dielectric layer 111.

[0060] Specifically, in this embodiment, the second opening 110 is formed by the isolation structure 109 and the first dielectric layer 111.

[0061] It should be noted that, in the step of forming the first dielectric material layer using atomic layer deposition process, the first dielectric material layer is also formed on the top surface of the stacked structure 102 and on the sidewall away from the second opening 110.

[0062] Correspondingly, the first dielectric layer 111 is also formed on the sidewall of the stacked structure 102 away from the first opening 110.

[0063] In other embodiments, in the step of forming a first dielectric layer on the sidewall of the first opening, the first dielectric layer is also formed on the bottom surface of the first opening.

[0064] The first dielectric layer on the bottom surface and sidewall of the first opening can be formed in one step, eliminating the need to remove the first dielectric layer on the bottom surface of the first opening, simplifying the process steps and improving the formation efficiency of the semiconductor structure.

[0065] refer to Figure 7 A second dielectric layer 112 is formed in the second opening 110.

[0066] Subsequently, source / drain doped layers and an interlayer dielectric layer covering the source / drain doped layers are formed in the stacked structure 102. Correspondingly, the source / drain doped layers in the first region I and the second region II are separated by a first dielectric layer 111 and a second dielectric layer 112. The interlayer dielectric layer is etched to form trenches, which expose the top surface of the source / drain doped layers and the sidewalls away from the second dielectric layer 112. After forming the trenches, the first dielectric layer between the source / drain doped layers and the second dielectric layer is removed to form grooves, which expose the sidewalls of the source / drain doped layers near the second dielectric layer 112. Contact plugs are formed in the trenches and grooves. The second dielectric layer 112 is used to electrically isolate the contact plugs in the first region I and the second region II, making it less likely for the contact plugs in the first region I and the second region II to bridge, thereby improving the electrical performance of the semiconductor structure.

[0067] Specifically, the material of the second dielectric layer 112 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride, and silicon boron carbide. In this embodiment, the material of the second dielectric layer 112 includes silicon nitride, which is a commonly used dielectric material in processes, which is beneficial to improving the process compatibility of the second dielectric layer 112 and reducing the difficulty of forming the second dielectric layer 112.

[0068] The step of forming a second dielectric layer 112 in the second opening 110 includes: forming a second dielectric material layer that conformally covers the stacked structure 102 and the second opening 110; removing the second dielectric material layer that exposes the second opening 110, and the remaining second dielectric material layer in the second opening 110 serving as the second dielectric layer 112.

[0069] In this embodiment, atomic layer deposition (ALD) is used to form the second dielectric material layer. ALD involves multiple deposition cycles, resulting in a film with a single-atom thickness. This minimizes voids in the second dielectric material layer, allowing it to conformally cover the bottom and sidewalls of the second opening 110, thus improving the film quality and resulting in a higher quality second dielectric layer 112. In other embodiments, chemical vapor deposition (CVD) can also be used to form the second dielectric material layer.

[0070] In this embodiment, an isotropic etching process is used to remove the second dielectric material layer that exposes the second opening 110, and the remaining second dielectric material layer located in the second opening 110 serves as the second dielectric layer 112.

[0071] It should be noted that during the process of removing the second dielectric material layer that exposes the second opening 110, the first dielectric layer 111 that exposes the second opening 110 is also removed.

[0072] In this embodiment, the isotropic etching process includes a wet etching process. Wet etching has a high etching rate, is simple to operate, and has low process cost.

[0073] It should be noted that in the step of forming the second dielectric layer 112 with the direction parallel to the surface of the substrate 100 and perpendicular to the extension direction of the stacked structure 102 as the lateral direction, the lateral dimension of the second dielectric layer 112 should not be too large or too small. If the lateral dimension of the second dielectric layer 112 is too large, the lateral dimension of the first dielectric layer 111 needs to be smaller. Subsequently, the first dielectric layer 111 between the source / drain doped layer and the second dielectric layer 112 is difficult to remove, and the corresponding groove is difficult to form. During the formation of the contact plug, the contact plug is difficult to form between the second dielectric layer 112 and the source / drain doped layer, resulting in the contact plug only contacting the top surface of the source / drain doped layer and the sidewall of the source / drain doped layer away from the second dielectric layer 112. The contact area between the contact plug and the source / drain doped layer is small, and the contact resistance between the contact plug and the source / drain doped layer is large, leading to poor electrical properties of the semiconductor structure. Furthermore, it occupies too much lateral dimension of the substrate 100 surface, resulting in low planar utilization of the substrate 100 surface and reduced integration density of the semiconductor structure. If the lateral dimension of the second dielectric layer 112 is too small, the subsequent electrical isolation effect of the second dielectric layer 112 on the contact plugs in the first region I and the second region II will be poor. The contact plugs in the first region I and the second region II are prone to bridging, resulting in poor electrical performance of the semiconductor structure. In this embodiment, the lateral dimension of the second dielectric layer 112 is 3 nanometers to 30 nanometers.

[0074] The method for forming the semiconductor structure further includes: after forming the second dielectric layer 112, removing the bottom sacrificial layer 104; after removing the bottom sacrificial layer 104, forming an isolation material layer on the fin 105, isolation structure 109 and capping layer 107 exposed on the stacked structure 102; etching back a portion of the isolation material layer to form an isolation layer 126, wherein the top surface of the isolation layer 126 is lower than or flush with the bottom surface of the stacked structure 102.

[0075] The isolation layer 126 is used to electrically isolate the fin 105 and subsequently form the gate structure.

[0076] refer to Figure 8 The method for forming the semiconductor structure includes: after forming the second dielectric layer 112 and before forming the source / drain doped layer, forming a pseudo-gate structure 113 that spans the stacked structure 102, the first dielectric layer 111, and the second dielectric layer 112, wherein the pseudo-gate structure 113 covers part of the top wall and part of the side wall of the stacked structure 102.

[0077] The pseudo-gate structure 113 occupies space for the gate structure to be formed in subsequent processes.

[0078] In this embodiment, the pseudo gate structure 113 includes a pseudo gate oxide layer (not shown in the figure) that conformally covers part of the top surface and part of the sidewalls of the channel stack 101, and a pseudo gate layer (not shown in the figure) located on the pseudo gate oxide layer.

[0079] In this embodiment, the material of the dummy gate oxide layer includes silicon oxide. In other embodiments, the material of the dummy gate oxide layer may also be silicon oxynitride.

[0080] In this embodiment, the dummy gate layer is made of polycrystalline silicon. In other embodiments, the dummy gate layer may also be made of amorphous carbon.

[0081] It should be noted that, in the step of providing the substrate, a gate sidewall layer (not shown in the figure) is formed on the sidewall of the pseudo-gate structure 113.

[0082] The gate sidewall layer is used to define the formation location of the subsequently formed source and drain doped layers, and also to protect the sidewalls of the dummy gate structure 113 from damage during the formation of the subsequent semiconductor structure.

[0083] The material of the gate sidewall layer includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride, and silicon boron carbide.

[0084] refer to Figures 9 to 14 In the stacked structure 102, a source / drain doped layer 114 is formed and a layer covering the source / drain doped layer 114 (e.g., ...) is formed. Figure 13 Interlayer dielectric layer 115 (as shown) Figure 13 (As shown).

[0085] When the semiconductor structure is in operation, the source and drain doped layers 114 are used to provide stress to the channel and improve the migration rate of carriers in the channel.

[0086] The second region II is used to form the NMOS, and the source and drain doped layers 114 serve as the source and drain of the NMOS. When the semiconductor structure is operating, the source and drain doped layers 114 apply tensile stress to the channel, which can increase the electron migration rate.

[0087] The first region I is used to form the PMOS, and the source and drain doped layers 114 are used as the source and drain of the PMOS. When the semiconductor structure is working, the source and drain doped layers 114 apply compressive stress to the channel, and compressing the channel can improve the hole mobility.

[0088] Interlayer dielectric layer 115 is used for electrical isolation of adjacent devices.

[0089] In this embodiment, the material of the interlayer dielectric layer 115 is an insulating material. Specifically, the material of the interlayer dielectric layer 115 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the interlayer dielectric layer 115.

[0090] Specifically, the steps for forming the source / drain doped layer 114 and the interlayer dielectric layer 115 include:

[0091] like Figure 9 and Figure 10 As shown, Figure 9 This is a top view. Figure 10 for Figure 9 In the cross-sectional view at CC, the steps of forming the source / drain doped layer 114 include: etching the stacked structure 102 on both sides of the pseudo-gate structure 113 to form source / drain openings 116.

[0092] The source / drain opening 116 provides process space for the subsequent formation of the source / drain doped layer. The source / drain opening 116 exposes the isolation layer 126.

[0093] In this embodiment, a dry etching process is used to etch the stacked structures 102 on both sides of the dummy gate structure 113 to form source / drain openings 116. The dry etching process has anisotropic etching characteristics, good control over the etching profile, and can achieve fairly accurate pattern transformation, which is beneficial for ensuring that the morphology of the source / drain openings 116 meets process requirements and also helps improve the removal efficiency of the stacked structures 102. Furthermore, during the formation of the source / drain openings 116 using the dry etching process, the top of the isolation layer 126 can be used as the etching stop position, reducing damage to other film layers; moreover, by changing the etching gas, the sacrificial layer 1011 and the channel layer 1012 can be etched in the same etching equipment, simplifying the process steps.

[0094] like Figure 11 As shown, the method for forming the semiconductor structure further includes: laterally etching the sacrificial layer 111 exposed by the source / drain opening 116 to form a sidewall groove 117.

[0095] The sidewall groove 117 provides process space for the subsequent formation of the inner sidewall layer.

[0096] In this embodiment, an isotropic etching process is used to remove the sacrificial layer 111 exposed by the source / drain opening 116, forming a sidewall groove 117. Specifically, the isotropic etching process includes a wet etching process, which has a high etching rate, is simple to operate, and has low process cost.

[0097] like Figure 12 As shown, an inner sidewall layer 118 is formed in the sidewall groove 117.

[0098] The inner wall layer 118 is used for electrical isolation of the subsequently formed source / drain doped layers and gate structure.

[0099] In this embodiment, the inner wall layer 118 is made of a low-k dielectric material. Low-k dielectric materials (referring to dielectric materials with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) have excellent insulating properties. This reduces the electrical coupling effect between the gate structure and the source / drain doped layers subsequently formed on both sides of the inner wall layer 118, thereby reducing parasitic capacitance and improving the electrical performance of the transistor structure.

[0100] Specifically, the material of the inner wall layer 118 includes: SiON, SiBCN, SiCN, carbon-doped SiN, or oxygen-doped SiN. In this embodiment, the material of the inner wall layer 118 includes carbon-doped SiN or oxygen-doped SiN.

[0101] The steps of forming the inner sidewall layer 118 include: forming a sidewall material layer (not shown in the figure) that conformally covers the source / drain opening 116, the sidewall groove 117, and the dummy gate structure 113; removing the sidewall material layer from the surface of the source / drain opening 116 and the dummy gate structure 113, and the remaining sidewall material layer located in the sidewall groove 117 as the inner sidewall layer 118.

[0102] like Figure 13 and Figure 14 As shown, Figure 14 for Figure 13 In the cross-sectional view at DD, an epitaxial layer is formed in the source / drain opening 116 using a selective epitaxial growth process. During the formation of the epitaxial layer, the epitaxial layer is in-situ doped to form a source / drain doped layer 114.

[0103] Specifically, source / drain doped layers 114 are formed in the stacked structure 102 on both sides of the pseudo-gate structure 113.

[0104] The epitaxial layer is formed by selective epitaxy to improve the formation quality and purity of the epitaxial layer, and to improve the adhesion of the epitaxial layer at the source / drain opening 116. The epitaxial layer obtained by selective epitaxial growth has high purity and few defects, which is beneficial to improving the formation quality of the source / drain doped layer 114.

[0105] Continue to refer to Figure 13 and Figure 14 The method for forming the semiconductor structure further includes: after forming the source / drain doped layer 114, forming the interlayer dielectric layer 115 covering the side of the dummy gate structure 113, and the interlayer dielectric layer 115 exposing the top of the dummy gate structure 113.

[0106] In this embodiment, the interlayer dielectric layer 115 is formed using a flowable chemical vapor deposition (FCVD) process. The FCVD process has good filling capabilities, which helps reduce the probability of voids and other defects forming within the interlayer dielectric layer 115, thereby improving the film quality of the interlayer dielectric layer 115.

[0107] refer to Figure 15 and Figure 16 The method for forming the semiconductor structure further includes: after forming the interlayer dielectric layer 115, removing the dummy gate structure 113, and forming a gate opening 119 in the interlayer dielectric layer 115.

[0108] The gate opening 119 provides process space for the subsequent formation of the gate structure.

[0109] In this embodiment, a wet etching process is used to remove the dummy gate structure 113. The wet etching process has a high etching rate, is simple to operate, and has low processing costs.

[0110] In this embodiment, the dummy gate structure 113 includes a dummy gate oxide layer and a dummy gate layer. The material of the dummy gate oxide layer includes silicon oxide, and the material of the dummy gate layer includes polysilicon. Specifically, in the step of removing the dummy gate structure 113, the etching solution used includes ammonia and tetramethylammonium hydroxide solution.

[0111] It should be noted that the method for forming the semiconductor structure further includes: after removing the dummy gate structure 113, the sacrificial layer 1011 is also removed to form the channel 120.

[0112] Specifically, during the process of removing the sacrificial layer 1011, the top sacrificial layer 127 is also removed.

[0113] The channel 120 provides process space for the subsequent formation of the gate structure.

[0114] In this embodiment, a wet etching process is used to remove the sacrificial layer 1011 and the top sacrificial layer 127. The wet etching process has a high etching rate, is simple to operate, and has low process cost.

[0115] Specifically, both the sacrificial layer 1011 and the top sacrificial layer 127 are made of silicon germanide. Correspondingly, the etching solution used in the wet etching process to remove the sacrificial layer 1011 and the top sacrificial layer 127 is an HCl solution.

[0116] It should be noted that, in the step of removing the pseudo-gate structure 113, the etching rate of the pseudo-gate structure 113 is greater than the etching rate of the channel layer 1012; in the step of removing the sacrificial layer 1011 and the top sacrificial layer 127, the etching rate of the sacrificial layer 1011 and the top sacrificial layer 127 is greater than the etching rate of the channel layer 1012, making the channel layer 1012 less susceptible to damage.

[0117] refer to Figure 17 The method for forming the semiconductor structure includes: removing the first dielectric layer 111 exposed by the gate opening 119 and the channel 120, and exposing the sidewall of the second dielectric layer 112.

[0118] The sidewalls of the second dielectric layer 112 are exposed to prepare for the subsequent formation of a third dielectric layer on the sidewalls of the second dielectric layer 112.

[0119] In this embodiment, an isotropic dry etching process is used to remove the first dielectric layer 111 exposed by the gate opening 119 and the channel 120. The isotropic dry etching process easily removes the first dielectric layer 111 between the channel layer 1012 and the second dielectric layer 112, providing process space for the subsequent formation of the third dielectric layer 122 between the second dielectric layer 112 and the channel layer 1012.

[0120] refer to Figure 18 A third dielectric layer 122 is formed on the sidewall of the second dielectric layer 112.

[0121] The third dielectric layer 122 and the second dielectric layer 112 serve as dielectric walls that block the channel layer 1012 of the first region I and the channel layer 1012 of the second region II. Compared with the case of only the second dielectric layer, forming the third dielectric layer can reduce the probability of bridging between the channel layers of the first region and the second region, thereby improving the electrical performance of the semiconductor structure.

[0122] Specifically, the material of the third dielectric layer 122 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, boron silicon nitride, and boron silicon carbide. In this embodiment, the material of the third dielectric layer 122 includes silicon nitride.

[0123] The step of forming a third dielectric layer 122 on the sidewall of the second dielectric layer 112 includes: forming a third dielectric material layer (not shown) conformally covering the gate opening 119, the channel 120 and the second dielectric layer 112; removing the third dielectric material layer in the gate opening 119 and the channel 120, and the remaining third dielectric material layer located on the sidewall of the second dielectric layer 112 as the third dielectric layer 122.

[0124] In this embodiment, the third dielectric material layer is formed using atomic layer deposition (ALD). ALD involves multiple deposition cycles, which improves the thickness uniformity of the third dielectric material layer, enabling it to conformally cover the surfaces of the gate opening 119, channel 120, and the second dielectric layer 112. Furthermore, ALD offers good gap-filling performance and step coverage, thereby enhancing the conformal coverage capability of the third dielectric material layer. In other embodiments, the third dielectric material layer can also be formed using chemical vapor deposition (CVD).

[0125] In this embodiment, a wet etching process is used to remove the third dielectric material layer in the gate opening 119 and channel 120. The wet etching process has a high etching rate, is simple to operate, and has low processing cost.

[0126] refer to Figure 19 and Figure 20 A gate structure 121 is formed in the gate opening 119 and the channel 120.

[0127] When the semiconductor structure is in operation, the gate structure 121 is used to control the opening and closing of the channel. The gate structure 121 is formed on the isolation layer 126.

[0128] In this embodiment, the gate structure 121 is made of a magnesium-tungsten alloy. In other embodiments, the gate structure may also be made of W, Al, Cu, Ag, Au, Pt, Ni, or Ti.

[0129] Accordingly, in the step of forming the gate structure 121, the gate structure 121 spans the second dielectric layer 112 and the third dielectric layer 122.

[0130] The method for forming the semiconductor structure further includes: before forming the gate structure 121, forming a gate dielectric layer (not shown in the figure) in the gate opening 119.

[0131] The gate dielectric layer is used to achieve electrical isolation between the gate structure 121 and the channel layer 1012. It should be noted that the material of the gate dielectric layer includes a high-k dielectric material. A high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide.

[0132] In this embodiment, the material of the gate dielectric layer includes HfO2. In other embodiments, the material of the gate dielectric layer may also be selected from one or more of ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.

[0133] refer to Figure 21 The interlayer dielectric layer 115 is etched to form a trench 123, which exposes the top surface of the source / drain doped layer 114 and the sidewalls away from the second dielectric layer 112.

[0134] The groove 123 provides process space for the subsequent formation of the contact plug.

[0135] In this embodiment, the interlayer dielectric layer 115 is etched using a dry etching process to form trenches 123. Dry etching has anisotropic etching characteristics, good control over the etching profile, and can achieve fairly accurate pattern transformation. This is beneficial for ensuring that the morphology of the trenches 123 meets process requirements and also helps improve the removal efficiency of the interlayer dielectric layer 115.

[0136] It should be noted that during the formation of the trench 123, the trench 123 also exposes the sidewalls of the source / drain doped layer 114 that are far from the gate structure 121.

[0137] The trench 123 exposes the sidewall of the source / drain doped layer 114 away from the gate structure 121. The contact plug subsequently formed in the trench 123 contacts the sidewall of the source / drain doped layer 114 away from the gate structure 121. The contact area between the contact plug and the source / drain doped layer 114 is large, which helps to reduce the contact resistance.

[0138] refer to Figure 22 After forming the trench 123, the first dielectric layer 111 between the source / drain doped layer 114 and the second dielectric layer 112 is removed to form a groove 124, which exposes the sidewall of the source / drain doped layer 114 near the second dielectric layer 112.

[0139] The trench 123 exposes the top surface of the source / drain doped layer 114 and the sidewall away from the second dielectric layer 112. After removing the first dielectric layer 111 between the source / drain doped layer 114 and the second dielectric layer 112, a groove 124 is formed, which exposes the sidewall of the source / drain doped layer 114 near the second dielectric layer 112. Thus, during the formation of contact plugs in the trench 123 and groove 124, the contact plugs contact the top surface of the source / drain doped layer 114, as well as the sidewalls of the source / drain doped layer 114 near and away from the second dielectric layer 112. The contact area between the contact plugs and the source / drain doped layer 114 is large, resulting in a small contact resistance, which is beneficial for improving the electrical performance of the semiconductor structure.

[0140] In this embodiment, a dry etching process is used to remove the first dielectric layer 111 between the source / drain doped layer 114 and the second dielectric layer 112, forming a groove 124. The groove 124 exposes the sidewall of the source / drain doped layer 114 near the second dielectric layer 112. The dry etching process has anisotropic etching characteristics, good control over the etching profile, and can achieve fairly accurate pattern transformation. It removes the first dielectric layer 111 without easily damaging the second dielectric layer 112. Furthermore, the dry etching process also helps to improve the removal efficiency of the first dielectric layer 111.

[0141] In this embodiment, the material of the first dielectric layer 111 includes silicon oxide. Correspondingly, in the process of dry etching to remove the first dielectric layer 111 between the source / drain doped layer 114 and the second dielectric layer 112, the etching gas used includes hydrogen fluoride.

[0142] It should be noted that, in this embodiment, the material of the isolation structure 109 includes silicon oxide, and the material of the first dielectric layer 111 also includes silicon oxide. The density of the first dielectric layer 111 is less than that of the isolation structure 109, so that the isolation structure 109 is less likely to be damaged during the step of removing the first dielectric layer 111.

[0143] refer to Figure 23 Contact plugs 125 are formed in the grooves 123 and recesses 124.

[0144] The contact plug 125 is used to connect the source / drain doped layer 114 to the subsequent metal. During the formation of the contact plug 125 in the trench 123 and recess 124, the contact plug 125 forms between the source / drain doped layer 114 and the second dielectric layer 112, on the top surface of the source / drain doped layer 114, and on the sidewall of the source / drain doped layer 114 away from the second dielectric layer 112. The contact area between the contact plug 125 and the source / drain doped layer 114 is large, resulting in a low contact resistance, which is beneficial for improving the electrical performance of the semiconductor structure.

[0145] The contact plug 125 is made of a conductive material. Specifically, the conductive material includes one or more of W, Co, Cu, and Al. In this embodiment, the contact plug 125 is made of W. W has stable chemical properties and a mature formation process, which is beneficial for controlling the formation quality of the semiconductor structure and improving the formation rate of the semiconductor structure.

[0146] It should be noted that, in this embodiment, the top surface of the contact plug 125 is lower than or flush with the top of the second dielectric layer 112.

[0147] The steps of forming the contact plug 125 include: forming a conductive material layer (not shown) in the trench 123 and the recess 124; removing the conductive material layer above the second dielectric layer 112, and the remaining conductive material layer serving as the contact plug 125.

[0148] It should be noted that the trench 123 also exposes the sidewall of the source / drain doped layer 114 away from the gate structure 121, and correspondingly, the contact plug 125 is in contact with the sidewall of the source / drain doped layer 114 away from the gate structure 121.

[0149] Accordingly, embodiments of this application also provide a semiconductor structure. (See reference...) Figure 24 and Figure 25 , Figure 24 This is a cross-sectional view of the source / drain doped layers, parallel to the extension direction of the gate structure. Figure 25 The diagram shows a schematic representation of an embodiment of the semiconductor structure of the present invention, with the gate structure excluding the gate structure and extending parallel to the gate structure.

[0150] The semiconductor structure includes: a substrate 200, the substrate 200 including a first region I and a second region II spaced apart; a first dielectric wall 212 located on the substrate 200 in the first region I and the second region II; a source / drain doped layer 214 disposed on the substrate 200 in the first region I and the second region II along the extending direction of the first dielectric wall 212, and the source / drain doped layer 214 being spaced apart from the first dielectric wall 212; and a contact plug 225 located between the source / drain doped layer 214 and the first dielectric wall 212, and covering the top surface of the source / drain doped layer 214 and the sidewall of the source / drain doped layer 214 away from the first dielectric wall 212.

[0151] In the semiconductor structure provided in this application embodiment, source / drain doped layers 214 are disposed on the substrate 200 of the first region I and the second region II along the extension direction of the first dielectric wall 212, and the source / drain doped layers 214 and the first dielectric wall 212 are spaced apart; a contact plug 225 is located between the source / drain doped layers 214 and the first dielectric wall 212, and covers the top surface of the source / drain doped layers 214 and the sidewalls of the source / drain doped layers 214 away from the first dielectric wall 212. Compared with the case where the contact plug only covers the top surface of the source / drain doped layers and the sidewalls of the source / drain doped layers away from the first dielectric wall, the contact area between the contact plug 225 and the source / drain doped layers 214 in this application embodiment is larger, thereby reducing the contact resistance between the contact plug 225 and the source / drain doped layers 214, which is beneficial to improving the electrical performance of the semiconductor structure.

[0152] In this embodiment, the first region I is used to form a first-type transistor, and the second region II is used to form a second-type transistor. The first-type transistor and the second-type transistor have different conductivity types. Specifically, the first-type transistor is a PMOS (Positive Channel Metal Oxide Semiconductor), and the second-type transistor is an NMOS (Negative Channel Metal Oxide Semiconductor).

[0153] In this embodiment, the substrate 200 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium bismuth, etc., and the substrate may also be other types of substrates such as silicon on insulator or germanium on insulator.

[0154] It should be noted that the substrate 200 includes multiple spaced device regions, with the first region I and the second region II located within the device regions. In this embodiment, adjacent regions within adjacent device regions may both be either the first region I or both be the second region II. In other embodiments, adjacent regions within adjacent device regions may also have one region being the first region and the other the second region.

[0155] During the formation of the semiconductor structure, the first dielectric wall 212 is used to electrically isolate the contact plug 225 in the first region I and the contact plug 225 in the second region II, so that the contact plug 225 in the first region I and the contact plug 225 in the second region II are not easily bridged, which is beneficial to improving the electrical performance of the semiconductor structure.

[0156] Specifically, the material of the first dielectric wall 212 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride, and silicon boron carbide. In this embodiment, the material of the first dielectric wall 212 includes silicon nitride, which is a commonly used dielectric material in processes. This is beneficial for improving the process compatibility of the first dielectric wall 212 and reducing the difficulty of forming the first dielectric wall 212.

[0157] It should be noted that the lateral direction of the first dielectric wall 212, which is parallel to the surface of the substrate 200 and perpendicular to the extension direction of the first dielectric wall 212, should not be too large or too small. If the lateral dimension of the first dielectric wall 212 is too large, it will occupy too much of the lateral dimension of the substrate 200 surface, resulting in low planar utilization of the substrate 200 surface and reducing the integration density of the semiconductor structure. In addition, if the lateral dimension of the first dielectric wall 212 is too large, it will occupy too much of the lateral region between the source / drain doped layer 214 of the first region I and the source / drain doped layer 214 of the second region II, resulting in a smaller lateral dimension of the contact plug 225 between the source / drain doped layer 214 and the first dielectric wall 212. The formation of the contact plug 225 between the source / drain doped layer 214 and the first dielectric wall 212 will be more difficult, and the effect of the contact plug 225 between the source / drain doped layer 214 and the first dielectric wall 212 in reducing the contact resistance between the source / drain doped layer 214 and the contact plug 225 will not be significant, making it difficult for the semiconductor structure to meet the process requirements. If the lateral dimension of the first dielectric wall 212 is too small, the effect of electrically isolating the contact plugs 225 in the first region I and the second region II will be poor. The contact plugs 225 in the first region I and the second region II are prone to bridging, resulting in poor electrical performance of the semiconductor structure. In this embodiment, the lateral dimension of the first dielectric wall 212 is 3 nanometers to 30 nanometers.

[0158] The source / drain doped layer 214 is spaced apart from the first dielectric wall 212, such that the contact plug 225 can be formed between the source / drain doped layer 214 and the first dielectric wall 212.

[0159] When the semiconductor structure is in operation, the source and drain doped layers 214 are used to provide stress to the channel and improve the migration rate of carriers in the channel.

[0160] The second region II is used to form the NMOS, and the source and drain doped layers 214 serve as the source and drain of the NMOS. When the semiconductor structure is operating, the source and drain doped layers 214 apply tensile stress to the channel, which can increase the electron migration rate.

[0161] The first region I is used to form the PMOS, and the source and drain doped layers 214 are used as the source and drain of the PMOS. When the semiconductor structure is working, the source and drain doped layers 214 apply compressive stress to the channel, and compressing the channel can improve the hole mobility.

[0162] The contact plug 225 is used to connect the source / drain doped layer 214 to the downstream metal.

[0163] A contact plug 225 is located between the source / drain doped layer 214 and the first dielectric wall 212, and covers the top surface of the source / drain doped layer 214 and the sidewall of the source / drain doped layer 214 away from the first dielectric wall 212. In this embodiment, compared with the case where the contact plug only covers the top surface of the source / drain doped layer and the sidewall of the source / drain doped layer away from the first dielectric wall, the contact area between the contact plug 225 and the source / drain doped layer 214 in this embodiment is larger, thereby reducing the contact resistance between the contact plug 225 and the source / drain doped layer 214, which is beneficial to improving the electrical performance of the semiconductor structure.

[0164] The contact plug 225 is made of a conductive material. Specifically, the conductive material includes one or more of W, Co, Cu, and Al. In this embodiment, the contact plug 225 is made of W. W has stable chemical properties and a mature formation process, which is beneficial for controlling the formation quality of the semiconductor structure and improving the formation rate of the semiconductor structure.

[0165] It should be noted that the lateral dimension of the contact plug 225 between the source / drain doped layer 214 and the first dielectric wall 212 should not be too large or too small. If the lateral dimension is too large, it will occupy too much of the lateral dimension of the substrate 200 surface, resulting in low planar utilization of the substrate 200 surface and reducing the integration density of the semiconductor structure. In addition, if the lateral dimension is too large, it will occupy the formation area of ​​the first dielectric wall 212, making it difficult for the lateral dimension of the first dielectric wall 212 to meet the process requirements. The first dielectric wall 212 will have a poor effect on electrically isolating the contact plug 225 in the first region I and the contact plug 225 in the second region II. The contact plug 225 in the first region I and the contact plug 225 in the second region II are prone to bridging, resulting in poor electrical performance of the semiconductor structure. If the lateral dimension is too small, the lateral dimension of the contact plug 225 between the source / drain doped layer 214 and the first dielectric wall 212 will be small, making the formation of the contact plug 225 more difficult and resulting in poor formation quality. Consequently, the contact plug 225 will not be effective in reducing the contact resistance between the source / drain doped layer 214 and the first dielectric wall 212, making it difficult for the semiconductor structure to meet process requirements. In this embodiment, the lateral dimension of the contact plug 225 between the source / drain doped layer 214 and the first dielectric wall 212 is 3 nanometers to 20 nanometers.

[0166] It should be noted that, in this embodiment, the top surface of the contact plug 225 is lower than or flush with the top of the first dielectric wall 212.

[0167] It should be noted that the contact plug 225 also contacts the sidewall of the source / drain doped layer 114 that is away from the gate structure 121.

[0168] The semiconductor structure further includes: a plurality of channel layers 2012 suspended on the substrate 200, the two ends of the channel layers 2012 being connected to the source / drain doped layers 214, and the plurality of channel layers 2012 being spaced apart in the normal direction of the surface of the substrate 200.

[0169] When the semiconductor structure is in operation, the channel layer 2012 serves as the channel region.

[0170] In this embodiment, the channel layer 2012 is made of silicon. In other embodiments, the channel layer may also be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0171] The semiconductor structure further includes a second dielectric wall 211 located between the first dielectric wall 212 and the channel layer 2012.

[0172] The second dielectric wall 211 and the first dielectric wall 212 are used together to electrically isolate the channel layer 2012 of the first region I and the channel layer 2012 of the second region II, making it less likely for the channel layer 2012 of the first region I and the channel layer 2012 of the second region II to bridge, which is beneficial to improving the electrical performance of the semiconductor structure.

[0173] Specifically, the material of the second dielectric wall 211 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride, and silicon boron carbide. In this embodiment, the material of the second dielectric wall 211 includes silicon nitride.

[0174] It should be noted that the lateral dimension of the second dielectric wall 211 is the same as the lateral dimension of the contact plug 225 between the source / drain doped layer 214 and the first dielectric wall 212, which is 3 nanometers to 20 nanometers.

[0175] The semiconductor structure further includes a gate structure 221 that spans multiple channel layers 2012, a first dielectric wall 212, and a second dielectric wall, and covers the channel layers 2012.

[0176] When the semiconductor structure is in operation, the gate structure 221 is used to control the opening and closing of the channel. The gate structure 221 surrounds the channel layer 212 on three sides, and the gate structure 221 has a strong control capability over the channel.

[0177] In this embodiment, the gate structure 221 is made of a magnesium-tungsten alloy. In other embodiments, the gate structure may also be made of W, Al, Cu, Ag, Au, Pt, Ni, or Ti.

[0178] The semiconductor structure further includes a gate dielectric layer (not shown) located between the gate structure 221 and the channel layer 2012.

[0179] The gate dielectric layer is used to achieve electrical isolation between the gate structure 221 and the channel layer 2012. It should be noted that the material of the gate dielectric layer includes a high-k dielectric material. Here, a high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide.

[0180] In this embodiment, the material of the gate dielectric layer includes HfO2. In other embodiments, the material of the gate dielectric layer may also be selected from one or more of ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.

[0181] The semiconductor structure further includes an inner sidewall layer (not shown in the figure), located between the source / drain doped layer 214 and the gate structure 221.

[0182] The inner wall layer is used for electrically isolating the source / drain doped layer 214 and the gate structure 221.

[0183] In this embodiment, the material of the inner wall layer includes a low-k dielectric material. Low-k dielectric material (referring to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) has excellent insulating properties. It can reduce the electrical coupling effect between the gate structure 221 and the source / drain doped layers 214 located on both sides of the inner wall layer, thereby reducing parasitic capacitance and improving the electrical performance of the transistor structure.

[0184] Specifically, the material of the inner wall layer includes: SiON, SiBCN, SiCN, carbon-doped SiN, or oxygen-doped SiN. In this embodiment, the material of the inner wall layer includes carbon-doped SiN or oxygen-doped SiN.

[0185] The semiconductor structure further includes an interlayer dielectric layer 215 covering the sidewalls of the contact plug 225.

[0186] The interlayer dielectric layer 215 is used for electrical isolation of adjacent devices.

[0187] In this embodiment, the material of the interlayer dielectric layer 215 includes an insulating material. Specifically, the material of the interlayer dielectric layer 215 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the interlayer dielectric layer 215.

[0188] The semiconductor structure further includes a fin 205 located between the gate structure 221 and the substrate 200.

[0189] In this embodiment, the material of the fin 205 is the same as the material of the substrate 200. In other embodiments, the material of the fin may be different from the material of the substrate.

[0190] In this embodiment, the semiconductor structure further includes a power track line 203 located in the substrate 200. The power track line 203 is an elongated structure, and the extension direction of the power track line 203 is parallel to that of the first dielectric wall 212.

[0191] Power rails 203 are used to provide power to different components of the chip. In this embodiment, the power rails 203 are located in the substrate 200 and are buried power rails (BPR). This facilitates the freeing up of wiring resources for back-end interconnects and reduces the height of standard cells to meet the needs of continuous logic chip miniaturization. In addition, the buried power rails employ a technique of increasing back-end (BEOL) resistance through pitch miniaturization, which also helps to provide a lower local current distribution with lower resistance.

[0192] The power track 203 is made of a conductive material. In this embodiment, the power track 203 is made of a metallic material, including one or more of Co, W, Ni, and Ru. The low resistivity of the power track 203 material is beneficial for improving RC delay and increasing the chip's processing speed.

[0193] In this embodiment, a cap layer 207 is formed on the top of the power track line 203.

[0194] The cap layer 207 is used to protect the power rail line 203 from damage.

[0195] Specifically, the material of the capping layer 207 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, boron silicon nitride, and boron silicon carbide. In this embodiment, the material of the capping layer 207 includes silicon nitride.

[0196] In this embodiment, an insulating layer 208 is also formed between the sidewall of the power track line 203 and the substrate 200. The insulating layer 208 is used to achieve insulation between the power track line 203 and the substrate 200. Therefore, the material of the insulating layer 208 is an insulating material, such as silicon oxide, silicon oxynitride, or silicon nitride.

[0197] The semiconductor structure can be formed using the formation method of the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here. Although the embodiments of this application have been disclosed above, the embodiments of this application are not limited thereto.

Claims

1. A method of forming a semiconductor structure, characterized by, Comprising: providing a substrate, the substrate comprising a first region and a second region spaced apart, a stack structure being formed on the first region and the second region, a first opening being formed between the stack structure of the first region and the stack structure of the second region; forming a first dielectric layer on sidewalls of the first opening, the first dielectric layer having a second opening therebetween; forming a second dielectric layer in the second opening; after forming the second dielectric layer, forming a source-drain doped layer in the stack structure and an interlayer dielectric layer covering the source-drain doped layer; etching the interlayer dielectric layer to form a trench, the trench exposing a top surface of the source-drain doped layer and sidewalls of the second dielectric layer away from the second dielectric layer; after forming the trench, removing the first dielectric layer between the source-drain doped layer and the second dielectric layer to form a recess; forming a contact plug in the trench and the recess.

2. The method of forming a semiconductor structure of claim 1, wherein, In the step of forming a first dielectric layer on sidewalls of the first opening, the first dielectric layer is also formed on a bottom surface of the first opening.

3. The method of forming a semiconductor structure of claim 1, wherein, The step of forming the first dielectric layer comprises: forming a conformal first dielectric material layer covering the sidewalls and the bottom surface of the first opening; removing the first dielectric material layer on the bottom surface of the first opening, the remaining first dielectric material layer on the sidewalls of the first opening serving as the first dielectric layer.

4. The method of forming a semiconductor structure of claim 3, wherein, The first dielectric material layer is formed by an atomic layer deposition process or a chemical vapor deposition process.

5. The method of forming a semiconductor structure of claim 3, wherein, The first dielectric material layer on the bottom surface of the first opening is removed by a dry etching process.

6. The method of forming a semiconductor structure of claim 1, wherein, The lateral direction is parallel to the surface of the substrate and perpendicular to the extension direction of the stack structure. In the step of forming the first dielectric layer, the lateral dimension of the first dielectric layer is 3-20 nm.

7. The method of forming a semiconductor structure of claim 1, wherein, The material of the first dielectric layer comprises one or both of silicon oxide and silicon oxynitride.

8. The method of forming a semiconductor structure of claim 1, wherein, The step of forming a second dielectric layer in the second opening comprises: forming a conformal second dielectric material layer covering the stack structure and the second opening; removing the second dielectric material layer exposing the second opening, the remaining second dielectric material layer in the second opening serving as the second dielectric layer.

9. The method of forming a semiconductor structure of claim 8, wherein, The second dielectric material layer is formed by an atomic layer deposition process or a chemical vapor deposition process.

10. The method of forming a semiconductor structure of claim 1, wherein, The lateral direction is parallel to the surface of the substrate and perpendicular to the extension direction of the stack structure. In the step of forming the second dielectric layer, the lateral dimension of the second dielectric layer is 3-30 nm.

11. The method of forming a semiconductor structure of claim 1, wherein, The material of the second dielectric layer comprises one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, boron nitride, boron silicon nitride, and boron silicon carbon nitride.

12. The method of forming a semiconductor structure of claim 1, wherein, The first dielectric layer between the source-drain doped layer and the second dielectric layer is removed by a dry etching process to form a recess.

13. The method of forming a semiconductor structure of claim 1, wherein, In the step of providing a substrate, the stack structure comprises a plurality of channel stacks, each channel stack comprising a sacrificial layer and a channel layer on the sacrificial layer. The method for forming the semiconductor structure comprises, after forming the second dielectric layer and before forming the source-drain doped layer, forming a dummy gate structure across the stack structure, the first dielectric layer, and the second dielectric layer, the dummy gate structure covering part of the top wall and part of the sidewall of the stack structure. The step of forming the source-drain doped layer comprises forming a source-drain doped layer in the stack structure on both sides of the dummy gate structure. The method of forming the semiconductor structure further comprises, after forming the interlayer dielectric layer, removing the dummy gate structure to form a gate opening in the interlayer dielectric layer; removing the sacrificial layer to form a channel; and forming a gate structure in the gate opening and the channel.

14. The method of forming a semiconductor structure of claim 13, wherein, The method of forming the semiconductor structure further comprises, after forming the gate opening and before forming the gate structure, removing the first dielectric layer exposed by the gate opening and the channel to expose a sidewall of the second dielectric layer. A third dielectric layer is formed on the sidewall of the second dielectric layer. In the step of forming the gate structure, the gate structure spans the second dielectric layer and the third dielectric layer.

15. The method of forming a semiconductor structure of claim 14, wherein, The first dielectric layer exposed by the gate opening and the channel is removed by an isotropic etching process to expose the sidewall of the second dielectric layer.

16. The method of forming a semiconductor structure of claim 14, wherein, The third dielectric layer comprises one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, boron nitride, boron silicon nitride, and boron carbon silicon nitride.

17. The method of forming a semiconductor structure of claim 14, wherein, The step of forming the third dielectric layer on the sidewall of the second dielectric layer comprises: forming a conformal layer of the third dielectric material that covers the gate opening, the channel, and the second dielectric layer; and removing the third dielectric material in the gate opening and the channel, leaving the third dielectric material on the sidewall of the second dielectric layer as the third dielectric layer.

18. The method of forming a semiconductor structure of claim 17, wherein, The third dielectric material layer is formed by a chemical vapor deposition process or an atomic layer deposition process.

19. The method of forming a semiconductor structure of claim 17, wherein, The third dielectric material layer in the gate opening is removed by a wet etching process.

20. A semiconductor structure, comprising: The semiconductor structure comprises: a substrate comprising a first region and a second region spaced apart; a first dielectric wall on the substrate between the first region and the second region; a source-drain doped layer on the substrate in the extension direction of the first dielectric wall, separated from the first region and the second region, and spaced apart from the first dielectric wall; a contact plug between the source-drain doped layer and the first dielectric wall, covering a top surface of the source-drain doped layer, and a sidewall of the source-drain doped layer away from the first dielectric wall.

21. The semiconductor structure of claim 20, wherein, The semiconductor structure further comprises: a plurality of channel layers suspended on the substrate, both ends of the channel layers connected to the source-drain doped layer, and the plurality of channel layers spaced apart in the normal direction of the substrate surface; The semiconductor structure further comprises: a second dielectric wall between the first dielectric wall and the channel layers; The semiconductor structure further comprises: a gate structure spanning the plurality of channel layers, the first dielectric wall, and the second dielectric wall, and covering part of the top wall and part of the sidewall of the channel layers.

22. The semiconductor structure of claim 20 or 21, wherein, The first dielectric wall comprises one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, boron nitride, boron silicon nitride, and boron carbon silicon nitride.

23. The semiconductor structure of claim 20 or 21, wherein, The lateral dimension of the first dielectric wall is 3 nanometers to 30 nanometers in a lateral direction parallel to the substrate surface and perpendicular to the extension direction of the first dielectric wall.

24. The semiconductor structure of claim 20 or 21, wherein, A lateral dimension of the contact plug between the source-drain doped layer and the first dielectric wall is 3 nm to 20 nm in a direction parallel to the substrate surface and perpendicular to an extension direction of the first dielectric wall.

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