Semiconductor structure and method of forming the same

Abstract

Semiconductor structures and methods of forming the same are provided herein. In one embodiment, a semiconductor structure includes a plurality of first channel components on a backside dielectric layer, a plurality of second channel components on the backside dielectric layer, a silicide structure on the backside dielectric layer, and a source / drain structure on the silicide structure and extending between the first channel components and the second channel components. The silicide structure extends through an entire depth of the backside dielectric layer.

Claims

1. A semiconductor structure, comprising: Multiple first channel components are located on a back-side dielectric layer; Multiple second channel components are located on the back dielectric layer; A metal silicide structure is located in the back dielectric layer; as well as A source / drain structure is located on the metal silicide structure and extends along a direction between the first channel assembly and the second channel assembly, wherein the metal silicide structure includes a first width along the direction, and the source / drain structure includes a second width along the direction, wherein the first width is greater than the second width. The metal silicide structure extends through all depths of the back dielectric layer.

2. The semiconductor structure as described in claim 1, further comprising: A back-side metal line is located beneath the back-side dielectric layer, wherein the metal silicide structure extends between the back-side metal line and the source / drain structure.

3. The semiconductor structure of claim 1, wherein the metal silicide structure comprises nickel silicide, platinum silicide, or titanium silicide.

4. The semiconductor structure as described in claim 1, further comprising: A dielectric liner is located between the metal silicide structure and the back dielectric layer.

5. The semiconductor structure of claim 4, wherein the dielectric pad layer comprises silicon nitride or silicon carbonitride, and wherein the back-side dielectric layer comprises silicon oxide.

6. The semiconductor structure of claim 1, further comprising: An isolation structure adjacent to the back dielectric layer. The isolation structure contacts the metal silicide structure.

7. The semiconductor structure of claim 1, further comprising: Multiple inner spacer structures are interspersed with the first channel assembly. The metal silicide structure contacts the bottommost inner spacer structure of the inner spacer structure.

8. A semiconductor structure, comprising: One side metal circuit; A metal silicide structure is located on and in contact with the back metal line; A source / drain structure is located on the metal silicide structure, wherein the source / drain structure extends along a direction between a plurality of first channel components and a plurality of second channel components; wherein the metal silicide structure includes a first width along the direction, and wherein the source / drain structure includes a second width along the direction, wherein the first width is greater than the second width. A contact etch stop layer is located on the source / drain structure; and A dielectric layer is located on the etch stop layer of the contact.

9. The semiconductor structure of claim 8, wherein the metal silicide structure comprises nickel silicide, platinum silicide, or titanium silicide.

10. The semiconductor structure of claim 8, wherein the contact etch stop layer comprises silicon nitride or silicon carbonitride, and wherein the dielectric layer comprises silicon oxide.

11. The semiconductor structure of claim 8, wherein the source / drain structure comprises: One outer epitaxial layer; as well as An inner epitaxial layer is located on the outer epitaxial layer.

12. The semiconductor structure of claim 8, wherein the metal silicide structure comprises silicon and germanium.

13. A method for forming a semiconductor structure, comprising: Receive a workpiece, which includes: A fin-like structure is located on a substrate, and the fin-like structure includes multiple channel layers, and A first dummy gate stack and a second dummy gate stack are located on the fin structure; A source opening is formed in the fin-like structure between the first dummy gate stack and the second dummy gate stack to expose the sidewall of the fin-like structure; The source opening is extended into the substrate to form an extended source opening; A semiconductor plug is formed in the extended source opening; A source structure is formed in the semiconductor plug in the extended source opening and on the exposed sidewall of the channel layer; Planarize the substrate to expose the semiconductor plug; After planarizing the substrate, the substrate is replaced with a back-side dielectric layer; Deposit a metal layer on the back-side dielectric layer and the exposed semiconductor plug; and An annealing process is performed to induce a siliconization reaction between the metal layer and the exposed semiconductor plug.

14. The method of forming a semiconductor structure as claimed in claim 13, wherein the semiconductor plug comprises silicon germanium.

15. The method of forming a semiconductor structure as claimed in claim 13, wherein the metal layer comprises nickel, platinum, or titanium.

16. The method for forming a semiconductor structure as claimed in claim 13, wherein the step of replacing the substrate includes: The semiconductor plug was etched back to its original state. A hard mask structure is formed on the semiconductor plug through the etch-back process; as well as Using this hard mask structure as an etching mask does not involve isotropic etching of the substrate.

17. The method for forming a semiconductor structure as described in claim 16, The anisotropic etching step retains a portion of the substrate along the sidewall of the etched semiconductor plug. The annealing process further causes a silanization reaction between the metal layer and that portion of the substrate.

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