Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor structure and a method of fabricating the same. The semiconductor structure includes a substrate defining an active region. A first gate structure is disposed in the active region and includes a dielectric material. A second gate structure is disposed in the active region and includes the dielectric material. A fin structure has a first upper surface that is interleaved with the first gate structure and the second gate structure. The first gate structure has a second upper surface, and the second gate structure has a third upper surface. The second upper surface and the third upper surface are lower than the first upper surface.

Description

[0001] This invention claims priority and benefits to U.S. Patent Application No. 17 / 066,923, filed October 9, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates to a semiconductor structure. In particular, it relates to a semiconductor structure having a fin-like structure and a method for fabricating the same. Background Technology

[0003] An embedded word line is a structure formed in a dynamic random access memory (DRAM) to improve the integration of a transistor in a cell, simplify a manufacturing process, and improve a device characteristic, such as a leakage current characteristic. Typically, a trench is formed, and a word line is embedded in the trench to form an embedded word line.

[0004] When forming multiple character lines, a single etch-back process is important because it creates spaces within the multiple trenches for depositing a conductive material. However, in a single etch-back process, etching selectivity often results in variations in the height of the various materials used to form the multiple character lines. Therefore, there is a need to improve the etch-back process for forming multiple embedded character lines.

[0005] The above description of "prior art" is merely a background description and does not acknowledge that the subject matter of this disclosure is disclosed. It does not constitute prior art in this disclosure, and no description of the above "prior art" should be considered part of this invention. Summary of the Invention

[0006] The purpose of this invention is to provide a semiconductor structure and its preparation method to solve at least one of the above-mentioned problems.

[0007] One embodiment of this disclosure provides a semiconductor structure. The semiconductor structure includes a substrate defining an active region. A first gate structure is disposed in the active region and includes a dielectric material. A second gate structure is disposed in the active region and includes the dielectric material. A fin structure has a first upper surface, which is alternately disposed with the first gate structure and the second gate structure. The first gate structure has a second upper surface, and the second gate structure has a third upper surface. The second and third upper surfaces are lower than the first upper surface.

[0008] In some embodiments, the third upper surface is lower than the second upper surface.

[0009] In some embodiments, the second gate structure is deeper than the first gate structure.

[0010] In some embodiments, the first gate structure and the second gate structure have different diameters and different depths.

[0011] Another embodiment of this disclosure provides a method for fabricating a semiconductor structure. The method includes forming a gate trench and a first fin structure in an active region of a substrate, the first fin structure being adjacent to the gate trench; filling the gate trench with a dielectric material; forming a first photoresist pattern on the active region; performing a first etching process to partially remove the first fin structure to form a second fin structure, wherein the second fin structure has a protrusion; forming a hard mask on the active region; and performing a second etching process to remove a portion of the dielectric material and the protrusion of the second fin structure to form a third fin structure.

[0012] In some embodiments, forming the gate trench includes forming a first gate trench adjacent to a second gate trench, wherein the first gate trench and the second gate trench are disposed along a first direction.

[0013] In some embodiments, the second gate trench is formed to be deeper than the first gate trench.

[0014] In some embodiments, forming the gate trench includes forming the first gate trench and the second gate trench to have different diameters and different depths.

[0015] In some embodiments, the execution of the first etching process includes forming a first recessed channel that extends along the first direction.

[0016] In some embodiments, after the first etching process, a second height of the second fin structure is smaller than a first height of the first fin structure.

[0017] In some embodiments, forming the hard mask includes: forming a capping layer to cover the active region; forming a mask layer on the capping layer; forming an anti-reflective coating (ARC) layer on the mask layer; and forming a second photoresist pattern on the anti-reflective coating layer.

[0018] In some embodiments, the mask layer uses the second photoresist pattern as an etching mask to etch in order to form a mask pattern.

[0019] In some embodiments, the cover layer uses the mask pattern as an etching mask to etch in order to form a cover pattern.

[0020] In some embodiments, the cover pattern is formed together with the mask pattern on the hard mask in the active area.

[0021] In some embodiments, the second etching process includes grinding the protrusion of the second fin structure.

[0022] In some embodiments, after the second etching process, a third height of the third fin structure is smaller than a second height of the second fin structure.

[0023] In some embodiments, the second etching process includes forming a second recessed channel that extends along the first direction.

[0024] In some embodiments, the second recessed channel passes through the dielectric material and the third fin structure.

[0025] In some embodiments, the second etching process uses an etching system that uses a plasma having a bias power of 200 to 300 watts and an on-off frequency of 100 to 300 hertz.

[0026] In some embodiments, in the second etching process, the ratio of a period of an on state to a period of an off state of the plasma is between 70:30 and 50:50.

[0027] This disclosure provides a method for fabricating a semiconductor structure with a fin structure having a generally flat upper surface after a first etch and a second etch process. The first fin structure is processed by the first etch process to form a second fin structure having an upper component including a hollow portion and a protrusion. The protrusion of the second fin structure prevents a third fin structure from forming a rounded shape after the second etch process. The contours of the plurality of third fin structures disclosed herein contribute to a desired electrical property of the plurality of subsequently formed embedded word line structures.

[0028] The technical features and advantages of this disclosure have been summarized quite extensively above to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0029] The disclosure of the present invention can be more fully understood by referring to the accompanying drawings in conjunction with the embodiments and claims, wherein the same element symbols in the drawings refer to the same elements.

[0030] Figure 1 A schematic diagram illustrating an etching system according to some embodiments of the present disclosure is shown.

[0031] Figure 2 A top view schematic diagram illustrating some embodiments of the present disclosure of a dynamic random access memory (DRAM) device.

[0032] Figure 3 A schematic diagram illustrating a comparative embodiment is shown.

[0033] Figure 4 Example in Figure 3 The cross-sectional schematic diagram of the comparative embodiment is shown in the figure.

[0034] Figure 5 A cross-sectional schematic diagram illustrating some embodiments of the present disclosure is shown.

[0035] Figure 6 Examples of some embodiments of this disclosure are shown in Figure 5 A schematic diagram of the process for fabricating the semiconductor structure shown in the figure.

[0036] Figure 7 Examples of embodiments of this disclosure are provided. Figure 6 A cross-sectional schematic diagram of the sequential manufacturing stages of the preparation method in the image.

[0037] Figure 8 Examples of embodiments of this disclosure are provided. Figure 6 A cross-sectional schematic diagram of the sequential manufacturing stages of the preparation method in the image.

[0038] Figure 9 Examples of embodiments of this disclosure are provided. Figure 6 A cross-sectional schematic diagram of the sequential manufacturing stages of the preparation method in the image.

[0039] Figure 10 Examples of embodiments of this disclosure are provided. Figure 6 A cross-sectional schematic diagram of the sequential manufacturing stages of the preparation method in the image.

[0040] Figure 11 Examples of embodiments of this disclosure are provided. Figure 6 A cross-sectional schematic diagram of the sequential manufacturing stages of the preparation method in the image.

[0041] Figure 12 Examples of embodiments of this disclosure are provided. Figure 6 A cross-sectional schematic diagram of the sequential manufacturing stages of the preparation method in the image.

[0042] Figure 13 Examples of embodiments of this disclosure are provided. Figure 6 A cross-sectional schematic diagram of the sequential manufacturing stages of the preparation method in the image.

[0043] Figure 14 A three-dimensional schematic diagram illustrating another semiconductor structure according to some embodiments of the present disclosure is shown.

[0044] Figure 15 Examples of embodiments of this disclosure are provided. Figure 6 A cross-sectional schematic diagram of the sequential manufacturing stages of the preparation method in the image.

[0045] Figure 16 Examples of some embodiments of this disclosure are illustrated after the first etching process, in Figure 14 A three-dimensional schematic diagram of the semiconductor structure.

[0046] Figure 17 Examples of some embodiments of this disclosure are shown in Figure 16 A cross-sectional schematic diagram of the semiconductor structure shown.

[0047] Figure 18 Examples of embodiments of this disclosure are provided. Figure 6 A cross-sectional schematic diagram of a sequential manufacturing stage in the preparation method.

[0048] Figure 19 Examples of some embodiments of this disclosure are shown in Figure 18 A cross-sectional schematic diagram of the semiconductor structure shown.

[0049] Figure 20 Examples of embodiments of this disclosure are provided. Figure 6 A cross-sectional schematic diagram of the sequential manufacturing stages of the preparation method in the image.

[0050] Figure 21 Examples of embodiments of this disclosure are provided. Figure 6 A cross-sectional schematic diagram of the sequential manufacturing stages of the preparation method in the image.

[0051] Figure 22 Examples of embodiments of this disclosure are provided. Figure 6A cross-sectional schematic diagram of the sequential manufacturing stages of the preparation method in the image.

[0052] Figure 23 Examples of embodiments of this disclosure are provided. Figure 6 A cross-sectional schematic diagram of the sequential manufacturing stages of the preparation method in the image.

[0053] Figure 24 Examples of embodiments of this disclosure are provided. Figure 6 A cross-sectional schematic diagram of the sequential manufacturing stages of the preparation method in the image.

[0054] Figure 25 Examples of embodiments of this disclosure are provided. Figure 6 A cross-sectional schematic diagram of the sequential manufacturing stages of the preparation method in the image.

[0055] Figure 26 Examples of embodiments of this disclosure are provided. Figure 6 A cross-sectional schematic diagram of the sequential manufacturing stages of the preparation method in the image.

[0056] Figure 27 Examples of some embodiments of this disclosure are shown in Figure 5 A three-dimensional schematic diagram of the semiconductor structure shown.

[0057] The attached figures are labeled as follows:

[0058] 10: Dynamic Random Access Memory (DRAM) element

[0059] 12: Base

[0060] 14: Dielectric materials

[0061] 16: Fin structure

[0062] 20: Semiconductor stacking

[0063] 22: Gas Inlet

[0064] 24: Plasma

[0065] 26: Vacuum System

[0066] 100: Base

[0067] 110: Insulating materials

[0068] 120: Dopant

[0069] 122: Second photoresist pattern

[0070] 130: First fin structure

[0071] 132: Second fin structure

[0072] 134: Third fin structure

[0073] 140: Dielectric materials

[0074] 142: Third photoresist pattern

[0075] 150L: Cover layer

[0076] 150: Cover pattern

[0077] 150A: Cover Features

[0078] 150B: Opening

[0079] 160: Mask pattern

[0080] 160A: Mask Features

[0081] 160B: Opening

[0082] 160L: Mask layer

[0083] 170: Anti-reflective coating pattern

[0084] 170A: Anti-reflective coating characteristics

[0085] 170B: Opening

[0086] 170L: Anti-reflective coating

[0087] 180: Photoresist pattern

[0088] 180A: Photoresist characteristics

[0089] 180B: Opening

[0090] 180L: Photoresist layer

[0091] 200: Preparation method

[0092] 300: Semiconductor Structure

[0093] 310: Semiconductor Structure

[0094] 320: Semiconductor Structure

[0095] 400: Semiconductor Structure

[0096] AA: Active Zone

[0097] AR: Active Zone

[0098] BB: Insulation Zone

[0099] CH1: First recessed channel

[0100] CH2: Second concave channel

[0101] D1: First Direction

[0102] D2: Second Direction

[0103] D3: Third direction

[0104] E1: Electrode

[0105] E2: Electrode

[0106] ES: Etching System

[0107] GT: Gate Trench

[0108] GT1: First gate trench

[0109] GT2: Second gate trench

[0110] Hv1: Radiation

[0111] H1: First Height

[0112] H2: Second Altitude

[0113] H3: Third Height

[0114] HM1: Hard Mask

[0115] MA: Photomask

[0116] O1: Opaque area

[0117] P1: Protrusion

[0118] R1: Hollow section

[0119] RA: Array area

[0120] RF: Power supply

[0121] S101: Steps

[0122] S103: Steps

[0123] S105: Steps

[0124] S107: Steps

[0125] S109: Steps

[0126] S111: Steps

[0127] S1: Upper surface

[0128] S2: Upper surface

[0129] S3: Upper surface

[0130] S4: Upper surface

[0131] SI: First upper surface

[0132] SR: Upper surface

[0133] T1: Transparent area

[0134] TA: Gate trench (insulating trench)

[0135] TA1: First gate trench

[0136] TA2: Second gate trench

[0137] θ: angle Detailed Implementation

[0138] The embodiments or examples of this disclosure shown in the accompanying drawings will now be described using specific language. It should be understood that the scope of this disclosure is not intended to be limited thereto. Any modifications or improvements to the described embodiments, and any further application of the principles described in this invention, will be considered commonplace by those skilled in the art. Component numbers may be repeated throughout the embodiments, but this does not necessarily mean that a feature of one embodiment is applicable to another embodiment, even if they share the same component numbers.

[0139] It should be understood that although the terms "first," "second," "third," etc., are used in this invention to describe different elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish an element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, the terms "first element," "component," "region," "layer," or "section" discussed below may be referred to as a second element, component, region, layer, or portion without departing from the teachings of this invention.

[0140] The terminology used in this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms “comprises” and / or “comprising” are used in this specification, the terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0141] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" may be used in this invention to describe the relationship between one element or feature shown in the figures and another (other) element or feature. These spatial relative terms are intended to encompass different orientations of the element in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used in this invention can be interpreted accordingly.

[0142] An etching process typically uses an ionized gas (such as plasma) to etch a semiconductor stack. Multiple plasma etching processes are particularly useful for etching multiple adjacent structures with fine features. However, as requirements for feature size and spacing become more stringent, the limitations of plasma etching processes become apparent. For example, reactive ion etching (RIE) is an etching process that uses chemically reactive plasma to remove individual materials deposited on a semiconductor stack. The plasma is generated at a low pressure by an electromagnetic field. Multiple high-energy ions from the plasma attack the materials of the semiconductor stack and react with them.

[0143] Figure 1 A schematic diagram illustrating an etching system ES according to some embodiments of this disclosure is provided. In some embodiments, the etching system ES is a reactive ion etching (RIE) system. The etching system ES includes at least a power supply RF and a pair of electrodes E1, E2. In a RIE process, firstly, a semiconductor stack 20 is placed on a wafer holder (not shown). Next, a plurality of gases are introduced via a gas inlet 22. A plasma 24 is used to bombard the gas mixture using the power supply RF, breaking the gas mixture into a plurality of energized ions. The plurality of energized ions are accelerated toward the surface of the semiconductor stack 20 and react thereon to form another gaseous by-product. Next, the gaseous by-product is removed via a vacuum system 26 to complete the reactive ion etching.

[0144] Multiple buried word lines in a semiconductor device include multiple gate electrodes and multiple buried word lines, wherein the multiple gate electrodes and multiple buried word lines are constructed in trenches located in multiple active regions and multiple insulating regions. Typically, the multiple buried word lines are processed after the multiple active regions are defined, for example after a shallow trench isolation (STI) process.

[0145] Figure 2The diagram illustrates a top view of a dynamic random access memory (DRAM) element 10 according to some embodiments of the present disclosure. The DRAM element 10 includes an array region RA and a surrounding region (not shown) on a substrate 12. The substrate 12 has a plurality of active regions AA, each of which is provided with an insulating region BB. In some embodiments, the plurality of active regions AA may be arranged at predetermined intervals and are insulated from each other by the insulating region BB.

[0146] In some embodiments, such as Figure 2 As shown, multiple active regions AA are arranged parallel to each other and extend along a first direction D1. In some embodiments, the multiple active regions AA are doped with various dopants to adjust their electronic characteristics and form multiple source regions (not shown) and multiple drain regions (not shown). The multiple source regions and multiple drain regions can constitute an important part of the array region RA.

[0147] In some embodiments, a plurality of parallel embedded word lines (not shown) or a plurality of parallel bit lines (not shown) may be disposed in the array region RA and pass through a plurality of active regions AA and an insulating region BB. The plurality of embedded word lines are disposed on the substrate 12 and extend along a second direction D2, which forms a predetermined angle θ relative to the first direction D1. In some embodiments, preferably, the predetermined angle θ is less than 90 degrees. The plurality of bit lines are disposed on the substrate 12 and extend along a third direction D3, which is orthogonal to the second direction D2. The first direction D1, the second direction D2, and the third direction D3 are all different from each other. In other words, the plurality of embedded word lines and the plurality of bit lines are orthogonally disposed relative to the plurality of active regions AA.

[0148] Figure 3 and Figure 4 A cross-sectional schematic diagram of a comparative embodiment is shown, wherein Figure 3 and Figure 4 along Figure 2 Viewed by section line A-A' in the diagram. Please refer to... Figure 3 A semiconductor structure 310 is provided having an active region AR. The active region AR has a first upper surface SI. Furthermore, the active region AR has a plurality of gate trenches TA and a plurality of fin structures 16, wherein the plurality of fin structures 16 and the plurality of gate structures TA are alternately arranged. The plurality of gate trenches TA have a plurality of first gate trenches TA1 and a plurality of second gate trenches TA2, which have different diameters and different depths. The plurality of gate trenches TA are filled with a dielectric material 14.

[0149] Please refer to Figure 4In order to form multiple buried word lines in semiconductor structure 310, an etch-back process is performed to partially remove dielectric material 14 and form a recessed channel (not shown). The removal of dielectric material 14 and the formation of the recessed channel are intended to create space to accommodate a conductive material, thereby forming multiple buried word lines, such as tungsten (W) or copper (Cu).

[0150] However, as Figure 4 As shown, during the etch-back process in the comparative embodiment, multiple fin structures 16 are inevitably trimmed, and the upper portions of each of the multiple fin structures 16 are rounded. After the etch-back process, a semiconductor structure 320 is formed. The semiconductor structure 320 has multiple rounded fin structures 16, which are detrimental to electronic performance after the deposition of conductive material. Therefore, there is a great need to improve the etch-back process used to form multiple buried word lines.

[0151] One object of this disclosure is to provide a semiconductor structure. Figure 5 A cross-sectional schematic diagram of a semiconductor structure 400 illustrating some embodiments of the present disclosure is shown. Figure 5 along Figure 2 Viewed by section line A-A' in the diagram. In some embodiments, after multiple active regions AA are formed, multiple embedded character lines are formed.

[0152] The semiconductor structure 400 mainly includes an active region AA. The active region AA includes multiple gate structures and multiple third fin structures 134, with the gate structures located in corresponding gate trenches GT. The third fin structure 134 has a generally flat upper surface S2. The multiple gate trenches GT have multiple first gate trenches GT1 and multiple second gate trenches GT2, which are partially homogeneous and have different depths. Compared to the first gate trenches GT1, the second gate trenches GT2 have a wider opening and a greater depth. The multiple first gate trenches GT1 and the multiple second gate trenches GT2 are partially filled with a dielectric material 140. The dielectric material 140 in the first gate trenches GT1 has an upper surface S3, which is generally lower than the upper surface S2 of the third fin structure 134. The dielectric material 140 in the second gate trenches GT2 has an upper surface S4, which is generally lower than the upper surface S3.

[0153] Figure 6 Examples of some embodiments of this disclosure are shown in Figure 5 A schematic diagram of a fabrication method 200 for the semiconductor structure 400 in the figure. Figures 7 to 27 Examples of embodiments of this disclosure are provided. Figure 6 Cross-sectional schematic diagrams of the sequential manufacturing stages of the preparation method 200.

[0154] Please refer to Figure 7 ,in accordance with Figure 6 In step S101, a substrate 100 is provided. In some embodiments, the substrate 100 may be a monocrystalline silicon substrate, a polycrystalline silicon substrate, a compound semiconductor substrate, or any other suitable substrate, and the compound semiconductor substrate may be, for example, a silicon-germanium substrate, a gallium arsenide substrate, or an insulator-on-silicon substrate. The substrate 100 has an upper surface S1.

[0155] Please refer to Figures 8 to 10 ,in accordance with Figure 6 In step S103, an active region defining process is performed on the substrate 100. In some embodiments, the active region defining process is a shallow trench isolation (STI) formation process that defines at least one active region in the substrate 100. In particular, the STI formation process includes at least a photolithography process, an etching process, a deposition process, and an ion implantation process.

[0156] Please refer to Figure 8 A first photoresist pattern (not shown) is formed on the upper surface S1 of the substrate 100. In some embodiments, the first photoresist pattern is a positive tone photoresist, characterized by removing multiple exposed areas using a developing solution. Next, the first photoresist pattern is used as an etch mask to form an insulating trench TA. After the insulating trench TA is formed within the substrate 100, the first photoresist pattern is removed using an ashing process or a wet stripping process.

[0157] Next, please refer to Figure 9 An insulating material 110 is deposited to fill the insulating trench TA. In some embodiments, the insulating material 110 may comprise silicon dioxide (SiO2), undoped silicate glass (USG), or other suitable materials, and is deposited using a chemical vapor deposition (CVD) process or a spin coating (SOC) process. In some embodiments, a chemical mechanical polishing (CMP) process is performed to remove the insulating material 110 from the upper surface S1 of the substrate 100. After the insulating trench TA is filled with the insulating material 110, an insulating region BB is formed.

[0158] Next, please refer to Figure 10An ion implantation process is performed on a substrate 100. In some embodiments, a dopant 120 is implanted into the substrate 100 to form an active region AA in the substrate 100, which is surrounded by an insulating region BB. The active region AA has an upper surface S1. In some embodiments, when the dopant 120 contains boron (B), gallium (GA), or indium (In), the active region AA may be a p-type doped region. In other embodiments, when the dopant 120 contains phosphorus (P) or arsenic (As), the active region AA may be an n-type doped region. After the ion implantation process, an annealing process may be performed to repair the damage caused by implantation and to activate the dopant 120.

[0159] Please refer to Figures 11 to 13 ,in accordance with Figure 6 In step S105, a gate trench formation process is performed on the active region AA. In particular, the gate trench formation process includes at least a photolithography process, an etching process, and a deposition process.

[0160] Please refer to Figure 11 A second photoresist pattern 122 is formed on the upper surface S1 of the active region AA. The second photoresist pattern 122 is used to define the location of a gate trench formed thereon. In some embodiments, the second photoresist pattern 122 includes a chemical amplifier (CA) photoresist. The CA photoresist contains a photoacid generator (PAG), which can be decomposed during a photolithography process to form acid. More acid can be generated due to the catalytic reaction.

[0161] Next, please refer to Figure 12 The second photoresist pattern 122 is used as an etching mask to etch the active region AA, thereby forming multiple gate trenches GT. Furthermore, multiple first fin structures 130 of the active region AA simultaneously form multiple gate trenches GT. Each first fin structure 130 has an upper surface S1.

[0162] After multiple gate trenches GT are formed in the active region AA, the second photoresist pattern 122 is removed using an ashing process or a wet stripping process. In some embodiments, the multiple gate trenches GT include multiple first gate trenches GT1 and multiple second gate trenches GT2, wherein the multiple first gate trenches GT1 and the multiple second gate trenches GT2 have different diameters and different depths. Compared to the first gate trenches GT1, the second gate trenches GT2 have a wider aperture and a greater depth. In some embodiments, the different dimensions of the first gate trenches GT1 and the second gate trenches GT2 are caused by the etching proximity effect. That is, a gate trench with a wider aperture is etched more efficiently, thereby having a greater depth after the etching process.

[0163] Next, please refer to Figure 13 A dielectric material 140 is deposited to fill a plurality of gate trenches GT. In some embodiments, the dielectric material 140 may comprise silicon dioxide or other suitable materials and is deposited using a CVD process or an atomic layer deposition (ALD) process. In some embodiments, a CMP process is performed to remove the dielectric material 140 on the upper surface S1 of the active region AA to expose the first fin structure 130. At this time, a semiconductor structure 300 is typically formed. The plurality of gate trenches GT filled with dielectric material 140 are configured to form a plurality of buried word line structures.

[0164] Figure 14 A perspective view of a semiconductor structure 300 illustrating some embodiments of the present disclosure is shown. In some embodiments, a plurality of first fin structures 130 have a first height H1, approximately equal to the thickness of the active region AA. In the perspective view, a plurality of first gate trenches GT1 filled with dielectric material 140 are alternately arranged with a plurality of second gate trenches GT2 filled with dielectric material 140 and extending along a second direction D2. Furthermore, the plurality of first fin structures 130 and the plurality of gate trenches GT are alternately arranged.

[0165] Please refer to Figures 15 to 17 ,in accordance with Figure 6 In step S107, a first etching process is performed on the active region AA. The first etching process includes at least one photolithography process and one etching process.

[0166] Please refer to Figure 15 A third photoresist pattern 142 is formed on the upper surface S1 to cover a portion of the active region AA. Next, please refer to... Figure 16The illustration, according to some embodiments of the present disclosure, shows a three-dimensional schematic diagram of a semiconductor structure 300 after a first etching process. The semiconductor structure 300 is etched using a third photoresist pattern 142 as an etching mask to form a shallow first recessed channel CH1. Specifically, portions of the etched dielectric material 140 and the plurality of first fin structures 130 exposed by the third photoresist pattern 142 are etched. In some embodiments, a portion of the upper surface S1 is excavated to form the first recessed channel CH1. Therefore, the upper portions of each of the plurality of first fin structures 130 are concave, forming a plurality of second fin structures 132. In some embodiments, the first recessed channel CH1 extends along a second direction D2.

[0167] Figure 17 Examples of some embodiments of this disclosure are shown in Figure 16 A cross-sectional schematic diagram of the semiconductor structure 300 is shown. The second fin structure 132 includes a hollow portion R1 and a protrusion P1. In some embodiments, the hollow portion R1 is a recess, which is fabricated using a first etch-back process. The protrusion P1, having a concave upper surface SR, is a portion retained on the upper surface of the second fin structure 132. In some embodiments, the outline of the protrusion P1 is not limited thereto. After the first etch-back process, a second height H2 of the second fin structure 132 is substantially smaller than the first height H1 of the first fin structure 130.

[0168] Please refer to Figures 18 to 25 ,in accordance with Figure 6 In step S109, a hard mask is formed on the active region AA. Please refer to... Figure 18 In some embodiments, multiple layers are sequentially formed on the active region AA. First, a capping layer 150L is formed on the upper surface S1. The capping layer 150L completely covers the dielectric material 140 in the plurality of gate trenches GT. In some embodiments, the capping layer 150L comprises an electrical material, such as silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof.

[0169] Next, a mask layer 160L is formed on the capping layer 150L. In some embodiments, the mask layer 160L primarily comprises carbon material and is used as a hard mask. Subsequently, an anti-reflective coating (ARC) layer 170L is optionally formed on the mask layer 160L, performed after a photoresist layer 180L is formed on the ARC layer 170L. In some embodiments, the ARC layer 170L minimizes light reflection from the photoresist layer 180L when it is irradiated. In some embodiments, the ARC layer 170L is fabricated using a spin coating process.

[0170] In some embodiments, the photoresist layer 180L comprises a chemical amplifying agent (CA) photoresist. The CA photoresist contains a photoacid generator (PAG), which can be decomposed during a photolithography process to form acid. More acid can be generated due to a catalytic reaction. At this time, the cap layer 150L, ​​mask layer 160L, ARC layer 170L, and photoresist layer 180L together form a multilayer film 200 in the active region AA.

[0171] Figure 19 Examples of some embodiments of this disclosure are shown in Figure 18 The diagram shows a cross-sectional view of the semiconductor structure. In some embodiments, the capping layer 150L covers the upper surface S1 of the dielectric material 140 and the upper surface SR of the second fin structure 132. Therefore, a portion of the capping layer 150L fills the hollow portion R1.

[0172] Please refer to Figure 20 A photolithography process is performed on a photoresist layer 180L. A photomask MA and a photolithography system (not shown) are used to expose the photoresist layer 180L to radiation hv1. In some embodiments, radiation hv1 may include deep ultraviolet (DUV) radiation, but is not limited thereto. The photomask MA includes a plurality of transparent portions T1 and a plurality of opaque portions O1.

[0173] In some embodiments, the photomask MA can be a binary mask, a phase-shift mask, or any other type of mask suitable for use in a photolithography system. Exposure causes a photochemical reaction that alters the chemical properties of some portions of the photoresist layer 180L. For example, exposing portions of the photoresist layer 180L corresponding to a plurality of transparent portions T1 makes it more reactive to a development process. In some embodiments, a post-exposure baking (PEB) can be performed after the photoresist layer 180L has been exposed.

[0174] Please refer to Figure 21 A suitable developer is used to rinse the exposed photoresist layer 180L. In some embodiments, multiple exposed portions of the photoresist layer 180L react with the developer and can be easily removed. After development of the exposed photoresist layer 190L, a photoresist pattern 180 is formed, which includes multiple photoresist features 180A and multiple openings 180B, with the multiple openings 180B configured with the multiple photoresist features 180A. In some embodiments, the multiple photoresist features 180A and the multiple openings 180B correspond to multiple opaque portions O1 and multiple transparent portions T1 of the photomask MA, respectively. In some embodiments, portions of the ARC layer 170L are covered by the multiple photoresist features 180A.

[0175] Please refer to Figure 22 An etching process is performed on the ARC layer 170L. In some embodiments, the first etching may be a RIE process, which anisotropically etches multiple portions of the ARC layer 170L exposed through multiple openings 180B. Thus, an antireflective coating (ARC) pattern 170 is formed, comprising multiple antireflective coating (ARC) features 170A and multiple openings 170B, the multiple openings 170B being disposed together with the multiple ARC features 170A. In some embodiments, the multiple ARC features 170A and the multiple openings 170B are respectively connected to multiple photoresist features 180A and the multiple openings 180B. In some embodiments, portions of the mask layer 160L are covered by the multiple ARC features 170A.

[0176] Please refer to Figure 23 A second etching is performed on the mask layer 160L. Specifically, the mask layer 160L is etched using a plurality of photoresist features 180A as an etch mask. In some embodiments, the second etching may be a RIE process that anisotropically etches multiple portions of the mask layer 160L exposed through a plurality of openings 170B. Thus, a mask pattern 160 is formed, comprising a plurality of mask features 160A and a plurality of openings 160B, the openings 160B being disposed together with the plurality of mask features 160A. In some embodiments, the plurality of mask features 160A and the plurality of openings 160B are respectively connected to a plurality of ARC features 170A and the plurality of openings 170B. In some embodiments, portions of the cap layer 150L are covered by the plurality of mask features 160A.

[0177] Please refer to Figure 24 Prior to the next process, the photoresist pattern 180 and the ARC pattern 170 are removed. In some embodiments, this removal may be performed using an ashing process or a wet stripping process.

[0178] Please refer to Figure 25A third etch is performed on the capping layer 150L. Specifically, the capping layer 150L is etched using a plurality of mask features 160A as an etch mask. In some embodiments, the third etch may be a RIE process, anisotropically removing multiple portions of the capping layer 150L exposed through a plurality of openings 160B. Thus, a capping pattern 150 is formed, comprising a plurality of capping features 150A and a plurality of openings 150B, the openings 150B being disposed together with the capping features 150A. In some embodiments, the plurality of capping features 150A and the plurality of openings 150B are respectively connected to the plurality of mask features 160A and the plurality of openings 160B. In some embodiments, dielectric material 140 is exposed through the openings 150B. In some embodiments, the capping pattern 150 and the mask pattern 160 together form a hard mask HM1 on the active layer AA.

[0179] Please refer to Figure 26 ,in accordance with Figure 6 In step S111, a second etch-back process is performed on the active region AA. Specifically, some portions of the dielectric material 140 exposed through the hard mask HM1 are etched. In some embodiments, the protrusion P1 of the second fin structure 132 formed in the first etch-back process (e.g., Figure 16 (As shown) and dielectric material 140 are simultaneously etched in the second etching process. The protrusion P1 of the second fin structure 132 is grounded to form a third fin structure 134, which has a generally flat upper surface S2, lower than the upper surface S1 of the active region AA.

[0180] In some embodiments, the dielectric material 140 in the first gate trench GT1 has an upper surface S3, which is substantially lower than the upper surface S2 of the third fin structure 134. Furthermore, the dielectric material 140 in the second gate trench GT2 has an upper surface S4, which is substantially lower than the upper surface S3. After the second etch-back process, the hard mask HM1 is removed using an ashing process or a wet stripping process. At this time, multiple recesses are formed within the multiple gate trenches GT, and a semiconductor structure 400 is typically formed. Next, a conductive material deposition process can be performed on the semiconductor structure 400 to form multiple buried word line structures.

[0181] In some embodiments, the second etching process uses an etching system employing a plasma having a bias power of 200 to 300 watts (W) and an on-off frequency of 100 to 300 hertz (Hz). The on-off frequency is the frequency at which the plasma is turned on and off within one second. In some embodiments, the period ratio of an on state to an off state of the plasma is between 70:30 and 50:50. According to the aforementioned method, the etching selectivity of the dielectric material and the plurality of fin structures can be adjusted, where the dielectric material is, for example, silicon dioxide, and the plurality of fin structures primarily comprise silicon.

[0182] Figure 27 A perspective view of a semiconductor structure 400 illustrating some embodiments of the present disclosure is provided. In some embodiments, after a second etch-back process, a second recessed channel CH2 is formed through the dielectric material 140 and a plurality of third fin structures 134. The second recessed channel CH2 extends along a second direction D2. In some embodiments, the plurality of third fin structures 134 have a third height H3, which is substantially smaller than that shown below. Figure 17 The first height H1 or the second height H2 is shown.

[0183] One embodiment of this disclosure provides a semiconductor structure. The semiconductor structure includes a substrate defining an active region. A first gate structure is disposed in the active region and includes a dielectric material. A second gate structure is disposed in the active region and includes the dielectric material. A fin structure has a first upper surface, which is alternately disposed with the first gate structure and the second gate structure. The first gate structure has a second upper surface, and the second gate structure has a third upper surface. The second and third upper surfaces are lower than the first upper surface.

[0184] Another embodiment of this disclosure provides a method for fabricating a semiconductor structure. The method includes forming a gate trench and a first fin structure in an active region of a substrate, the first fin structure being adjacent to the gate trench; filling the gate trench with a dielectric material; forming a first photoresist pattern on the active region; performing a first etching process to partially remove the first fin structure to form a second fin structure, wherein the second fin structure has a protrusion; forming a hard mask on the active region; and performing a second etching process to remove a portion of the dielectric material and the protrusion of the second fin structure to form a third fin structure.

[0185] Compared to Figure 4The comparative embodiment shown depicts multiple fin structures with a convex annular upper surface after a single etching process; in contrast, the preparation method provided in this disclosure forms multiple fin structures with a generally flat surface after a combination of multiple etching processes. After a first etching process, a first fin structure is processed to form a second fin structure having a protrusion and a hollow portion. The protrusion of the second fin structure prevents the fin structure from becoming convex annular in a second etching process (e.g., ...). Figure 4 (As shown). The outlines of the multiple fin structures disclosed herein contribute to a desired electronic characteristic of the subsequent formation of multiple embedded character line structures.

[0186] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0187] Furthermore, the scope of this invention is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this invention that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described in this invention can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this invention.

Claims

1. A semiconductor structure, comprising: One base defines one active region; A first gate structure is disposed in the active region and includes a dielectric material; A second gate structure is disposed in the active region and includes the dielectric material; and A third fin structure has a first upper surface, which is alternately disposed with the first gate structure and the second gate structure; The first gate structure has a second upper surface, the second gate structure has a third upper surface, and the second upper surface and the third upper surface are lower than the first upper surface; The method for preparing this semiconductor structure includes: A gate trench and a first fin structure are formed in an active region of a substrate, the first fin structure being adjacent to the gate trench; The gate trench is filled with a dielectric material; A first photoresist pattern is formed on the active region; A first etching process is performed to partially remove the first fin structure to form a second fin structure, wherein the second fin structure has a protrusion. A hard mask is formed on the active region; and A second etching process is performed to remove a portion of the dielectric material and the protrusion of the second fin structure to form the third fin structure.

2. The semiconductor structure of claim 1, wherein the third upper surface is lower than the second upper surface.

3. The semiconductor structure of claim 1, wherein the second gate structure is deeper than the first gate structure.

4. The semiconductor structure of claim 1, wherein the first gate structure and the second gate structure have different diameters and different depths.

5. A method for fabricating a semiconductor structure, comprising: A gate trench and a first fin structure are formed in an active region of a substrate, the first fin structure being adjacent to the gate trench; The gate trench is filled with a dielectric material; A first photoresist pattern is formed on the active region; A first etching process is performed to partially remove the first fin structure to form a second fin structure, wherein the second fin structure has a protrusion. A hard mask is formed on the active region; and A second etching process is performed to remove a portion of the dielectric material and the protrusion of the second fin structure to form a third fin structure.

6. The method of claim 5, wherein the forming of the gate trench comprises forming a first gate trench adjacent to a second gate trench, wherein, The first gate trench and the second gate trench are disposed along a first direction.

7. The preparation method of claim 6, wherein the second gate trench is formed to be deeper than the first gate trench.

8. The method for fabricating a semiconductor structure as described in claim 6, wherein the formation of the gate trench includes forming the first gate trench and the second gate trench, having different diameters and different depths.

9. The method for fabricating a semiconductor structure as claimed in claim 6, wherein the execution of the first etching process includes forming a first recessed channel extending along the first direction.

10. The method for fabricating a semiconductor structure as claimed in claim 9, wherein after the first etching process, a second height of the second fin structure is less than a first height of the first fin structure.

11. The method for fabricating a semiconductor structure as described in claim 5, wherein forming the hard mask comprises: A capping layer is formed to cover the active area; A mask layer is formed on the cover layer; An anti-reflective coating layer is formed on the mask layer; as well as A second photoresist pattern is formed on the antireflective coating layer.

12. The method for fabricating a semiconductor structure as claimed in claim 11, wherein the mask layer is etched using the second photoresist pattern as an etching mask to form a mask pattern.

13. The method for fabricating a semiconductor structure as claimed in claim 12, wherein the capping layer is etched using the mask pattern as an etching mask to form a capping pattern.

14. The method for fabricating a semiconductor structure as claimed in claim 13, wherein the cover pattern and the mask pattern are formed together on the hard mask in the active region.

15. The method for fabricating a semiconductor structure as claimed in claim 8, wherein the second etching process includes grinding the protrusion of the second fin structure.

16. The method for fabricating a semiconductor structure as claimed in claim 9, wherein after the second etching process, a third height of the third fin structure is less than a second height of the second fin structure.

17. The method for fabricating a semiconductor structure as claimed in claim 9, wherein the execution of the second etching process includes forming a second recessed channel extending along the first direction.

18. The method for fabricating a semiconductor structure as claimed in claim 17, wherein the second recessed channel passes through the dielectric material and the third fin structure.

19. The method for fabricating a semiconductor structure as claimed in claim 9, wherein the second etching process uses an etching system that uses a plasma having a bias power of 200 to 300 watts and a switching frequency of 100 to 300 Hz.

20. The method for fabricating a semiconductor structure as claimed in claim 19, wherein in the second etching process, the ratio of a period of a conduction state to a period of a cutoff state of the plasma is between 70:30 and 50:50.

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