Chip input and output pin direction control circuit structure

Abstract

A chip input / output pin direction control circuit structure includes multiple first input / output pins and multiple second input / output pins corresponding to the multiple first input / output pins. The multiple first input / output pins are connected to the multiple second input / output pins via a processing part of the chip. Each first input / output pin is connected to the processing part via a first control element, and each second input / output pin is connected to the processing part via a second control element. This invention is implemented inside the chip. Each input / output pin is equipped with a control element composed of two tri-state gates, wherein one tri-state gate is active low and the other tri-state gate is active high. When the input is low, the input / output pin can be used as an input; when the input is high, the input / output pin can be used as an output. Therefore, complex wiring is not required outside the chip, reducing development difficulty and time, improving production efficiency, and providing high flexibility.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a chip input / output pin direction control circuit structure. Background Technology

[0002] In multi-chip cascaded design, data can be sent sequentially from the first chip to the next lower chip, or vice versa, from the last chip to the next higher chip. Therefore, the same pin of the chip needs to be able to be used as both an input and an output. Currently, this is achieved by using external wiring on the chip. The wiring structure is relatively complex, and the development time is long and the development difficulty is high, resulting in low production efficiency. Summary of the Invention

[0003] Based on this, and to address the aforementioned technical problems, a chip input / output pin direction control circuit structure is provided.

[0004] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0005] A chip input / output pin direction control circuit structure includes a plurality of first input / output pins and a plurality of second input / output pins corresponding to the plurality of first input / output pins. The plurality of first input / output pins are connected to the plurality of second input / output pins via a processing part of the chip. The characteristic is that each first input / output pin is connected to the processing part via a first control element, and each second input / output pin is connected to the processing part via a second control element.

[0006] The first control unit includes a first active-high tri-state gate and a first active-low tri-state gate. The output terminal of the first active-high tri-state gate and the input terminal of the first active-low tri-state gate are both connected to the corresponding first input / output pins. The enable terminal of the first active-high tri-state gate and the enable terminal of the first active-low tri-state gate are both connected to the control pins of the chip. The input terminal of the first active-high tri-state gate and the output terminal of the first active-low tri-state gate are both connected to the processing part.

[0007] The second control unit includes a second active-high tri-state gate and a second active-low tri-state gate. The input terminal of the second active-high tri-state gate and the output terminal of the second active-low tri-state gate are both connected to the corresponding second input / output pins. The enable terminal of the second active-high tri-state gate and the enable terminal of the second active-low tri-state gate are both connected to the control pins. The output terminal of the second active-high tri-state gate and the input terminal of the second active-low tri-state gate are both connected to the processing section.

[0008] This invention is implemented inside the chip. Each input / output pin is equipped with a control device consisting of two tri-state gates, one of which is active low and the other is active high. When the input is low, the input / output pin can be used as an input, and when the input is high, the input / output pin can be used as an output. This method eliminates the need for complex wiring outside the chip, reduces development difficulty and time, improves production efficiency, and offers high flexibility. Attached Figure Description

[0009] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments:

[0010] Figure 1 This is a schematic diagram of the structure of the present invention. Detailed Implementation

[0011] This specification provides a chip input / output pin direction control circuit structure, including multiple first input / output pins, multiple second input / output pins, multiple first control components A, multiple second control components B, and control pins.

[0012] like Figure 1 As shown, taking chip C as an example, it has one power supply pin (pin 1), one control pin (pin 2), six first input / output pins (pins 3, 4, 5, 9, 10, and 11), and six second input / output pins (pins 6, 7, 8, 12, 13, and 14). The six first input / output pins are connected to the six second input / output pins through the processing part C1 of chip C. Among them, pin 3 corresponds to pin 14. When pin 3 is used as an input, it is processed by the processing part C1 and output from pin 14. Conversely, when pin 14 is used as an input, it is processed by the processing part C1 and output from pin 3. Similarly, pin 4 corresponds to pin 13, pin 5 corresponds to pin 12, pin 11 corresponds to pin 6, pin 10 corresponds to pin 7, and pin 9 corresponds to pin 8. Further details are omitted here.

[0013] Of course, the number of the first input / output pin and the second input / output pin is not limited to 6, and the two can be one-to-many or many-to-one, which is determined by the processing section C1.

[0014] The number of first control units A is the same as the number of first input / output pins, the number of second control units B is the same as the number of second input / output pins, each first input / output pin is connected to the processing unit C1 via a first control unit A, and each second input / output pin is connected to the processing unit C1 via a second control unit B.

[0015] The following uses pins 3 and 14 as examples to illustrate the structure and control principle of the first control component A and the second control component B:

[0016] The first control unit A includes a first high-level active tri-state gate A1 and a first low-level active tri-state gate A2. The output terminal of the first high-level active tri-state gate A1 and the input terminal of the first low-level active tri-state gate A2 are both connected to the corresponding pin 3. The enable terminal of the first high-level active tri-state gate A1 and the enable terminal of the first low-level active tri-state gate A2 are both connected to pin 2. The input terminal of the first high-level active tri-state gate A1 and the output terminal of the first low-level active tri-state gate A2 are both connected to the processing part C1.

[0017] The second control unit B includes a second active-high tri-state gate B1 and a second active-low tri-state gate B2. The input terminal of the second active-high tri-state gate B1 and the output terminal of the second active-low tri-state gate B2 are both connected to the corresponding pin 14. The enable terminal of the second active-high tri-state gate B1 and the enable terminal of the second active-low tri-state gate B2 are both connected to pin 2. The output terminal of the second active-high tri-state gate B1 and the input terminal of the second active-low tri-state gate B2 are both connected to the processing section C1.

[0018] When pin 2 is low, both A2 and B2 are turned on, and both A1 and B1 are in a high-impedance state. At this time, pin 3 is used as the input and pin 14 is used as the output.

[0019] When pin 2 is high, both high-level active tri-state gates A1 and B1 are turned on, and both low-level active tri-state gates A2 and B2 are in a high-impedance state. At this time, pin 14 is used as the input and pin 3 is used as the output.

[0020] Similarly, the direction of each input / output pin can be controlled.

[0021] However, those skilled in the art should recognize that the above embodiments are only used to illustrate the present invention and are not intended to limit the present invention. Any changes or modifications to the above embodiments that are within the essential spirit of the present invention will fall within the scope of the claims of the present invention.

Claims

1. A chip input / output pin direction control circuit structure, comprising a plurality of first input / output pins and a plurality of second input / output pins corresponding to the plurality of first input / output pins, wherein the plurality of first input / output pins are connected to the plurality of second input / output pins via a processing section of the chip, characterized in that, Each first input / output pin is connected to the processing unit via a first control element, and each second input / output pin is connected to the processing unit via a second control element. The number of first control elements is the same as the number of first input / output pins, and the number of second control elements is the same as the number of second input / output pins. The first control unit includes a first active-high tri-state gate and a first active-low tri-state gate. The output terminal of the first active-high tri-state gate and the input terminal of the first active-low tri-state gate are both connected to the corresponding first input / output pins. The enable terminal of the first active-high tri-state gate and the enable terminal of the first active-low tri-state gate are both connected to the control pins of the chip. The input terminal of the first active-high tri-state gate and the output terminal of the first active-low tri-state gate are both connected to the processing part. The second control unit includes a second active-high tri-state gate and a second active-low tri-state gate. The input terminal of the second active-high tri-state gate and the output terminal of the second active-low tri-state gate are both connected to the corresponding second input / output pins. The enable terminal of the second active-high tri-state gate and the enable terminal of the second active-low tri-state gate are both connected to the control pins. The output terminal of the second active-high tri-state gate and the input terminal of the second active-low tri-state gate are both connected to the processing section.

2. The chip input / output pin direction control circuit structure according to claim 1, characterized in that, The number of the first input / output pins and the second input / output pins are the same, and they correspond one-to-one.

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