Display panel and display device

Abstract

The embodiment of the present invention provides a display panel and a display device, which relate to the field of display technology and improve the uniformity of voltage signals on data lines. The display panel includes: a data line located in a display area; a power bus located in a non-display area; a connecting line located in the non-display area, the connecting line is coupled to the data line, the connecting line and the power bus overlap at least partially, and the connecting line has a first area, which is the overlapping area of ​​the connecting line and the power bus; a control circuit located in the non-display area, the control circuit includes a control transistor, the first electrode and / or the second electrode of the control transistor is coupled to the connecting line; the control transistor includes a first control transistor and a second control transistor, the first area of ​​the connecting line coupled to the first control transistor is different from the first area of ​​the connecting line coupled to the second control transistor, and the channel area of ​​the first control transistor and the second control transistor is different.

Description

[Technical field]

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. [Background technology]

[0002] As is well known, the display area of ​​the display panel includes multiple data lines, which are electrically connected to the connecting lines in the non-display area and the pixel circuits in the display area. The voltage signal is transmitted to the data lines via the connecting lines, and then transmitted to the pixel circuit to control the pixel circuit to drive the light-emitting element to emit light.

[0003] In the prior art, there are differences in loads between different connection lines, and the voltage changes generated when the voltage signal is transmitted on the connection lines are different, which leads to inconsistent voltage signals transmitted to the data lines, affecting the screen display. [Summary of the invention]

[0004] In view of this, embodiments of the present invention provide a display panel and a display device to improve the uniformity of voltage signals transmitted on different data lines.

[0005] In one aspect, an embodiment of the present invention provides a display panel, including:

[0006] a display area and a non-display area surrounding the display area;

[0007] a plurality of data lines located in the display area;

[0008] A power bus located in the non-display area;

[0009] A connection line located in the non-display area, the connection line is coupled to the data line, and at least partially overlaps with the power bus in a direction perpendicular to the plane where the display panel is located, and the connection line has a first area, and the first area is an overlapping area between the connection line and the power bus;

[0010] A control circuit located in the non-display area, the control circuit comprising a plurality of control transistors, a first electrode and / or a second electrode of the control transistor being coupled to the connection wiring;

[0011] The control transistor includes a first control transistor and a second control transistor, wherein the first area of ​​the connection wiring coupled to the first control transistor is different from the first area of ​​the connection wiring coupled to the second control transistor, and the channel areas of the first control transistor and the second control transistor are different.

[0012] On the other hand, an embodiment of the present invention provides a display device, including the above-mentioned display panel.

[0013] One of the above technical solutions has the following beneficial effects:

[0014] In the embodiment of the present invention, for the first control transistor and the second control transistor, when the first areas of the connection lines coupled to the two control transistors are different, the loads of the two connection lines are different, and the voltage change degrees of the voltage signal when transmitted on the two connection lines are different. At this time, by differentially designing the channel areas of the first control transistor and the second control transistor, the sizes of the gates covering the channels in the two control transistors can be different, thereby making the parasitic capacitances of the two control transistors different.

[0015] With such a configuration, the difference in the amount of change in the voltage signal caused by the difference in the parasitic capacitance of the two control transistors can be used to compensate for the difference in the amount of change in the voltage signal caused by the difference in the load of the two connecting lines, thereby making the voltage signals transmitted to the two data lines coupled to the first control transistor and the second control transistor tend to be consistent, effectively improving the uniformity of the voltage signals in different data lines.

[0016] Especially when performing dot screen testing on a display panel, the uniformity of the test voltage signals input on different data lines can be improved, thereby avoiding uneven display or moiré phenomenon on the test screen and improving the reliability of product evaluation.

Brief Description of the Drawings

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 It is a schematic diagram of an overlap between the connection wiring and the power bus in the prior art;

[0019] Figure 2 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0020] Figure 3 A schematic diagram of a circuit structure of a control circuit provided by an embodiment of the present invention;

[0021] Figure 4 A schematic diagram of a membrane structure of a control circuit provided by an embodiment of the present invention;

[0022] Figure 5 Another structural schematic diagram of a display panel of a control circuit provided in an embodiment of the present invention;

[0023] Figure 6Another circuit structure schematic diagram of a control circuit provided by an embodiment of the present invention;

[0024] Figure 7 A schematic diagram of another film layer structure of a control circuit provided in an embodiment of the present invention;

[0025] Figure 8 A schematic diagram of the structure of a first test circuit provided by an embodiment of the present invention;

[0026] Fig. 9 A signal timing diagram provided by an embodiment of the present invention;

[0027] Fig.10 A schematic diagram of an equivalent structure of parasitic capacitance of a transistor and a signal line provided by an embodiment of the present invention;

[0028] Fig.11 A schematic diagram of a channel comparison between a first gating transistor and a second gating transistor provided in an embodiment of the present invention;

[0029] Fig.12 Another channel comparison schematic diagram of the first gating transistor and the second gating transistor provided in an embodiment of the present invention;

[0030] Fig.13 A schematic diagram of the structure of the first wiring group and the second wiring group provided in an embodiment of the present invention;

[0031] Fig.14 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0032] Fig.15 A schematic diagram of another circuit structure of the control circuit provided in an embodiment of the present invention;

[0033] Fig.16 A schematic diagram of another film layer structure of the control circuit provided in an embodiment of the present invention;

[0034] Fig.17 A schematic diagram of an equivalent structure of parasitic capacitance of a transistor and a signal line provided by an embodiment of the present invention;

[0035] Fig.18 A channel comparison schematic diagram of a first test transistor and a second test transistor provided in an embodiment of the present invention;

[0036] Fig.19 Another channel comparison schematic diagram of the first test transistor and the second test transistor provided by the embodiment of the present invention;

[0037] Fig. 20A schematic diagram of the structure of the third wiring group and the fourth wiring group provided in an embodiment of the present invention;

[0038] Fig.21 A schematic diagram of another circuit structure of a control transistor provided in an embodiment of the present invention;

[0039] Fig. 22 A schematic diagram of another film layer structure of a control transistor provided in an embodiment of the present invention;

[0040] Fig.23 A schematic diagram of the structure of a display device provided by an embodiment of the present invention. [Specific implementation method]

[0041] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0042] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0044] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0045] At present, in order to further reduce the border width of the display panel, the connection lines in the non-display area will inevitably overlap with the power bus. Figure 1 As shown, Figure 1 This is a schematic diagram of the overlap between the connecting lines and the power bus in the prior art. Since the overlapping areas between the connecting lines 101 and the power bus 102 at different positions are different, there are differences in the loads between different connecting lines 101. Such load differences will cause different voltage changes when the voltage signals are transmitted on different connecting lines 101, thereby causing differences in the voltage signals transmitted to the data line 103.

[0046] For example, before the display panel leaves the factory, it is usually necessary to perform a dot screen test on the display panel to verify the display performance of the display panel. When performing the dot screen test, the test voltage signal provided by the test terminal is further transmitted to the data line 103 via the connecting line 101. If the test voltage signal has different degrees of voltage changes when being transmitted on the connecting line 101, then the test voltage signals input on different data lines 103 will be different, which will cause uneven display or moiré phenomenon on the test screen, which will have an adverse effect on the evaluation of the product.

[0047] To this end, an embodiment of the present invention provides a display panel that can effectively improve the problem of uneven voltage signals transmitted on data lines caused by differences in connection wiring loads.

[0048] like Figure 2 As shown, Figure 2 A schematic diagram of the structure of a display panel provided in an embodiment of the present invention, wherein the display panel comprises a display area 1 and a non-display area 2 surrounding the display area 1 .

[0049] The display panel also includes:

[0050] A plurality of data lines Data are located in the display area 1 . The data lines Data are electrically connected to the pixels in the display area 1 and are used to transmit voltage signals to the pixel circuits to control the pixel circuits to drive the light-emitting elements to emit light.

[0051] The power bus 4 located in the non-display area 2 is electrically connected to the power signal terminals in the non-display area 2 and the power signal lines in the display area 1, respectively, and is used to transmit the power signal provided by the power signal terminals to the power signal lines.

[0052] The connecting line 5 is located in the non-display area 2, and the connecting line 5 is coupled to the data line Data. In the direction perpendicular to the plane where the display panel is located, the connecting line 5 at least partially overlaps with the power bus 4, wherein the connecting line 5 has a first area, and the first area is the overlapping area between the connecting line 5 and the power bus 4.

[0053] The control circuit 6 located in the non-display area 2 is as follows: Figure 3 and Figure 4 As shown, Figure 3 A circuit structure diagram of a control circuit provided by an embodiment of the present invention, Figure 4 A schematic diagram of a film layer structure of a control circuit provided in an embodiment of the present invention, wherein the control circuit 6 comprises a plurality of control transistors 7 , and a first electrode and / or a second electrode of the control transistor 7 is coupled to a connection line 5 .

[0054] Among them, the control transistor 7 includes a first control transistor 71 and a second control transistor 72, the first area of ​​the connecting wire 5 coupled to the first control transistor 71 is different from the first area of ​​the connecting wire 5 coupled to the second control transistor 72, and the channel areas of the first control transistor 71 and the second control transistor 72 are different.

[0055] It should be noted that see Figure 4 , each control transistor 7 includes a gate g, a first electrode s, a second electrode d and a channel p, wherein the channel p is located between the first electrode s and the second electrode d, and the gate g covers the channel p in a direction perpendicular to the plane where the display panel is located. When the gate g receives a turn-on voltage, the first electrode s and the second electrode d are electrically connected through the channel p, thereby forming a signal transmission path between the first electrode s and the second electrode d. The channel area described in the embodiment of the present invention refers to the area of ​​the positive projection of the channel p in a direction perpendicular to the plane where the display panel is located.

[0056] When the data line Data is coupled to the control transistor 7, the voltage signal transmitted on the data line Data is affected by the parasitic capacitance of the control transistor 7. Specifically, when the control transistor 7 switches the switch state (on / off), the gate potential of the control transistor 7 jumps, and due to the coupling effect of the parasitic capacitance in the control transistor 7, the potential on the first electrode and / or the second electrode of the control transistor 7 fluctuates, thereby affecting the voltage signal transmitted to the data line Data.

[0057] In the embodiment of the present invention, for the first control transistor 71 and the second control transistor 72, when the first areas of the connection lines 5 coupled to the two control transistors 7 are different, the loads of the two connection lines 5 are different, and the voltage change degrees of the voltage signal when transmitted on the two connection lines 5 are different. At this time, by differentially designing the channel areas of the first control transistor 71 and the second control transistor 72, the sizes of the gates covering the channels in the two control transistors 7 can be made different, thereby making the parasitic capacitances between the two control transistors 7 and the connection lines 5 different.

[0058] With such a configuration, the difference in the amount of change in the voltage signal caused by the difference in the parasitic capacitance of the two control transistors 7 can be used to compensate for the difference in the amount of change in the voltage signal caused by the difference in the load of the two connecting lines 5, thereby making the voltage signals on the two data lines Data coupled to the first control transistor 71 and the second control transistor 72 tend to be consistent, effectively improving the uniformity of the voltage signals in different data lines Data.

[0059] Especially when performing a dot screen test on a display panel, the uniformity of the test voltage signals input on different data lines Data can be improved, thereby avoiding uneven display or moiré phenomenon on the test screen and improving the reliability of product evaluation testing.

[0060] It should be noted that the above-mentioned first control transistor 71 and the second control transistor 72 are not specific limitations on two control transistors 7. For any two control transistors 7, when the channel areas of the two control transistors 7 and the connecting wiring 5 coupled thereto meet the above conditions, one of them can be regarded as the first control transistor 71 and the other can be regarded as the second control transistor 72.

[0061] In one embodiment, the channel area of ​​the first control transistor 71 is S C1 , the first area of ​​the connection line 5 coupled to the first control transistor 71 is S O1 ; The channel area of ​​the second control transistor 72 is S C2 , the first area of ​​the connection line 5 coupled to the second control transistor 72 is S O2 ; S O1 >S O2 , S C1 <S C2 .

[0062] Compared with the second control transistor 72, the overlapping area between the connection line 5 coupled to the first control transistor 71 and the power bus 4 is larger, so the load of the connection line 5 is larger, and the attenuation degree of the voltage signal when transmitted on the connection line 5 is larger. At this time, by reducing the channel area S of the first control transistor 71 C1 , the parasitic capacitance between the first control transistor 71 itself and the connection line 5 can be reduced. When the gate potential of the first control transistor 71 jumps, the voltage fluctuation degree on the first electrode and the second electrode of the first control transistor 71 can be reduced, thereby reducing the influence on the voltage signal transmitted to the data line Data. Therefore, compared with the second control transistor 72, the first control transistor 71 can use the part of the influence reduced by its own parasitic capacitance on the voltage signal to compensate for the part of the influence increased by the load of the coupled connection line 5 on the voltage signal, thereby making the voltage signals transmitted on the two data lines Data coupled to the first control transistor 71 and the second control transistor 72 tend to be consistent.

[0063] In one embodiment, Figure 5 to Figure 7 As shown, Figure 5 Another structural schematic diagram of a display panel of a control circuit provided in an embodiment of the present invention, Figure 6 Another circuit structure diagram of the control circuit provided in the embodiment of the present invention is shown in FIG. Figure 7Another schematic diagram of the film layer structure of the control circuit provided in an embodiment of the present invention, the connection line 5 includes a first sub-connection line 51 and a second sub-connection line 52. The control circuit 6 includes a gating circuit 8, and the gating circuit 8 includes a plurality of gating transistors 9. The first electrode of the gating transistor 9 is coupled to the data signal transmission terminal 10 through the first sub-connection line 51, and the second electrode of the gating transistor 9 is coupled to the data line Data through the second sub-connection line 52. In the direction perpendicular to the plane where the display panel is located, the first sub-connection line 51 overlaps with the power bus 4, that is, the gating transistor 9 is located on the side of the power bus 4 close to the display area 1.

[0064] The gate transistor 9 includes a first gate transistor 91 and a second gate transistor 92 , and the first area of ​​the first sub-connection wiring 51 coupled to the first gate transistor 91 and the second gate transistor 92 is different, and the channel areas of the first gate transistor 91 and the second gate transistor 92 are different.

[0065] See also Figure 6 The gating circuit 8 may specifically include a plurality of gating units 11, the gating unit 11 includes a plurality of gating transistors 9, wherein the gate of the i-th gating transistor 9 in the plurality of gating units 11 is electrically connected to the same gating control signal line Mux ( Figure 6 and Figure 7 In the figure, the two selection control signal lines are represented by Mux1 and Mux2 respectively), the first electrodes of the multiple selection transistors 9 in each selection unit 11 are electrically connected to the data signal transmission terminal 10 through the first sub-connection wiring 51, and the second electrodes of the multiple selection transistors 9 in each selection unit 11 are electrically connected to the multiple data lines Data one by one through multiple second sub-connection wirings 52.

[0066] The gating circuit 8 is used to control the time-sharing conduction of multiple gating transistors 9 in the same gating unit 11, thereby controlling the voltage signal provided by the data signal transmission terminal 10 to be transmitted to the data line Data electrically connected to the multiple gating transistors 9 via the first connecting wire 5 in a time-sharing manner. Based on this time-sharing driving method, only a small number of first sub-connecting wires 51 and data signal transmission terminals 10 need to be set in the display panel, which is more conducive to realizing a narrow frame design of the display panel.

[0067] When the first areas of the first sub-connection wiring 51 coupled to the first selection transistor 91 and the second selection transistor 92 are different, the parasitic capacitances of the two selection transistors 9 can be adjusted by differentially designing the channel areas of the two selection transistors 9, so that there is a difference in the parasitic capacitances of the two selection transistors 9. At this time, the difference in the amount of change of the voltage signal caused by the difference in the parasitic capacitance of the two selection transistors 9 can be used to compensate for the difference in the amount of change of the voltage signal caused by the difference in the load of the two first sub-connection wirings 51, thereby making the voltage signals transmitted to the two data lines Data coupled to the first selection transistor 91 and the second selection transistor 92 tend to be consistent, thereby improving the uniformity of the voltage signals input on different data lines Data.

[0068] Furthermore, if Figure 8 As shown, Figure 8 A structural schematic diagram of the first test circuit provided in an embodiment of the present invention, the display panel also includes a first test circuit 12, the first test circuit 12 includes a first type of test transistor 13, the first type of test transistor 13 is coupled to the first sub-connection wiring 51, the first type of test transistor 13 is also coupled to the test pin 14, and / or the first type of test transistor 13 is also coupled to the test control switch signal line SW.

[0069] The first test circuit 12 is used to perform a dot screen test on the display panel before the display panel leaves the factory. The test pin 14 may specifically include a first test pin 141 for providing a red test voltage signal, a second test pin 142 for providing a green test voltage signal, and a third test pin 143 for providing a blue test voltage signal.

[0070] When performing a point screen test, combine Fig. 9 As shown in the signal timing diagram, when testing the red screen, the test control switch signal line SW controls the first type test transistor 13 electrically connected to the first test pin 141 to turn on, so that the path between the first test pin 141 and the first connecting wire 5 is turned on. At the same time, the selection control signal line Mux controls part of the selection transistor 9 to turn on, so that the path between the data line Data coupled to the red sub-pixel and the first connecting wire 5 is turned on, thereby forming a signal transmission path between the first test pin 141 and the data line Data coupled to the red sub-pixel, so that the red test voltage signal is transmitted to the data line Data via the first type test transistor 13, the first connecting wire 5, the selection transistor 9 and the second connecting wire 5.

[0071] When testing the green screen, the test control switch signal line SW controls the first type test transistor 13 electrically connected to the second test pin 142 to turn on, so that the path between the second test pin 142 and the first connecting wire 5 is turned on. At the same time, the selection control signal line Mux controls part of the selection transistor 9 to turn on, so that the path between the data line Data coupled to the green sub-pixel and the first connecting wire 5 is turned on, thereby forming a signal transmission path between the second test pin 142 and the data line Data coupled to the green sub-pixel, so that the green test voltage signal is transmitted to the data line Data via the first type test transistor 13, the first connecting wire 5, the selection transistor 9 and the second connecting wire 5.

[0072] When testing the blue screen, the test control switch signal line SW controls the first type test transistor 13 electrically connected to the third test pin 143 to turn on, so that the path between the third test pin 143 and the first connecting wire 5 is turned on. At the same time, the selection control signal line Mux controls part of the selection transistor 9 to turn on, so that the path between the data line Data connected to the blue sub-pixel and the first connecting wire 5 is turned on, thereby forming a signal transmission path between the third test pin 143 and the data line Data coupled to the blue sub-pixel, so that the blue test voltage signal is transmitted to the data line Data via the first type test transistor 13, the first connecting wire 5, the selection transistor 9 and the second connecting wire 5.

[0073] It should be noted that after the display panel dot screen test is completed, in order to avoid the test pin 14 or the test control switch signal line SW occupying the border width in the display panel, the test pin 14 or the test control switch signal line SW can be cut out from the display panel motherboard so that it is not retained in the display panel.

[0074] When the test pin 14 is cut out, it corresponds to the above-mentioned “the first type of test transistor 13 is also coupled to the test control switch signal line SW”; when the test control switch signal line SW is cut out, it corresponds to the above-mentioned “the first type of test transistor 13 is also coupled to the test pin 14”; when the test control switch signal line SW and the test pin 14 are not cut out, it corresponds to the above-mentioned “the first type of test transistor 13 is also coupled to the test pin 14 and the test control switch signal line SW”.

[0075] In one embodiment, the channel area of ​​the first gate transistor 91 is S C11 , the channel area of ​​the second selection transistor 92 is S C12 , S C11- S C12 satisfy:

[0076] Among them, C 11is the parasitic capacitance of the first sub-connection wiring 51 coupled to the first selection transistor 91, C 12 is the parasitic capacitance of the first sub-connection wiring 51 coupled to the second selection transistor 92, W s is the channel width of the first type of test transistor 13, L s is the channel length of the first type of test transistor 13, C 2 is the parasitic capacitance of the second sub-connection trace 52, C Data is the parasitic capacitance of the data line Data.

[0077] Combined with the above analysis of the dot screen test process, when performing the dot screen test, it is necessary to control the conduction state of the first type test transistor 13 and the selection transistor 9 to ensure that the test voltage signal can be transmitted to the data line Data via the test signal terminal. When the conduction state of the first type test transistor 13 and the selection transistor 9 is switched, the gate potential of the first type test transistor 13 and the selection transistor 9 jumps, and under the effect of the parasitic capacitance of the transistor, the jump of the gate potential will affect the test voltage signal transmitted on the data line Data.

[0078] Specifically, Fig.10 As shown, Fig.10 FIG. 1 is a schematic diagram of an equivalent structure of the parasitic capacitance of the transistor and the signal line provided in an embodiment of the present invention. When the first type test transistor 13 is turned off, the voltage change on the data line Data is ΔV1. Wherein, VGH is the cut-off voltage of the transistor (the first type test transistor 13 and the gate transistor 9), VGL is the on-voltage of the transistor (the first type test transistor 13 and the gate transistor 9), and C 1 is the parasitic capacitance of the first sub-connection wiring 51, and Cgs1 is the parasitic capacitance of the first type test transistor 13. When the selection transistor 9 is turned off, the voltage change on the data line Data is ΔV2, Cgs2 is the parasitic capacitance of the gate transistor 9 .

[0079] The parasitic capacitance C of the first sub-connection wiring 51 is 1 The effect on the voltage change on the data line Data can be obtained by taking the partial differential of ΔV1: The influence of the parasitic capacitance Cgs2 of the gate transistor 9 on the voltage change on the data line Data can be obtained by taking the partial differential of ΔV2:

[0080] For the first selection transistor 91 and the second selection transistor 92, the parasitic capacitance C of the first sub-connection wiring 51 coupled to the first selection transistor 91 is 11 and the parasitic capacitance C of the first sub-connection wiring 51 coupled to the second selection transistor 9212 The difference between them is ΔC 1 , ΔC 1 =C 11 -C 12 The difference between the parasitic capacitances of the first pass transistor 91 and the second pass transistor 92 is ΔCgs2, ΔCgs2=ΔCgs21-ΔCgs22.

[0081] Capacitance difference ΔC 1 The impact on the voltage change on the data line Data is Right now The effect of the capacitance difference ΔCgs2 on the voltage change on the data line Data is: Right now

[0082] At this time, you can use the command and are equal, so that the influences of the two parts of the capacitance difference on the voltage change on the data line Data cancel each other out, thereby making the voltage signals transmitted on different data lines Data tend to be consistent.

[0083] according to It turns out that: Where, Cgs1=k×W s ×L s , ΔCgs2=k×(S C11 -S C12 ), k is a process parameter value, k is a constant, and the value of k is related to factors such as the film thickness and dielectric constant of the transistor. Since the gate transistor 9 and the first type of test transistor 13 are formed by the same patterning process, the values ​​of k in the two formulas are the same. At this time, it is further concluded that: Then we can conclude

[0084] In summary, the difference between the channel areas of the first gate transistor 91 and the second gate transistor 92 satisfies: The effect of the capacitance difference ΔCgs2 on the voltage change on the data line Data can compensate for the capacitance difference ΔC 1 The influence on the voltage change on the data line Data makes the voltage signal on the data line Data coupled to the first selection transistor 91 and the second selection transistor 92 tend to be consistent.

[0085] Furthermore, if Fig.11 As shown, Fig.11 A channel comparison diagram of the first gating transistor and the second gating transistor provided in an embodiment of the present invention. When designing the channel size of the gating transistor 9, the channel length L of the gating transistor 9 can be DSimilarly, only the channel widths of the first pass transistor 91 and the second pass transistor 92 are designed differently.

[0086] At this time, the channel width of the first selection transistor 91 is W D1 , the channel width of the second selection transistor 92 is W D2 , W D1 and W D2 The difference between them satisfies: So that the effect of the capacitance difference ΔCgs2 on the voltage change on the data line Data can compensate for the capacitance difference ΔC 1 The impact on the voltage change on the data line Data.

[0087] Or, if Fig.12 As shown, Fig.12 Another channel comparison diagram of the first gate transistor and the second gate transistor provided in an embodiment of the present invention is shown. When designing the channel size of the gate transistor 9, the channel width W of the gate transistor 9 may also be D Similarly, only the channel lengths of the first pass transistor 91 and the second pass transistor 92 are designed differently.

[0088] At this time, the channel length of the first selection transistor 91 is L D1 , the channel length of the second selection transistor 92 is L D2 , L D1 and L D2 The difference between them satisfies: So that the effect of the capacitance difference ΔCgs2 on the voltage change on the data line Data can compensate for the capacitance difference ΔC 1 The impact on the voltage change on the data line Data.

[0089] It is understandable that in other optional embodiments of the present invention, the channel length and channel width of the first pass transistor 91 and the second pass transistor 92 can be adjusted simultaneously to differentiate the channel areas of the first pass transistor 91 and the second pass transistor 92.

[0090] In one embodiment, Fig.13 As shown, Fig.13 A schematic diagram of the structure of the first wiring group and the second wiring group provided in an embodiment of the present invention, the display panel includes a first wiring group 15 and a second wiring group 16, and the first wiring group 15 and the second wiring group 16 respectively include a plurality of first sub-connection wirings 51. The first selection transistor 91 is a selection transistor 9 coupled to the first sub-connection wiring 51 in the first wiring group 15, and the second selection transistor 92 is a selection transistor 9 coupled to the first sub-connection wiring 51 in the second wiring group 16.

[0091] The channel area of ​​the first selection transistor 91 is S C11 ', the channel area of ​​the second selection transistor 92 is S C12 ', The derivation process of this formula is similar to that in the above embodiment, and will not be repeated here. 11 ' is the average value of the parasitic capacitance of the first sub-connection wirings 51 in the first wiring group 15, C 12 ' is the average value of the parasitic capacitance of the plurality of first sub-connection wirings 51 in the second wiring group 16, W s is the channel width of the first type of test transistor 13, L s is the channel length of the first type of test transistor 13, C 2 is the parasitic capacitance of the second sub-connection trace 52, C Data is the parasitic capacitance of the data line Data.

[0092] In the above-mentioned setting, by grouping the first sub-connection routing lines 51, only the channel areas of the selection transistors 9 coupled to different routing groups are designed differently, while the channel areas of the selection transistors 9 coupled to the same routing group are designed with the same channel area. This can improve the uniformity of the voltage signals transmitted on different data lines Data and reduce the difficulty of transistor design.

[0093] Further, see Fig.13 The power bus 4 includes a plurality of hollow areas 17. In a direction perpendicular to the plane of the display panel, the first sub-connection wiring 51 in the first wiring group 15 at least partially overlaps with the hollow area 17, and the first sub-connection wiring 51 in the second wiring group 16 does not overlap with the hollow area 17.

[0094] In the embodiment of the present invention, a plurality of hollow areas 17 may be provided on the power bus 4 to reduce the load of the power bus 4. After the hollow areas 17 are provided on the power bus 4, part of the first sub-connection routing lines 51 overlap with the hollow areas 17, and part of the first sub-connection routing lines 51 do not overlap with the hollow areas 17. Among them, for the part of the first sub-connection routing lines 51 overlapping with the hollow areas 17, the overlapping area between the part of the first sub-connection routing lines 51 and the power signal line is small, so the load of the part of the first sub-connection routing lines 51 is small, and the attenuation degree of the voltage signal when transmitting on the part of the first sub-connection routing lines 51 is small. For the part of the first sub-connection routing lines 51 that does not overlap with the hollow areas 17, the overlapping area between the part of the first sub-connection routing lines 51 and the power signal line is large, so the load of the part of the first sub-connection routing lines 51 is large, and the attenuation degree of the voltage signal when transmitting on the part of the first sub-connection routing lines 51 is correspondingly large.

[0095] By making the first sub-connection routing lines 51 included in the first routing group 15 all overlap the hollow area 17, and the first sub-connection routing lines 51 included in the second routing group 16 all overlap the hollow area 17. On the one hand, the loads of the first sub-connection routing lines 51 included in the same routing group are similar. When the gating transistors 9 coupled to the same routing group are designed with the same channel area, the load differences of the first sub-connection routing lines 51 in the routing group can still be accurately compensated. On the other hand, the load differences of the first sub-connection routing lines 51 included in different routing groups are relatively large. By differentially designing the channel areas of the gating transistors 9 coupled to different routing groups, the load differences of different first sub-connection routing lines 51 with relatively large load differences can also be accurately compensated.

[0096] Furthermore, when designing the channel size of the gate transistor 9, the channel length L of the gate transistor 9 may be D ' is the same, only the channel widths of the first pass transistor 91 and the second pass transistor 92 are designed differently. At this time, the channel width of the first pass transistor 91 is W D1 ', the channel width of the second selection transistor 92 is W D2 ',W D1 ' and W D2 The difference between them satisfies: The difference ΔCgs2′ of the parasitic capacitance of the two gate transistors 9 affects the voltage change on the data line Data, thereby compensating the difference ΔCgs2′ of the parasitic capacitance of the first sub-connection wiring 51 coupled to the two gate transistors 9. 1 'The impact on the voltage change on the data line Data.

[0097] Alternatively, the channel width W of the gate transistor 9 may be set to D ' is the same, only the channel lengths of the first selection transistor 91 and the second selection transistor 92 are designed differently. At this time, the channel length of the first selection transistor 91 is L D1 ', the channel length of the second selection transistor 92 is L D2 ',L D1 ' and L D2 The difference between them satisfies: The difference ΔCgs2′ of the parasitic capacitance of the two gate transistors 9 affects the voltage change on the data line Data, thereby compensating the difference ΔCgs2′ of the parasitic capacitance of the first sub-connection wiring 51 coupled to the two gate transistors 9. 1 'The impact on the voltage change on the data line Data.

[0098] It is understandable that in other optional embodiments of the present invention, the channel length and channel width of the first pass transistor 91 and the second pass transistor 92 can be adjusted simultaneously so that the channel areas of the first pass transistor 91 and the second pass transistor 92 can be designed differently.

[0099] In one embodiment, Figure 14 to Figure 16 As shown, Fig.14 A schematic diagram of another structure of a display panel provided in an embodiment of the present invention is shown in FIG. Fig.15 A schematic diagram of another circuit structure of the control circuit provided in an embodiment of the present invention is shown in FIG. Fig.16 A schematic diagram of another film layer structure of the control circuit provided in an embodiment of the present invention, wherein the connecting line 5 includes a third sub-connecting line 53; the control circuit 6 includes a second test circuit 18, the second test circuit 18 includes a second type of test transistor 19, and the second electrode of the second type of test transistor 19 is coupled to the data line Data through the third sub-connecting line 53, and in the direction perpendicular to the plane where the display panel is located, the third sub-connecting line 53 overlaps with the power bus 4.

[0100] It should be noted that see Fig.15 and Fig.16 The test transistor may also be coupled to the test pin 14, and / or the test transistor may also be coupled to the test control switch signal line SW.

[0101] Among them, the second type test transistor 19 includes a first test transistor 191 and a second test transistor 192, and the first area of ​​the third sub-connection wiring 53 coupled to the first test transistor 191 and the second test transistor 192 is different, and the channel areas of the first test transistor 191 and the second test transistor 192 are different.

[0102] Specifically, the second test circuit 18 is used to perform a dot screen test on the display panel before the display panel leaves the factory. The test pin 14 may specifically include a first test pin 141 for providing a red test voltage signal, a second test pin 142 for providing a green test voltage signal, and a third test pin 143 for providing a blue test voltage signal.

[0103] When performing a dot screen test, when testing the red screen, the test control switch signal line SW controls the second type test transistor 19 electrically connected to the first test pin 141 to turn on, so that the transmission path between the first test pin 141 and the data line Data coupled to the red sub-pixel is turned on, so that the red test voltage signal is transmitted to the data line Data via the second type test transistor 19 and the third connecting line 5.

[0104] When testing the green screen, the test control switch signal line SW controls the second type test transistor 19 electrically connected to the second test pin 142 to turn on, so that the transmission path between the second test pin 142 and the data line Data coupled to the green sub-pixel is turned on, so that the green test voltage signal is transmitted to the data line Data via the second type test transistor 19 and the third connecting line 5.

[0105] When testing the blue screen, the test control switch signal line SW controls the second type test transistor 19 electrically connected to the third test pin 143 to turn on, so that the transmission path between the third test pin 143 and the data line Data coupled to the blue sub-pixel is turned on, so that the blue test voltage signal is transmitted to the data line Data via the second type test transistor 19 and the third connecting line 5.

[0106] In the embodiment of the present invention, for the first test transistor 191 and the second test transistor 192, when the first areas of the third connection wiring 5 coupled to the two second-type test transistors 9 are different, the parasitic capacitances of the two second-type test transistors 9 can be made different by differentially designing the channel areas of the two second-type test transistors 9. At this time, the difference in the amount of change of the voltage signal caused by the difference in the parasitic capacitance of the two second-type test transistors 9 can be used to compensate for the difference in the amount of change of the voltage signal caused by the difference in the load of the two third connection wirings 5, thereby making the voltage signals transmitted to the two data lines Data coupled to the first test transistor 191 and the second test transistor 192 tend to be consistent, thereby improving the uniformity of the voltage signals input on different data lines Data.

[0107] Furthermore, the channel area of ​​the first test transistor 191 is S C21 , the channel area of ​​the second test transistor 192 is S C22 , Among them, C 31 is the parasitic capacitance of the third sub-connection wiring 53 coupled to the first test transistor 191, C 32 is the parasitic capacitance of the third sub-connection wiring 53 coupled to the second test transistor 192, C Data is the parasitic capacitance of the data line Data.

[0108] Combined with the above analysis of the dot screen test process, when performing the dot screen test, it is necessary to control the conduction state of the second type test transistor 19 to ensure that the test voltage signal can be transmitted to the data line Data via the test signal terminal. When the conduction state of the second type test transistor 19 is switched, the gate potential of the first type test transistor 13 jumps, and under the effect of the parasitic capacitance of the transistor, the jump of the gate potential will affect the test voltage signal transmitted on the data line Data.

[0109] Specifically, Fig.17 As shown, Fig.17 FIG. 1 is a schematic diagram of an equivalent structure of the parasitic capacitance of the transistor and the signal line provided in an embodiment of the present invention. When the second type test transistor 19 is turned off, the voltage change on the data line Data is ΔV3. Wherein, VGH is the cut-off voltage of the transistor (the second type of test transistor 19), VGL is the on-voltage of the transistor (the second type of test transistor 19), C 3 is the parasitic capacitance of the third sub-connection wiring 53 , and Cgs3 is the parasitic capacitance of the second type test transistor 19 .

[0110] The parasitic capacitance C of the third sub-connection wiring 53 is 3 The effect on the voltage change on the data line Data can be obtained by taking the partial differential of ΔV3: The influence of the parasitic capacitance Cgs3 of the second type test transistor 19 on the voltage change on the data line Data can be obtained by taking the partial differential of ΔV3:

[0111] For the first test transistor 191 and the second test transistor 192, the parasitic capacitance C of the third sub-connection wiring 53 coupled to the first test transistor 191 is 31 and the parasitic capacitance C of the third sub-connection wiring 53 coupled to the second test transistor 192 32 The difference between them is ΔC 3 , ΔC 3 =C 31 -C 32 , the difference between the parasitic capacitances of the first test transistor 191 and the second test transistor 192 is ΔCgs3, ΔCgs3 = ΔCgs31 - ΔCgs32.

[0112] Capacitance difference ΔC 3 The impact on the voltage change on the data line Data is Right now The effect of the capacitance difference ΔCgs3 on the voltage change on the data line Data is: Right now

[0113] At this time, you can use the command and The capacitances of the two parts are equal, so that the influence of the difference between the two parts of capacitance on the voltage change on the data line Data cancels each other, thereby making the voltage signals transmitted on different data lines Data tend to be consistent.

[0114] according to It turns out that: Where, Cgs3=k×W s ×Ls , that is, Cgs3=k×S C21 , ΔCgs3=k×(S C12 -S C22 ), k is the process parameter value, k is a constant, and the value of k is related to factors such as the film thickness and dielectric constant of the transistor. Since the test transistor is formed using the same patterning process, the values ​​of k in the two formulas are the same. At this point, it is further concluded that:

[0115] In summary, the difference between the channel areas of the first test transistor 191 and the second test transistor 192 satisfies: The effect of the capacitance difference ΔCgs3 on the voltage change on the data line Data can compensate for the capacitance difference ΔC 3 The impact on the voltage change on the data line Data.

[0116] In one embodiment, Fig.18 As shown, Fig.18 A schematic diagram of a channel comparison of a first test transistor and a second test transistor provided in an embodiment of the present invention. When designing the channel size of the test transistor, the channel length L of the test transistor can be s Similarly, only the channel widths of the first test transistor 191 and the second test transistor 192 are designed differently.

[0117] At this time, the channel width of the first test transistor 191 is W s1 , the channel width of the second test transistor 192 is W s2 , W s1 and W s2 The difference between them satisfies: So that the effect of the capacitance difference ΔCgs3 on the voltage change on the data line Data can compensate for the capacitance difference ΔC 3 The impact on the voltage change on the data line Data.

[0118] Or, if Fig.19 As shown, Fig.19 Another channel comparison diagram of the first test transistor and the second test transistor provided in an embodiment of the present invention is shown. When designing the channel size of the test transistor, the channel width W of the test transistor may also be S Similarly, only the channel lengths of the first test transistor 191 and the second test transistor 192 are designed differently.

[0119] At this time, the channel length of the first test transistor 191 is L s1 , and the channel length of the second test transistor 192 is L s2 , Ls1 and L s2 The difference between them satisfies: So that the effect of the capacitance difference ΔCgs3 on the voltage change on the data line Data can compensate for the capacitance difference ΔC 3 The impact on the voltage change on the data line Data.

[0120] It is understandable that in other optional embodiments of the present invention, the channel length and channel width of the first test transistor 191 and the second test transistor 192 can be adjusted simultaneously so that the channel areas of the first test transistor 191 and the second test transistor 192 can be designed differently.

[0121] In one embodiment, Fig. 20 As shown, Fig. 20 A schematic diagram of the structure of the third wiring group and the fourth wiring group provided in an embodiment of the present invention, the display panel includes a third wiring group 20 and a fourth wiring group 21, and the third wiring group 20 and the fourth wiring group 21 respectively include a plurality of third sub-connection wirings 53. The first test transistor 191 is a test transistor coupled to the third sub-connection wiring 53 in the third wiring group 20, and the second test transistor 192 is a test transistor coupled to the third sub-connection wiring 53 in the fourth wiring group 21.

[0122] The channel area of ​​the first test transistor 191 is S C21 ', and the channel area of ​​the second test transistor 192 is S C22 ', The derivation process of this formula is similar to that in the above embodiment, and will not be repeated here. 31 ' is the average value of the parasitic capacitance of the plurality of third sub-connection wirings 53 in the third wiring group 20, C 32 ' is the average value of the parasitic capacitance of the plurality of third sub-connection wirings 53 in the fourth wiring group 21, C Data is the parasitic capacitance of the data line Data.

[0123] In the above-mentioned setting, by grouping the first sub-connection routing group 51, only the channel areas of the test transistors coupled to different routing groups are designed differently, while the channel areas of the test transistors coupled to the same routing group are designed with the same channel area. This can improve the uniformity of the voltage signal transmitted on the data line Data while reducing the difficulty of transistor design.

[0124] Further, see Fig. 20, the power supply bus 4 includes a hollowed-out area 17. In the direction of the plane where the vertical display panel is located, the third sub-connection trace 53 in the third trace group 20 at least partially overlaps with the hollowed-out area 17, and the third sub-connection trace 53 in the fourth trace group 21 does not overlap with the hollowed-out area 17.

[0125] In an embodiment of the present invention, a plurality of hollowed-out areas 17 are provided on the power supply bus 4 to reduce the load of the power supply bus 4. After the hollowed-out area 17 is provided on the power supply bus 4, some of the third sub-connection traces 53 overlap with the hollowed-out area 17, and some of the third sub-connection traces 53 do not overlap with the hollowed-out area 17. Among them, for this part of the third sub-connection trace 53 that overlaps with the hollowed-out area 17, the overlapping area between this part of the third sub-connection trace 53 and the power signal line is relatively small, so the load of this part of the third sub-connection trace 53 is relatively small, and the attenuation degree of the voltage signal when transmitted on this part of the third sub-connection trace 53 is relatively small. For this part of the third sub-connection trace 53 that does not overlap with the hollowed-out area 17, the overlapping area between this part of the third sub-connection trace 53 and the power signal line is relatively large, so the load of this part of the third sub-connection trace 53 is relatively large, and the attenuation degree of the voltage signal when transmitted on this part of the third sub-connection trace 53 is correspondingly large.

[0126] By making all the third sub-connection traces 53 included in the first trace group 15 be the third sub-connection traces 53 that overlap with the hollowed-out area 17, and all the third sub-connection traces 53 included in the second trace group 16 be the third sub-connection traces 53 that do not overlap with the hollowed-out area 17, on the one hand, the loads of the third sub-connection traces 53 included in the same trace group are similar. When the test transistors coupled to the same trace group adopt the design of the same channel area, the load difference of the third sub-connection traces 53 in this trace group can still be accurately compensated. On the other hand, the load differences of the third sub-connection traces 53 included in different trace groups are relatively large. When the channel areas of the test transistors coupled to different trace groups are designed differently, the load differences of the different third sub-connection traces 53 with relatively large load differences can also be accurately compensated.

[0127] Further, when designing the channel size of the test transistor, the channel length L of the test transistor can be made s ' the same, and only the channel widths of the first test transistor 191 and the second test transistor 192 are designed differently. At this time, the channel width of the first test transistor 191 is W s1 ', and the channel width of the second test transistor 192 is W s2 ', and the difference between W s1 ' and W s2 ' satisfies: The difference ΔCgs3′ of the parasitic capacitance of the two test transistors affects the voltage change on the data line Data, thereby compensating the difference ΔCgs3′ of the parasitic capacitance of the third sub-connection wiring 53 coupled to the two test transistors. 3 'The impact on the voltage change on the data line Data.

[0128] Alternatively, the channel width W of the test transistor can be S ' is the same, only the channel lengths of the first test transistor 191 and the second test transistor 192 are designed differently. At this time, the channel length of the first test transistor 191 is L s1 ', the channel length of the second test transistor 192 is L s2 ',L s1 ' and L s2 The difference between them satisfies: The influence of the parasitic capacitance difference ΔCgs3′ of the two test transistors on the voltage change on the data line Data can compensate for the parasitic capacitance difference ΔCgs3′ of the third sub-connection wiring 53 coupled to the two test transistors. 3 'The impact on the voltage change on the data line Data.

[0129] It is understandable that in other optional embodiments of the present invention, the channel length and channel width of the first test transistor 191 and the second test transistor 192 can be adjusted simultaneously so that the channel areas of the first test transistor 191 and the second test transistor 192 can be designed differently.

[0130] In one embodiment, see Fig.13 and Fig. 20 The power bus 4 includes a plurality of hollow areas 17 to reduce the load of the power bus 4, thereby reducing the attenuation of the power signal when it is transmitted on the power bus 4. In addition, in order to further reduce the load of the connecting wire 5, at least part of the connecting wire 5 overlaps with the hollow area 17 in a direction perpendicular to the plane where the display panel is located.

[0131] In one embodiment, Fig.21 and Fig. 22 As shown, Fig.21 A schematic diagram of another circuit structure of a control transistor provided in an embodiment of the present invention is shown. Fig. 22 A schematic diagram of another film layer structure of a control transistor provided in an embodiment of the present invention, wherein at least part of the control transistor 7 includes a first sub-transistor 22 and a second sub-transistor 23, a gate of the first sub-transistor 22 and a gate of the second sub-transistor 23 are coupled to the same control signal line CL, and a first electrode of the first sub-transistor 22 is coupled to a second electrode of the second sub-transistor 23.

[0132] With the above-mentioned arrangement, in the control circuit 6, at least part of the control transistors 7 are dual-gate transistors. Since the size of the gate in the dual-gate transistor is larger, the size of the channel covered by the corresponding gate is also larger. Therefore, the embodiment of the present invention can adjust the coverage area of ​​the gate in the control transistor 7 and further adjust the channel area in the control transistor 7 by designing part of the control transistor 7 as dual-gate transistors.

[0133] Based on the same inventive concept, an embodiment of the present invention further provides a display device, such as Fig.23 As shown, Fig.23 1 is a schematic diagram of a structure of a display device provided in an embodiment of the present invention, and the display device includes the above-mentioned display panel 100. The specific structure of the display panel 100 has been described in detail in the above-mentioned embodiment, and will not be repeated here. Fig.23 The display device shown is for illustration only, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a laptop computer, an e-reader or a television.

[0134] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0135] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, It is characterized in that include: a display area and a non-display area surrounding the display area; a plurality of data lines located in the display area; A power bus located in the non-display area; A connection line located in the non-display area, the connection line is coupled to the data line, and at least partially overlaps with the power bus in a direction perpendicular to the plane where the display panel is located, and the connection line has a first area, and the first area is an overlapping area between the connection line and the power bus; A control circuit located in the non-display area, the control circuit comprising a plurality of control transistors, a first electrode and / or a second electrode of the control transistor being coupled to the connection wiring; The control transistor comprises a first control transistor and a second control transistor, wherein the first area of ​​the connection wire coupled to the first control transistor is different from the first area of ​​the connection wire coupled to the second control transistor, and the channel areas of the first control transistor and the second control transistor are different; The connecting wire comprises a first sub-connecting wire and a second sub-connecting wire; The control circuit includes a gating circuit, the gating circuit includes a plurality of gating transistors, a first electrode of the gating transistor is coupled to a data signal transmission terminal through a first sub-connection wiring, a second electrode of the gating transistor is coupled to the data line through a second sub-connection wiring, and in a direction perpendicular to the plane where the display panel is located, the first sub-connection wiring overlaps with the power bus; The gating transistor includes a first gating transistor and a second gating transistor, the first area of ​​the first sub-connection wiring coupled to the first gating transistor and the second gating transistor is different, and the channel areas of the first gating transistor and the second gating transistor are different; The display panel further includes a first test circuit, the first test circuit includes a first type of test transistor, the first type of test transistor is coupled to the first sub-connection wiring, the first type of test transistor is also coupled to a test pin, and / or the first type of test transistor is also coupled to a test control switch signal line; The channel area of ​​the first gate transistor is S C11 , the channel area of ​​the second gate transistor is S C12 ; ； Among them, C 11 is the parasitic capacitance of the first sub-connection wiring coupled to the first selection transistor, C 12 is the parasitic capacitance of the first sub-connection wiring coupled to the second selection transistor, W s is the channel width of the first type of test transistor, L s is the channel length of the first type of test transistor, C 2 is the parasitic capacitance of the second sub-connection trace, C Data is the parasitic capacitance of the data line.

2. The display panel according to claim 1, It is characterized in that The channel area of ​​the first control transistor is S C1 , the first area of ​​the connection wiring coupled to the first control transistor is S O1 ; The channel area of ​​the second control transistor is S C2 , the first area of ​​the connection wiring coupled to the second control transistor is S O2 ; S O1 >S O2 ,S C1 <S C2 。 3. The display panel according to claim 1, It is characterized in that The channel length L of the gate transistor D same; The channel width of the first gate transistor is W D1 , the channel width of the second pass transistor is W D2 , 。 4. The display panel according to claim 1, It is characterized in that The channel width W of the gate transistor D same; The channel length of the first gate transistor is L D1 , the channel length of the second gate transistor is L D2 , 。 5. The display panel according to claim 1, It is characterized in that The power bus includes a plurality of hollow areas; In a direction perpendicular to the plane where the display panel is located, at least part of the connecting wires overlap with the hollow area.

6. The display panel according to claim 1, It is characterized in that At least part of the control transistor includes a first sub-transistor and a second sub-transistor, a gate of the first sub-transistor and a gate of the second sub-transistor are coupled to the same control signal line, and a first electrode of the first sub-transistor is coupled to a second electrode of the second sub-transistor.

7. A display panel, It is characterized in that include: a display area and a non-display area surrounding the display area; a plurality of data lines located in the display area; A power bus located in the non-display area; A connection line located in the non-display area, the connection line is coupled to the data line, and at least partially overlaps with the power bus in a direction perpendicular to the plane where the display panel is located, and the connection line has a first area, and the first area is an overlapping area between the connection line and the power bus; A control circuit located in the non-display area, the control circuit comprising a plurality of control transistors, a first electrode and / or a second electrode of the control transistor being coupled to the connection wiring; The control transistor comprises a first control transistor and a second control transistor, wherein the first area of ​​the connection wire coupled to the first control transistor is different from the first area of ​​the connection wire coupled to the second control transistor, and the channel areas of the first control transistor and the second control transistor are different; The connecting wire comprises a first sub-connecting wire and a second sub-connecting wire; The control circuit includes a gating circuit, the gating circuit includes a plurality of gating transistors, a first electrode of the gating transistor is coupled to a data signal transmission terminal through a first sub-connection wiring, a second electrode of the gating transistor is coupled to the data line through a second sub-connection wiring, and in a direction perpendicular to the plane where the display panel is located, the first sub-connection wiring overlaps with the power bus; The gating transistor includes a first gating transistor and a second gating transistor, the first area of ​​the first sub-connection wiring coupled to the first gating transistor and the second gating transistor is different, and the channel areas of the first gating transistor and the second gating transistor are different; The display panel further includes a first test circuit, the first test circuit includes a first type of test transistor, the first type of test transistor is coupled to the first sub-connection wiring, the first type of test transistor is also coupled to a test pin, and / or the first type of test transistor is also coupled to a test control switch signal line; The display panel includes a first wiring group and a second wiring group, wherein the first wiring group and the second wiring group respectively include a plurality of first sub-connection wirings; The first gating transistor is the gating transistor coupled to the first sub-connecting wiring in the first wiring group, and the second gating transistor is the gating transistor coupled to the first sub-connecting wiring in the second wiring group; The channel area of ​​the first gate transistor is S C11 ', the channel area of ​​the second gate transistor is S C12 ', ； Among them, C 11 ' is the average value of the parasitic capacitance of the first sub-connection wirings in the first wiring group, C 12 ' is the average value of the parasitic capacitances of the plurality of first sub-connection wirings in the second wiring group, W s is the channel width of the first type of test transistor, L s is the channel length of the first type of test transistor, C 2 is the parasitic capacitance of the second sub-connection trace, C Data is the parasitic capacitance of the data line.

8. The display panel according to claim 7, It is characterized in that The channel area of ​​the first control transistor is S C1 , the first area of ​​the connection wiring coupled to the first control transistor is S O1 ; The channel area of ​​the second control transistor is S C2 , the first area of ​​the connection wiring coupled to the second control transistor is S O2 ; S O1 >S O2 ,S C1 <S C2 。 9. The display panel according to claim 7, It is characterized in that The power bus includes a plurality of hollow areas; In a direction perpendicular to the plane where the display panel is located, the first sub-connecting routing line in the first routing line group at least partially overlaps with the hollow area, and the first sub-connecting routing line in the second routing line group does not overlap with the hollow area.

10. The display panel according to claim 7, It is characterized in that The channel length L of the gate transistor D 'same; The channel width of the first gate transistor is W D1 ', the channel width of the second selection transistor is W D2 ', ； Alternatively, the channel width W of the gate transistor D 'same; The channel length of the first gate transistor is L D1 ', the channel length of the second gate transistor is L D2 ', 。 11. The display panel according to claim 7, It is characterized in that The power bus includes a plurality of hollow areas; In a direction perpendicular to the plane where the display panel is located, at least part of the connecting wires overlap with the hollow area.

12. The display panel according to claim 7, It is characterized in that At least part of the control transistor includes a first sub-transistor and a second sub-transistor, a gate of the first sub-transistor and a gate of the second sub-transistor are coupled to the same control signal line, and a first electrode of the first sub-transistor is coupled to a second electrode of the second sub-transistor.

13. A display panel, It is characterized in that include: a display area and a non-display area surrounding the display area; a plurality of data lines located in the display area; A power bus located in the non-display area; A connection line located in the non-display area, the connection line is coupled to the data line, and at least partially overlaps with the power bus in a direction perpendicular to the plane where the display panel is located, and the connection line has a first area, and the first area is an overlapping area between the connection line and the power bus; A control circuit located in the non-display area, the control circuit comprising a plurality of control transistors, a first electrode and / or a second electrode of the control transistor being coupled to the connection wiring; The control transistor comprises a first control transistor and a second control transistor, wherein the first area of ​​the connection wire coupled to the first control transistor is different from the first area of ​​the connection wire coupled to the second control transistor, and the channel areas of the first control transistor and the second control transistor are different; The connecting wire includes a third sub-connecting wire; The control circuit includes a second test circuit, the second test circuit includes a second type of test transistor, a second electrode of the second type of test transistor is coupled to the data line through a third sub-connection line, and the third sub-connection line overlaps the power bus in a direction perpendicular to the plane where the display panel is located; The second type of test transistors includes a first test transistor and a second test transistor, the first area of ​​the third sub-connection wiring coupled to the first test transistor and the second test transistor is different, and the channel areas of the first test transistor and the second test transistor are different; The channel area of ​​the first test transistor is S C21 , the channel area of ​​the second test transistor is S C22 , ； Among them, C 31 is the parasitic capacitance of the third sub-connection wiring coupled to the first test transistor, C 32 is the parasitic capacitance of the third sub-connection wiring coupled to the second test transistor, C Data is the parasitic capacitance of the data line.

14. The display panel according to claim 13, It is characterized in that The channel area of ​​the first control transistor is S C1 , the first area of ​​the connection wiring coupled to the first control transistor is S O1 ; The channel area of ​​the second control transistor is S C2 , the first area of ​​the connection wiring coupled to the second control transistor is S O2 ; S O1 >S O2 ,S C1 <S C2 。 15. The display panel according to claim 13, It is characterized in that The channel length L of the second type of test transistor S same; The channel width of the first test transistor is W s1 , the channel width of the second test transistor is W s2 , .

16. The display panel according to claim 13, It is characterized in that The channel width W of the second type of test transistor S same; The channel length of the first test transistor is L s1 , and the channel length of the second test transistor is L s2 , .

17. The display panel according to claim 13, It is characterized in that The power bus includes a plurality of hollow areas; In a direction perpendicular to the plane where the display panel is located, at least part of the connecting wires overlap with the hollow area.

18. The display panel according to claim 13, It is characterized in that At least part of the control transistor includes a first sub-transistor and a second sub-transistor, a gate of the first sub-transistor and a gate of the second sub-transistor are coupled to the same control signal line, and a first electrode of the first sub-transistor is coupled to a second electrode of the second sub-transistor.

19. A display panel, It is characterized in that include: a display area and a non-display area surrounding the display area; a plurality of data lines located in the display area; A power bus located in the non-display area; A connection line located in the non-display area, the connection line is coupled to the data line, and at least partially overlaps with the power bus in a direction perpendicular to the plane where the display panel is located, and the connection line has a first area, and the first area is an overlapping area between the connection line and the power bus; A control circuit located in the non-display area, the control circuit comprising a plurality of control transistors, a first electrode and / or a second electrode of the control transistor being coupled to the connection wiring; The control transistor comprises a first control transistor and a second control transistor, wherein the first area of ​​the connection wire coupled to the first control transistor is different from the first area of ​​the connection wire coupled to the second control transistor, and the channel areas of the first control transistor and the second control transistor are different; The connecting wire includes a third sub-connecting wire; The control circuit includes a second test circuit, the second test circuit includes a second type of test transistor, a second electrode of the second type of test transistor is coupled to the data line through a third sub-connection line, and the third sub-connection line overlaps the power bus in a direction perpendicular to the plane where the display panel is located; The second type of test transistors includes a first test transistor and a second test transistor, the first area of ​​the third sub-connection wiring coupled to the first test transistor and the second test transistor is different, and the channel areas of the first test transistor and the second test transistor are different; The display panel comprises a third wiring group and a fourth wiring group, and the third wiring group and the fourth wiring group respectively comprise a plurality of the third sub-connection wirings; The first test transistor is the second type test transistor coupled to the third sub-connection wiring in the third wiring group, and the second test transistor is the second type test transistor coupled to the third sub-connection wiring in the fourth wiring group; The channel area of ​​the first test transistor is S C21 ', and the channel area of ​​the second test transistor is S C22 ', ; Among them, C 31 ' is the average value of the parasitic capacitance of the plurality of third sub-connection wirings in the third wiring group, C 32 ' is the average value of the parasitic capacitances of the plurality of third sub-connection wirings in the fourth wiring group, C Data is the parasitic capacitance of the data line.

20. The display panel according to claim 19, It is characterized in that The channel area of ​​the first control transistor is S C1 , the first area of ​​the connection wiring coupled to the first control transistor is S O1 ; The channel area of the second control transistor is S C2 , and the first area of the connection trace coupled to the second control transistor is S O2 ; S O1 >S O2 ,S C1 <S C2 。 21. The display panel according to claim 19, It is characterized in that The power bus includes a hollow area; In a direction perpendicular to the plane where the display panel is located, the third sub-connecting routing line in the third routing line group at least partially overlaps with the hollow area, and the third sub-connecting routing line in the fourth routing line group does not overlap with the hollow area.

22. The display panel according to claim 19, It is characterized in that The channel length L of the second type of test transistor S 'same; The channel width of the first test transistor is W s1 ', the channel width of the second test transistor is W s2 ', ; Alternatively, the channel width W of the second type of test transistor S 'same; The channel length of the first test transistor is L s1 ', the channel length of the second test transistor is L s2 ', .

23. The display panel according to claim 19, It is characterized in that The power bus includes a plurality of hollow areas; In a direction perpendicular to the plane where the display panel is located, at least part of the connecting wires overlap with the hollow area.

24. The display panel according to claim 19, It is characterized in that At least part of the control transistor includes a first sub-transistor and a second sub-transistor, a gate of the first sub-transistor and a gate of the second sub-transistor are coupled to the same control signal line, and a first electrode of the first sub-transistor is coupled to a second electrode of the second sub-transistor.

25. A display device, It is characterized in that Includes the display panel as described in any one of claims 1 to 6, or includes the display panel as described in any one of claims 7 to 12, or includes the display panel as described in any one of claims 13 to 18, or includes the display panel as described in any one of claims 19 to 24.

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