Integrated chip with composite deep trench isolation structure and method of forming the same

Abstract

An integrated chip includes first and second image sensing elements arranged over a substrate. A first microlens is arranged over the first image sensing element, and a second microlens is arranged over the second image sensing element. A compound deep trench isolation structure is arranged between the first and second image sensing elements. The compound deep trench isolation structure includes a lower portion arranged over the substrate and an upper portion arranged over the lower portion. The lower portion includes a first material, and the upper portion includes a second material having a lower reflectivity than the first material.

Description

Technical Field

[0001] This invention relates to an integrated chip with a composite deep trench isolation structure and a method for forming the same. Background Technology

[0002] Many modern electronic devices (e.g., digital cameras and camcorders) contain image sensors to convert optical images into digital data. To achieve this, image sensors comprise an array of pixel regions. Each pixel region contains a photodiode configured to capture optical signals (e.g., light) and convert them into digital data (e.g., a digital image). Complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) are often used in charge-coupled device (CCD) image sensors because CMOS image sensors offer many advantages, such as low power consumption, fast data processing, and low manufacturing cost. Summary of the Invention

[0003] This invention provides an integrated chip, comprising: a first image sensing element disposed on a substrate; a first microlens disposed on the first image sensing element; a second image sensing element disposed on the substrate; a second microlens disposed on the second image sensing element; and a composite deep trench isolation structure disposed between the first image sensing element and the second image sensing element. The composite deep trench isolation structure includes: a lower portion disposed on the substrate and comprising a first material, and an upper portion disposed on the lower portion and comprising a second material having a lower reflectivity than the first material.

[0004] This invention provides an integrated chip, comprising: a plurality of image sensing elements disposed on a substrate; a processing circuit system coupled to the plurality of image sensing elements; microlenses disposed on the plurality of image sensing elements; and a composite deep trench isolation structure disposed on the substrate, separating the plurality of image sensing elements from each other. The composite deep trench isolation structure includes: a lower portion comprising a first material having a first reflectivity, and an upper portion comprising a second material having a second reflectivity less than the first reflectivity, wherein the bottom surface of the upper portion of the composite deep trench isolation structure is disposed below the top surface of the plurality of image sensing elements.

[0005] This invention provides a method comprising: forming an image sensing element on a substrate by forming trenches within an image sensing material; forming a barrier layer on the outer sidewall and upper surface of the image sensing element; forming a first material on the substrate to fill the trenches between the image sensing elements; removing an upper portion of the first material to form a lower portion of a composite deep trench isolation structure between the image sensing elements; removing a portion of the barrier layer disposed on the upper surface of the image sensing element; forming a second material on the lower portion of the composite deep trench isolation structure to fill the trenches and form an upper portion of the composite deep trench isolation structure containing the second material; and forming a microlens on the image sensing element. Attached Figure Description

[0006] The best understanding of all aspects of this disclosure will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 The diagram shows a cross-sectional view of some embodiments of a CMOS image sensor, which includes a plurality of pixel regions, wherein each pixel region is spaced apart by a composite deep trench isolation structure.

[0008] Figure 2 A top view showing some embodiments of a CMOS image sensor, the CMOS image sensor including a plurality of pixel regions spaced apart from each other by a composite deep trench isolation structure.

[0009] Figure 3A The diagram shows a cross-sectional view of some embodiments of a backside illumination (BSI) image sensor, which includes a plurality of pixel regions arranged on an interconnect structure, wherein each pixel region is spaced apart by a composite deep trench isolation structure.

[0010] Figure 3B The diagram shows a cross-sectional view of some embodiments of a frontside illumination (FSI) image sensor, which includes a plurality of pixel regions disposed on a substrate, wherein interconnecting structures are disposed on an image sensing element.

[0011] Figure 4 Cross-sectional views of some embodiments of a BSI image sensor including a composite deep trench isolation structure and exemplary optical paths leading into the pixel region in parallel are shown.

[0012] Figure 5The diagrams shown illustrate how the thickness of the upper and lower portions of the composite deep trench isolation structure affects the light intensity entering the pixel area of ​​the BSI image sensor and the light crosstalk entering adjacent pixel areas.

[0013] Figures 6 to 15 Some embodiments of a method for forming a BSI image sensor having a composite deep trench isolation structure disposed between pixel regions are shown, wherein the composite deep trench isolation structure includes a dielectric portion disposed over a metal portion.

[0014] Figure 16 Show Figures 6 to 15 The flowcharts show some embodiments of the method illustrated. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity and is not, in itself, intended to indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative terms used herein may be interpreted accordingly.

[0017] A complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) may include multiple pixel regions disposed on or within a substrate. Each pixel region includes an image sensing element (e.g., a photodiode) configured to receive incident light comprising photons. Once light is received, the image sensing element is configured to convert the light into an electrical signal, which is processed by a circuit system to determine an image captured by the CIS. In a back-illuminated (BSI) CIS, the image sensing element is disposed above an interconnect structure such that incident light travels through the image sensing element, is converted into an electrical signal, and enters and travels through the interconnect structure. In a front-illuminated (FSI) CIS, the image sensing element is disposed below the interconnect structure. The interconnect structure may be coupled to various devices (e.g., transistors, processing circuitry, capacitors, etc.) to process the electrical signal.

[0018] Pixel regions can be separated from each other using deep trench isolation structures to improve the quantum efficiency (QE) of a visual image sensor (CIS). Quantum efficiency (QE) is the ratio of the number of photons contributing to the electrical signal generated by the image sensing element within a pixel region to the number of photons incident on the pixel region. Typically, deep trench isolation structures contain dielectric materials with low reflectivity, preventing incident light from being reflected away from the image sensing element, or even away from it. However, in the case of deep trench isolation structures containing dielectrics and low-reflectivity materials, crosstalk may occur between pixel regions. When crosstalk increases due to light escaping from the image sensing element through the deep trench isolation structure, the number of photons contributing to the electrical signal decreases, thereby reducing the QE of the pixel region.

[0019] Various embodiments of this disclosure relate to a CMOS image sensor including a composite deep trench isolation structure comprising an upper portion disposed above a lower portion, wherein the upper portion comprises a lower reflective material compared to the lower portion. In some embodiments, the upper portion comprises a dielectric material, and the lower portion comprises a metal. Because the upper portion comprises a dielectric material with low reflectivity, incident light is not immediately reflected away from the pixel area. Because the lower portion comprises a metal with high reflectivity, traveling light is reflected from the lower portion and directed toward the interconnect structure, rather than escaping from the pixel area to another pixel area, and therefore, the lower portion reduces crosstalk. Since the upper and lower portions of the composite deep trench isolation structure help guide light toward the processing circuitry system and prevent light from escaping from the image sensing element, the QE and reliability of the CMOS image sensor are improved.

[0020] Figure 1A cross-sectional view 100 is shown of some embodiments of an integrated chip including a CMOS image sensor, in which a composite deep trench isolation structure is arranged between the image sensing elements of the image sensor.

[0021] In some embodiments, Figure 1 The illustrated image sensor includes a plurality of pixel regions 101 disposed on a substrate 102. In some embodiments, each pixel region 101 includes a microlens 116 disposed on each image sensing element 106. In some embodiments, the image sensing element 106 is configured to convert incident radiation (e.g., photons) entering through the microlens 116 into electrical signals (i.e., generating electron-hole pairs from the incident radiation). In some embodiments, the image sensing element 106 may include a photodiode, a phototransistor, etc.

[0022] In some embodiments, a passivation layer 108 is disposed on the outer sidewall of the image sensing element 106. In some embodiments, a barrier layer 109 is disposed on the passivation layer 108. In some embodiments, the passivation layer 108 comprises, for example, tantalum oxide, titanium oxide, etc. In some embodiments, the barrier layer 109 is a diffusion barrier layer to prevent metal from diffusing into the image sensing element 106. In some such embodiments, the barrier layer 109 may comprise, for example, titanium nitride, tantalum nitride, or some other diffusion barrier material.

[0023] In some embodiments, a composite deep trench isolation structure 110 is disposed between image sensing elements 106. In some embodiments, the composite deep trench isolation structure 110 includes a lower portion 112 and an upper portion 114 disposed above the lower portion 112. In some embodiments, the lower portion 112 of the composite deep trench isolation structure 110 comprises a first material, and the upper portion 114 of the composite deep trench isolation structure 110 comprises a second material having a lower reflectivity than the first material.

[0024] For example, in some embodiments, the first material of the lower portion 112 includes a metal with high reflectivity, such as (for example) copper, aluminum, tantalum, titanium, tungsten, etc. The reflectance of the material (a measure of reflectivity) may depend on the wavelength of the incident light. Reflectance is a measure of the amount of light reflected from the material relative to the amount of light incident on the material. In some embodiments, the lower portion 112 of the composite deep trench isolation structure 110 comprises aluminum or aluminum-copper because aluminum and aluminum-copper have high reflectance and small reflectance values ​​that change with the wavelength of the incident light. In some embodiments, the second material of the upper portion 114 of the composite deep trench isolation structure 110 includes, for example, oxides (e.g., silicon dioxide), nitrides (e.g., silicon nitride), or some other suitable dielectric material having a lower reflectance than the first material of the composite deep trench isolation structure 110. Since the reflectance of a material can depend on the wavelength of the incident light, at a given wavelength of incident light, the second material of the upper portion 114 of the composite deep trench isolation structure 110 has a lower reflectance than the first material of the lower portion 112 of the composite deep trench isolation structure. In some embodiments, the ratio of the reflectance of the first material of the lower portion 112 to the reflectance of the second material of the upper portion 114 is in the range, for example, approximately 2 to approximately 9.

[0025] In some embodiments, an upper isolation layer 115 is disposed directly over the image sensing element 106 and the composite deep trench isolation structure 110. In some embodiments, the upper isolation layer 115 also comprises a second material and is continuously connected to the upper portion 114 of the composite deep trench isolation structure 110. In some embodiments, a microlens isolation structure 118 is disposed between microlenses 116 to help guide incident light toward the image sensing element 106. In some embodiments, a color filter 120 is disposed between the microlenses 116 and the upper isolation layer 115, such that each pixel region 101 analyzes a specific color from the incident light.

[0026] In some embodiments, the upper portion 114 and upper isolation layer 115 of the composite deep trench isolation structure 110 comprise a second material with low reflectivity, such that incident light is not immediately reflected from the upper isolation layer 115 and upper portion 114 and travels away from the pixel region 101. Therefore, the second material of the upper portion 114 and upper isolation layer 115 increases the percentage of incident light entering the image sensing element 106 of the pixel region 101. In some embodiments, the lower portion 112 of the composite deep trench isolation structure 110 comprises a second material with a higher reflectivity than the first material to prevent light from traveling into other image sensing elements 106. Therefore, by increasing the intensity of incident light received by the image sensing elements 106 and by preventing crosstalk between the image sensing elements 106, the composite deep trench isolation structure 110 increases the quantum efficiency of the pixel region 101 of the CMOS image sensor.

[0027] Figure 2 A top view 200 showing some embodiments of a CMOS image sensor, the CMOS image sensor including an array of pixel regions spaced apart from each other by a composite deep trench isolation structure.

[0028] In some embodiments, Figure 2 The top view 200 shown corresponds to Figure 1 The section line AA' of the sectional view 100 shown. Therefore, Figure 2 The top view 200 shown illustrates the composite deep trench isolation structure. Figure 1 The lower portion 112 of (shown as 110) and not showing a composite deep trench isolation structure ( Figure 1 The upper part of (shown 110) Figure 1 (See Figure 114). In some embodiments, the image sensing element 106 has a square outline when viewed from top view 200. In some other embodiments, the image sensing element 106 may have a circular, rectangular, or other shaped outline when viewed from top view 200. In some embodiments, a passivation layer 108 continuously surrounds the outer sidewall of each image sensing element 106. Similarly, in some embodiments, a barrier layer 109 continuously surrounds the outer sidewall of the passivation layer 108.

[0029] Furthermore, in some embodiments, composite deep trench isolation structures ( Figure 1 As shown in Figure 110 (corresponding to the lower portion 112), the structure continuously surrounds and is continuously connected around the image sensing element 106. Therefore, from the top view 200, the image sensing element 106, the passivation layer 108, and the barrier layer 109 are embedded in the same composite deep trench isolation structure. Figure 1 As shown in Figure 110), due to the composite deep trench isolation structure ( Figure 1As shown in Figure 110), the pixel regions 101 are continuously arranged around the image sensing element 106, so that the pixel regions 101 can be arranged in an array while still maintaining optical and electrical isolation from each other, thereby increasing the quantum efficiency of the CMOS image sensor.

[0030] Figure 3A A cross-sectional view 300A is shown, illustrating some embodiments of a back-illuminated (BSI) CMOS image sensor, the BSI CMOS image sensor including a composite deep trench isolation structure disposed on and coupled to the interconnect structure.

[0031] In some embodiments, the BSI image sensor includes an interconnect structure 302 disposed between a substrate 102 and an image sensing element 106. In some embodiments, the interconnect structure 302 includes a network of interconnect wirings 306 and interconnect vias 304 disposed within an interconnect dielectric structure 308. In some embodiments, the interconnect wirings 306 and interconnect vias 304 are coupled to a transistor gate structure 310. In some embodiments, the transistor gate structure 310 includes a gate spacer structure 314 surrounding a gate electrode 312. In some embodiments, the transistor gate structure 310 extends through a lower isolation structure 316. In some embodiments, each image sensing element 106 is disposed on one of the transistor gate structures 310, and incident light entering the image sensing element 106 through a microlens 116 can be converted into an electrical signal, which exits the image sensing element 106 through the transistor gate structure 310. The electrical signal can travel through the interconnect wirings 306 and interconnect vias 304 to other devices for processing the electrical signal. Therefore, in some embodiments, devices (e.g., transistors, capacitors, memory storage devices, etc.) may be arranged on or within substrate 102. In some other embodiments, substrate 102 may be integrated with another integrated chip such that devices (e.g., transistors, capacitors, memory storage devices, etc.) are arranged below substrate 102. The interconnect structure 302, together with other devices coupled to image sensing element 106, constitutes a processing circuitry system configured to analyze images received by the CMOS image sensor.

[0032] In some embodiments, the lower portion 112 of the composite deep trench isolation structure 110 has a first thickness t1 measured between the bottommost and topmost surfaces of the lower portion 112. In some embodiments, the upper portion 114 of the composite deep trench isolation structure 110 has a second thickness t2 measured between the bottommost surface of the upper portion 114 and the topmost surface of the image sensing element 106. In some embodiments, the first thickness t1 is greater than or equal to the second thickness t2. Therefore, in some embodiments, the ratio of the first thickness t1 to the sum of the first thickness t1 and the second thickness t2 is in the range of about 50% to about 100% to optimize the quantum efficiency of the BSI image sensor. In some embodiments, the second thickness t2 is greater than zero, such that the upper portion 114 of the composite deep trench isolation structure 110 has a bottommost surface located below the topmost surface of the image sensing element 106.

[0033] Figure 3B A cross-sectional view 300B shows some embodiments of a front-illuminated (FSI) image sensor including a composite deep trench isolation structure.

[0034] In some embodiments, the interconnect structure 302 is disposed between the image sensing element 106 and the microlens 116. In some embodiments, a transistor gate structure 310 may be disposed above the image sensing element 106 and extend through the upper isolation layer 115 to contact the image sensing element 106. In some such embodiments, incident light must travel through the interconnect dielectric structure 308 of the interconnect structure 302 before entering the image sensing element 106. Light traveling through the interconnect structure 302 may be scattered and / or reflected from the internal via 304 and the internal wiring 306 and return to exit the microlens 116 before reaching the image sensing element 106. Therefore, in some embodiments, Figure 3A The BSI image sensor shown has a higher performance than... Figure 3B The FSI image sensor shown exhibits high quantum efficiency. However, in some embodiments, once the incident light reaches... Figure 3B The composite deep trench isolation structure 110 in the image sensing element 106 of the FSI image sensor shown helps to retain light within the image sensing element 106 and prevent crosstalk between pixel areas 101, thereby increasing the quantum efficiency of the FSI image sensor.

[0035] Figure 4 A cross-sectional view 400 is shown of some embodiments of a BSI image sensor including a composite deep trench isolation structure, and cross-sectional view 400 shows some exemplary optical paths of the image sensing element traveling through the pixel area.

[0036] In some embodiments, the barrier layer 109 includes an upper portion 109u disposed directly between the upper portion 114 and the lower portion 112 of the composite deep trench isolation structure 110. In this embodiment, the lower portion 112 of the composite deep trench isolation structure 110 is completely surrounded by the barrier layer 109, thereby mitigating the diffusion of metallic material from the lower portion 112 towards the image sensing element 106 and / or the upper portion 114 of the composite deep trench isolation structure.

[0037] In some embodiments, Figure 4 The exemplary optical path 402 illustrates how incident light can enter pixel region 101 via microlens 116, which helps focus the incident light toward image sensing element 106. In some embodiments, incident light may be filtered based on wavelength through color filter 120 before entering image sensing element 106, allowing pixel region 101 to collect data for a specific color. In some embodiments, because upper isolation layer 115 comprises a first material with low reflectivity, light travels through upper isolation layer 115 as shown using exemplary optical path 402, and very little light is reflected from upper isolation layer 115 and leaves pixel region 101. Similarly, in some embodiments, light guided at the upper portion 114 of composite deep trench isolation structure 110 travels through upper portion 114, and very little light is reflected from upper portion 114 and leaves pixel region 101. Furthermore, light may be refracted in the upper portion 114 of composite deep trench isolation structure 110 and guided toward image sensing element 106. Therefore, in some embodiments, the microlens 116, the upper isolation layer 115, and the upper portion 114 of the composite deep trench isolation structure 110 help guide incident light into the image sensing element 106, thereby reducing the escape of incident light from the pixel area 101.

[0038] Furthermore, as light continues to travel toward the interconnect structure 302, the exemplary optical path 402 illustrates how light is reflected from the lower portion 112 of the composite deep trench isolation structure 110 (because the lower portion 112 contains a second material with high reflectivity). Therefore, the lower portion 112 of the composite deep trench isolation structure 110 retains light within the image sensing element 106 and prevents optical crosstalk between pixel regions 101. Reducing crosstalk and increasing the amount of light traveling through pixel regions 101 increases the ratio of the number of photons to the electrical signal generated by the light (i.e., photons), and thus, quantum efficiency is increased.

[0039] Figure 5 A graph 500 is shown for some embodiments, illustrating how the ratio of the first thickness t1 of the composite deep trench isolation structure to the sum of the first thickness t1 and the second thickness t2 affects the light intensity entering the pixel area of ​​the BSI image sensor and the light crosstalk entering adjacent pixel areas.

[0040] Curve 500 includes light intensity relative to the composite deep trench isolation structure ( Figure 4 The lower part of (shown 110) Figure 4 The ratio of the thickness t1 of the composite deep trench isolation structure (as shown in Figure 112) to the sum of t1 and t2, where t2 is the thickness of the composite deep trench isolation structure (as shown in Figure 112). Figure 4 The upper part of (shown 110) Figure 4 The thickness of the composite deep trench isolation structure (as shown in Figure 114) increases. Therefore, as the ratio of t1 to the sum of t1 and t2 increases, the thickness of the composite deep trench isolation structure (as shown in Figure 114) also increases. Figure 4 The lower part of (shown 110) Figure 4 The first thickness t1 of (as shown in 112) increases. It is assumed that the sum of t1 and t2 in graph 500 is constant. Furthermore, in some embodiments, intensity represents the percentage of light received in a particular element relative to the incident light on the image sensor.

[0041] In some embodiments, as shown in Figure 506, the image sensor is inserted into the desired image sensing element ( Figure 4 The amount of light (shown as 106) is indicated by the first line 502 and enters the adjacent image sensing element (through crosstalk). Figure 4 The amount of light in (shown as 106) is indicated by the second line 504. To optimize the quantum efficiency of the image sensor, the optimal ratio of t1 to the sum of t1 and t2 will have a high light intensity of the first line 502 and a low light intensity of the second line 504. In some embodiments, the optimal ratio of t1 to the sum of t1 and t2 is in the range of about 25% to about 100%. In some other embodiments, the optimal ratio of t1 to the sum of t1 and t2 is in the range of about 50% to about 100%. In some embodiments, the first line 502 increases at a certain point and then decreases because the incident light from the composite deep trench isolation structure ( Figure 4 The lower part of (shown 110) Figure 4 The surface of 112 (as shown) reflects and leaves the image sensing element ( Figure 4 (As shown in 106). Therefore, in some embodiments, the ratio of t1 to the sum of t1 and t2 is less than 100% to increase the input to the desired image sensing element (as shown in 106). Figure 4 The intensity of light (as shown in Figure 106). In other words, the composite deep trench isolation structure ( Figure 4 The upper part of (shown 110) Figure 4 The second thickness (as shown in Figure 114) Figure 4 As shown, t2) is greater than zero.

[0042] It should be understood that the relationship between the ratio and light intensity in graph 500 will vary between image sensors depending on the material and size of different components in the image sensor and the wavelength and angle of the incident light on the image sensor.

[0043] Figures 6 to 15 Cross-sectional views 600 to 1500 illustrate some embodiments of a method for forming an integrated chip, wherein the integrated chip includes a composite deep trench isolation structure between image sensing elements to increase the quantum efficiency of the entire CMOS image sensor. It should be understood that... Figures 6 to 15 The steps shown are illustrated for a BSI image sensor, but can be adapted to, for example, a BSI image sensor. Figure 3B The composite deep trench isolation structure in the FSI image sensor shown is modified. Furthermore, although a method is described with reference to... Figures 6 to 15 However, it should be understood that Figures 6 to 15 The structure disclosed herein is not limited to this method, but can exist independently of the method.

[0044] like Figure 6 As shown in the cross-sectional view 600, in some embodiments, interconnect structures 302 are formed on a bulk substrate 602. In some embodiments, the bulk substrate 602 comprises a semiconductor material, such as silicon or germanium (for example). In some embodiments, the bulk substrate 602 may comprise, for example, a silicon-on-insulator substrate, and therefore may comprise multiple layers including a base substrate, an insulating layer, and an active layer. In some embodiments, the bulk substrate 602 is doped and / or includes doped regions via an implantation process. In some embodiments, the bulk substrate 602 has a first height h1 in the range of, for example, approximately 1 micrometer to approximately 2 micrometers.

[0045] In some embodiments, a transistor gate structure 310 may be formed on a first side of a bulk substrate 602. In some embodiments, the transistor gate structure 310 includes a gate electrode 312 and a gate spacer structure 314 surrounding the gate electrode 312. In some embodiments, the transistor gate structure 310 may correspond to a transfer transistor, a source follower transistor, a row select transistor, and / or a reset transistor. In some embodiments, the transistor gate structure 310 is formed by depositing a gate electrode film (e.g., a conductive metal, semiconductor, etc.) on the bulk substrate 602. The gate electrode film is then patterned using photolithography and removal processes to form a plurality of gate electrodes 312. In some embodiments, the gate spacer structure 314 is formed by depositing a spacer layer (e.g., a nitride, oxide, etc.) on the bulk substrate 602 and then selectively etching the spacer layer. In some embodiments, a lower isolation structure 316 is then formed on the transistor gate structure 310 by a deposition process (e.g., physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc.) and a removal process (e.g., etching, planarization, etc.).

[0046] In some embodiments, an interconnect structure 302 may then be formed on the transistor gate structure 310. In some embodiments, the interconnect structure 302 includes an interconnect dielectric structure 308, which includes a plurality of dielectric layers comprising, for example, nitrides (e.g., silicon nitride, silicon oxynitride), carbides (e.g., silicon carbide), oxides (e.g., silicon oxide), borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), low-dielectric-constant (low-k) oxides (e.g., carbon-doped oxides, SiCOH), etc. In some embodiments, a network of interconnecting vias 304 and interconnecting wiring 306 is formed within the interconnecting dielectric structure 308 through various steps of deposition processes (e.g., PVD, CVD, ALD, sputtering, etc.), removal processes (e.g., wet etching, dry etching, chemical mechanical planarization (CMP), etc.), and / or patterning processes (e.g., photolithography / etching). In some embodiments, the interconnecting vias 304 and interconnecting wiring 306 comprise, for example, tantalum, titanium, aluminum, copper, tungsten, or some other suitable conductive material.

[0047] In some embodiments, the interconnect structure 302 may then be bonded to the substrate 102. In some embodiments, the substrate 102 comprises a semiconductor material, such as silicon. In some embodiments, the substrate 102 may include various semiconductor devices, interconnect structures, and / or other processing circuitry systems coupled to the interconnect structure 302.

[0048] like Figure 7 As shown in the cross-sectional view 700, in some embodiments, the substrate 102 is flipped so that the bulk substrate ( Figure 6 Patterning is performed on the second side of the bulk substrate (602). In some embodiments, the pattern is performed on the bulk substrate (602). Figure 6 Trench 702 is formed in (shown 602) to form image sensing element 106 on substrate 102. In some embodiments, it may be arranged on a bulk substrate (shown 602) Figure 6Trench 702 is formed by openings in a mask structure (not shown) above a substrate (602). In some embodiments, the mask structure is formed by various steps of deposition processes (e.g., PVD, CVD, ALD, sputtering, etc.), removal processes (e.g., wet etching, dry etching, CMP, etc.), and / or patterning processes (e.g., photolithography / etching). In some embodiments, either a wet etching process or a dry etching process can be used to form trench 702 according to the mask structure. Trench 702 extends completely through a bulk substrate ( Figure 6 As shown in 602), the image sensing elements 106 are completely spaced apart from each other.

[0049] In some embodiments, each image sensing element 106 is disposed on one of the transistor gate structures 310. In some embodiments, the image sensing element 106 is doped to form a photodiode. For example, the photodiode can be formed by selectively performing a first implantation process (e.g., according to a mask layer) to form a first region having a first doping type (e.g., n-type); and subsequently performing a second implantation process to form a second region adjacent to the first region and having a second doping type (e.g., p-type) different from the first doping type. In some embodiments, either the first implantation process or the second implantation process can also be used to form a floating diffusion well (not shown). In some other embodiments, for example, it can be formed as follows: Figure 7 The formation of trench 702, as described above, precedes the implementation of a doping / implantation process for forming the photodiode of the image sensing element 106. However, in some embodiments, a bulk substrate ( Figure 6 As shown in 602), it includes image sensing material for image sensing element 106.

[0050] In some embodiments, the image sensing element 106 has a first width w1, and the trenches 702 that space the image sensing elements 106 apart have a second width w2. In some embodiments, the first width w1 is in the range of, for example, approximately 0.1 micrometers to approximately 0.2 micrometers. In some embodiments, the second width w2 is in the range of, for example, approximately 0.5 micrometers to approximately 1 micrometer.

[0051] like Figure 8As shown in the cross-sectional view 800, in some embodiments, a passivation layer 108 is formed over the image sensing element 106 and the lower isolation structure 316. In some embodiments, the passivation layer 108 comprises, for example, tantalum nitride, titanium nitride, etc. In some embodiments, the passivation layer 108 is used to protect the image sensing element 106 from damage during future processing steps. In some embodiments, the passivation layer 108 is formed by a deposition process (e.g., PVD, CVD, ALD, sputtering, etc.). The passivation layer 108 does not completely fill the trench 702. Therefore, the passivation layer 108 has a thickness less than half the second width w2 of the trench 702.

[0052] like Figure 9 As shown in the cross-sectional view 900, in some embodiments, a barrier layer 109 is formed over the passivation layer 108. In some embodiments, the barrier layer 109 comprises, for example, titanium nitride, tantalum nitride, or some other diffusion-blocking material. In some embodiments, the barrier layer 109 is used to prevent metal from diffusing from the metal material to be formed on the substrate 102 into the image sensing element 106. In some embodiments, the barrier layer 109 is formed by a deposition process (e.g., PVD, CVD, ALD, sputtering, etc.). The barrier layer 109 and the passivation layer 108 do not completely fill the trench 702. Therefore, the sum of the thickness of the passivation layer 108 and the thickness of the barrier layer 109 is less than half the second width w2 of the trench 702. After depositing the passivation layer 108 and the barrier layer 109, the trench 702 has a third width w3 that is less than the second width w2.

[0053] like Figure 10 As shown in the cross-sectional view 1000, a first material 1002 is formed on the image sensing element 106 to completely fill the trench. Figure 9 (See Figure 702). In some embodiments, the first material 1002 is formed by a deposition process (e.g., PVD, CVD, ALD, sputtering, etc.). In some embodiments, the first material 1002 comprises a material having high reflectivity when incident light of different wavelengths is applied to the first material 1002. For example, in some embodiments, the first material 1002 may include copper, aluminum, aluminum-copper, tantalum, titanium, tungsten, titanium nitride, or some other suitable reflective material. In some embodiments, the portion of the first material 1002 directly disposed between the image sensing elements 106 has a width equal to the third width w3.

[0054] like Figure 11 As shown in the cross-sectional view 1100, a removal process is performed to remove the first material ( Figure 10 The upper portion of (shown as 1002) forms the lower portion 112 of the composite deep trench isolation structure 110 arranged between the image sensing elements 106, thereby forming the lower portion 112 of the image sensing element 106. In some embodiments, Figure 11The removal processes shown include, for example, wet etching, dry etching, and / or metal plating removal processes. In some embodiments, Figure 11 The removal process shown is time-controlled and is controlled to remove sufficient first material. Figure 10 As shown in Figure 1002), the lower portion 112 has a desired first thickness t1. In some embodiments, the first thickness t1 is between about 50% and about 100% of the first height h1. In some embodiments, the first thickness t1 is less than the first height h1, such that the topmost surface 112t of the lower portion 112 is located below the topmost surface 106t of the image sensing element 106. In some embodiments, the segment of the lower portion 112 of the composite deep trench isolation structure disposed between the image sensing elements 106 has a width equal to a third width w3. Figure 11 After the removal process shown, the upper part of the trench 702 is opened in the direction above the lower part 112 of the composite deep trench isolation structure.

[0055] like Figure 12A As shown in the cross-sectional view 1200A, in some embodiments, after forming the lower portion 112 of the composite deep trench isolation structure, the method continues to form an additional barrier layer 1202 on the lower portion 112 of the composite deep trench isolation structure. In some embodiments, the additional barrier layer 1202 comprises the same material as the barrier layer 109. In some embodiments, the additional barrier layer 1202 is formed by a deposition process (e.g., PVD, CVD, ALD, sputtering, etc.). In some embodiments, the additional barrier layer 1202 is selectively formed on the lower portion 112 of the composite deep trench isolation structure, and therefore the additional barrier layer 1202 is not formed directly on the barrier layer 109. Thus, in some embodiments, the trench 702 disposed on the lower portion 112 of the composite deep trench isolation structure has a fourth width w4 approximately equal to the third width w3.

[0056] In some embodiments, due to the barrier layer 109 and the additional barrier layer 1202, all surfaces of the lower portion 112 of the composite deep trench isolation structure are covered by a metal diffusion barrier material, so that the metal material of the lower portion 112 does not diffuse into the image sensing element 106.

[0057] Figure 12B A cross-sectional view 1200B is shown of some alternative embodiments in which an additional barrier layer 1202 is formed on the lower portion 112 of the composite deep trench isolation structure.

[0058] like Figure 12BAs shown in the cross-sectional view 1200B, in some embodiments, an additional barrier layer 1202 is not selectively formed over the lower portion 112 of the composite deep trench isolation structure. Alternatively, in some embodiments, an additional barrier layer 1202 is formed over both the barrier layer 109 and the lower portion 112 of the composite deep trench isolation structure. In some such embodiments, the trench 702 disposed over the lower portion 112 has a fourth width w4 that is less than the third width w3. Therefore, in some embodiments, the composite deep trench isolation structure will... Figure 12B The upper portion formed within the trench 702 shown will be narrower than the lower portion 112 of the composite deep trench isolation structure.

[0059] In some other embodiments, omitting Figure 12A and 12B The formation of the additional barrier layer 1202 is shown. By omitting the additional barrier layer 1202, time and materials can be saved during manufacturing. However, by including the additional barrier layer 1202, metal diffusion from the lower portion 112 is mitigated. Therefore, in some embodiments, the method can be used to reduce metal diffusion from the lower portion 112. Figure 11 Progressing to Figure 12A And then proceed to Figure 13 ;from Figure 11 Progressing to Figure 12B And then proceed to Figure 13 Or from Figure 11 Progressing to Figure 13 This eliminates the need for the formation of the additional barrier layer 1202.

[0060] Figure 13 The sectional view shown is from 1300. Figure 12A The steps shown in the sectional view 1200A begin. As... Figure 13 As shown in the cross-sectional view 1300, in some embodiments, a removal process is performed to remove the barrier layer 109 and the passivation layer 108 from the top surface 106t of the image sensing element 106. In some embodiments, Figure 13 The removal process shown includes a planarization process (e.g., CMP) such that the top surface of the passivation layer 108 and the top surface of the barrier layer 109 are substantially coplanar with the top surface 106t of the image sensing element 106.

[0061] like Figure 14 As shown in the cross-sectional view 1400, in some embodiments, a second material is formed over the lower portion 112 and the image sensing element 106 to fill the trench. Figure 13The remaining portion of (shown in 702) forms the upper portion 114 of the composite deep trench isolation structure 110. In some embodiments, the second material is formed by a planarization process (e.g., CMP) following a deposition process (e.g., PVD, CVD, ALD, etc.). The portion of the second material disposed above the image sensing element 106 forms an upper isolation layer 115. In some embodiments, the upper isolation layer 115 has a thickness in the range of approximately 0.1 micrometers to approximately 1 micrometer. In some embodiments, the second material includes a dielectric material, such as (for example) a nitride (e.g., silicon nitride), an oxide (e.g., silicon dioxide), etc. Furthermore, in some embodiments, the second material of the upper portion 114 has a lower reflectivity than the first material of the lower portion 112 of the composite deep trench isolation structure 110.

[0062] In some embodiments, the upper portion 114 of the composite deep trench isolation structure 110 has a fourth width w4 that is less than or equal to the third width w3 of the lower portion 112 of the composite deep trench isolation structure 110. In some embodiments, the upper portion 114 has a second thickness t2 measured between the bottom surface of the upper portion 114 and the top surface 106t of the image sensing element 106. In some embodiments, the sum of the second thickness t2 and the first thickness t1 is approximately equal to the first height h1 of the image sensing element.

[0063] like Figure 15 As shown in the cross-sectional view 1500, a color filter 120 is formed over the upper isolation layer 115. In some embodiments, the color filter 120 may be formed between and after the formation of the microlens isolation structure 118. In some embodiments, the microlens isolation structure 118 and the color filter 120 are formed by various steps of deposition processes (e.g., PVD, CVD, ALD, sputtering, etc.), removal processes (e.g., wet etching, dry etching, CMP, etc.), and / or patterning processes (e.g., photolithography / etching). In some embodiments, the color filter 120 comprises a material that allows radiation (e.g., light) with a specific range of wavelengths to pass through while blocking light with wavelengths outside the specific range.

[0064] In some embodiments, a microlens 116 is formed on the color filter 120. In some embodiments, the microlens 116 is formed by depositing a microlens material on the color filter 120 using a spin-coating or deposition process. The microlens 116 can then be formed by etching a patterned surface onto the microlens material using a microlens template. The microlens 116 helps focus incident light toward the image sensing element 106 of the pixel region 101. Each pixel region 101 may include the microlens 116, the color filter 120, the image sensing element 106, and processing circuitry (e.g., transistor gate structure 310, interconnect structure 302, etc.).

[0065] The composite deep trench isolation structure 110 continuously surrounds the image sensing element 106 of each pixel region 101. The second material of the upper portion 114 and the upper isolation layer 115 increases the percentage of incident light entering the image sensing element 106 of the pixel region 101 (because the second material has low reflectivity). In some embodiments, the lower portion 112 of the composite deep trench isolation structure 110 includes a second material having a higher reflectivity than the first material to prevent light from traveling into other image sensing elements 106. Therefore, by increasing the intensity of incident light received by the image sensing elements 106 and by preventing crosstalk between the image sensing elements 106, the composite deep trench isolation structure 110 increases the quantum efficiency of the pixel region 101 of the CMOS image sensor.

[0066] Figure 16 Showing the corresponding Figures 6 to 15 Flowcharts of some embodiments of method 1600.

[0067] Although method 1600 is shown and described below as a series of actions or events, it should be understood that the order in which these actions or events are shown should not be construed as limiting. For example, some actions may occur in a different order, and / or may occur simultaneously with other actions or events besides those shown and / or described herein. Furthermore, not all of the actions shown may be necessary to implement one or more aspects or embodiments described herein. Additionally, one or more of the actions depicted herein may be performed in one or more separate actions and / or phases.

[0068] At action 1602, an image sensing element is formed on the substrate by forming a trench within the image sensing material. Figure 7 A cross-sectional view 700 is shown, corresponding to some embodiments of action 1602.

[0069] At action 1604, a barrier layer is formed on the outer wall and upper surface of the image sensing element. Figure 9 A cross-sectional view 900 is shown, corresponding to some embodiments of action 1604.

[0070] At action 1606, a first material is formed on the substrate to fill the trenches between the image sensing elements. Figure 10 A cross-sectional view 1000 is shown, corresponding to some embodiments of action 1606.

[0071] At action 1608, the upper portion of the first material is removed to form the lower portion of the composite deep trench isolation structure between the image sensing elements. Figure 11 A cross-sectional view 1100 is shown, corresponding to some embodiments of action 1608.

[0072] At action 1610, a portion of the blocking layer disposed on the upper surface of the image sensing element is removed. Figure 13 A cross-sectional view 1300 is shown, corresponding to some embodiments of action 1610.

[0073] At action 1612, a second material is formed on the lower portion of the composite deep trench isolation structure to fill the trench and form the upper portion of the composite deep trench isolation structure containing the second material. Figure 14 A cross-sectional view 1400 is shown, corresponding to some embodiments of action 1612.

[0074] At action 1614, a microlens is formed on the image sensing element. Figure 15 A cross-sectional view 1500 is shown, corresponding to some embodiments of action 1614.

[0075] Therefore, this disclosure relates to a method for forming a composite deep trench isolation structure between pixel regions of a CMOS image sensor, wherein the composite deep trench isolation structure includes a lower portion having a higher reflectivity than the upper portion, in order to increase the quantum efficiency of the CMOS image sensor.

[0076] Therefore, in some embodiments, this disclosure relates to an integrated chip comprising: a first image sensing element disposed on a substrate; a first microlens disposed on the first image sensing element; a second image sensing element disposed on the substrate; a second microlens disposed on the second image sensing element; and a composite deep trench isolation structure disposed between the first image sensing element and the second image sensing element, and comprising: a lower portion disposed on the substrate and comprising a first material, and an upper portion disposed on the lower portion and comprising a second material having a lower reflectivity than the first material.

[0077] In some embodiments, the integrated chip further includes: an interconnect structure coupled to the first image sensing element and the second image sensing element, and disposed between the substrate and the first image sensing element and the second image sensing element. In some embodiments, the lower portion has a first height and the upper portion has a second height, wherein the first image sensing element has a third height, wherein the sum of the first height and the second height is approximately equal to the third height, and wherein the first height is at least 50% of the third height. In some embodiments, the bottom surface of the upper portion of the composite deep trench isolation structure is located below the top surface of the first image sensing element. In some embodiments, the composite deep trench isolation structure continuously surrounds the outermost outer wall of the first image sensing element and the outermost outer wall of the second image sensing element. In some embodiments, the first material is a metal, and wherein the second material is a dielectric material. In some embodiments, the integrated chip further includes: a barrier layer disposed directly between the composite deep trench isolation structure and the first image sensing element and the second image sensing element. In some embodiments, the barrier layer is also disposed directly between the upper portion and the lower portion of the composite deep trench isolation structure.

[0078] In other embodiments, this disclosure relates to an integrated chip comprising: a plurality of image sensing elements disposed on a substrate; a processing circuit system coupled to the plurality of image sensing elements; microlenses disposed on the plurality of image sensing elements; and a composite deep trench isolation structure disposed on the substrate, separating the plurality of image sensing elements from each other, and comprising: a lower portion comprising a first material having a first reflectivity, and an upper portion comprising a second material having a second reflectivity less than the first reflectivity, wherein the bottom surface of the upper portion of the composite deep trench isolation structure is disposed below the top surface of the plurality of image sensing elements.

[0079] In some embodiments, the upper portion of the composite deep trench isolation structure directly contacts the lower portion of the composite deep trench isolation structure. In some embodiments, the composite deep trench isolation structure continuously surrounds the outer sidewall of each of the plurality of image sensing elements. In some embodiments, the lower portion of the composite deep trench isolation structure has a greater thickness than the upper portion of the composite deep trench isolation structure. In some embodiments, the integrated chip further includes: a passivation layer disposed directly on the outermost sidewall of the image sensing element; and a barrier layer disposed directly on the passivation layer and the outermost sidewall of the composite deep trench isolation structure. In some embodiments, the barrier layer is disposed directly between the upper and lower portions of the composite deep trench isolation structure. In some embodiments, the barrier layer and the passivation layer are disposed below the bottom surface of the composite deep trench isolation structure.

[0080] In some other embodiments, this disclosure relates to a method comprising: forming an image sensing element on a substrate by forming trenches within an image sensing material; forming a barrier layer on an outer sidewall and an upper surface of the image sensing element; forming a first material on the substrate to fill the trenches between the image sensing elements; removing an upper portion of the first material to form a lower portion of a composite deep trench isolation structure between the image sensing elements; removing a portion of the barrier layer disposed on the upper surface of the image sensing element; forming a second material on the lower portion of the composite deep trench isolation structure to fill the trenches and form an upper portion of the composite deep trench isolation structure containing the second material; and forming a microlens on the image sensing element.

[0081] In some embodiments, the second material is further formed on the image sensing element to form an upper isolation layer comprising the second material on the image sensing element and on the composite deep trench isolation structure. In some embodiments, the thickness of the lower portion of the composite deep trench isolation structure is greater than 50% of the depth of the trench. In some embodiments, the first material has a higher reflectivity than the second material. In some embodiments, the method further includes forming an additional barrier layer on the lower portion of the composite deep trench isolation structure after forming the lower portion of the composite deep trench isolation structure and before removing the portion of the barrier layer disposed on the upper surface of the image sensing element.

[0082] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. An integrated chip comprising: a first image sensing element arranged over a substrate; a first microlens arranged over the first image sensing element; a second image sensing element arranged over the substrate; a second microlens arranged over the second image sensing element; and a composite deep trench isolation structure arranged between the first image sensing element and the second image sensing element and comprising: a lower portion arranged over the substrate and including a first material, wherein the first material is a metal, and an upper portion arranged over the lower portion and including a second material having a lower reflectivity than the first material, wherein the second material is a dielectric material, wherein the lower portion has a first height and the upper portion has a second height, wherein the first image sensing element has a third height, wherein a sum of the first height and the second height is approximately equal to the third height, and wherein the first height is at least 50% of the third height.

2. The integrated chip of claim 1, further comprising: an interconnect structure coupled to the first image sensing element and the second image sensing element and arranged between the substrate and the first image sensing element and the second image sensing element.

3. The integrated chip of claim 1, wherein a bottommost surface of the upper portion of the composite deep trench isolation structure is below an uppermost surface of the first image sensing element.

4. The integrated chip of claim 1, wherein the composite deep trench isolation structure continuously surrounds an outermost sidewall of the first image sensing element and an outermost sidewall of the second image sensing element.

5. The integrated chip of claim 1, wherein the second material also extends over the first image sensing element and the second image sensing element to form an upper isolation layer including the second material over the first image sensing element and the second image sensing element and over the composite deep trench isolation structure.

6. The integrated chip of claim 1, further comprising: a barrier layer arranged directly between the composite deep trench isolation structure and the first image sensing element and the second image sensing element.

7. The integrated chip of claim 6, wherein the barrier layer is also arranged directly between the upper portion and the lower portion of the composite deep trench isolation structure.

8. An integrated chip comprising: a plurality of image sensing elements arranged over a substrate; processing circuitry coupled to the plurality of image sensing elements; a microlens arranged over the plurality of image sensing elements; and a composite deep trench isolation structure arranged over the substrate, separating the plurality of image sensing elements from one another, and comprising: a lower portion including a first material having a first reflectivity, wherein the first material is a metal, and an upper portion including a second material having a second reflectivity less than the first reflectivity, wherein the second material is a dielectric material. ​ ​ wherein a bottommost surface of the upper portion of the composite deep trench isolation structure is disposed below a topmost surface of the plurality of image sensing elements, wherein the lower portion has a first height and the upper portion has a second height, wherein the plurality of image sensing elements has a third height, wherein a sum of the first height and the second height is approximately equal to the third height, and wherein the first height is at least 50% of the third height.

9. The integrated chip of claim 8, wherein the upper portion of the composite deep trench isolation structure directly contacts the lower portion of the composite deep trench isolation structure.

10. The integrated chip of claim 8, wherein the composite deep trench isolation structure continuously surrounds an outer sidewall of each image sensing element of the plurality of image sensing elements.

11. The integrated chip of claim 8, wherein the lower portion of the composite deep trench isolation structure has a greater thickness than the upper portion of the composite deep trench isolation structure.

12. The integrated chip of claim 8, further comprising: a passivation layer disposed directly on an outermost sidewall of the image sensing elements; and a barrier layer disposed directly on the passivation layer and an outermost sidewall of the composite deep trench isolation structure.

13. The integrated chip of claim 12, wherein the barrier layer is disposed directly between the upper portion and the lower portion of the composite deep trench isolation structure.

14. The integrated chip of claim 12, wherein the barrier layer and the passivation layer are disposed below a bottommost surface of the composite deep trench isolation structure.

15. A method of forming an integrated chip, comprising: forming image sensing elements over a substrate by forming trenches within an image sensing material; forming a barrier layer on an outer sidewall and an upper surface of the image sensing elements; forming a first material over the substrate to fill the trenches between the image sensing elements, wherein the first material is a metal; removing an upper portion of the first material to form a lower portion of a composite deep trench isolation structure between the image sensing elements, wherein a thickness of the lower portion of the composite deep trench isolation structure is greater than 50% of a depth of the trenches; removing a portion of the barrier layer disposed on the upper surface of the image sensing elements; forming a second material over the lower portion of the composite deep trench isolation structure to fill the trenches and form an upper portion of the composite deep trench isolation structure comprising the second material, wherein the first material has a higher reflectivity than the second material, and the second material is a dielectric material; and forming a microlens over the image sensing elements.

16. The method of forming an integrated chip of claim 15, wherein the second material is also formed over the image sensing elements to form an upper isolation layer comprising the second material over the image sensing elements and over the composite deep trench isolation structure.

17. The method of forming an integrated chip of claim 15, further comprising: ​ ​ After forming the lower portion of the composite deep trench isolation structure and before removing the portion of the barrier layer disposed on the upper surface of the image sensing element, an additional barrier layer is formed over the lower portion of the composite deep trench isolation structure.

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