Image sensing device

Abstract

We provide an image sensing device that generates image data. [Solution] The image sensing device 100 may include a pixel array 110 that includes a plurality of pixels connected to a plurality of row lines RL and a plurality of column lines CL and outputs a plurality of pixel signals PS via the plurality of column lines CL; a lamp generator 150 that generates a first lamp signal RAMP1 and a second lamp signal RAMP2; an analog-to-digital converter 160 that converts the plurality of pixel signals PS into digital signals corresponding to the first lamp signal RAMP1 and the second lamp signal RAMP2; and a column line control unit 140 that selectively connects the plurality of column lines CL and the analog-to-digital converter 160.

Description

Technical Field

[0005]

[0001] The present disclosure relates to an image sensing apparatus for generating image data.

Background Art

[0002] Generally, a CMOS (Complementary Metal Oxide Semiconductor) image sensor (CIS) implemented in a CMOS process has rapidly expanded its market due to advantages such as low power consumption, low cost, and small size compared to other competing products. In particular, the CMOS image sensor has gradually expanded its application range to the video field that requires high resolution and high frame rate through image quality improvement that was relatively lacking compared to competing products.

[0003] Unlike a solid-state imaging device, such a CMOS image sensor requires an operation of converting an analog signal (pixel signal) output from a pixel array into a digital signal. The CMOS image sensor uses a high-resolution analog-to-digital converter (ADC) internally for the conversion from an analog signal to a digital signal.

[0004] The analog-to-digital converter can perform correlated double sampling (CDS) on an analog output voltage that is an output signal of the pixel array. Also, the analog-to-digital converter can provide a comparison signal for digital code generation by comparing the voltage stored in the correlated double sampling operation in response to a ramp signal generated by a ramp signal generator with a predetermined reference voltage (ramp signal). <00​​However, since the lamp signal generator generates the lamp signal based on the power supply voltage, power noise or noise from the lamp signal generator itself may be directly included in the output lamp signal. Such noise can increase horizontal noise in CMOS image sensors (CIS). Therefore, in order to realize high-resolution and high-speed CMOS image sensors, a method for efficiently reducing horizontal noise is necessary. [Overview of the project] [Problems that the invention aims to solve]

[0006] Embodiments of the present invention provide an image sensing device that can remove lamp noise and reduce horizontal noise. [Means for solving the problem]

[0007] An image sensing device according to an embodiment of the present invention may include a pixel array that includes a plurality of pixels connected to a plurality of row lines and a plurality of column lines and outputs a plurality of pixel signals via the plurality of column lines; a lamp generator that generates a first lamp signal and a second lamp signal; an analog-to-digital converter that converts the plurality of pixel signals into digital signals in response to the first lamp signal and the second lamp signal; and a column line control unit that selectively connects the plurality of column lines and the analog-to-digital converter.

[0008] An image sensing device according to another embodiment of the present invention may include: a first pixel that outputs a first pixel signal via a first column line; a second pixel that outputs a second pixel signal via a second column line; a switching circuit that selectively connects the first column line to either a first or second node and the second column line to either the first or second node based on a switching control signal; a first lamp generator that generates a first lamp signal; a second lamp generator that generates a second lamp signal; a first conversion circuit that compares and amplifies the first lamp signal and a signal applied to the first node to generate a first output signal; and a first conversion circuit that compares and amplifies the second lamp signal and a signal applied to the second node to generate a second output signal. [Effects of the Invention]

[0009] Embodiments of the present invention can reduce horizontal noise and improve the noise characteristics of an image sensor.

[0010] Furthermore, the embodiments of the present invention are illustrative, and those skilled in the art will be able to make various modifications, changes, substitutions, and additions through the technical idea and scope of the appended claims, and such modifications and changes should be considered to fall within the following claims. [Brief explanation of the drawing]

[0011] [Figure 1] This is a block diagram showing an imaging apparatus according to one embodiment of the present disclosure. [Figure 2] Figure 1 shows a detailed configuration of the pixel array and low driver. [Figure 3a] Figure 2 is a diagram illustrating the operation of the pixel array and low driver shown. [Figure 3b] Figure 2 is a diagram illustrating the operation of the pixel array and low driver shown. [Figure 3c]Figure 2 is a diagram illustrating the operation of the pixel array and low driver shown. [Figure 3d] Figure 2 is a diagram illustrating the operation of the pixel array and low driver shown. [Figure 4] Figure 2 shows a detailed circuit diagram of the column line selection unit and ADC. [Figure 5] This figure illustrates the operation of the column line selection unit and ADC according to the embodiment shown in Figure 4. [Figure 6] This figure shows the detailed configuration of the lamp generator shown in Figure 1. [Figure 7] Figure 1 shows another embodiment of the pixel array, column line selection unit, and ADC in the image sensing device. [Figure 8] Figure 7 illustrates the operation of the column line selection unit and ADC according to the embodiment shown. [Modes for carrying out the invention]

[0012] Various embodiments will be described below with reference to the attached drawings. However, this disclosure should be understood not to be limited to any particular embodiment, but to include various modifications, equivalents, and / or alternatives of the embodiments. Embodiments of this disclosure can provide various effects that can be recognized directly or indirectly through this disclosure.

[0013] Figure 1 is a block diagram showing an imaging apparatus according to one embodiment of the present disclosure.

[0014] Referring to Figure 1, the imaging device 10 may refer to a device such as a digital still camera for capturing still images or a digital video camera for capturing moving images. For example, the imaging device 10 may be embodied in a digital single-lens reflex (DSLR), mirrorless camera, or smartphone, but is not limited to these. The imaging device 10 may be a concept that includes a device capable of capturing a subject, including an image sensor, and generating an image.

[0015] The imaging device 10 may include an image sensing device 100 and an image signal processor (hereinafter referred to as "ISP") 200.

[0016] For example, the image sensing device 100 may be a CIS (Complementary Metal Oxide Semiconductor Image Sensor) that converts incident light into electrical signals. The image sensing device 100 may include a pixel array 110, a row driver 120, a column line selection unit 130, a column selection control unit 140, a ramp generator 150, an analog-to-digital converter (ADC) 160, an output buffer 170, a column driver 180, and a timing controller 190. Here, each component of the image sensing device 100 is merely illustrative, and at least some components may be added or omitted as needed.

[0017] The pixel array 110 can include a plurality of pixels arranged in a plurality of rows and a plurality of columns. In one embodiment, the plurality of pixels may be arranged in a two-dimensional pixel array including rows and columns. In other embodiments, the plurality of unit image pixels may be arranged in a three-dimensional pixel array. The plurality of pixels can convert an optical signal into an electrical signal in pixel units or pixel group units and output a pixel signal PS. In the pixel array 110, the pixels within a pixel group can share at least one internal circuit. The pixel array 110 can receive a driving signal RCON including a row selection signal, a pixel reset signal, a transmission signal, etc. from the load driver 120. The pixel array 110 can be activated by the driving signal RCON so that the corresponding pixels of the pixel array 110 perform operations corresponding to the row selection signal, the pixel reset signal, and the transmission signal.

[0018] The load driver 120 can activate the pixel array 110 to perform a specific operation on the pixels included in the corresponding row based on the instructions and / or control signal CON1 supplied by the timing controller 190. In one embodiment, the load driver 120 can select at least one pixel arranged in at least one row line of the pixel array 110. The load driver 120 can generate a row selection signal to select at least one row line among the plurality of row lines. In other embodiments, the load driver 120 can also generate a row selection signal for selecting adjacent row lines in pairs among the plurality of row lines.

[0019] The load driver 120 can sequentially enable a pixel reset signal and a transmission signal for pixels corresponding to at least one selected row. Thereby, an analog reference signal and a video signal generated from each of the pixels in the selected row can be sequentially transmitted to the ADC 160. Here, the reference signal is an electrical signal provided to the ADC 160 when the sensing node (e.g., floating diffusion region) of the pixel is reset, and the video signal may be an electrical signal provided to the ADC 160 when the photoelectric charge generated by the pixel is accumulated in the sensing node. A reference signal indicating pixel-specific reset noise and a video signal indicating the intensity of incident light may be referred to as a pixel signal PS.

[0020] The column line selection unit 130 can selectively connect the column line CL to which the pixel signal PS is applied to the ADC 160 based on the selection control signal SCON applied from the column selection control unit 140. For example, the column line selection unit 130 can connect one of a pair of column lines CL selected by the selection control signal SCON among a plurality of column lines CL to the first ADC 161 and connect the remaining one to the second ADC 162. The detailed connection structure of such a column line selection unit 130 will be described in more detail with reference to FIG. 4 described later.

[0021] The column selection control unit 140 can generate a selection control signal SCON for selectively controlling the connection of a plurality of column lines CL based on the control signal CON3 applied from the timing controller 190. For example, the column selection control unit 140 can control so that a pair of adjacent column lines among a plurality of column lines CL are selected. In the embodiment of the present disclosure, the column selection control unit 140 is shown as a separate component for convenience of explanation, but the present invention is not limited thereto, and the column selection control unit 140 may be included inside the timing controller 190.

[0022] The lamp generator 150 can output a first lamp signal RAMP1 and a second lamp signal RAMP2, which are necessary for the analog-to-digital conversion operation of the ADC 160, based on the control signal CON3 applied from the timing controller 190. The lamp generator 150 can include a first lamp generator 151 and a second lamp generator 152. The first lamp generator 151 can generate the first lamp signal RAMP1 based on the control signal CON3. The second lamp generator 152 can generate the second lamp signal RAMP2 based on the control signal CON3. The detailed configuration of such a lamp generator 150 will be explained in more detail later with reference to Figure 6.

[0023] In the embodiments of this disclosure, the lamp generator 150 was described as including two lamp generators 151 and 152 as an example. However, this disclosure is not limited thereto, and the number of lamp generators may be three or more, and the number of noise generators can be easily changed.

[0024] A CMOS image sensor can use correlated double sampling to remove unwanted offset values ​​of pixels, such as fixed pattern noise, by sampling the pixel signal PS twice to remove the difference between two samples. For example, correlated double sampling may measure only the pixel output voltage based on incident light by comparing the pixel output voltage obtained before and after the photocharge generated by the incident light is accumulated at the sensing node, thereby removing unwanted offset values.

[0025] In one embodiment, the ADC 160 can sequentially sample and hold reference signals and video signals provided from each of a plurality of column lines of the pixel array 110. In one embodiment, the ADC 160 can be embodied as a ramp-compare type ADC. The ADC 160 can sample and hold the pixel signals PS for each column output from each column line CL of the pixel array 110 by a control signal CON 4 applied from the timing controller 190, convert them into digital signals DS, and output them.

[0026] Depending on the embodiment, the ADC160 may include a first ADC161, a second ADC162, and a counter 163. In the embodiments of this disclosure, the ADC160 is described as being embodied by two ADCs as an example. However, this disclosure is not limited thereto, and the number of ADCs may be three or more, and the number of ADCs is sufficiently variable.

[0027] The first ADC 161 receives the input of the first ramp signal RAMP1 and the pixel signal PS output from the column line CL selected by the column line selection unit 130, and outputs the output signal OUT1 to the counter 163. The second ADC 162 receives the input of the second ramp signal RAMP2 and the pixel signal PS output from the column line CL selected by the column line selection unit 130, and outputs the output signal OUT2 to the counter 163. The detailed connection structure of these ADCs 160 will be explained in more detail later with reference to Figure 4.

[0028] The counter 163 can perform counting operations until the ramp signals RAMP1 and RAMP2 match the analog pixel signal PS. The counter 163 performs counting in response to logic high-level output signals OUT1 and OUT2 and can output the counting result to the digital signal DS. The counter 163 can then initialize the counting value with the control signal CON4.

[0029] The output buffer 170 can temporarily hold and output the image data for each column provided by the ADC 160 (i.e., the digitally converted data of the pixel signals; IDATA). The output buffer 170 can temporarily store the image data IDATA output from the ADC 160 based on the control signal CON5 applied from the timing controller 190. The output buffer 170 can operate as an interface to compensate for differences in transmission (or processing) speeds between the image sensing device 100 and other devices connected to it.

[0030] The column driver 180 can select a column in the output buffer 170 based on a control signal CON6 applied from the timing controller 190, and control the output buffer 170 so that the image data IDATA temporarily stored in the selected column of the output buffer 170 is output sequentially. In one embodiment, the column driver 180 can receive an address signal from the timing controller 190, and the column driver 180 can generate a column selection signal based on the address signal to select a column in the output buffer 170, thereby controlling the output buffer 170 so that the image data IDATA is output to the outside from the selected column.

[0031] The timing controller 180 can control at least one of the following: the low driver 120, the column selection control unit 140, the ramp generator 150, the ADC 160, the output buffer 170, and the column driver 180.

[0032] The timing controller 190 can provide clock signals required for the operation of each component of the image sensing device 100, control signals for timing control, and address signals for selecting a low or column to at least one of the low driver 120, column selection control unit 140, ramp generator 150, ADC 160, output buffer 170, and column driver 180. In one embodiment, the timing controller 190 may include a logic control circuit (LogiCcontrol circuit), a phase lock loop (PLL) circuit, a timing control circuit, and a communication interface circuit.

[0033] The ISP200 can perform video signal processing on image data IDATA received from the image sensing device 100. The ISP200 can reduce noise in the image data IDATA and perform video signal processing for image quality improvement, such as interpolation, synthesis, gamma correction, color filter array interpolation, color matrix, color correction, color enhancement, and lens distortion correction. Furthermore, the ISP200 can compress the image data generated by performing video signal processing for image quality improvement to produce a video file, or it can repair image data from the video file. The video compression format may be lossless or lossy. As an example of a compression format, for still images, the JPEG (Joint PhotographiC Experts Group) format or JPEG2000 format may be used. For moving images, a moving image file may be generated by compressing multiple frames according to the MPEG (Moving Picture Experts Group) standard. The video file may be generated according to the Exif (Exchangeable image file format) standard, for example.

[0034] The ISP200 can transmit image data after image processing is complete to a host device (not shown). The host device (not shown) may be a processor (e.g., an application processor) that processes the image-processed image data received from the ISP200, a memory (e.g., non-volatile memory) that stores the image data, or a display device (e.g., an LCD (liquid crystal display)) that visually outputs the image data. The ISP200 can also transmit control signals to the image sensing device 100 to control its operation (such as whether it is operational, the timing of operation, and the mode of operation).

[0035] The aforementioned lamp generator 150 generates a lamp signal based on the power supply voltage (or ground voltage), so power noise (or ground noise) may be directly included in the output lamp signal. In addition, noise generated by the lamp generator 150 itself (such noise is also called "lamp noise") may be included in the output lamp signal without filtering. Such noise can increase the horizontal noise in the CMOS image sensor CIS.

[0036] Therefore, in the embodiment of the present disclosure, the lamp generator 150 is divided into a first lamp generator 151 and a second lamp generator 152, and the ADC 160 is divided into a first ADC 161 and a second ADC 162, with the first lamp generator 151 and the first ADC 161 being connected, and the second lamp generator 152 being connected to the second ADC 162. In other words, the two lamp signals RAMP1 and RAMP2 can be alternately mapped half each to the two ADCs 161 and 162. Furthermore, the column line selection unit 130 can control each column line to be selectively connected to the first ADC 161 and the second ADC 162.

[0037] The noise level of the ramp generator 150 can be determined by the root mean square (RMS) value of the noise. The degree of horizontal noise can then be measured by summing the output signals OUT1 and OUT2 of the first ADC 161 and the second ADC 162 and averaging them or by measuring the standard deviation. Thus, in this embodiment of the disclosure, horizontal noise can be reduced because the ramp signals RAMP1 and RAMP2 are mapped independently and uncorrelatedly to each other, even though the RMS values ​​of the noise generated by the ramp generator 150 are the same.

[0038] Figure 2 shows a detailed configuration of the pixel array and low driver shown in Figure 1.

[0039] Referring to Figure 2, the pixel array 110 can include multiple pixels PX11-PX14, PX21-PX24, PX31-PX34, and PX41-PX44 arranged in the row and column directions. Multiple pixels PX11-PX14, PX21-PX24, PX31-PX34, and PX41-PX44 may be connected between multiple row lines RL1-RL8 and multiple column lines CL1-CL8.

[0040] In embodiments of this disclosure, the pixel array 110 is shown to include eight row lines RL1 to RL8 and eight column lines CL1 to CL8. However, embodiments of this disclosure are not limited thereto, and the number of row lines and column lines can be easily modified.

[0041] In the pixel array 110, pixels in a single column may be alternately connected to column lines positioned to the left and column lines positioned to the right, based on the pixel. Pixels positioned odd-numbered in a column may be connected to the left column line, and pixels positioned even-numbered may be connected to the right column line.

[0042] For example, pixels PX11, PX21, PX31, PX41, PX51, PX61, PX71, and PX81 located in the first column can output a pair of pixel signals PS1 and PS2 via a pair of column lines CL1 and CL2. Pixels PX11, PX21, PX31, PX41, PX51, PX61, PX71, and PX81 may be arranged adjacent to each other in the first column. Column lines CL1 and CL2 may be arranged on either side of pixels PX11, PX21, PX31, PX41, PX51, PX61, PX71, and PX81 located in the first column. The first pair of pixels PX11 in the first column may be connected to row line RL1 and the left column line CL1. The second pixel PX21 in the first column may be connected to row line RL2 and the right column line CL2.

[0043] Furthermore, pixels PX12, PX22, PX32, PX42, PX52, PX62, PX72, and PX82 located in the second column can output a pair of pixel signals PS3 and PS4 via a pair of column lines CL3 and CL4. Pixels PX12, PX22, PX32, PX42, PX52, PX62, PX72, and PX82 may be arranged adjacent to each other in the second column. Column lines CL3 and CL4 may be located on either side of pixels PX12, PX22, PX32, PX42, PX52, PX62, PX72, and PX82 in the second column. The first pair of pixels PX12 in the second column may be connected to row line RL1 and the left column line CL3. The second pixel PX22 in the second column may be connected to row line RL2 and the right column line CL4. Since the pixels in the remaining columns included in the pixel array 110 can be understood to be connected to the column lines and row lines in a similar manner, redundant explanations will be omitted.

[0044] On the other hand, the low driver 120 may include multiple low decoders 121 to 128 for selecting each low line RL1 to RL8 in the pixel array 110. The multiple low decoders 121 to 128 can selectively activate multiple low line selection signals RLS1 to RLS8 based on a control signal CON1 applied from the timing controller 190. Here, the multiple low line selection signals RLS1 to RLS8 may be signals included in the aforementioned drive signal RCON.

[0045] For example, when the low-line selection signal RLS1 is activated by the low-decoder 121, pixels PX11 to PX14 connected to low-line RL1 may be selected. As another example, when the low-line selection signal RLS2 is activated by the low-decoder 122, pixels PX21 to PX24 connected to low-line RL2 may be selected. It can be understood that pixels in the remaining columns included in the pixel array 110 are selected in a similar manner. The operation of such a low-driver 120 will be explained in more detail in Figures 3a to 3d below.

[0046] Figures 3a to 3d are diagrams illustrating the operation of the pixel array and low driver shown in Figure 2.

[0047] Referring to Figures 3a to 3d, in the embodiments of this disclosure, a pair of adjacent low decoders among the plurality of low decoders 121 to 128 can be activated simultaneously. When a pair of low decoders are activated simultaneously, a pair of adjacent low line selection signals among the plurality of low line selection signals RLS1 to RLS8 can be activated simultaneously. That is, the plurality of low decoders 121 to 128 can be activated one pair at a time, and the plurality of low line selection signals RLS1 to RLS8 can be activated one pair at a time sequentially.

[0048] For example, as shown in Figure 3a(A), when a pair of low decoders 127 and 128 are activated in the T1 section, a pair of low-line selection signals RLS7 and RLS8 can be activated. When the pair of low-line selection signals RLS7 and RLS8 are activated, the pair of low lines RL7 and RL8 are selected, and a total of eight pixels PX71-PX74 and PX81-PX84 can be activated. As a result, a pair of pixel signals PS1 and PS2 can be output via column line CL1, a pair of pixel signals PS3 and PS4 can be output via column line CL2, a pair of pixel signals PS5 and PS6 can be output via column line CL3, and a pair of pixel signals PS7 and PS8 can be output via column line CL4.

[0049] As shown in Figure 3b(B), when a pair of low decoders 125 and 126 are activated in the T2 section, a pair of low-line selection signals RLS5 and RLS6 can be activated. When the pair of low-line selection signals RLS5 and RLS6 are activated, a pair of low lines RL5 and RL6 are selected, and a total of eight pixels PX51-PX54 and PX61-PX64 can be activated. As a result, a pair of pixel signals PS1 and PS2 are output via column line CL1, a pair of pixel signals PS3 and PS4 are output via column line CL2, a pair of pixel signals PS5 and PS6 are output via column line CL3, and a pair of pixel signals PS7 and PS8 are output via column line CL4. As shown in Figures 3c and 3d(C) and (D), it can be understood that a pair of pixel signals are output in the same manner in the remaining T3 and T4 sections, so redundant explanations will be omitted.

[0050] Here, intervals T1 to T4 indicate the timing at which the ADC160 is activated. For example, in interval T1, the ADC160 can be selected and the AD conversion operation can be performed on pixels PX71 to PX74 and PX81 to PX84. Subsequently, in interval T2, the ADC160 can be selected and the AD conversion operation can be performed on pixels PX51 to PX54 and PX61 to PX64. Next, in interval T3, the ADC160 can be selected and the AD conversion operation can be performed on pixels PX31 to PX34 and PX41 to PX44. Then, in interval T4, the ADC160 can be selected and the AD conversion operation can be performed on pixels PX11 to PX14 and PX21 to PX24.

[0051] As described above, in the embodiments shown in Figures 3a to 3d, a pair of pixel signals (e.g., PS1, PS2) are output based on a pixel (e.g., PX11, PX21 (one column unit)) provided in one column, so this type of system can be referred to as a dual readout system.

[0052] In the embodiments of this disclosure, one example has been described in which pairs of low decoders 121 to 128 are activated sequentially, from low decoders 127 and 128 to low decoders 121 and 122. However, the embodiments of this disclosure are not limited thereto, and the pairs of low decoders 121 to 128 may be activated sequentially, from low decoders 121 and 122 to low decoders 127 and 128, or they may be activated selectively and randomly, and the order in which the low decoders 121 to 128 are activated can be sufficiently changed.

[0053] Figure 4 shows a detailed circuit diagram of the column line selection unit and ADC shown in Figure 2.

[0054] In the embodiment shown in Figure 4, we will explain as an example the case in which the low decoders 121 and 122 are activated and low lines RL1 and RL2 are selected by a pair of low line selection signals RLS1 and RLS2, as shown in Figures 2 and 3d(D).

[0055] Referring to Figure 4, the column line selection unit 130 can include multiple switching circuits SC1 to SC4.

[0056] Multiple switching circuits SC1 to SC4 can be selectively switched by multiple switching control signals S1 to S4 to selectively output multiple pixel signals PS1 to PS8 to the first ADC161 or the second ADC162. In other words, multiple switching circuits SC1 to SC4 can selectively connect multiple column lines CL1 to CL8 to the first ADC161 or the second ADC162 based on the multiple switching control signals S1 to S4. Here, the multiple switching control signals S1 to S4 may be signals included in the selection control signal SCON applied from the column selection control unit 140 described above.

[0057] The switching circuit SC1 can control one of a pair of column lines CL1 and CL2 to connect to the first ADC161 and the other to the second ADC162 based on switching control signals S1 and S2. In other words, the switching circuit SC1 can include multiple switching elements SW1 to SW4. Switching element SW1 can selectively connect column line CL1 to node ND1 based on switching control signal S1, and switching element SW2 can selectively connect column line CL2 to node ND5 based on switching control signal S1. Switching element SW3 can selectively connect column line CL1 to node ND5 based on switching control signal S2, and switching element SW4 can selectively connect column line CL2 to node ND1 based on switching control signal S2.

[0058] The switching circuit SC2 can control one of a pair of column lines CL3 and CL4 to connect to the first ADC161 and the other to the second ADC162 based on switching control signals S1 and S2. In other words, the switching circuit SC2 can include multiple switching elements SW5 to SW8. Switching element SW5 can selectively connect column line CL3 to node ND2 based on switching control signal S1, and switching element SW6 can selectively connect column line CL4 to node ND6 based on switching control signal S1. Switching element SW7 can selectively connect column line CL3 to node ND6 based on switching control signal S2, and switching element SW8 can selectively connect column line CL4 to node ND2 based on switching control signal S2.

[0059] The switching circuit SC3 can control one of a pair of column lines CL5 and CL6 to connect to the first ADC161 and the other to the second ADC162 based on switching control signals S3 and S4. In other words, the switching circuit SC3 can include multiple switching elements SW9 to SW12. Switching element SW9 can selectively connect column line CL5 to node ND3 based on switching control signal S3, and switching element SW10 can selectively connect column line CL6 to node ND7 based on switching control signal S3. Switching element SW11 can selectively connect column line CL5 to node ND7 based on switching control signal S4, and switching element SW12 can selectively connect column line CL6 to node ND3 based on switching control signal S4.

[0060] The switching circuit SC4 can control one of a pair of column lines CL7 and CL8 to connect to the first ADC161 and the other to the second ADC162 based on switching control signals S3 and S4. In other words, the switching circuit SC4 can include a plurality of switching elements SW13 to SW16. Switching element SW13 can selectively connect column line CL7 to node ND4 based on switching control signal S3, and switching element SW14 can selectively connect column line CL8 to node ND8 based on switching control signal S3. Switching element SW15 can selectively connect column line CL7 to node ND8 based on switching control signal S4, and switching element SW16 can selectively connect column line CL8 to node ND4 based on switching control signal S4.

[0061] The first ADC161 can include multiple conversion circuits CC1 to CC4. The second ADC162 can include multiple conversion circuits CC5 to CC8.

[0062] Multiple conversion circuits CC1 to CC4 compare the pixel signals applied to nodes ND1 to ND4 with the first ramp signal RAMP1 and generate output signals OUT2, OUT4, OUT6, and OUT8 based on the comparison result, which are then transmitted to counter 163. Multiple conversion circuits CC5 to CC8 compare the pixel signals applied to nodes ND5 to ND8 with the second ramp signal RAMP2 and output output signals OUT1, OUT3, OUT5, and OUT7 based on the comparison result.

[0063] Here, the conversion circuit CC1 may include multiple capacitors C1, C2, comparator A1, and multiple switching elements SW20, SW21.

[0064] Multiple capacitors C1 and C2 are provided at the input terminal of the conversion circuit CC1 and can reduce the noise bandwidth of the noise applied via node ND1 and the first ramp signal RAMP1. In other words, multiple capacitors C1 and C2 can perform the function of transmitting only the voltage change amount, regardless of the DC level of the input signal.

[0065] Comparator A1 can compare and amplify the pixel signal PS and the first ramp signal RAMP1 applied via node ND1 and output an output signal OUT2 to counter 163. Comparator A1 may be provided one for each pair of column lines CL1 and CL2. In one embodiment, comparator A1 can generate a logic high-level output signal OUT2 when the second ramp signal VRAMP1 is greater than the pixel signal PS. Also, comparator A1 can generate a logic low-level output signal OUT2 when the first ramp signal VRAMP1 is less than the pixel signal PS. That is, the output signal OUT2 can indicate the magnitude relationship between the first ramp signal VRAMP1 and the pixel signal PS.

[0066] Furthermore, comparator A1 may include multiple switching elements SW20, SW21 for auto-zeroing operation.

[0067] Auto-zeroing operation can be performed by an auto-zeroing signal AZ (not shown). For example, the auto-zeroing signal AZ may be a signal included in the control signal CON4 generated by the timing controller 190. Here, the auto-zeroing operation may be an operation that adjusts the voltage level of the first ramp signal RAMP1 and the voltage level of the pixel signal PS for comparison between the first ramp signal RAMP1 and the pixel signal PS. Multiple switching elements SW20, SW21 may be turned on during the interval when the auto-zeroing signal AZ is at a logic high level to perform the auto-zeroing operation of comparator A1.

[0068] Conversion circuit CC2 may include multiple capacitors C3, C4, comparator A2, and multiple switching elements SW22, SW23. Conversion circuit CC3 may include multiple capacitors C5, C6, comparator A3, and multiple switching elements SW24, SW25. Conversion circuit CC4 may include multiple capacitors C7, C8, comparator A4, and multiple switching elements SW26, SW27. Conversion circuit CC5 may include multiple capacitors C9, C10, comparator A5, and multiple switching elements SW28, SW29. Conversion circuit CC6 may include multiple capacitors C11, C12, comparator A6, and multiple switching elements SW30, SW31. Conversion circuit CC7 may include multiple capacitors C13, C14, comparator A7, and multiple switching elements SW32, SW33. Conversion circuit CC8 may include multiple capacitors C15, C16, comparator A8, and multiple switching elements SW34, SW35.

[0069] In Figure 4, it can be understood that the operation of the remaining conversion circuits CC2 to CC8 is carried out in the same manner as the conversion circuit CC1 described above, so redundant explanations will be omitted.

[0070] Figure 5 is a diagram illustrating the operation of the column line selection unit and ADC according to the embodiment shown in Figure 4.

[0071] Referring to Figure 5, in the interval in which the aforementioned ADC160 is activated (for example, interval T1), one pair of switching control signals S1 and S4 (for example, the first group of switching control signals) from the multiple switching control signals S1 to S4 can be activated, while the remaining pair of switching control signals S2 and S3 (for example, the second group of switching control signals) can be deactivated.

[0072] However, the embodiments of this disclosure are not limited thereto. Conversely, a pair of switching control signals S2 and S3 among the multiple switching control signals S1 to S4 can be activated while the remaining pair of switching control signals S1 and S4 can be deactivated. In the embodiment shown in Figure 5, a case in which a pair of switching control signals S1 and S4 are activated and a pair of switching control signals S2 and S3 are deactivated will be explained as an example.

[0073] For example, among multiple column lines CL1 to CL8, column lines CL1, CL3, CL5, and CL7 can be referred to as odd-numbered column lines, and column lines CL2, CL4, CL6, and CL8 can be referred to as even-numbered column lines.

[0074] When switching signals S1 and S4 are activated and switching signals S2 and S3 are deactivated, switching elements SW1, SW2, SW5, SW6, SW11, SW12, SW15, and SW16 may be turned on, while switching elements SW3, SW4, SW7, SW8, SW9, SW10, SW13, and SW14 may be turned off.

[0075] In this case, of the odd-numbered column lines CL1, CL3, CL5, and CL7, column lines CL1 and CL3 may be connected to the first ADC161, and column lines CL5 and CL7 may be connected to the second ADC162. Furthermore, of the even-numbered column lines CL2, CL4, CL6, and CL8, column lines CL2 and CL4 may be connected to the second ADC162, and column lines CL6 and CL8 may be connected to the first ADC161.

[0076] In other words, of a pair of adjacent column lines CL1 and CL2, the odd-numbered column line CL1 may be connected to the first ADC161, and the even-numbered column line CL2 may be connected to the second ADC162. Of a pair of adjacent column lines CL3 and CL4, the odd-numbered column line CL3 may be connected to the first ADC161, and the even-numbered column line CL4 may be connected to the second ADC162.

[0077] Furthermore, of the adjacent pair of column lines CL5 and CL6, the odd-numbered column line CL5 may be connected to the second ADC162, and the even-numbered column line CL6 may be connected to the first ADC161. Of the adjacent pair of column lines CL7 and CL8, the odd-numbered column line CL7 may be connected to the second ADC162, and the even-numbered column line CL8 may be connected to the first ADC161.

[0078] In other words, when we examine the matching relationships between the ramp signals RAMP1, RAMP2 and ADC161, 162 in the direction in which column lines CL1 to CL8 are arranged, we find the following: Column line CL1 can be mapped to the first ramp signal RAMP1 and the first ADC161; column line CL2 can be mapped to the second ramp signal RAMP2 and the second ADC162; column line CL3 can be mapped to the first ramp signal RAMP1 and the first ADC161; column line CL4 can be mapped to the second ramp signal RAMP2 and the second ADC162; column line CL5 can be mapped to the second ramp signal RAMP2 and the second ADC162; column line CL6 can be mapped to the first ramp signal RAMP1 and the first ADC161; column line CL7 can be mapped to the second ramp signal RAMP2 and the second ADC162; and column line CL8 can be mapped to the first ramp signal RAMP1 and the first ADC161.

[0079] In the mapping described above, the column lines CL1, CL3, CL6, and CL8 connected to the first ADC161 can be defined as the first group of column lines, and the column lines CL2, CL4, CL5, and CL7 connected to the second ADC162 can be defined as the second group of column lines. Then, the output signals OUT2, OUT4, OUT6, and OUT8 output via the first group of column lines CL1, CL3, CL6, and CL8 can be defined as the first group of output signals, and the output signals OUT1, OUT3, OUT5, and OUT7 output via the second group of column lines CL2, CL4, CL5, and CL7 can be defined as the second group of output signals. In this disclosure, a method that distributes and matches two ramp signals RAMP1 and RAM2 with two ADCs 161 and 162 in this way can be defined as a zigzag pattern mapping method.

[0080] Thus, the present disclosure includes two ramp generators 151, 152 and two ADCs 161, 162, wherein one pixel signal applied from a pair of column lines and a first ramp signal RAMP1 may be transmitted to the first ADC 161, or the remaining pixel signal and a second ramp signal RAMP2 may be transmitted to the second ADC 162. This allows the first ADC 161 and the second ADC 162, receiving the two ramp signals RAMP1 and RAMP2, to be mapped uncorrelatedly to reduce horizontal noise.

[0081] Figure 6 shows a detailed configuration of the lamp generator shown in Figure 1.

[0082] Referring to Figure 6, the first lamp generator 151 may include a current generator 153, a current control unit 154, a voltage converter 155, a lamp signal generator 156, and a resistor circuit 157.

[0083] Here, the current generator 153 can generate a reference current IREF1 based on a bandgap reference voltage VBGR1. In one example, the bandgap reference voltage VBGR1 may be a reference voltage having a constant voltage level with little variation due to electrical load, time, or temperature changes. In one example, the current generator 153 can receive the bandgap reference voltage VBGR1 from a bandgap reference voltage circuit (not shown) located outside the first lamp generator 151. In another example, the current generator 153 can receive the bandgap reference voltage VBGR1 from a bandgap reference voltage circuit (not shown) located in the timing controller 190.

[0084] In one example, the current generator 153 may correspond to a circuit that converts an input voltage into a current. For example, the current generator 153 may include an operational amplifier-based voltage-to-current converter, a transistor-based voltage-to-current converter, or an integrated circuit IC-based voltage-to-current converter.

[0085] The current control unit 154 can generate a digital-to-analog converting (DAC) current IDAC1 based on a reference current IREF1. In one example, the DAC current IDAC1 may be the underlying current for generating a bias voltage VBIAS1 to perform the DAC operation of the first ramp signal VRAMP1. For example, the current control unit 154 can receive the reference current IREF1 and adjust the received reference current IREF1 to convert it into the DAC current IDAC1. The DAC current IDAC1 may be the reference current for determining the ramp offset voltage and / or swing width of the first ramp signal RAMP1. In one example, the current control unit 154 may include a current mirror circuit and a current steering circuit.

[0086] Furthermore, the voltage converter 155 can generate a bias voltage VBIAS1 based on the DAC current IDAC1. In one example, the bias voltage VBIAS1 can determine the reference voltage level for the first ramp signal VRAMP1.

[0087] In one example, the voltage converter 155 may correspond to a circuit that converts an input current to a voltage. For example, the voltage converter 155 may include a resistor, an operational amplifier, a transistor, or an integrated circuit board current-voltage converter. In one example, when the voltage converter 155 is embodied in a transistor-based current-voltage converter, it may include a transistor P1. The transistor P1 may be a PMOS transistor. The transistor P1 may be connected between the power supply voltage terminal and the application terminal of the DAC current IDAC1. The gate terminal and drain terminal of the transistor P1 may be commonly connected.

[0088] The ramp signal generator 156 can generate a first ramp signal VRAMP1 based on a bias voltage VBIAS1 and a switch control signal SWC1. The ramp signal generator 156 may include a transistor P2 and a switch SW40.

[0089] Transistor P2 can selectively supply the power supply voltage VCC to the switch SW40 based on the bias voltage VBIAS1. Transistor P2 can also operate as a variable current source that adjusts the minute current supplied to the switch SW40 in accordance with the bias voltage VBIAS1. Transistor P2 may be a PMOS transistor. Transistor P2 can be connected between the power supply voltage VCC application terminal and the switch SW40, and the bias voltage VBIAS1 can be applied via its gate terminal.

[0090] Switch SW40 is connected between transistor P2 and resistor circuit 157, and its switching operation can be selectively controlled by switching control signal SWC1. In one example, the switching control signal SWC1 may be included in the control signal CON3 generated by timing controller 190.

[0091] Depending on the embodiment, there may be multiple lamp signal generators 156. Multiple lamp signal generators 156 can control the first lamp signal RAMP1 by adjusting the number of switches SW40 connected by a switching control signal SWC1.

[0092] The resistor circuit 157 can control the loading of the first ramp signal RAMP1 generated by the ramp signal generator 156. Such a resistor circuit 157 may include a variable resistor whose resistance value can be changed to perform offset adjustment, but the scope of this disclosure is not limited thereto. The variable resistor R1 may be connected between the switch SW40 and the ground voltage terminal so that its resistance level can be adjusted.

[0093] As the resistance of resistor circuit 157 decreases, the distance between the maximum and minimum voltage levels of the first ramp signal VRAMP1, i.e., the swing range, can decrease. In one example, if the swing range of the first ramp signal VRAMP1 is relatively small, image data IDATA corresponding to a relatively large value may be generated for the same xel signal. In other words, the analog gain can increase. On the other hand, as the resistance of resistor circuit 157 increases, the swing range of the first ramp signal VRAMP1 can increase. In one example, if the swing range of the first ramp signal VRAMP1 is relatively large, image data IDATA corresponding to a relatively small value may be generated for the same pixel signal. In other words, the analog gain can decrease.

[0094] On the other hand, the second lamp generator 152 may include a current generator 153-1, a current control unit 154-1, a voltage converter 155-1, a lamp signal generator 156-1, and a resistor circuit 157-1.

[0095] Here, the current generator 153-1 can generate a reference current IREF1 based on the bandgap reference voltage VBGR1. The current control unit 154-1 can generate a DAC current IDAC2 based on the reference current IREF2. The voltage converter 155-1 can generate a bias voltage VBIAS2 based on the DAC current IDAC2. In one example, if the voltage converter 155-1 is embodied in a transistor-based current-voltage converter, it may include a transistor P3. The ramp signal generator 156-1 can generate a second ramp signal VRAMP2 based on the bias voltage VBIAS2 and a switch control signal SWC2. The ramp signal generator 156-1 may include a transistor P4 and a switch SW41. The resistor circuit 157-1 may include a variable resistor R2.

[0096] The detailed circuit and operation of the second lamp generator 152, which has this configuration, can be understood in the same way as the detailed circuit and operation of the first lamp generator 151, so redundant explanations will be omitted.

[0097] In the embodiments of this disclosure, since the detailed circuit diagrams of the first lamp generator 151 and the second lamp generator 152 are identical, the waveforms of the first lamp signal RAMP1 and the second lamp signal RAMP2 may be similar or identical. Consequently, the noise components generated by the first lamp generator 151 and the second lamp generator 152 may also be substantially similar or identical.

[0098] Figure 7 shows another embodiment of the pixel array, column line selection unit, and ADC in the image sensing device of Figure 1.

[0099] The embodiment in Figure 7 can perform substantially the same operations as the embodiments described in Figures 2 to 5, with only a few differences. Therefore, in the embodiment of Figure 7, only the configurations and operations that differ from those shown in Figures 2 to 5 will be described, the same reference numerals will be assigned to identical configurations, and redundant explanations will be omitted.

[0100] Referring to Figure 7, the pixel array 110-1 may include multiple pixels PX11-PX14 and PX21-PX24 arranged in the row and column directions. Multiple pixels PX11-PX14 and PX21-PX24 may be connected between multiple row lines RL1 and RL2 and multiple column lines CL1 and CL4. Multiple pixels PX11-PX14 may be arranged adjacent to each other in the same first row. Multiple pixels PX21-PX24 may be arranged adjacent to each other in the same second row.

[0101] In the embodiment shown in Figure 7, for the sake of explanation, the pixel array 110-1 is shown to include two row lines RL1 and RL2 and four column lines CL1 to CL4. However, embodiments of the present disclosure are not limited thereto, and the number of row lines and column lines can be easily changed.

[0102] In the embodiments shown in Figures 3a to 3d described above, it was explained that a pair of adjacent low decoders among the multiple low decoders 121 to 128 are activated simultaneously. However, in the embodiment shown in Figure 7, the multiple low decoders 121 and 122 can be activated one by one in sequence, and the low line selection signals RLS1 and RLS2 can be activated sequentially. The activation of the low line selection signals RLS1 and RLS2 may select low lines RL1 and RL2.

[0103] For example, when the low-line selection signal RLS1 is activated by the low-decoder 121, pixels PX11 to PX14 connected to low-line RL1 may be selected. As another example, when the low-line selection signal RLS2 is activated by the low-decoder 122, pixels PX21 to PX24 connected to low-line RL2 may be selected.

[0104] Pixels PX11 and PX21 located in the first column can output pixel signal PS1 via column line CL1. Pixels PX12 and PX22 located in the second column can output pixel signal PS2 via column line CL2. Pixels PX13 and PX23 located in the third column can output pixel signal PS3 via column line CL3. Pixels PX14 and PX24 located in the fourth column can output pixel signal PS4 via column line CL4.

[0105] Thus, in the embodiment shown in Figure 7, one pixel signal (e.g., PS1) is output per row line based on the pixels provided in one row (e.g., PX11, PX21 (one column unit)), so this method can be referred to as a single readout method.

[0106] In the embodiment shown in Figure 7, a plurality of low decoders 121 to 128 are activated sequentially as an example. However, the embodiments of this disclosure are not limited thereto, and the low decoders 121 to 128 may be activated selectively and randomly, and the order in which the low decoders 121 to 128 are activated can be sufficiently changed.

[0107] On the other hand, the column line selection unit 130-1 can include multiple switching circuits SC5, SC6.

[0108] Multiple switching circuits SC5 and SC6 can be selectively switched by multiple switching control signals S1 to S4 to selectively output multiple pixel signals PS1 to PS4 to the first ADC161-1 or the second ADC162-1. In other words, multiple switching circuits SC5 and SC6 can selectively connect multiple column lines CL1 to CL4 to the first ADC161-1 or the second ADC162-1 based on multiple switching control signals S1 to S4.

[0109] The switching circuit SC5 can control one of a pair of adjacent column lines CL1 and CL2 to connect to the first ADC161-1 and the other to the second ADC162-1 based on switching control signals S1 and S2. In other words, the switching circuit SC5 can include multiple switching elements SW50 to SW53. Switching element SW50 can selectively connect column line CL1 to node ND10 based on switching control signal S1, and switching element SW51 can selectively connect column line CL2 to node ND12 based on switching control signal S1. Switching element SW52 can selectively connect column line CL1 to node ND12 based on switching control signal S2, and switching element SW53 can selectively connect column line CL2 to node ND10 based on switching control signal S2.

[0110] The switching circuit SC6 can control one of a pair of adjacent column lines CL3 and CL4 to connect to the first ADC 161-1 and the other to the second ADC 162-1 based on switching control signals S3 and S4. In other words, the switching circuit SC6 can include a plurality of switching elements SW54 to SW57. Switching element SW54 can selectively connect column line CL3 to node ND11 based on switching control signal S3, and switching element SW55 can selectively connect column line CL4 to node ND13 based on switching control signal S3. Switching element SW56 can selectively connect column line CL3 to node ND13 based on switching control signal S4, and switching element SW57 can selectively connect column line CL4 to node ND11 based on switching control signal S4.

[0111] The first ADC161-1 can include multiple conversion circuits CC10, CC11. The second ADC162-1 can include multiple conversion circuits CC12, CC13.

[0112] Multiple conversion circuits CC10 and CC11 can compare the pixel signals applied to nodes ND10 and ND11 with the first ramp signal RAMP1, and generate output signals OUT2 and OUT4 based on the comparison result, which can then be transmitted to counter 163. Furthermore, multiple conversion circuits CC12 and CC13 can compare the pixel signals applied to nodes ND12 and ND13 with the second ramp signal RAMP2, and output output signals OUT1 and OUT3 based on the comparison result.

[0113] Here, the conversion circuit CC10 may include multiple capacitors C20, C21, a comparator A10, and multiple switching elements SW60, SW61.

[0114] Multiple capacitors C20 and C21 are provided at the input terminal of the conversion circuit CC10 and can reduce the noise bandwidth of the noise applied via node ND10 and the first ramp signal RAMP1.

[0115] Comparator A10 can compare and amplify the pixel signal PS applied via node ND10 with the first ramp signal RAMP1 to output the output signal OUT2 to counter 163. Furthermore, the conversion circuit CC10 may include multiple switching elements SW60, SW61 for the auto-zeroing operation of comparator A10.

[0116] The conversion circuit CC11 may include multiple capacitors C22, C23, comparator A11, and multiple switching elements SW62, SW63. The conversion circuit CC12 may include multiple capacitors C24, C25, comparator A12, and multiple switching elements SW64, SW65. The conversion circuit CC13 may include multiple capacitors C26, C27, comparator A13, and multiple switching elements SW66, SW67. The operation of the remaining conversion circuits CC11 to CC13 in Figure 7 can be understood to be performed in the same manner as the conversion circuit CC10 described above, so redundant explanations will be omitted.

[0117] Figure 8 is a diagram illustrating the operation of the column line selection unit and ADC according to the embodiment shown in Figure 7.

[0118] Referring to Figure 8, in the interval in which the aforementioned ADC160-1 is activated, one pair of switching control signals S1 and S4 out of the multiple switching control signals S1 to S4 can be activated, while the remaining pair of switching control signals S2 and S3 can be deactivated.

[0119] However, the embodiments of this disclosure are not limited thereto. Conversely, a pair of switching control signals S2 and S3 among the multiple switching control signals S1 to S4 can be activated while the remaining pair of switching control signals S1 and S4 can be deactivated. In the embodiment shown in Figure 8, a case in which a pair of switching control signals S1 and S4 are activated and a pair of switching control signals S2 and S3 are deactivated will be explained as an example.

[0120] For example, a pair of adjacent column lines CL1 and CL2 from among the multiple column lines CL1 to CL4 may be connected to the switching circuit SC5. Furthermore, a pair of adjacent column lines CL3 and CL4 from among the multiple column lines CL1 to CL4 may be connected to the switching circuit SC6.

[0121] When switching signals S1 and S4 are activated and switching signals S2 and S3 are deactivated, switching elements SW50, SW51, SW56, and SW57 may be turned on, while switching elements SW52, SW53, SW54, and SW55 may be turned off.

[0122] For example, of the pair of column lines CL1 and CL2, column line CL1 may be connected to the first ADC161-1, and column line CL2 may be connected to the second ADC162-1. Furthermore, of the pair of column lines CL3 and CL4, column line CL3 may be connected to the second ADC162-1, and column line CL4 may be connected to the first ADC161-1.

[0123] In other words, of a pair of adjacent column lines CL1 and CL2, the odd-numbered column line CL1 may be connected to the first ADC161-1, and the even-numbered column line CL2 may be connected to the second ADC162-1. Of a pair of adjacent column lines CL3 and CL4, the odd-numbered column line CL3 may be connected to the second ADC162-1, and the even-numbered column line CL4 may be connected to the first ADC161-1.

[0124] Thus, the present disclosure includes two ramp generators 151, 152 and two ADCs 161-1, 162-1, wherein one pixel signal and a first ramp signal RAMP1 applied from a pair of adjacently arranged column lines may be transmitted to the first ADC 161-1, or the remaining pixel signal and a second ramp signal RAMP2 may be transmitted to the second ADC 162-1. This allows the first ADC 161-1 and the second ADC 162-1, which receive the two ramp signals RAMP1 and RAMP2, to be distributed in a zigzag pattern to reduce horizontal noise. [Explanation of symbols]

[0125] 10 Imaging equipment 100 Image Sensing Devices 110 pixel array 120 Low Driver 130 Column line selection section 140 Column Selection Control Unit 150 Lamp generator 160 ADC 170 Output buffer 180 Column Driver 190 Timing controller

Claims

1. A pixel array comprising multiple pixels connected to multiple row lines and multiple column lines, and outputting multiple pixel signals via the multiple column lines; A lamp generator that generates a first lamp signal and a second lamp signal; An analog-to-digital converter that converts the plurality of pixel signals into digital signals in response to the first lamp signal and the second lamp signal; and An image sensing apparatus including a column line control unit that selectively connects the plurality of column lines and the analog-to-digital converter.

2. The aforementioned multiple pixels are A first pixel connected to the first row line and the first column line; and It includes a second pixel formed adjacent to the first pixel and connected to a second row line and a second column line, The image sensing apparatus according to claim 1, wherein the first pixel and the second pixel are arranged in a first column.

3. The first column line is positioned to the left of the plurality of pixels and outputs the first pixel signal. The image sensing device according to claim 2, wherein the second column line is positioned to the right of the plurality of pixels and outputs a second pixel signal.

4. The aforementioned multiple pixels are A first pixel connected to the first row line and the first column line; and A second pixel is formed adjacent to the first pixel and is connected to the first row line and the second column line, The image sensing apparatus according to claim 1, wherein the first pixel and the second pixel are arranged in a first row.

5. The lamp generator is, A first lamp generator that generates the first lamp signal; and The image sensing apparatus according to claim 1, comprising a second lamp generator for generating the second lamp signal.

6. The first lamp generator and the second lamp generator are each, A current generator that produces a reference current; A current control unit that generates a digital-to-analog conversion current based on the aforementioned reference current; A voltage converter that generates a bias voltage based on the aforementioned digital-to-analog conversion current; A ramp signal generator that generates a ramp signal based on the bias voltage and switch control signal; The image sensing device according to claim 5, further comprising a resistor circuit for controlling the loading of the lamp signal.

7. The aforementioned analog-to-digital converter is A first analog-to-digital converter that takes the first lamp signal and samples and holds the first group of column lines selected by the column line control unit from among the plurality of column lines to output the output signal of the first group; A second analog-to-digital converter that receives the second lamp signal and samples and holds the second group of column lines selected by the column line control unit from among the plurality of column lines to output the output signal of the second group; and The image sensing apparatus according to claim 1, further comprising a counter that counts the output signals of the first group and the output signals of the second group and outputs them as a digital signal.

8. The column line control unit is The image sensing apparatus according to claim 7, comprising a plurality of switching circuits that selectively connect the first group of column lines to the first analog-to-digital converter and the second group of column lines to the second analog-to-digital converter based on a plurality of switching control signals.

9. The image sensing apparatus according to claim 8, further comprising a column selection control unit that generates the plurality of switching control signals.

10. The image sensing apparatus according to claim 1, further comprising a plurality of low decoders that generate low line selection signals for activating adjacent low lines one pair at a time from among the plurality of low lines.

11. The first pixel that outputs the first pixel signal via the first column line; The second pixel outputs the second pixel signal via the second column line; A switching circuit that selectively connects the first column line to either the first or second node and the second column line to either the first or second node based on a switching control signal; A first lamp generator that generates a first lamp signal; A second lamp generator that generates a second lamp signal; A first conversion circuit that compares and amplifies the first lamp signal and the signal applied to the first node to generate a first output signal; and An image sensing device including a second conversion circuit that compares and amplifies the second lamp signal and the signal applied to the second node to generate a second output signal.

12. The image sensing device according to claim 11, wherein the first pixel and the second pixel belong to the same row and are arranged adjacent to each other.

13. The first pixel is connected to the first row line, The second pixel is connected to the second row line, The image sensing apparatus according to claim 11, wherein the first row line and the second row line are activated simultaneously.

14. The image sensing device according to claim 11, wherein the first pixel and the second pixel are arranged adjacent to each other in the same row.

15. The image sensing device according to claim 11, wherein the first pixel and the second pixel are activated simultaneously when the first row line is selected.

16. The first lamp generator and the second lamp generator are each, A current generator that produces a reference current; A current control unit that generates a digital-to-analog conversion current based on the aforementioned reference current; A voltage converter that generates a bias voltage based on the aforementioned digital-to-analog conversion current; A ramp signal generator that generates a ramp signal based on the bias voltage and switch control signal; The image sensing device according to claim 11, further comprising a resistor circuit for controlling the loading of the lamp signal.

17. Each of the first and second conversion circuits is: Multiple capacitors are provided at the input terminals of the pixel signal and the ramp signal to reduce the noise bandwidth; A comparator that compares and amplifies the outputs of the aforementioned plurality of capacitors to generate an output signal; and The image sensing apparatus according to claim 11, further comprising a plurality of switching elements that control the auto-zeroing operation of the comparator.

18. The image sensing apparatus according to claim 11, further comprising a counter that counts the first output signal and the second output signal and outputs them as a digital signal.

19. The image sensing apparatus according to claim 11, further comprising a column selection control unit that generates the switching control signal.

20. The image sensing apparatus according to claim 11, further comprising a low driver that generates a low line selection signal for selecting the first pixel and the second pixel.

Images