Imaging device and semiconductor device

Abstract

The present invention relates to an imaging device and a semiconductor device. The imaging device includes a first substrate including one or more pixels; a contact disposed on the first substrate and including a first surface facing the first substrate and a second surface opposite the first surface; a first insulating layer on the first substrate and including an opening above the second surface of the contact; at least one bump pad including a first metal layer disposed in the opening of the first insulating layer and electrically connected to the contact, and a second metal layer on the first metal layer and disposed in the opening of the first insulating layer; a second insulating layer on the first insulating layer and including an opening above the second metal layer; a second substrate including a logic circuit and at least one electrode; and a micro bump electrically connecting the at least one bump pad to the at least one electrode and located in the opening of the second insulating layer.

Description

[0001] This application is a divisional application of patent application No. 201680058117.2, filed on October 7, 2016, entitled "Semiconductor Device and Method for Manufacturing a Semiconductor Device". Technical Field

[0002] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device, and particularly to a semiconductor device and a method for manufacturing such a semiconductor device in which the electrodes of stacked semiconductor elements are electrically interconnected by Sn-based solder.

[0003] Cross-references to related applications

[0004] This application claims priority to Japanese patent application JP2015-207233, filed on October 21, 2015, the entire contents of which are incorporated herein by reference. Background Technology

[0005] In the prior art, during the manufacturing process of a semiconductor device formed by stacked semiconductor elements, a method for forming microbumps made of Sn-based solder (SnAg, etc.) is used when the electrodes of the stacked semiconductor elements are interconnected.

[0006] Figure 1 This paper presents an outline of a method used in the prior art for forming microbumps made of Sn-based solder when stacking semiconductor components.

[0007] like Figure 1 As shown, an opening is formed on one side of the first semiconductor element 1 at the location of the Al pad 2, and Ni or the like is formed there as a barrier metal 3. Microbumps 6 made of Sn-based solder are formed on one side of the second semiconductor element 4, and the barrier metal 3 and the Sn-based solder 6 are connected by diffusion through formic acid reduction.

[0008] Figure 2 The figure shows the theoretical diffusion distances between Sn and various metals that can be used as barrier metals, with time as the horizontal axis (at 200°C). It is clear from this figure that when bonding is performed via diffusion through formic acid reduction, and considering the diffusivity of diffusion into the Sn-based solder, the thickness of the barrier metal 3 should be set to the micrometer (μm) level, and specifically, not less than 3 μm.

[0009] However, in the manufacturing process of semiconductor devices, it is very difficult to make the barrier metal 3 flow at the μm level.

[0010] Furthermore, Patent Literature 1 discloses a die bond technique that employs Ti as a barrier metal for Sn-based solder and forms approximately 200 nanometers (nm) of Ti that can flow in a wafer process using a sputtering technique.

[0011] Bibliographic List

[0012] Patent Literature

[0013] [PTL 1] Japanese Patent Application Laid-Open JP 2006-108604 A SUMMARY

[0014] [PROBLEMS TO BE SOLVED BY THE INVENTION]

[0015] However, in the method disclosed in PTL 1, only the semiconductor elements are physically connected as the die bond technique, and thus it is apparent that a high resistance due to alloy growth and oxidation occurs at the interface between the Sn-based solder and Ti, as the result of a high temperature shelf experiment performed by the applicant of the present application. Therefore, it is understood that, by the method disclosed in PTL 1, although the electrodes of the stacked semiconductor elements can be physically connected to each other, the electrodes are not electrically connected to each other.

[0016] The present application has been obtained under the above-described circumstances, and it is desirable for the present application that the electrodes of the stacked semiconductor elements are electrically connected to each other.

[0017] [TECHNICAL SOLUTION]

[0018] According to some aspects of the present application, there is provided a semiconductor device including: a first semiconductor element including at least one bump pad having a recessed shape, the at least one bump pad including a first metal layer and a second metal layer on the first metal layer; a second semiconductor element including at least one electrode; and a micro bump electrically connecting the at least one bump pad to the at least one electrode. Here, the micro bump includes a diffusion portion of the second metal layer, and the first semiconductor element or the second semiconductor element includes a pixel unit.

[0019] According to some aspects of the present application, there is provided a method for manufacturing a semiconductor device, including: forming at least one contact on a first substrate; forming an insulating layer on the at least one contact; etching the insulating layer to provide at least one opening portion exposing a portion of the at least one contact; forming at least one bump pad in the opening portion, and the at least one bump pad has a recessed shape; and electrically connecting the at least one bump pad to an electrode of a second substrate by diffusing a portion of the at least one bump pad into a micro bump connected with the electrode of the second substrate. Here, the first substrate or the second substrate includes a pixel unit.

[0020] According to a first aspect of the present application, in a semiconductor device formed by stacking semiconductor elements, electrodes of opposing semiconductor elements are electrically connected to each other. In the semiconductor device, a second semiconductor element is one of the opposing semiconductor elements, a micro bump made of Sn-based solder is formed on an electrode of the second semiconductor element; and a first semiconductor element is the other of the opposing semiconductor elements and is connected to the electrode of the second semiconductor element via the micro bump, a recessed bump pad opposite to the micro bump is formed on an electrode of the first semiconductor element.

[0021] On the bump pad, from the micro bump side, a third metal layer diffused into the micro bump, and a second metal layer made of Co can be formed in this order.

[0022] On the first semiconductor element, a plurality of bump pads having different diameters can be provided.

[0023] The diameters of the bump pads can be different from each other according to the use of the electrodes to be connected.

[0024] The diameter of the micro bump of the second semiconductor element can correspond to the diameter of the bump pad of the corresponding first semiconductor element.

[0025] On the bump pad, from the micro bump side, the third metal layer, the second metal layer, and a first metal layer made of TiN can be formed in this order.

[0026] The average thickness of the second metal layer can be set to 15 nm or more.

[0027] The average thickness of the first metal layer can be set to 10 nm or more.

[0028] The first metal layer can be made of TiN, Ta, or TaN.

[0029] The third metal layer can be made of Cu, Ni, Pd, Au, or Pt.

[0030] The bump pad can be formed by an opening portion provided from a surface of the first semiconductor element to a through electrode in the first semiconductor element.

[0031] The bump pad can be formed by an opening portion provided from a surface of the first semiconductor element to a metal wiring in the first semiconductor element.

[0032] The semiconductor device can be a stacked CMOS image sensor in which a logic chip corresponding to the second semiconductor element is connected to a pixel substrate corresponding to the first semiconductor element by CoW connection (chip on wafer connection).

[0033] The manufacturing method according to the second aspect of the present application is a manufacturing method of a manufacturing apparatus for manufacturing a semiconductor device, wherein the semiconductor device is formed of stacked semiconductor elements, and electrodes of opposing semiconductor elements are electrically connected to each other in the semiconductor device. The manufacturing method includes a step of forming a micro bump by the manufacturing apparatus for forming a micro bump made of a Sn-based solder on an electrode of a second semiconductor element, which is one of the opposing semiconductor elements, and a step of forming a bump pad by the manufacturing apparatus for forming a recessed bump pad opposite to the micro bump on an electrode of a first semiconductor element, which is the other of the opposing semiconductor elements and connected to the electrode of the second semiconductor element via the micro bump.

[0034] In the step of forming the bump pad, a second metal layer made of Co can be formed on the electrode of the first semiconductor element, which is the other of the opposing semiconductor elements and connected to the electrode of the second semiconductor element via the micro bump, a third metal layer to be diffused into the micro bump can be formed on the second metal layer, the micro bump is brought into contact with the third metal layer, an oxide film on a surface of the third metal layer and on a surface of the micro bump is reduced by heat treatment in a reducing atmosphere, and the third metal layer is diffused into the micro bump, whereby the micro bump is brought into contact with the second metal layer, and the electrode of the first semiconductor element and the electrode of the second semiconductor element are electrically connected.

[0035] Further, in the step of forming the bump pad, a passivation layer can be formed on the third metal layer of the first semiconductor element, and the passivation layer is etched to provide an opening portion exposing the third metal layer.

[0036] Further, in the step of forming the bump pad, a first metal layer made of TiN can be formed on the electrode of the first semiconductor element which is connected to the electrode of the second conductor element via the micro bump and which is the other of the opposed semiconductor elements, before the second metal layer is formed.

[0037] In the step of forming the bump pad, the bump pad can be formed by providing an opening portion from a surface of the first semiconductor element to a through electrode in the first semiconductor element.

[0038] In the step of forming the bump pad, the bump pad can be formed by providing an opening portion from a surface of the first semiconductor element to a metal wiring in the first semiconductor element.

[0039] [Advantages of the Invention]

[0040] According to the first aspect of the present application, a semiconductor device in which an electrode of a first semiconductor element and an electrode of a second semiconductor element are electrically connected can be obtained.

[0041] According to the second aspect of the present application, a semiconductor device in which an electrode of a first semiconductor element and an electrode of a second semiconductor element are electrically connected can be manufactured. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 is a diagram showing an outline of a method of connecting electrodes of stacked semiconductor elements using a micro bump made of a Sn-based solder.

[0043] Figure 2 is a diagram showing a theoretical diffusion distance between Sn and various metals which can be used as barrier metals, with time as the horizontal axis.

[0044] Figure 3 is a cross-sectional view showing a configuration example of a semiconductor device to which the present application is applied.

[0045] Figure 4 is a flowchart showing a method for manufacturing a semiconductor device in Figure 3

[0046] Figure 5 is a cross-sectional view of a semiconductor device in a manufacturing step.

[0047] Figure 6 is a cross-sectional view of a semiconductor device in a manufacturing step.

[0048] Figure 7 is a diagram showing the results of Kelvin resistance measurement at a high temperature of 150°C for a long time.

[0049] ​Figure 8 is a diagram showing examples of materials and thicknesses of the first, second, and third metal layers.

[0050] Figure 9 is a cross-sectional view of a first modified example of a semiconductor device to which the present application is applied.

[0051] Figure 10 is a cross-sectional view of a second modified example of a semiconductor device to which the present application is applied.

[0052] Figure 11 is a diagram showing a relationship between diameters of bump pads and micro bumps and bump capacitances.

[0053] Figure 12 is a diagram showing a relationship between diameters of bump pads and micro bumps and resistance values.

[0054] Figure 13 is a block diagram showing an application example of the second modified example of the semiconductor device.

[0055] Figure 14 is a cross-sectional view showing a state of a semiconductor device to which the present application is applied before stacking in a case where the semiconductor device is applied to a stacked CMOS image sensor.

[0056] Figure 15 is a cross-sectional view showing a state of a semiconductor device to which the present application is applied after stacking in a case where the semiconductor device is applied to a stacked CMOS image sensor.

[0057] Figure 16 is a cross-sectional view showing a state where I / Os are connected to WB pads formed on a logic chip.

[0058] Figure 17 is a cross-sectional view showing a modified example related to formation of bump pads.

[0059] Figure 18 is a cross-sectional view showing a modified example related to formation of bump pads.

[0060] Figure 19 is a cross-sectional view showing a modified example related to formation of bump pads. DETAILED DESCRIPTION

[0061] Hereinafter, a best mode for carrying out the present application (hereinafter, referred to as an embodiment) will be described in detail with reference to the accompanying drawings.

[0062] <Configuration Example of Semiconductor Device>

[0063] Figure 3This is a cross-sectional view illustrating a construction example of a semiconductor device as an embodiment of the present invention. Note that this figure only shows the side of the first semiconductor element without microbumps, one of the first semiconductor element and the second semiconductor element to be stacked and electrically interconnected by Sn-based solder.

[0064] Meanwhile, Sn-based indicates that the solder material includes SnAg-based, SnBi-based, SnCu-based, SnIn-based, SnAgCu-based, etc.

[0065] As shown in the figure, an Al pad 11 (or contact, or at least one contact) serving as an electrode is provided on the first semiconductor element 10, and a portion of the Al pad 11 is formed into an opening 21 for connection with a microbump on the second semiconductor element. Figure 5 In the opening 21, a first metal layer 13, a second metal layer 14, and a third metal layer 15 are sequentially formed. A SiO2 layer (or insulating layer) 12 is formed on the portion other than the opening 21, and a SiN layer 16 is formed on the SiO2 layer 12. For ease of explanation, layers 13, 14, and 15 are referred to herein as the first, second, and third metal layers, respectively. However, the exemplary embodiments are not limited thereto. For example, depending on the embodiment, the first metal layer 13 may be referred to as the second metal layer or the third metal layer, the second metal layer 14 may be referred to as the first metal layer or the third metal layer, and the third metal layer 15 may be referred to as the first metal layer or the second metal layer. The same principle also applies to other elements in the present invention described as first, second, third, etc.

[0066] The first metal layer 13, serving as the barrier metal, is, for example, TiN. The average thickness of the first metal layer 13 is set to approximately 10 nm or more. This allows the first metal layer 13 to be formed in a wafer fabrication pipeline, where the risk of dust particles can be significantly reduced. The first metal layer can also be Ta or TaN.

[0067] By providing a first metal layer (barrier metal) 13, reactions between the Al pads 11 and the second metal layer 14 can be prevented, as well as reactions between the alloy layer and the Al pads 11 that may occur due to reactions between the Sn-based solder used to form microbumps in the second semiconductor element and the second metal layer 14. Accordingly, it is expected that the reliability and electrical characteristics of the semiconductor device can be improved. Alternatively, the first metal layer 13 can be omitted.

[0068] The second metal layer 14 employs a material with a phase diagram specific to Sn-based solders and low diffusion, such as Co. The average thickness of the second metal layer 14 is set to approximately 15 nm or more. This enables the formation of the second metal layer 14 in a wafer fabrication pipeline, where the risk of dust particles can be significantly reduced.

[0069] The third metal layer 15 employs a material, such as Cu, which can reduce the surface oxide film on the surface of the second metal layer 14 by a non-cleaning flux and a reducing gas, etc., and which has a high diffusivity with respect to Sn. The average thickness of the third metal layer 15 is set to be approximately 80 nm or more, thereby preventing oxidation of the second metal layer 14. In addition to Cu, the third metal layer 15 can employ Ni, Pd, Au, or Pt, etc.

[0070] By employing the above-described configuration, even when the material of the second metal layer 14 employs Co which is extremely easily oxidized and relatively difficult to reduce, the contact (reaction) between the Sn-based solder and the second metal layer 14 becomes easier. In addition, by employing Co as the second metal layer 14, the reliability and the electrical characteristics can be improved.

[0071] <Method for manufacturing semiconductor device>

[0072] Next, a method for manufacturing a semiconductor device shown in Figures 4 to 6 will be described with reference to the accompanying drawings. Figure 3

[0073] Figure 4 is a flowchart showing a method for manufacturing a semiconductor device in Figure 3 . Figure 5 and Figure 6 are cross-sectional views of the semiconductor device showing the manufacturing process.

[0074] In step SI, as shown in A in Figure 5 , a SiO2layer 12 is formed on a first semiconductor element 10 provided with an Al pad 11 as an electrode. Then, on the SiO2layer 12, a resist pattern (not shown) for protecting a portion other than an opening portion 21 is provided in accordance with the position and diameter of the opening portion 21 which will be described later. In addition, as shown in B in Figure 5 , the SiO2layer 12 is ground by dry etching until the Al pad 11 is exposed, thereby providing the opening portion 21.

[0075] In step S2, as shown in C in Figure 5 , a first metal layer (TiN) 13, a second metal layer (Co) 14, and a third metal layer (Cu) 15 are formed by a sputtering method. Then, in step S3, as shown in D in Figure 5 ​As shown in D, the thickness of the third metal layer 15 is increased by electroplating with the same material as the third metal layer 15 (in this case, copper), and the third metal layer 15 fills the recess of the opening 21. In other words, the third metal layer 15 is formed by a first deposition process and a second deposition process. The first deposition process forms a portion of the third metal layer 15 that is in a recessed shape, and the second deposition process forms the remaining portion of the third metal film 15 to fill the recessed shape.

[0076] In step S4, as Figure 5 As shown in E, the third metal layer 15 and the second metal layer 14 on the portion other than the opening 21 are removed or planarized by chemical mechanical polishing (CMP). In step S5, a SiN layer 16 as a passivation layer is formed on the entire surface, and an annealing treatment of, for example, 400°C / 1h is performed to restore Tr damage. Further, a resist pattern (not shown) is formed on the SiN layer 16, and as shown... Figure 6 As shown in Figure A, the SiN layer 16 is ground by dry etching until the third metal layer 15 on the opening 21 is exposed. Accordingly, the opening 21 has a recessed structure to facilitate positioning with respect to the microbump 24 made of Sn-based solder and formed on the second semiconductor element 23. Hereinafter, the opening 21 opposite to the microbump 24 is also referred to as the bump pad 21 (or at least one bump pad).

[0077] In step S6, as Figure 6 As shown in B, the microbumps 24 formed on the second semiconductor element 23 are brought into contact with the third metal layer 15 of the bump pad 21, and the oxide film on the surface of the third metal layer 15 and the surface of the Sn-based solder used to form the microbumps 24 is reduced by heat treatment in a reducing atmosphere such as formic acid. Subsequently, in step S7, as... Figure 6 As shown in C, the third metal layer 15 diffuses into the Sn-based solder, and the Sn-based solder comes into contact (reacts) with the second metal layer 14, thereby establishing a connection between the Al pad 11 of the first semiconductor element 10, which serves as an electrode, and the electrode of the second semiconductor element 23. This concludes the description of the manufacturing method.

[0078] <Kelvin resistance measurement results under high temperature resting time>

[0079] under, Figure 7Kelvin resistance measurement results at 150°C high temperature shelf time when the second metal layer 14 is connected to the micro-bump 24 made of Sn-based solder are shown in the case where the first metal layer 13, the second metal layer 14, and the third metal layer 15 employ TiN, Co, and Cu, respectively.

[0080] As shown in the figure, the resistance value does not change after 504 hours have passed. Thus, the electrical connection between the electrode of the first semiconductor element 10 and the electrode of the second semiconductor element 23 is also maintained over time.

[0081] <Materials and thicknesses of the first metal layer 13, the second metal layer 14, and the third metal layer 15>

[0082] Next, Figure 8 Evaluation in the first to fourth examples and each comparative example (the configuration disclosed in PTL 1) is shown in the case where the thickness of the second metal layer 14 and the material and thickness of the third metal layer 15 are changed.

[0083] In the first example, the first metal layer 13, the second metal layer 14, and the third metal layer 15 employ 20 nm of TiN, 270 nm of Co, and 200 nm of Cu, respectively. In the second example, the first metal layer 13, the second metal layer 14, and the third metal layer 15 employ 20 nm of TiN, 100 nm of Co, and 200 nm of Cu, respectively. In the third example, the first metal layer 13, the second metal layer 14, and the third metal layer 15 employ 20 nm of TiN, 30 nm of Co, and 200 nm of Cu, respectively. In the fourth example, the first metal layer 13, the second metal layer 14, and the third metal layer 15 employ 20 nm of TiN, 270 nm of Co, and 80 nm of Cu, respectively.

[0084] In any of the first to fourth examples, the results of the connectability and high temperature shelf experiments are not problematic, and a physical and electrical connection between the electrode of the first semiconductor element 10 and the electrode of the second semiconductor element 23 is established. Meanwhile, in Comparative Example 1, the first metal layer Ti diffuses into the Co of the second metal layer during the sintering annealing process introduced for Tr damage recovery, thus hindering the connectability with the solder. In Comparative Example 2, the connectability between the first metal layer TiN and the solder is not established. In Comparative Example 3, the connectability with the solder is not ensured even in the case where the second metal layer Co is set to 10 nm.

[0085] <First modification example of the semiconductor device>

[0086] Figure 9 is a cross-sectional view showing a first modification example of the semiconductor device as an embodiment of the present application.

[0087] This first modification example is obtained by omitting the first metal layer 13 from the configuration example in Figure 3 Accordingly, the process cycle time can be shortened, and the cost can be reduced.

[0088] <Second Modification Example of Semiconductor Device>

[0089] Next, Figure 10 is a sectional view showing a second modification example of a semiconductor device as an embodiment of the present application.

[0090] The second modification example is obtained by changing the diameter of the bump pad 21 provided on the first semiconductor element 10 according to the purpose of the electrode (wire) to be connected. The two bump pads 21 provided on the first semiconductor element 10 are formed so that the bump pad 21-2 has a larger diameter than the diameter of the bump pad 21-1.

[0091] Further, the diameter of the plurality of bump pads 21 provided on the same substrate (in this case, the first semiconductor element 10) can be easily changed by changing the resist pattern provided on the SiO2 layer 12 in step S1 of the above manufacturing process and the resist pattern provided on the SiN layer 16 in step S5.

[0092] On the other hand, the diameter of the micro bump 24 made of Sn-based solder of the second semiconductor element is also changed according to the diameter of the corresponding bump pad 21.

[0093] <Change in Bump Capacitance According to Difference in Diameter of Bump Pad 21 and Micro Bump 24>

[0094] Figure 11 The change in the bump capacitance according to the difference in the diameter of the bump pad 21 (opening diameter) and the diameter of the micro bump is shown.

[0095] As shown in the graph, when the case where the bump pad 21 and the micro bump 24 have a small diameter is compared with the case where the bump pad 21 and the micro bump 24 have a large diameter, the bump capacitance is smaller in the case where the bump pad 21 and the micro bump 24 have a small diameter. Therefore, when the signal line is connected by using the bump pad 21 and the micro bump 24 having a small diameter, it is expected that the signal characteristics of the electrical signal for communication can be improved. In addition, in this case, the arrangement of the wiring to be connected is easy.

[0096] <Change in Resistance Value According to Difference in Diameter of Bump Pad 21 and Micro Bump 24>

[0097] Figure 12 The change in the resistance value according to the difference in the diameter of the bump pad 21 (opening diameter) and the diameter of the micro bump 24 is shown.

[0098] As shown in the drawing, the greater the diameters of the bump pad 21 and the micro bump 24, the smaller the resistance value. Therefore, when the power supply line is connected by using the bump pad 21 and the micro bump 24 having a large diameter, it is possible to prevent defects related to power supply such as IR drop.

[0099] <Application example of the second modification example of the semiconductor device>

[0100] Next, Figure 13 An application example of the second configuration example shown in the drawing is shown. Figure 10 An application example of the second configuration example shown in the drawing is shown.

[0101] In this application example, the power supply line 35 for connecting the power supply unit 31 of the first semiconductor element 10 and the power supply unit 33 of the second semiconductor element 23 is connected by using the bump pad 21-2 and the micro bump 24 having a large diameter. In addition, the signal lines 36 and 37 for connecting the signal processor 32 of the first semiconductor element 10 and the signal processor 34 of the second semiconductor element 23 are connected by using the bump pad 21-1 and the micro bump 24 having a small diameter.

[0102] According to Figure 13 According to the application example shown in the drawing, it is possible to improve the signal characteristics of the electrical signal that communicates between the first semiconductor element 10 and the second semiconductor element 23, and it is possible to suppress defects related to power supply such as IR drop.

[0103] <Application example of the semiconductor device>

[0104] Next, a configuration example of a semiconductor device according to an embodiment of the present application when applied to a stacked CMOS image sensor (hereinafter, referred to as a stacked CIS) will be described.

[0105] Figure 14 A state of a stacked CIS to which a semiconductor device according to an embodiment of the present application is applied before stacking is shown, and Figure 15 A state of the stacked CIS after stacking is shown.

[0106] That is, the stacked CIS is formed to have a form in which a pixel unit for performing photoelectric conversion is formed on a pixel substrate 51, and a logic chip 52 for processing a pixel signal output from the pixel substrate 51 is stacked on the pixel substrate 51 by chip on wafer (CoW) connection.

[0107] The pixel substrate 51 corresponds to the first semiconductor element 10, and the bump pads 21 to be connected to the micro bumps 24 of the logic chip 52 are formed on the surface of the pixel substrate 51 on the light incident side. On the other hand, the logic chip 52 corresponds to the second semiconductor element 23, and the micro bumps 24 are formed on the surface of the logic chip 52 to be connected to the pixel substrate 51.

[0108] In a state where the bump pads 21 and the micro bumps 24 are stacked in contact with each other, the pixel substrate 51 and the logic chip 52 are subjected to heat treatment so as to electrically connect the pixel substrate 51 and the logic chip 52 to each other. At the same time, as shown in FIG. 6, the WB pads 71 are formed on the surface of the logic chip 52 opposite to the surface to be connected to the pixel substrate 51, and the I / Os 72 are connected to the WB pads 71. Figure 16

[0109] As shown in the drawing, by applying the semiconductor device according to the embodiment of the present application to a stacked CMOS image sensor, it is possible to prevent damage such as a dust defect in the pixel unit, which occurs when the micro bumps are also formed on the pixel substrate 51 side for connection. In addition, the height at which the pixel substrate 51 and the logic chip 52 are stacked can be reduced, and it is possible to prevent sweeping unevenness of the CF.

[0110] <Modification example related to formation of bump pad>

[0111] Next, a modification example related to the formation of the bump pad will be described.

[0112] Figure 17 A modification example is shown in which, in a case where a through electrode 81 is formed in the pixel substrate 51, an opening portion 21 is formed at the position of the through electrode 81, and the through electrode 81 becomes a bump pad corresponding to the micro bump 24 of the logic chip 52. When the through electrode 81 itself becomes a bump pad, the formation of the first, second, and third metal layers 13 to 15 can be omitted.

[0113] Figure 18 And Figure 19 A modification example is shown in which the Al pad 11 is omitted from the pixel substrate 51 (the first semiconductor element 10), an opening portion 21 is formed to reach a metal wiring (Cu wiring) 91 in the pixel substrate 51, and the metal wiring 91 in the pixel substrate becomes a bump pad corresponding to the micro bump 24 of the logic chip 52.

[0114] ​In a case where the Al pad 11 is omitted and the metal wiring 91 in the pixel substrate 51 becomes a bump pad, sweep unevenness in a custom process can be improved, and chip shrink can be achieved. In addition, the height of the logic chip 52 can also be reduced.

[0115] In addition, the semiconductor device according to the embodiment of the present application can be applied to all types of electronic devices in which electrodes of semiconductor elements to be stacked are connected to each other, in addition to the above-described stacked CIS.

[0116] The embodiments of the present application are not limited to the above-described embodiments, and the embodiments of the present application can be variously changed without departing from the scope of the present application.

[0117] Meanwhile, the present application can be designed as the following technical solutions.

[0118] (1) A semiconductor device having a first semiconductor element including at least one bump pad having a recessed shape, wherein the at least one bump pad includes a first metal layer and a second metal layer on the first metal layer. The semiconductor device includes a second semiconductor element including at least one electrode. The semiconductor device includes a micro bump electrically connecting the at least one bump pad and the at least one electrode, wherein the micro bump includes a diffusion portion of the second metal layer, and wherein the first semiconductor element or the second semiconductor element includes a pixel unit.

[0119] (2) The semiconductor device according to the above (1),

[0120] wherein the micro bump includes a Sn-based solder, and the first metal layer includes Co.

[0121] (3) The semiconductor device according to the above (1) or (2),

[0122] wherein the at least one bump pad includes a plurality of bump pads having different diameters, and

[0123] wherein the at least one electrode includes a plurality of electrodes corresponding to the plurality of bump pads.

[0124] (4) The semiconductor device according to any one of the above (1) to (3),

[0125] wherein the different diameters are different from each other according to uses of the plurality of electrodes to be connected.

[0126] (5) The semiconductor device according to any one of (1) to (4) above,

[0127] wherein a diameter of the micro bump corresponds to a diameter of the at least one bump pad.

[0128] (6) The semiconductor device according to any one of (1) to (5) above,

[0129] wherein the at least one bump pad includes a third metal layer, and

[0130] wherein the first metal layer is on the third metal layer.

[0131] (7) The semiconductor device according to any one of (1) to (6) above,

[0132] wherein an average thickness of the first metal layer is 15 nm or more.

[0133] (8) The semiconductor device according to any one of (1) to (7) above,

[0134] wherein an average thickness of the third metal layer is 10 nm or more.

[0135] (9) The semiconductor device according to any one of (1) to (8) above,

[0136] wherein the third metal layer is formed of TiN, Ta, or TaN.

[0137] (10) The semiconductor device according to any one of (1) to (9) above,

[0138] wherein the second metal layer is formed of Cu, Co, Ni, Pd, Au, or Pt.

[0139] (11) The semiconductor device according to (1) above,

[0140] wherein the at least one bump pad is an opening portion provided on a surface of the first semiconductor element for connecting the micro bump to a through electrode in the first semiconductor element.

[0141] (12) The semiconductor device according to (1) above,

[0142] wherein the at least one bump pad is an opening portion provided on a surface of the first semiconductor element for connecting the micro bump to a metal wiring in the first semiconductor element.

[0143] (13) The semiconductor device according to (1) above,

[0144] The first semiconductor element is the pixel unit, and the second semiconductor element is a logic chip connected to the first semiconductor element by a chip-on-wafer connection (CoW connection).

[0145] (14) A method for manufacturing a semiconductor device, comprising:

[0146] forming at least one contact on a first substrate;

[0147] forming an insulating layer on the at least one contact;

[0148] etching the insulating layer to provide at least one opening portion exposing a portion of the at least one contact;

[0149] forming at least one bump pad in the opening portion, and the at least one bump pad has a recessed shape; and

[0150] electrically connecting the at least one bump pad to an electrode of a second substrate by diffusing a portion of the at least one bump pad into a micro bump connected to the electrode of the second substrate.

[0151] (15) The method according to the above (14), wherein the step of forming the at least one bump pad comprises:

[0152] forming a first metal layer on the at least one contact; and

[0153] forming a second metal layer on the first metal layer,

[0154] wherein the diffused portion of the at least one bump pad comprises the second metal layer.

[0155] (16) The method according to the above (15), wherein the step of forming the second metal layer comprises:

[0156] forming a portion of the second metal layer according to a first deposition process, the portion being a recessed shape; and

[0157] forming a remaining portion of the second metal layer according to a second deposition process to fill the recessed shape.

[0158] (17) The method according to the above (15), wherein the step of forming the at least one bump pad comprises:

[0159] forming a third metal layer on the insulating layer before forming the first metal layer and the second metal layer.

[0160] (18) The method according to the above (17), wherein the step of forming the at least one bump pad comprises:

[0161] planarizing the first metal layer, the second metal layer, and the third metal layer, thereby making upper surfaces of the first metal layer, the second metal layer, and the third metal layer coplanar with an upper surface of the insulating layer.

[0162] (19) The method according to the above (18),

[0163] wherein the second metal layer diffuses into the micro-bump such that a top portion of the micro-bump extends beyond the upper surface of the insulating layer, while other portions of the micro-bump are present in a space between the upper surface of the insulating layer and the electrode.

[0164] (20) The method according to the above (18), wherein the step of forming the at least one bump pad comprises:

[0165] forming a passivation layer on the insulating layer and the first metal layer, the second metal layer, and the third metal layer; and

[0166] etching the passivation layer to expose the second metal layer and create a recessed shape.

[0167] (21) A semiconductor device formed of stacked semiconductor elements, wherein electrodes of opposing semiconductor elements are electrically connected to each other,

[0168] wherein a second semiconductor element is one of the opposing semiconductor elements, a micro-bump made of a Sn-based solder is formed on an electrode of the second semiconductor element, and,

[0169] a first semiconductor element is the other of the opposing semiconductor elements and is connected to the electrode of the second semiconductor element via the micro-bump, and a recessed bump pad opposing the micro-bump is formed on an electrode of the first semiconductor element.

[0170] (22) The semiconductor device according to the above (21),

[0171] wherein on the bump pad, a third metal layer that diffuses into the micro-bump and a second metal layer made of Co are formed in this order from the micro-bump side.

[0172] (23) The semiconductor device according to the above (21) or (22),

[0173] wherein a plurality of bump pads having different diameters are provided on the first semiconductor element.

[0174] (24) The semiconductor device according to any one of the above (21) to (23),

[0175] wherein diameters of the bump pads are different from each other according to uses of the electrodes to be connected.

[0176] (25) The semiconductor device according to any one of (21) to (24) above,

[0177] wherein diameters of the micro-bumps of the second semiconductor elements correspond to diameters of the bump pads of the respective first semiconductor elements.

[0178] (26) The semiconductor device according to any one of (21) to (25) above,

[0179] wherein the third metal layer, the second metal layer, and a first metal layer formed of TiN are formed in this order on the bump pad from the side of the micro-bump.

[0180] (27) The semiconductor device according to any one of (21) to (26) above,

[0181] wherein an average thickness of the second metal layer is 15 nm or more.

[0182] (28) The semiconductor device according to any one of (21) to (27) above,

[0183] wherein an average thickness of the first metal layer is 10 nm or more.

[0184] (29) The semiconductor device according to any one of (21) to (28) above,

[0185] wherein the first metal is formed of TiN, Ta, or TaN.

[0186] (30) The semiconductor device according to any one of (21) to (29) above,

[0187] wherein the third metal layer is formed of Cu, Ni, Pd, Au, or Pt.

[0188] (31) The semiconductor device according to (21) above,

[0189] wherein the bump pad is formed by an opening portion provided from a surface of the first semiconductor element to a through electrode in the first semiconductor element.

[0190] (32) The semiconductor device according to (21) above,

[0191] wherein the bump pad is formed by an opening portion provided from a surface of the first semiconductor element to a metal wiring in the first semiconductor element.

[0192] (33) The semiconductor device according to the above (21), which is a stacked CMOS image sensor, wherein a logic chip corresponding to the second semiconductor element is connected to a pixel substrate corresponding to the first semiconductor element by CoW connection.

[0193] (34) A manufacturing method of a manufacturing apparatus for manufacturing a semiconductor device formed of stacked semiconductor elements in which electrodes of the opposing semiconductor elements are electrically connected to each other, the manufacturing method comprising:

[0194] a step of forming a micro bump by the manufacturing apparatus for forming a micro bump made of a Sn-based solder on an electrode of a second semiconductor element which is one of the opposing semiconductor elements; and

[0195] a step of forming a bump pad by the manufacturing apparatus for forming a recessed bump pad opposite to the micro bump on an electrode of a first semiconductor element which is the other of the opposing semiconductor elements and connected to the electrode of the second semiconductor element via the micro bump.

[0196] (35) The manufacturing method according to the above (34), wherein, in the step of forming the bump pad,

[0197] a second metal layer formed of Co is formed on the electrode of the first semiconductor element which is the other of the opposing semiconductor elements and connected to the electrode of the second semiconductor element via the micro bump;

[0198] a third metal layer to be diffused into the micro bump is formed on the second metal layer; and

[0199] the micro bump is brought into contact with the third metal layer, an oxide film on a surface of the third metal layer and on a surface of the micro bump is reduced by heat treatment in a reducing atmosphere, and the third metal layer is diffused into the micro bump, whereby the micro bump is brought into contact with the second metal layer, and the electrode of the first semiconductor element and the electrode of the second semiconductor element are electrically connected.

[0200] (36) The manufacturing method according to the above (35), wherein, in the step of forming the bump pad,

[0201] a passivation layer is further formed on the third metal layer of the first semiconductor element, and the passivation layer is etched to provide an opening portion exposing the third metal layer.

[0202] (37) The manufacturing method according to the above (35), wherein, in the step of forming the bump pad,

[0203] A first metal layer formed of TiN is also formed on the electrode of the first semiconductor element, which is the other of the opposing semiconductor elements, and which is connected to the electrode of the second semiconductor element via the micro bump, before the second metal layer is formed.

[0204] (38) The manufacturing method according to the above (34), wherein, in the step of forming the bump pad,

[0205] The bump pad is formed by providing an opening portion from a surface of the first semiconductor element to a through electrode in the first semiconductor element.

[0206] (39) The manufacturing method according to the above (34), wherein, in the step of forming the bump pad,

[0207] The bump pad is formed by providing an opening portion from a surface of the first semiconductor element to a metal wiring in the first semiconductor element.

[0208] List of Reference Numerals

[0209] 10 first semiconductor element

[0210] 11 Al pad

[0211] 12 SiO2 layer

[0212] 13 first metal layer

[0213] 14 second metal layer

[0214] 15 third metal layer

[0215] 16 SiN layer

[0216] 21 opening portion (bump pad)

[0217] 23 second semiconductor element

[0218] 24 micro bump

[0219] 31 power supply unit

[0220] 32 signal processor

[0221] 33 power supply unit

[0222] 34 signal processor

[0223] 35 power supply line

[0224] 36, 37 signal line

[0225] 51 pixel substrate

[0226] 52 logic chip

[0227] 81 through electrode

[0228] 91 Cu wiring

Claims

1. An imaging device comprising: a first substrate including one or more pixels; a contact disposed on the first substrate and including a first surface facing the first substrate and a second surface opposite the first surface; a first insulating layer on the first substrate and including an opening over the second surface of the contact; at least one bump pad including: a first metal layer disposed in the opening of the first insulating layer and electrically connected to the contact; a second metal layer on the first metal layer and disposed in the opening of the first insulating layer; and a third metal layer disposed in the opening of the first insulating layer and the first metal layer is on the third metal layer; a second insulating layer on the first insulating layer and including an opening over the second metal layer; a second substrate including a logic circuit and at least one electrode; and a micro bump electrically connecting the at least one bump pad to the at least one electrode and located in the opening of the second insulating layer, wherein the micro bump includes a diffusion portion of the second metal layer, and wherein the micro bump includes a Sn-based solder and the first metal layer includes Co, a diffusivity of the second metal layer to the micro bump is higher than a diffusivity of the first metal layer to the micro bump.

2. The imaging device according to claim 1, wherein, the at least one bump pad includes a plurality of bump pads having different diameters, and wherein the at least one electrode includes a plurality of electrodes corresponding to the plurality of bump pads.

3. The imaging device according to claim 2, wherein the different diameters are different from each other according to a use of the plurality of electrodes to be connected to the corresponding bump pads.

4. The imaging device according to claim 1 or 2, wherein, a diameter of the micro bump corresponds to a diameter of the at least one bump pad.

5. The imaging device according to claim 1 or 2, wherein an average thickness of the first metal layer is 15 nm or more.

6. The imaging device according to claim 1 or 2, wherein an average thickness of the third metal layer is 10 nm or more.

7. The imaging device according to claim 1 or 2, wherein, the third metal layer includes TiN, Ta, or TaN.

8. The imaging device according to claim 1 or 2, wherein the second metal layer includes Cu, Ni, Pd, Au, or Pt.

9. The imaging device according to claim 1 or 2, wherein, a surface of the second metal layer is coplanar with a surface of the first insulating layer.

10. The imaging device according to claim 1 or 2, wherein, the first insulating layer contacts the second surface of the contact.

11. The imaging device according to claim 1 or 2, wherein the at least one bump pad is disposed outside of an area of the first substrate including the one or more pixels.

12. A semiconductor device comprising: a first substrate; a contact disposed on the first substrate and including a first surface facing the first substrate and a second surface opposite the first surface; a first insulating layer on the first substrate and including an opening over the second surface of the contact; at least one bump pad including: a first metal layer disposed in the opening of the first insulating layer and electrically connected to the contact; a second metal layer on the first metal layer and disposed in the opening of the first insulating layer; and a third metal layer disposed in the opening of the first insulating layer and the first metal layer on the third metal layer; a second insulating layer on the first insulating layer and including an opening over the second metal layer; a second substrate including at least one electrode; and a micro bump electrically connecting the at least one bump pad to the at least one electrode and located in the opening of the second insulating layer, wherein the micro bump includes a diffusion portion of the second metal layer, and wherein the micro bump includes a Sn-based solder and the first metal layer includes Co, diffusion of the second metal layer to the micro bump is higher than diffusion of the first metal layer to the micro bump.

13. The semiconductor device according to claim 12, wherein, the at least one bump pad includes a plurality of bump pads having different diameters, and wherein the at least one electrode includes a plurality of electrodes corresponding to the plurality of bump pads.

14. The semiconductor device according to claim 13, wherein, the different diameters are different from each other according to uses of the plurality of electrodes to be connected to the corresponding bump pads.

15. The semiconductor device according to claim 12 or 13, wherein a diameter of the micro bump corresponds to a diameter of the at least one bump pad.

16. The semiconductor device according to claim 12 or 13, wherein an average thickness of the first metal layer is 15 nm or more.

Images