An enhanced SiC heterojunction transistor epitaxial structure and preparation method thereof

Abstract

The present invention discloses an enhancement-mode SiC heterojunction transistor epitaxial structure and a preparation method thereof. The enhancement-mode SiC heterojunction transistor epitaxial structure comprises, from bottom to top, a SiC substrate layer, an N-type highly doped 4H-SiC buffer layer, an N-type lowly doped 4H-SiC buffer layer, a V-doped high-resistance 4H-SiC buffer layer, a V-doped high-resistance 4H-SiC drift layer, a 4H-SiC channel layer, a 3C-SiC barrier layer, and a P-type 3C-SiC layer. An enhancement-mode device is formed by growing a P-type 3C-SiC on a depletion-mode 4H-SiC / 3C-SiC heterojunction, thereby improving device reliability.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology and relates to an enhanced SiC heterojunction transistor epitaxial structure and a preparation method thereof. Background Art

[0002] The third generation of wide bandgap semiconductor materials represented by SiC have the characteristics of wide bandgap, high critical breakdown electric field, high thermal conductivity, high carrier saturation drift, etc., and are particularly suitable for the production of high temperature, high voltage, high frequency, high power, radiation-resistant and other semiconductor devices.

[0003] Among SiC polytypes, 3C-SiC, 4H-SiC, and 6H-SiC are the most widely used. The band gap of 3C-SiC is 2.3eV, and the band gap of 4H-SiC is as high as 3.2eV, with a band gap difference of 0.9eV. Due to the large difference in band gaps, the heterojunction device formed by 3C-SiC and 4H-SiC has great potential.

[0004] However, when a 3C-SiC / 4H-SiC heterojunction structure is applied to a field-effect transistor device, in the off state, with the device source grounded, the gate negatively charged, and the drain positively charged, the leakage path of the device bulk material primarily passes vertically through the 4H-SiC epitaxial layer and then horizontally through the interface between the 4H-SiC substrate and the 4H-SiC epitaxial buffer layer. Therefore, conventional growth of 3C-SiC / 4H-SiC heterojunction structures is based on semi-insulating substrates. However, semi-insulating SiC substrates are expensive, so using relatively inexpensive, highly doped conductive SiC substrates is the future development direction.

[0005] However, currently, highly doped conductive SiC substrates all have small facet growth and large substrate concentration non-uniformity, such as Figure 3 As shown. The small facet is the part of the growth interface parallel to the (0001) plane. Step flow growth cannot be carried out on the small facet, and the (0001) plane is also the crystal plane that is most easily nitrogen-doped, so it will appear darker in color on the substrate. The depth of the color on the substrate is mainly determined by the nitrogen content. The darker the color, the higher the nitrogen content and the lower the resistivity. Therefore, the leakage current of the 3C-SiC / 4H-SiC heterojunction device made of the epitaxial layer grown on the small facet is much greater than that of the normal crystal facet. Therefore, there is an urgent need to improve the compressive strength of the 4H-SiC epitaxial layer.

[0006] Typically, when the 4H-SiC / 3C-SiC heterojunction is prepared, a high-density two-dimensional electron gas conduction channel has already been formed. Field-effect transistor devices made from such materials are all depletion-mode devices. They can only be turned off when a negative bias is applied to the gate. They are normally-on devices and have been plagued by reliability issues. Summary of the Invention

[0007] To solve the above technical problems, the present invention provides an enhancement-mode SiC heterojunction transistor epitaxial structure and a preparation method thereof, wherein an enhancement-mode device is formed by growing a P-type 3C-SiC on a depletion-mode 4H-SiC / 3C-SiC heterojunction, thereby improving device reliability.

[0008] The technical solution adopted by the present invention is as follows:

[0009] An enhanced SiC heterojunction transistor epitaxial structure comprises, from bottom to top, a SiC substrate layer, an N-type highly doped 4H-SiC buffer layer, an N-type low-doped 4H-SiC buffer layer, a V-doped high-resistance 4H-SiC buffer layer, a V-doped high-resistance 4H-SiC drift layer, a 4H-SiC channel layer, a 3C-SiC barrier layer, and a P-type 3C-SiC layer.

[0010] The substrate layer is a positive-axis N-type SiC substrate layer.

[0011] The thickness of the N-type highly doped 4H-SiC buffer layer is 0.5 to 1 μm, and the N doping concentration is 5×10 17 cm -3 ~2×10 18 cm -3 .

[0012] The thickness of the N-type low-doped 4H-SiC buffer layer is 1-2 μm, and the N doping concentration is 8×10 15 cm -3 ~2×10 16 cm -3 .

[0013] The thickness of the V-doped high-resistance 4H-SiC buffer layer is 5 to 10 μm; the V doping concentration is 1×10 15 cm -3 ~5×10 15 cm -3 .

[0014] The thickness of the V-doped high-resistance 4H-SiC drift layer is 5 to 10 μm; the V doping concentration is 1×10 16 cm -3 ~5×10 16 cm -3 .

[0015] The thickness of the 4H-SiC channel layer is 1-2 μm.

[0016] The thickness of the 3C-SiC barrier layer is 5-10 μm.

[0017] The thickness of the P-type 3C-SiC layer is 0.2-1 μm.

[0018] The present invention also provides a method for preparing the enhanced SiC heterojunction transistor epitaxial structure, comprising the following steps:

[0019] (1) in-situ etching of the SiC substrate to obtain a SiC substrate layer;

[0020] (2) growing an N-type highly doped 4H-SiC buffer layer on the SiC substrate layer;

[0021] (3) growing an N-type low-doped 4H-SiC buffer layer on the N-type highly-doped 4H-SiC buffer layer;

[0022] (4) growing a V-doped high-resistance 4H-SiC buffer layer on the N-type low-doped 4H-SiC buffer layer;

[0023] (5) growing a V-doped high-resistance 4H-SiC drift layer on the V-doped high-resistance 4H-SiC buffer layer;

[0024] (6) growing a 4H-SiC channel layer on the V-doped high-resistance 4H-SiC epitaxial layer;

[0025] (7) growing a 3C-SiC barrier layer on the 4H-SiC channel layer;

[0026] (8) A P-type 3C-SiC layer is grown on the 3C-SiC barrier layer.

[0027] The growth method of the V-doped high-resistance 4H-SiC buffer layer is as follows: introducing carrier gas H2, chlorine-containing silicon source gas, carbon source and VCl4 at flow rates of 160-240 slm, 80-500 sccm, 80-500 sccm and 5-20 sccm respectively, and growing at a temperature of 1700-1750°C and a pressure of 50-200 mbar.

[0028] The growth method of the V-doped high-resistance 4H-SiC drift layer is as follows: introducing carrier gas H2, chlorine-containing silicon source gas, carbon source and VCl4 at flow rates of 160-240 slm, 80-500 sccm, 80-500 sccm and 30-60 sccm respectively, and growing at a temperature of 1700-1750°C and a pressure of 50-200 mbar.

[0029] The present invention also provides a device containing the enhanced SiC heterojunction transistor epitaxial structure, in which a source electrode, a Schottky contact gate electrode, a drain electrode, and a SiN isolation layer are arranged on the 3C-SiC barrier layer of the enhanced SiC heterojunction high electron mobility transistor epitaxial structure; the source electrode and the drain electrode are respectively located on both sides of the Schottky contact gate electrode; a SiN isolation layer is arranged between the source electrode and the Schottky contact gate electrode; and a SiN isolation layer is arranged between the Schottky contact gate electrode and the drain electrode.

[0030] The enhanced SiC heterojunction transistor epitaxial structure device provided by the present invention is based on a depletion-mode device and is turned off in a zero-bias state by reducing the density of the two-dimensional electron gas in the channel. That is, it does not require negative electrode voltage drive in a non-working state. This can greatly reduce the additional power loss of the circuit and improve the reliability of the device.

[0031] In the enhanced SiC heterojunction transistor epitaxial structure provided by the present invention, V is doped in both the 4H-SiC buffer layer and the 4H-SiC drift layer to serve as a high-resistance buffer layer and a high-resistance epitaxial layer, thereby reducing leakage channels and avoiding device failure caused by large leakage current in the small growth area of ​​the substrate.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] 1. The present invention adopts a 3C / 4H-SiC heterojunction structure in the epitaxial structure of an enhanced SiC heterojunction transistor. The 3C / 4H-SiC heterojunction is a heterojunction composed of the same elemental materials but different crystal forms. This novel heterojunction structure can easily avoid the interface state problem that is difficult to solve in the heterojunction structure formed by traditional AlGaN / GaN. The interface state is mainly caused by lattice mismatch. For most different crystal forms of the same material, the lattice mismatch between the (111) plane of the cubic crystal form and the (0001) plane of the hexagonal crystal form is negligible. Therefore, the epitaxial structure of the enhanced SiC heterojunction transistor provided by the present invention has high electron mobility.

[0034] 2. In the epitaxial structure of the enhanced SiC heterojunction transistor, the present invention selects a positive-axis N-type SiC carbon-surface substrate as the SiC substrate layer, which is cheaper than a semi-insulating substrate; and arranges an N-type highly doped 4H-SiC buffer layer on the positive-axis N-type SiC carbon-surface substrate to buffer the mismatch stress generated by the concentration difference between the substrate and the epitaxial layer; and arranges an N-type low-doped 4H-SiC buffer layer on the N-type highly doped 4H-SiC buffer layer. The N-doped SiC lattice shrinks, while the V-doped SiC lattice expands. The presence of the N-type low-doped 4H-SiC buffer layer can buffer the mismatch stress generated by the V-doped SiC layer arranged on the N-type highly doped 4H-SiC buffer layer. The high-resistance layer has a lattice mismatch; a V-doped high-resistance 4H-SiC drift layer is arranged on the V-doped high-resistance 4H-SiC buffer layer to block reverse breakdown and serve as a voltage-resistant layer; a 4H-SiC channel layer is arranged thereon as an intrinsic SiC layer to reduce the influence of interface roughness scattering and defect scattering; a 3C-SiC barrier layer is then arranged on the 4H-SiC channel layer to form a 4H-SiC / 3C-SiC heterojunction structure; and a P-type 3C-SiC layer is then arranged on the 3C-SiC barrier layer to form an enhancement-mode SiC heterojunction transistor epitaxial structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1A structural diagram of the epitaxial structure of an enhancement-mode SiC heterojunction transistor;

[0036] Figure 2 Schematic diagram of leakage channel when the enhancement mode SiC heterojunction transistor epitaxial structure is applied to field effect transistor devices;

[0037] Figure 3 Schematic diagram of facet growth of highly doped conductive SiC substrate;

[0038] In the figure, 1-SiC substrate layer, 2-N-type highly doped 4H-SiC buffer layer, 3-N-type low-doped 4H-SiC buffer layer, 4-V-doped high-resistance 4H-SiC buffer layer, 5-V-doped high-resistance 4H-SiC drift layer, 6-4H-SiC channel layer, 7-3C-SiC barrier layer, 8-P-type 3C-SiC layer, 9-source, 10-drain, 11-Schottky contact gate, 12-SiN isolation layer. DETAILED DESCRIPTION

[0039] An enhanced SiC heterojunction high electron mobility transistor epitaxial structure comprises, from bottom to top, a SiC substrate layer, an N-type highly doped 4H-SiC buffer layer, an N-type low-doped 4H-SiC buffer layer, a V-doped high-resistance 4H-SiC buffer layer, a V-doped high-resistance 4H-SiC drift layer, a 4H-SiC channel layer, a 3C-SiC barrier layer, and a P-type 3C-SiC layer.

[0040] The method for preparing the enhanced SiC heterojunction high electron mobility transistor epitaxial structure comprises the following steps:

[0041] 1) In-situ etching of SiC substrate: Select a positive axis N-type SiC carbon surface substrate, introduce H2 at a flow rate of 160-240 slm and HCl at a flow rate of 30-100 sccm, and etch at a pressure of 50-200 mbar and a temperature of 1450-1500°C for 10-30 minutes;

[0042] 2) Growth of N-type highly doped 4H-SiC buffer layer: Stop the HCl flow and introduce carrier gas H2, chlorine-containing silicon source gas, carbon source and N2 at flow rates of 160-240 slm, 80-500 sccm, 80-500 sccm and 40-100 sccm, respectively. Grow a 0.5-1 μm thick N-type highly doped 4H-SiC buffer layer at a temperature of 1580-1700°C and a pressure of 50-200 mbar. The doping concentration is 5×10 17 cm -3 ~2×10 18 cm -3; The chlorine-containing silicon source gas is SiCl4, SiHCl3, SiH2C12 or SiH3Cl;

[0043] 3) Growth of N-type low-doped 4H-SiC buffer layer: H2 carrier gas, chlorine-containing silicon source gas, carbon source gas and N2 were introduced at flow rates of 160-240 slm, 80-500 sccm, 80-500 sccm and 5-10 sccm, respectively, at a temperature of 1580-1650°C and a pressure of 50-200 mbar to grow a 1-2 μm thick N-type low-doped 4H-SiC buffer layer with a doping concentration of 8×10 15 cm -3 ~2×10 16 cm -3 ; The chlorine-containing silicon source gas is SiCl4, SiHCl3, SiH2C12 or SiH3Cl;

[0044] 4) Growth of V-doped high-resistance 4H-SiC buffer layer: N2 was turned off, and carrier gas H2, chlorine-containing silicon source gas, carbon source and VCl4 were introduced at flow rates of 160-240 slm, 80-500 sccm, 80-500 sccm and 5-20 sccm, respectively. At a temperature of 1700-1750°C and a pressure of 50-200 mbar, a 5-10 μm thick doped semi-insulating 4H-SiC high-resistance layer was grown, with a doping concentration of 1×10 15 cm -3 ~5×10 15 cm -3 ;

[0045] 5) Growth of V-doped high-resistance 4H-SiC drift layer: N2 was turned off, and carrier gas H2, chlorine-containing silicon source gas, carbon source, and VCl4 were introduced at flow rates of 160-240 slm, 80-500 sccm, 80-500 sccm, and 30-60 sccm, respectively. A 5-10 μm thick doped semi-insulating 4H-SiC high-resistance layer was grown at a temperature of 1700-1750°C and a pressure of 50-200 mbar. The doping concentration was 1×10 16 cm -3 ~5×10 16 cm -3 ;

[0046] 6) Growth of 4H-SiC channel layer: Turn off VCl4, introduce carrier gas H2, chlorine-containing silicon source gas, and carbon source at flow rates of 160-240 slm, 80-500 sccm, and 80-500 sccm, respectively, at a temperature of 1580-1650°C and a pressure of 50-200 mbar to grow a 1-2 μm thick 4H-SiC channel layer;

[0047] 7) 3C-SiC barrier layer growth: H2, silicon source, carbon source, and N2 are introduced at flow rates of 160-240 slm, 100-500 sccm, 100-500 sccm, and 15-50 sccm, respectively, at a temperature of 1400-1500°C and a pressure of 200-500 mbar to grow a 5-10 μm thick 3C-SiC epitaxial layer;

[0048] 8) Growth of a p-type 3C-SiC layer: introducing H2, a silicon source, a carbon source, and TMAl at flow rates of 160-240 slm, 100-500 sccm, 100-500 sccm, and 20-60 sccm, respectively, at a temperature of 1550-1650°C and a pressure of 200-500 mbar to grow a p-type 3C-SiC layer with a thickness of 0.2-1 μm;

[0049] 9) Cooling to room temperature under H2 protection;

[0050] In the above steps, the chlorine-containing silicon source gas is SiCl4, SiHCl3, SiH2C12 or SiH3Cl.

[0051] The present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0052] Example 1

[0053] An enhanced SiC heterojunction high electron mobility transistor epitaxial structure comprises, from bottom to top, a SiC substrate layer, an N-type highly doped 4H-SiC buffer layer, an N-type low-doped 4H-SiC buffer layer, a V-doped high-resistance 4H-SiC buffer layer, a V-doped high-resistance 4H-SiC drift layer, a 4H-SiC channel layer, a 3C-SiC barrier layer, and a P-type 3C-SiC layer.

[0054] The method for preparing the enhanced SiC heterojunction high electron mobility transistor epitaxial structure comprises the following steps:

[0055] 1) In-situ etching of SiC substrates: A positive-axis N-type SiC carbon-surface substrate was selected, and H2 and HCl were introduced at a flow rate of 196 slm and 30 sccm, respectively, at a pressure of 80 mbar and a temperature of 1450°C for 10 min.

[0056] 2) Growth of N-type highly doped 4H-SiC buffer layer: Stop the HCl flow and introduce H2 carrier gas, chlorine-containing silicon source gas, carbon source, and N2 at flow rates of 196 slm, 200 sccm, 224 sccm, and 46 sccm, respectively. Grow a 1 μm thick N-type highly doped 4H-SiC buffer layer at 1700°C and 80 mbar. The doping concentration is 1×10 18 cm-3 ;

[0057] 3) Growth of N-type low-doped 4H-SiC buffer layer: A 2 μm thick N-type low-doped 4H-SiC buffer layer was grown at 1650°C and 80 mbar at a doping concentration of 1×10 16 cm -3 ;

[0058] 4) Growth of V-doped high-resistance 4H-SiC buffer layer: With N2 turned off, H2 carrier gas, chlorine-containing silicon source gas, carbon source, and VCl4 were introduced at flow rates of 196 slm, 100 sccm, 110 sccm, and 5 sccm, respectively. A 5 μm thick doped semi-insulating 4H-SiC high-resistance layer was grown at a temperature of 1700°C and a pressure of 80 mbar. The doping concentration was 1×10 15 cm -3 cm -3 ;

[0059] 5) Growth of V-doped high-resistance 4H-SiC epitaxial layer: N2 was turned off, and carrier gas H2, chlorine-containing silicon source gas, carbon source, and VCl4 were introduced at flow rates of 196 slm, 100 sccm, 110 sccm, and 30 sccm, respectively. At a temperature of 1750°C and a pressure of 80 mbar, a 10 μm thick doped semi-insulating 4H-SiC high-resistance layer was grown with a doping concentration of 5×10 16 cm -3 ;

[0060] 6) Growth of 4H-SiC channel layer: With the VCl4 process turned off, a carrier gas of H2, a chlorine-containing silicon source gas, and a carbon source were introduced at flow rates of 196 slm, 300 sccm, and 330 sccm, respectively, at a temperature of 1600°C and a pressure of 80 mbar to grow a 2 μm thick 4H-SiC channel layer;

[0061] 7) 3C-SiC barrier layer growth: H2, silicon source, carbon source, and N2 were introduced at flow rates of 196 slm, 200 sccm, 220 sccm, and 15 sccm, respectively, at a temperature of 1400°C and a pressure of 200 mbar to grow a 5 μm thick 3C-SiC epitaxial layer;

[0062] 8) Growth of a p-type 3C-SiC layer: H2, silicon source, carbon source, and TMAl were introduced at flow rates of 196 slm, 300 sccm, 340 sccm, and 20 sccm, respectively, at a temperature of 1550°C and a pressure of 200-500 mbar to grow a 1 μm thick p-type 3C-SiC layer;

[0063] 9) Cooling to room temperature under H2 protection;

[0064] In the above steps, the chlorine-containing silicon source gas is SiCl4, SiHCl3, SiH2C12 or SiH3Cl.

[0065] Example 2

[0066] A field effect transistor device is obtained by arranging a source electrode, a Schottky contact gate electrode, a drain electrode, and a SiN isolation layer on a P-type 3C-SiC layer of the enhanced SiC heterojunction high electron mobility transistor epitaxial structure in Example 1; the source electrode and the drain electrode are respectively located on either side of the Schottky contact gate electrode; a SiN isolation layer is arranged between the source electrode and the Schottky contact gate electrode; and a SiN isolation layer is arranged between the Schottky contact gate electrode and the drain electrode.

[0067] Comparative Example 1

[0068] A conventional AlGaN / GaN-based enhancement mode transistor epitaxial structure comprises, from bottom to top, a Si-based substrate, an AlN nucleation layer, a carbon-doped GaN drift layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, and a P-type GaN layer. The fabrication steps are as follows:

[0069] (1) An AlN nucleation layer with a thickness of 100 nm was grown on a Si-based substrate. The temperature and pressure of the epitaxial growth were 1150°C and 100 mbar, respectively.

[0070] (2) A carbon-doped GaN drift layer with a thickness of 5 μm was grown on the AlN nucleation layer; the temperature and pressure of the epitaxial growth were 1050°C and 100 mbar, respectively;

[0071] (3) Growing a GaN channel layer with a thickness of 1 μm on the carbon-doped GaN drift layer; the temperature and pressure of the epitaxial growth are 1150°C and 100 mbar, respectively;

[0072] (4) Growing an AlN insertion layer with a thickness of 1 nm on the GaN channel layer; the temperature and pressure of the epitaxial growth are 1100°C and 100 mbar, respectively;

[0073] (5) growing an AlGaN barrier layer with a thickness of 20 nm on the AlN insertion layer at a temperature of 1100°C and a pressure of 100 mbar;

[0074] (6) A P-type GaN layer is epitaxially grown on the AlGaN barrier layer, with a thickness of 20 nm; the temperature and pressure of the epitaxial growth are 900° C. and 300 mbar, respectively.

[0075] A source electrode, a Schottky contact gate electrode, a drain electrode, and a SiN isolation layer are arranged on the P-type 3C-SiC layer of this comparative example to obtain a field effect transistor device; the source electrode and the drain electrode are respectively located on both sides of the Schottky contact gate electrode; a SiN isolation layer is arranged between the source electrode and the Schottky contact gate electrode; and a SiN isolation layer is arranged between the Schottky contact gate electrode and the drain electrode.

[0076] The reliability test results of the field effect transistor devices in Example 2 and Comparative Example 1 are shown in Table 1 and Table 2.

[0077] Table 1

[0078]

[0079] Table 2

[0080]

[0081] The detailed description of an enhanced SiC heterojunction transistor epitaxial structure and a method for preparing the same with reference to the above-mentioned embodiments is illustrative rather than restrictive. Several embodiments may be listed according to the limited scope. Therefore, changes and modifications without departing from the overall concept of the present invention should fall within the scope of protection of the present invention.

Claims

1. An enhanced SiC heterojunction transistor epitaxial structure, characterized in that: The enhanced SiC heterojunction transistor epitaxial structure includes, from bottom to top, a SiC substrate layer, an N-type highly doped 4H-SiC buffer layer, an N-type low-doped 4H-SiC buffer layer, a V-doped high-resistance 4H-SiC buffer layer, a V-doped high-resistance 4H-SiC drift layer, a 4H-SiC channel layer, a 3C-SiC barrier layer, and a P-type 3C-SiC layer.

2. The enhancement mode SiC heterojunction transistor epitaxial structure according to claim 1, characterized in that: The thickness of the N-type highly doped 4H-SiC buffer layer is 0.5 to 1 μm, and the N doping concentration is 5×10 17 cm -3 ~2×10 18 cm -3 .

3. The enhancement mode SiC heterojunction transistor epitaxial structure according to claim 1, characterized in that: The thickness of the N-type low-doped 4H-SiC buffer layer is 1-2 μm, and the N doping concentration is 8×10 15 cm -3 ~2×10 16 cm -3 .

4. The enhancement mode SiC heterojunction transistor epitaxial structure according to claim 1, characterized in that: The thickness of the V-doped high-resistance 4H-SiC buffer layer is 5 to 10 μm; the V doping concentration is 1×10 15 cm -3 ~5×10 15 cm -3 .

5. The enhancement mode SiC heterojunction transistor epitaxial structure according to claim 1, characterized in that: The thickness of the V-doped high-resistance 4H-SiC drift layer is 5 to 10 μm; the V doping concentration is 1×10 16 cm -3 ~5×10 16 cm -3 .

6. The enhancement mode SiC heterojunction transistor epitaxial structure according to claim 1, characterized in that: The thickness of the 4H-SiC channel layer is 1-2 μm; the thickness of the 3C-SiC barrier layer is 5-10 μm; and the thickness of the P-type 3C-SiC layer is 0.2-1 μm.

7. The method for preparing an enhancement mode SiC heterojunction transistor epitaxial structure according to any one of claims 1 to 6, wherein: The preparation method comprises the following steps: (1) in-situ etching of the SiC substrate to obtain a SiC substrate layer; (2) growing an N-type highly doped 4H-SiC buffer layer on the SiC substrate layer; (3) growing an N-type low-doped 4H-SiC buffer layer on the N-type highly-doped 4H-SiC buffer layer; (4) growing a V-doped high-resistance 4H-SiC buffer layer on the N-type low-doped 4H-SiC buffer layer; (5) growing a V-doped high-resistance 4H-SiC drift layer on the V-doped high-resistance 4H-SiC buffer layer; (6) growing a 4H-SiC channel layer on the V-doped high-resistance 4H-SiC drift layer; (7) growing a 3C-SiC barrier layer on the 4H-SiC channel layer; (8) A P-type 3C-SiC layer is grown on the 3C-SiC barrier layer.

8. The preparation method according to claim 7, characterized in that The growth method of the V-doped high-resistance 4H-SiC buffer layer is as follows: introducing carrier gas H2, chlorine-containing silicon source gas, carbon source and VCl4 at flow rates of 160-240 slm, 80-500 sccm, 80-500 sccm and 5-20 sccm respectively, and growing at a temperature of 1700-1750°C and a pressure of 50-200 mbar.

9. The preparation method according to claim 7, characterized in that The growth method of the V-doped high-resistance 4H-SiC drift layer is as follows: introducing carrier gas H2, chlorine-containing silicon source gas, carbon source and VCl4 at flow rates of 160-240 slm, 80-500 sccm, 80-500 sccm and 30-60 sccm respectively, and growing at a temperature of 1700-1750°C and a pressure of 50-200 mbar.

10. A device comprising the enhancement-mode SiC heterojunction transistor epitaxial structure according to any one of claims 1 to 6.

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