Split gate non-volatile memory cell with erase gate disposed above word line gate and method of making the same

Abstract

The present invention discloses a memory device and a method for preparing the same. The memory device includes a substrate of a semiconductor material of a first conductivity type; a first region and a second region separated in the substrate and having a second conductivity type different from the first conductivity type, wherein a first channel region in the substrate extends between the first region and the second region; a first floating gate disposed above a first portion of the first channel region adjacent to the second region and insulated from the first portion; a first coupling gate disposed above the first floating gate and insulated from the first floating gate; a first word line gate disposed above a second portion of the first channel region adjacent to the first region and insulated from the second portion; and a first erase gate disposed above the first word line gate and insulated from the first word line gate.

Description

Technical Field

[0001] The present invention relates to nonvolatile memory arrays and, more particularly, to split-gate memory cell designs and fabrication methods. Background Art

[0002] Split gate nonvolatile memory cells and arrays of such cells are well known. For example, U.S. Pat. No. 5,029,130 ​​("the '130 patent") discloses a split gate nonvolatile memory cell array and is incorporated herein by reference for all purposes. Figure 1 1. Each memory cell 110 includes a source region 114 and a drain region 116 formed in a semiconductor substrate 112, with a channel region 118 therebetween. A floating gate 120 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 118, and is formed over a portion of the drain region 116. A control gate 122 has a first portion 122a disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 118, and a second portion 122b extending upwardly along and over the floating gate 120. The floating gate 120 and the control gate 122 are insulated from the substrate 112 by a gate oxide 126.

[0003] The memory cell is erased (electrons are removed from the floating gate) by placing a high positive voltage on the control gate 122, which causes the electrons on the floating gate 120 to tunnel from the floating gate 120 through the intermediate insulator 123 to the control gate 122 via the Fowler-Nordheim tunneling effect.

[0004] The memory cell is programmed by placing a positive voltage on the control gate 122 and a positive voltage on the drain region 116 (where electrons are placed on the floating gate). Electron current will flow from the source region 114 to the drain region 116. When the electrons reach the gap between the control gate 122 and the floating gate 120, the electrons will accelerate and become hot. Due to the electrostatic attraction from the floating gate 120, some of the heated electrons will be injected through the gate oxide 126 onto the floating gate 120.

[0005] The memory cell is read by placing a positive read voltage across the drain region 116 and the control gate 122 (which turns on the channel region 118 below the control gate first portion 122a). If the floating gate 120 is positively charged (i.e., electrons are erased and positively coupled to the drain region 116), the portion of the channel region 118 below the floating gate 120 is also turned on, and current will flow through the channel region 118, which is sensed as an erased state or a "1" state. If the floating gate 120 is negatively charged (i.e., programmed by electrons), the portion of the channel region below the floating gate 120 is mostly or completely turned off, and current will not (or very little) flow through the channel region 118, which is sensed as a programmed state or a "0" state. Those skilled in the art understand that the source and drain regions may be interchangeable, wherein the floating gate 120 may extend partially over the source region 114 instead of the drain region 116, such as Figure 2 shown.

[0006] Split gate memory cells with more than two gates are also known. For example, U.S. Pat. No. 8,711,636 ("the '636 patent") discloses a memory cell with an additional coupling gate disposed above and insulated from a source region to better capacitively couple to a floating gate. See, e.g. Figure 3 , which shows the coupling gate 124 disposed above the source region 14 .

[0007] A quad-gate memory is disclosed in U.S. Patent 6,747,310 ("the '310 patent"). Figure 4 As shown, the memory cell has a source region 114, a drain region 116, a floating gate 120 located over a first portion of a channel region 118, a select (word line) gate 128 located over a second portion of the channel region 118, a control gate 122 located over the floating gate 120, and an erase gate 130 located over the source region 14. Programming occurs as heated electrons from the channel region 118 inject themselves onto the floating gate 120. Erasing occurs as electrons are tunneled from the floating gate 120 to the erase gate 130 by placing a positive voltage on the erase gate 130 (and optionally a negative voltage on the control gate 122). However, this configuration is not ideal because erase efficiency can be affected by the high coupling ratio between the erase gate and the floating gate, and it can be complex to manufacture.

[0008] Conventional memory cell design and fabrication methods make it challenging to reduce the size of the memory cell while maintaining or even enhancing performance and simplifying the fabrication process. Summary of the invention

[0009] The above-mentioned problems and needs are solved by a memory device, which includes a substrate of a semiconductor material of a first conductivity type; a first region and a second region separated in the substrate and having a second conductivity type different from the first conductivity type, wherein a first channel region in the substrate extends between the first region and the second region; a first floating gate arranged above a first portion of the first channel region adjacent to the second region and insulated from the first portion; a first coupling gate arranged above the first floating gate and insulated from the first floating gate; a first word line gate arranged above a second portion of the first channel region adjacent to the first region and insulated from the second portion; and a first erase gate arranged above the first word line gate and insulated from the first word line gate.

[0010] The method for forming a memory cell includes forming a first insulating layer on a semiconductor substrate having a first conductivity type; forming a first conductive layer on the first insulating layer; forming a second insulating layer on the first conductive layer; forming a second conductive layer on the second insulating layer; forming a third insulating layer on the second conductive layer; forming a trench extending through the third insulating layer, the second conductive layer, and the second insulating layer; forming insulating spacers along sidewalls of the trench; extending the trench through the first conductive layer between the insulating spacers; forming a first conductive material block in the trench, wherein the first conductive material block is vertically disposed above the substrate and insulated from the substrate and laterally adjacent to and insulated from the first conductive layer; forming a first erase gate and a second erase gate in the trench, wherein the first erase gate and the second erase gate are vertically disposed above the first conductive material block and insulated from the first conductive material block; removing the first erase gate and the second erase gate; removing the first erase gate and the second erase gate from the trench .... The invention relates to a method for forming a first conductive material block between the gates, while keeping the first and second portions of the first conductive material block as corresponding first word line gates and second word line gates; forming a first region having a second conductivity type different from the first conductivity type in a portion of the substrate between the first word line gate and the second word line gate; removing a portion of the second conductive layer, while keeping the first and second portions of the second conductive layer as corresponding first coupling gates and second coupling gates; removing a portion of the first conductive layer, while keeping the first and second portions of the first conductive layer as corresponding first floating gates and second floating gates; and forming a second region and a third region having a second conductivity type in the substrate, wherein the second region is adjacent to the first floating gate and the third region is adjacent to the second floating gate, wherein the first channel region in the substrate extends between the first region and the second region, and the second channel region in the substrate extends between the first region and the third region. The first floating gate is disposed above the substrate and insulated from the substrate and is laterally adjacent to and insulated from the first word line gate. The second floating gate is disposed above the substrate and insulated from the substrate and is laterally adjacent to and insulated from the second word line gate. The first coupling gate is disposed above the first floating gate and is insulated from the first floating gate. The second coupling gate is disposed above the second floating gate and is insulated from the second floating gate. The first erase gate is disposed above the first word line gate and is insulated from the first word line gate. The second erase gate is disposed above the second word line gate and is insulated from the second word line gate.

[0011] Other objects and features of the present invention will become apparent by examining the specification, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a cross-sectional view of a conventional dual-gate memory cell.

[0013] Figure 2 is a cross-sectional view of a conventional dual-gate memory cell.

[0014] Figure 3 is a cross-sectional view of a conventional tri-gate memory cell.

[0015] Figure 4 is a cross-sectional view of a conventional quad-gate memory cell.

[0016] FIG. 5A to FIG. 5F is a side cross-sectional view showing the steps of forming a pair of memory cells according to the present invention.

[0017] Figure 6 2 is a side cross-sectional view showing the final structure of the pair of memory cells of the present invention.

[0018] FIG. 7A to FIG. 7B is a side cross-sectional view showing the steps of forming a pair of memory cells according to an alternative embodiment of the present invention.

[0019] Figure 8 is a plan view showing a control circuit for operating an array of memory cells of the present invention. DETAILED DESCRIPTION

[0020] The present invention is a memory cell design, architecture, and method for manufacturing a split-gate memory cell design. FIG. 5A to FIG. 5F , showing a cross-sectional view of a step in the process of preparing a memory cell. Although the formation of only one pair of memory cells is shown in the drawings, it should be understood that an array of such memory cell pairs is formed simultaneously when a memory device containing an array of such memory cells is formed. The process first forms a first insulating layer 12 (e.g., a silicon dioxide layer, also referred to herein as an oxide layer 12) on a top surface 10a of a substrate 10 of a semiconductor material (e.g., single crystal silicon). Thereafter, a first conductive layer 14 (e.g., polycrystalline silicon (also referred to herein as "poly") or amorphous silicon) is formed on the oxide layer 12. A second insulating layer 16 is formed on the first conductive layer 14. Preferably, the second insulating layer 16 is an ONO layer, meaning that it has an oxide-nitride-oxide sublayer. A second conductive layer 18 (e.g., polycrystalline silicon or amorphous silicon) is formed on the second insulating layer 16. A third insulating layer 20 (e.g., silicon nitride - referred to herein as "nitride") is formed on the second conductive layer 18. A photoresist material (not shown) is applied over the structure, and a photolithographic masking step is performed to expose selected portions of the photoresist material. The photoresist is developed, so that portions of the photoresist are removed. Using the remaining photoresist as a mask, the structure is etched. Specifically, the third insulating layer 20, the second conductive layer 18, and the second insulating layer 16 are anisotropically etched (using the conductive layer 14 as an etch stop layer), thereby leaving a trench 22 extending through the third insulating layer 20, the second conductive layer 18, and the second insulating layer 16. The resulting structure is shown in FIG. Figure 5A in (after photoresist removal).

[0021] Insulating spacers 24 / 26 (e.g., ON - oxide and nitride, respectively) spacers 24 / 26 are formed along the sidewalls of the trench 22. The formation of spacers is well known in the art and involves the deposition of material over the contours of the structure, followed by an anisotropic etching process, thereby removing the material from the horizontal surfaces of the structure while the material remains largely intact on the vertically oriented surfaces of the structure (with a rounded upper surface, not shown). The insulating (ON) spacers 24 / 26 are formed by oxide deposition, nitride deposition, and subsequent nitride anisotropic etching and oxide anisotropic etching. Oxide spacers 28 are then formed in the trench 22 by oxide deposition and subsequent oxide anisotropic etching. An anisotropic etch is then performed to remove the exposed portions of the first conductive layer 14 located below the areas between the oxide spacers 28 (e.g., ). Figure 5B ), thereby deepening trench 22. An implant may be performed at this time (through oxide layer 12 at the bottom of trench 22 and into the underlying portion of substrate 10 (which will ultimately be the wordline portion of the channel region, as further described below).

[0022] Next, oxide spacers 30 are formed along the sidewalls of the trench 22 (including along the exposed sidewalls of the first conductive layer 14 and the adjacent oxide spacers 28) by oxide deposition and anisotropic oxide etching. The spacer formation, in particular the anisotropic oxide etching that removes the portion of the oxide layer 12 at the bottom of the trench 22, exposes the portion of the substrate surface 10a between the oxide spacers 30. The oxide layer 32 is preferably formed on the exposed portion of the substrate surface 10a at the bottom of the trench 22 by thermal oxidation. It is also preferred that the thickness of the oxide layer 32 is less than the thickness of the oxide layer 12. A first conductive material block 34 is formed on the oxide layer 32 within the trench 22 by material deposition, chemical mechanical polishing (CMP) using the third insulating layer 20 as a stop layer, and etching back. Preferably, the first conductive material block 34 is formed of polysilicon, and the top surface of the first conductive material block 34 is lower than the top surface of the first conductive layer 14. The first conductive material block 34 is laterally adjacent to the first conductive layer 14 and is insulated from the first conductive layer by the oxide spacers 30. If polysilicon is used for the first conductive material block 34, an implantation may be performed to dope the first conductive material block 34. The resulting structure is shown in FIG. Figure 5C middle.

[0023] Oxide etching (e.g., wet etching) is used to remove the upper portion of the oxide spacer 30 (above the first conductive material block 34) and all of the oxide spacers 28. An oxide layer 36 is then formed over the structure by oxide deposition. A second conductive material block 38a and a third conductive material block 38b are formed on the oxide layer 36 within the trench 22 by material deposition and etching. Preferably, the second conductive material block 38a and the third conductive material block 38b are a pair of spaced-apart spacers formed by polysilicon deposition and anisotropic etching, thereby exposing a portion of the oxide layer 36 between the second conductive material block 38a and the third conductive material block 38b. Oxide etching is used to remove the exposed portion of the oxide layer 36 at the bottom of the trench 22 between the second conductive material block and the third conductive material block (e.g., by anisotropic etching), thereby exposing a portion of the first conductive material block 34. Etching is then used to remove the exposed (middle) portion of the first conductive material block 34, thereby leaving a fourth conductive material block 34a and a fifth conductive material block 34b from the first conductive material block 34. The resulting structure is shown in Figure 5D middle.

[0024] Implantation is then performed to form a drain region 40 in the substrate 10 between the fourth conductive material block 34a and the fifth conductive material block 34b. The drain region 40 is the first region in the substrate 10 whose conductivity type is different from the conductivity type of the substrate 10 near the drain region 40. A photoresist material 42 is coated on the structure, and a photolithography masking step is performed to expose selected portions of the photoresist material. The photoresist material 42 is developed so that portions of the photoresist material 42 are removed (except for the photoresist material 42 in the trench 22, above the second conductive material block 38a and the third conductive material block 38b, above the layer 36, above the spacer 24 / 26, and above the portion of the third insulating layer 20 adjacent to the second conductive material block 38a and the third conductive material block 38b). Using the remaining photoresist material 42 as a mask, the structure is etched to remove the exposed portions of the third insulating layer 20, the second conductive layer 18, the second insulating layer 16, and the first conductive layer 14, as shown in FIG. Figure 5EAs shown. Implantation is then performed to form a first source region 44a and a second source region 44b in the substrate 10 adjacent to the outer edge first conductive layer 14. The first source region 44a and the second source region 44b are the second and third regions in the substrate, which have the same conductivity type as the drain region 40 (i.e., different from the substrate 10 near the first source region 44a and the second source region 44b), and partially extend under the corresponding adjacent first conductive layer 14. For example, the substrate 10 near the first source region 44a and the second source region 44b and the drain region 40 may be P-type conductivity, and the first source region 44a and the second source region 44b and the drain region 40 may be N-type conductivity, and vice versa. After removing the photoresist 42, insulating spacers 48 (e.g., nitride) may be formed on the sides of the structure, as shown. Fig. 5F shown.

[0025] The resulting memory cell is Figure 6 4, wherein a pair of memory cells sharing a common drain region 40 are formed, namely memory cells 50 and 52. For memory cell 50, a first channel region 46a is defined in substrate 10 by first source region 44a and drain region 40 and extends between first source region 44a and drain region 40. A first floating gate 14a (a first material block remaining from first conductive layer 14) is disposed over and insulated from a first portion of first channel region 46a adjacent to first source region 44a (so as to control its conductivity), and preferably the first floating gate 14a is partially disposed over the first source region 44a and insulated from the first source region by a corresponding remaining portion of oxide layer 12. A first coupling gate 18a (a first material block remaining from second conductive layer 18) is disposed over and insulated from the first floating gate 14a by a corresponding remaining portion of second insulating layer 16 (so as to couple voltage to floating gate 14a). The fourth conductive material block 34a is a first word line gate, which is vertically disposed above and insulated from the second portion of the first channel region 46a (so as to control its conductivity), and is laterally adjacent to the first floating gate 14a and insulated from the first floating gate by the corresponding remaining portion of the oxide spacer 30. The second conductive material block 38a is a first erase gate, which is vertically disposed above the first word line gate 34a and insulated from the first word line gate by the corresponding remaining portion of the oxide layer 36, and is laterally adjacent to the first coupling gate 18a and insulated from the first coupling gate by the combination of the corresponding remaining portion of the oxide layer 36 and the insulating spacers 24, 26. The first erase gate 38a includes a notch 38c facing the edge 14c of the first floating gate 14a. The insulating block 20a (a block of material remaining from the insulating layer 20) is disposed above the first coupling gate 18a.

[0026] For the memory cell 52, the second channel region 46b is defined in the substrate 10 by the source region 44b and the drain region 40 and extends between the source region 44b and the drain region 40. The second floating gate 14b (a second material block remaining from the first conductive layer 14) is disposed over and insulated from a first portion of the second channel region 46b adjacent to the source region 44b (so as to control its conductivity), and preferably the second floating gate 14b is partially disposed over the second source region 44b and insulated from the second source region by a corresponding remaining portion of the oxide layer 12. The second coupling gate 18b (a second material block remaining from the second conductive layer 18) is disposed over the second floating gate 14b and insulated from the second floating gate by a corresponding remaining portion of the second insulating layer 16 (so as to couple voltage to the floating gate 14b). The fifth conductive material block 34b is a second word line gate, which is vertically disposed above the second portion of the second channel region 46b and insulated from the second portion (so as to control its conductivity), and is laterally adjacent to the second floating gate 14b and insulated from the second floating gate by the corresponding remaining portion of the oxide spacer 30. The third conductive material block 38b is a second erase gate, which is vertically disposed above the second word line gate 34b and insulated from the second word line gate by the corresponding remaining portion of the oxide layer 36, and is laterally adjacent to the second coupling gate 18b and insulated from the second coupling gate by the combination of the corresponding remaining portion of the oxide layer 36 and the insulating spacers 24, 26. The second erase gate 38b includes a notch 38c facing the edge 14c of the second floating gate 14b. The insulating block 20b (a block of material remaining from the insulating layer 20) is disposed above the second coupling gate 18b.

[0027] Table 1 below shows exemplary operating voltages and currents for programming, reading, and erasing operations of memory cells 50 and 52 .

[0028] Table 1

[0029]

[0030] Vcc may be, for example, 0.9 to 3.3 V. Vblr may be, for example, 0.5 to 1.1 V.

[0031] Programming the memory cell 50 (i.e., programming the first floating gate 14a with electrons) will store the first bit of information, and programming the memory cell 52 (i.e., programming the second floating gate 14b with electrons) will store the second bit of information. To program the memory cell 50, a positive voltage of 4.5V is applied to the first erase gate 38a, a positive voltage of 1V is applied to the first word line gate 34a, a positive voltage of 10.5V is applied to the first coupling gate 18a, a positive voltage of 4.5V is applied to the first source region 44a, and a current of -1uA is applied to the drain region 40. Electrons travel from the drain region 40 toward the first source region 44a in the first channel region 46a and inject themselves onto the first floating gate 14a, because the first coupling gate 18a capacitively couples the positive voltage to the first floating gate 14a. The combination of voltages and currents in Table 1 is similarly used to program the memory cell 52.

[0032] To erase memory cell 50 (i.e., erase first floating gate 14a by removing electrons therefrom), a positive voltage of 11.5 V is applied to first erase gate 38a, which causes electrons to tunnel from first floating gate 14a to first erase gate 38a through insulating layer 36. Memory cell 52 is similarly erased by applying a positive voltage of 11.5 V to second erase gate 38b. The notch 38a facing edge 14c enhances the efficiency of this tunneling.

[0033] To read the memory cell 50 (i.e., read the first floating gate 14a by determining the state of the electrons thereon), a positive voltage of Vcc (e.g., 0.9-3.3V) is applied to the first word line gate 34a and the first coupling gate 18a, and a positive voltage of Vblr (e.g., 0.5-1.1V) is applied to the drain region 40. If the memory cell 50 is erased, current will flow through the first channel region 46a (i.e., the first floating gate 14a is in an erased state and therefore has a positive voltage due to the positive charge on the first floating gate 14a after erasing and small voltage coupling from the word line gate 34a, thereby the portion of the first channel region 46a under the first floating gate 14a is turned on). The current is sensed as the erased state. If the first floating gate 14a is programmed (i.e., the first floating gate is programmed with electrons sufficient to prevent the portion of the first channel region 46a under the floating gate 14a from being turned on), the current will decrease or will not flow through the first channel region 46a. This low or no current is sensed as a programmed state.Memory cell 52 is similarly read using the combination of voltages in Table 1.

[0034] The formation and resulting structure of memory cells 50 and 52 have many advantages. The insulating layer (i.e., oxide layer 32) under the first word line gate 34a and the second word line gate 34b can be much thinner than the insulating layer (i.e., oxide layer 12) under the first floating gate 14a and the second floating gate 14b to achieve higher performance, especially for high-speed applications. The insulating layer (i.e., oxide layer 36) between the first floating gate 14a and the second floating gate 14b and the first erase gate 38a and the second erase gate 38b can be thinner than the insulating layer (i.e., oxide spacer 30) between the first floating gate 14a and the second floating gate 14b and the first word line gate 34a and the second word line gate 34b. The erase performance is enhanced due to the relatively low voltage coupling ratio between the first erase gate 38a and the second erase gate 38b and the first floating gate 14a and the second floating gate 14b simply because the corner regions (having notches 38c) of the first erase gate 38a and the second erase gate 38b are in close proximity to the corner regions (having edges 14c) of the first floating gate 14a and the second floating gate 14b. Only two photolithography masking steps are required to define the structure, one photolithography masking step for forming the trench 22, and another photolithography masking step for etching through the conductive layers 18 and 14 to complete the formation of the first coupling gate 18a and the second coupling gate 18b and the first floating gate 14a and the second floating gate 14b. The word line gate 34a / 38b and the first erase gate 38a and the second erase gate 38b are all self-aligned to the first floating gate 14a and the second floating gate 14b. This self-alignment provides better control over the lengths of the first channel region 46a and the second channel region 46b. Finally, the ability to scale memory cell 50 / 52 to smaller sizes is facilitated by having first and second coupling gates 18a and 18b disposed above first and second floating gates 14a and 14b, respectively, and having first and second erase gates 38a and 38b disposed above first and second word line gates 34a and 34b, respectively.

[0035] FIG. 7A to FIG. 7B An alternative embodiment for forming memory cell 50 / 52 is shown, which is Figure 5A The execution is relative to Figure 5B The above processing steps are described, except that the formation of oxide spacer 28 is omitted, thereby obtaining Fig. 7A Then, execute the above relative to FIG. 5C to FIG. 5F The remaining processing steps are described (except that oxide spacers 28 are not removed because they were never formed), resulting in Figure 7B The final structure is shown in Figure 6The main difference between the structures of is that no notches are formed in the erase gates. Instead, the nitride spacers 26 are aligned with the sides of the first and second floating gates 14a and 14b, which means that the sidewalls of the trench 22 are planar when the first and second erase gates 38a and 38b are formed. Even though the lack of notches in the first and second erase gates 38a and 38b may reduce the erase efficiency, the size of the memory cell 50 / 52 can be reduced to a greater extent than if notches were formed, and the lack of notches will reduce the capacitive coupling between the first and second erase gates 38a and 38b and the first and second floating gates 14a and 14b.

[0036] The control circuit 96 (eg, Figure 8 ) is configured to program, read, and erase an array 98 of memory cells 50 or 52 described herein by applying voltages as described above in Table 1.

[0037] It should be understood that the present invention is not limited to the embodiments described above and shown herein, but covers any and all variations that fall within the scope of the appended claims. For example, reference to the present invention herein is not intended to limit the scope of any claim or claim term, but only refers to one or more features that can be covered by one or more of these claims. The examples of materials, processes and numerical values ​​described above are merely exemplary and should not be considered as limiting the claims. In addition, it is obvious from the claims and the specification that not all method steps need to be performed in the exact order shown or claimed, but need to be performed in any order that allows the proper formation of the memory cell array of the present invention. Finally, a single material layer can be formed into multiple such or similar material layers, and vice versa.

[0038] It should be noted that, as used herein, the terms "above" and "on" both include inclusively "directly on" (without intermediate materials, elements, or spaces disposed therebetween) and "indirectly on" (with intermediate materials, elements, or spaces disposed therebetween). Similarly, the term "adjacent" includes "directly adjacent" (without intermediate materials, elements, or spaces disposed therebetween) and "indirectly adjacent" (with intermediate materials, elements, or spaces disposed therebetween), "mounted to" includes "mounted directly to" (without intermediate materials, elements, or spaces disposed therebetween) and "mounted indirectly to" (with intermediate materials, elements, or spaces disposed therebetween), and "electrically connected to" includes "directly electrically connected to" (without intermediate materials or elements electrically connecting the elements together) and "indirectly electrically connected to" (with intermediate materials or elements electrically connecting the elements together). For example, forming an element "above a substrate" may include forming the element directly on the substrate without intermediate materials / elements therebetween, and indirectly forming the element on the substrate with one or more intermediate materials / elements therebetween.

Claims

1. A memory device, comprising: a semiconductor material substrate of a first conductivity type; a first region and a second region spaced apart in the substrate and having a second conductivity type different from the first conductivity type, wherein a first channel region in the substrate extends between the first region and the second region; a first floating gate disposed over a first portion of the first channel region adjacent to the second region and insulated from the first portion; A first coupling gate disposed above the first floating gate and insulated from the first floating gate; a first word line gate disposed over a second portion of the first channel region adjacent to the first region and insulated from the second portion; a first erase gate disposed above the first word line gate and insulated from the first word line gate; a third region of the substrate having the second conductivity type, wherein a second channel region in the substrate extends between the first region and the third region; a second floating gate disposed over a first portion of the second channel region adjacent to the third region and insulated from the first portion; a second coupling gate disposed above the second floating gate and insulated from the second floating gate; a second word line gate disposed over a second portion of the second channel region adjacent to the first region and insulated from the second portion; as well as A second erase gate is disposed above and insulated from the second word line gate. 2 . The memory device of claim 1 , wherein the first floating gate is partially disposed over and insulated from the second region, and the second floating gate is partially disposed over and insulated from the third region. 3 . The memory device of claim 1 , wherein the first erase gate includes a notch facing an edge of the first floating gate, and the second erase gate includes a notch facing an edge of the second floating gate.

4. The memory device of claim 1 , wherein the insulating layer between the first word line gate and the substrate is thinner than the insulating layer between the first floating gate and the substrate, and the insulating layer between the second word line gate and the substrate is thinner than the insulating layer between the second floating gate and the substrate.

5. The memory device of claim 1 , wherein the insulating layer between the first erase gate and the first floating gate is thinner than the insulating layer between the first word line gate and the first floating gate, and wherein the insulating layer between the second erase gate and the second floating gate is thinner than the insulating layer between the second word line gate and the second floating gate.

6. The memory device of claim 1, wherein: The first word line gate is disposed laterally adjacent to the first floating gate and insulated from the first floating gate; The first erase gate is disposed laterally adjacent to and insulated from the first coupling gate; The second word line gate is disposed laterally adjacent to the second floating gate and insulated from the second floating gate; and The second erase gate is disposed laterally adjacent to and insulated from the second coupling gate.

7. The memory device of claim 1, further comprising: A control circuit, the control circuit being configured to: programming the first floating gate by applying a positive voltage to the first erase gate, the first word line gate, the first coupling gate, and the second region and applying a current to the first region; reading the first floating gate by applying a positive voltage to the first word line gate, the first coupling gate, and the first region; as well as The first floating gate is erased by applying a positive voltage to the first erase gate.

8. A method of forming a memory cell, the method comprising: forming a first insulating layer on a semiconductor substrate having a first conductivity type; forming a first conductive layer on the first insulating layer; forming a second insulating layer on the first conductive layer; forming a second conductive layer on the second insulating layer; forming a third insulating layer on the second conductive layer; forming a trench extending through the third insulating layer, the second conductive layer, and the second insulating layer; forming insulating spacers along sidewalls of the trench; extending the trench through the first conductive layer between the insulating spacers; forming a first conductive material block in the trench, wherein the first conductive material block is vertically disposed above and insulated from the substrate and laterally adjacent to and insulated from the first conductive layer; forming a first erase gate and a second erase gate in the trench, wherein the first erase gate and the second erase gate are vertically disposed above the first conductive material block and insulated from the first conductive material block; removing a portion of the first conductive material block between the first erase gate and the second erase gate while keeping a first portion and a second portion of the first conductive material block as respective first word line gates and second word line gates; forming a first region having a second conductivity type different from the first conductivity type in a portion of the substrate between the first word line gate and the second word line gate; removing a portion of the second conductive layer while maintaining a first portion and a second portion of the second conductive layer as respective first and second coupling gates; removing a portion of the first conductive layer while maintaining a first portion and a second portion of the first conductive layer as respective first and second floating gates; as well as forming a second region and a third region having the second conductivity type in the substrate, wherein the second region is adjacent to the first floating gate and the third region is adjacent to the second floating gate, wherein a first channel region in the substrate extends between the first region and the second region, and a second channel region in the substrate extends between the first region and the third region; in: The first floating gate is disposed above the substrate and insulated from the substrate and is laterally adjacent to and insulated from the first word line gate. The second floating gate is disposed above and insulated from the substrate and is laterally adjacent to and insulated from the second word line gate. The first coupling gate is disposed above the first floating gate and is insulated from the first floating gate. The second coupling gate is disposed above the second floating gate and is insulated from the second floating gate. The first erase gate is disposed above the first word line gate and is insulated from the first word line gate, and The second erase gate is disposed above the second word line gate and is insulated from the second word line gate.

9. The method according to claim 8, wherein: The first word line gate is disposed laterally adjacent to the first floating gate and insulated from the first floating gate; The first erase gate is disposed laterally adjacent to and insulated from the first coupling gate; The second word line gate is disposed laterally adjacent to the second floating gate and insulated from the second floating gate; and The first erase gate is disposed laterally adjacent to and insulated from the first coupling gate.

10. The method according to claim 8, wherein before forming the first erase gate and the second erase gate, the method further comprises: At least one of the insulating spacers is removed along the sidewalls of the trench. 11 . The method of claim 10 , wherein the first erase gate includes a notch facing an edge of the first floating gate, and the second erase gate includes a notch facing an edge of the second floating gate. 12 . The method of claim 8 , wherein the first floating gate is partially disposed over and insulated from the second region, and the second floating gate is partially disposed over and insulated from the third region.

13. The method according to claim 8, wherein the insulating layer between the first word line gate and the substrate is thinner than the insulating layer between the first floating gate and the substrate, and wherein the insulating layer between the second word line gate and the substrate is thinner than the insulating layer between the second floating gate and the substrate.

14. The method according to claim 8, wherein the insulating layer between the first erase gate and the first floating gate is thinner than the insulating layer between the first word line gate and the first floating gate, and wherein the insulating layer between the second erase gate and the second floating gate is thinner than the insulating layer between the second word line gate and the second floating gate.

15. The method according to claim 8, wherein the forming of the first erase gate and the second erase gate comprises: depositing polysilicon in the trench; as well as An anisotropic etch is performed, wherein the first erase gate and the second erase gate are spaced apart spacers of the polysilicon.

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