A PPM capacitor and its preparation method

Abstract

The present invention provides a PPM capacitor and a preparation method thereof, comprising: a substrate, a support layer formed on the substrate; a PIP capacitor structure, comprising a first electrode plate, a first dielectric layer and a second electrode plate, the first electrode plate being located on the substrate and wrapping the support layer so that the first electrode plate is in a convex shape, the first dielectric layer and the second electrode plate being located on the convex top surface of the first electrode plate in sequence; a second dielectric layer being located on the second electrode plate and covering a portion of the top surface of the second electrode plate; and a third electrode plate being located on the second dielectric layer. By adding the third electrode plate, the capacitor formed by the third electrode plate and the second electrode plate is connected in parallel with the PIP capacitor structure, thereby increasing the capacitance value of the capacitor without increasing the size of the capacitor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a PPM capacitor and a preparation method thereof. Background Art

[0002] Capacitors play a wide range of roles in integrated circuits. Capacitors can play a variety of roles such as coupling, filtering and compensation. PIP capacitors are commonly used passive devices in integrated circuit chips and are often used for noise emission and frequency modulation in RF and analog circuits.

[0003] The upper first plate of the PIP capacitor is a polysilicon layer, and an oxide layer or a silicon nitride layer is used as a dielectric layer between the two plates to form a capacitor structure, and the electrode plate of the PIP capacitor can be formed together with the polysilicon gate in the MOS device, so that the production of the PIP capacitor can be compatible with the MOS device, thereby reducing the production cost of the PIP capacitor. For the above reasons, the PIP capacitor is widely used in the production of semiconductor devices. When the device requires a large capacitance, it is usually achieved by increasing the area of ​​the upper first plate or reducing the thickness of the dielectric layer. However, since the uniformity of the dielectric layer will deteriorate after being thinned to a certain extent, the method of increasing the area of ​​the second plate and the first plate is generally adopted. However, increasing the area of ​​the plate will significantly affect the size of the semiconductor device, restricting the miniaturization of semiconductor devices in integrated circuits. Summary of the invention

[0004] An object of the present invention is to provide a PPM capacitor and a method for preparing the same, which can increase the capacitance of the capacitor without increasing the size of the capacitor.

[0005] In order to achieve the above object, the present invention provides a PPM capacitor, comprising:

[0006] a substrate having a support layer formed thereon;

[0007] A PIP capacitor structure, comprising a first electrode plate, a first dielectric layer and a second electrode plate, wherein the first electrode plate is located on the substrate and wraps the support layer so that the first electrode plate is in a convex shape, and the first dielectric layer and the second electrode plate are sequentially located on the convex top surface of the first electrode plate;

[0008] A second dielectric layer, located on the second electrode plate and covering a portion of the top surface of the second electrode plate;

[0009] The third electrode plate is located on the second dielectric layer.

[0010] Optionally, the PPM capacitor further includes:

[0011] A dielectric layer, located on the substrate and covering the PIP capacitor structure and the third electrode plate;

[0012] The metal wiring layer is located on the dielectric layer and is electrically connected to the first electrode plate, the second electrode plate and the third electrode plate through an electrical connector.

[0013] Optionally, the height of the support layer is

[0014] Optionally, the support layer includes a plurality of support pillars arranged at intervals, and the support pillars include a polysilicon layer and an insulating layer covering the polysilicon layer.

[0015] Based on the same inventive concept, the present invention also provides a method for preparing a PPM capacitor, comprising:

[0016] Providing a substrate, and forming a support layer on the substrate, wherein the support layer covers a portion of the substrate;

[0017] A PIP capacitor structure is formed on the substrate, wherein the PIP capacitor structure includes a first electrode plate, a first dielectric layer, and a second electrode plate, wherein the first electrode plate is located on the substrate and wraps the support layer so that the first electrode plate is in a convex shape, and the first dielectric layer and the second electrode plate sequentially cover the convex top surface of the first electrode plate;

[0018] forming a second dielectric layer on the second electrode plate, wherein the second dielectric layer covers a portion of the top surface of the second electrode plate;

[0019] A third electrode plate is formed on the second dielectric layer, wherein the third electrode plate covers the second dielectric layer.

[0020] Optionally, before forming the second dielectric layer and after forming the PIP capacitor structure, the method further includes:

[0021] forming a first dielectric layer on the substrate, wherein the first dielectric layer covers the PIP capacitor structure and the substrate;

[0022] The first dielectric layer is planarized until the upper surface of the second electrode plate is exposed.

[0023] Optionally, the step of forming the second dielectric layer and the third electrode plate includes:

[0024] forming a second dielectric layer and a third electrode plate in sequence on the first dielectric layer, wherein the second dielectric layer covers the first dielectric layer and the second electrode plate, and the third electrode plate covers the second dielectric layer;

[0025] Part of the second dielectric layer and the third electrode plate are removed by etching, and the remaining second dielectric layer covers a part of the top surface of the second electrode plate, and the remaining third electrode plate covers the second electrode plate.

[0026] Optionally, after forming the third electrode plate, the method further includes:

[0027] Etching the first dielectric layer to form a first opening exposing the step surface of the first electrode plate;

[0028] Filling the first opening with a first conductive material to form a plug;

[0029] forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer covers the third electrode plate, the second electrode plate and the first dielectric layer, and the second dielectric layer and the first dielectric layer form a dielectric layer;

[0030] Etching the second dielectric layer to form second openings respectively exposing the second electrode plate, the third electrode plate and the plug;

[0031] A second conductive material is formed on the second dielectric layer. The second conductive material also fills the second opening. The portion of the second conductive material located in the second opening constitutes a plurality of electrical connectors. The portion of the second conductive material located on the second dielectric layer constitutes a metal wiring layer. The metal wiring layer is electrically connected to the first electrode plate, the second electrode plate, and the third electrode plate through the plurality of electrical connectors.

[0032] Optionally, the substrate has a capacitor region and a storage region, a gate structure is formed in the storage region, the support layer is formed in the capacitor region, and the support layer and the gate structure are formed synchronously.

[0033] The present invention provides a PPM capacitor and a preparation method thereof, wherein the PPM capacitor comprises: a substrate, a support layer formed on the substrate; a PIP capacitor structure, comprising a first electrode plate, a first dielectric layer and a second electrode plate, wherein the first electrode plate is located on the substrate and wraps the support layer so that the first electrode plate is in a convex shape, and the first dielectric layer and the second electrode plate are sequentially located on the convex top surface of the first electrode plate; a second dielectric layer is located on the second electrode plate and covers a portion of the top surface of the second electrode plate; and a third electrode plate is located on the second dielectric layer. By adding the third electrode plate, the capacitor formed by the third electrode plate and the second electrode plate is connected in parallel with the PIP capacitor structure, thereby increasing the capacitance value of the capacitor without increasing the size of the capacitor.

[0034] In addition, the support layer is formed under the first electrode plate to raise the height of the PIP capacitor structure, thereby ensuring the overall thickness of the device while facilitating the contact between the PIP capacitor structure and the second dielectric layer; at the same time, the support layer makes the thickness of the convex-shaped first electrode plate consistent at all locations; the step surface of the first electrode plate and the second electrode plate not covered by the second dielectric layer facilitate the lead-out of the first electrode plate and the second electrode plate in subsequent processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A flow chart of a method for preparing a PPM capacitor provided by an embodiment of the present invention;

[0036] Figures 2 to 9 A schematic structural diagram corresponding to corresponding steps of a method for preparing a PPM capacitor provided in an embodiment of the present invention;

[0037] The accompanying drawings are as follows:

[0038] 100 - substrate; 104 - support layer; 105 - first polysilicon layer; 106 - first electrode plate; 108 - first dielectric layer; 109 - second polysilicon layer; 110 - second electrode plate; 112 - first dielectric layer; 111 - plug; 114 - second dielectric layer; 116 - third electrode plate; 117 - second dielectric layer; 118 - electrical connector. DETAILED DESCRIPTION

[0039] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0040] Hereinafter, the terms "first", "second", etc. are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological sequence. It is to be understood that these terms used in this manner are interchangeable where appropriate. Similarly, if the method described herein includes a series of steps, the steps presented herein are not necessarily the only order in which the steps can be performed, and some of the steps described may be omitted and / or other steps not described in the text may be added to the method.

[0041] Fig. 9 The schematic diagram of the structure of the PPM capacitor provided in this embodiment is as follows: Fig. 9 As shown, this embodiment provides a PPM capacitor, including: a substrate 100 , a PIP capacitor structure, a second dielectric layer 114 and a third electrode plate 116 .

[0042] Specifically, the substrate 100 further has a support layer 104, the support layer 104 covers a portion of the substrate 100, the support layer 104 includes a plurality of support pillars arranged at intervals, and the support pillars include a polysilicon layer and an insulating layer covering the polysilicon layer. The height of the support layer 104 is The width of the support column in the support layer 104 And the distance between each of the support columns is less than

[0043] The PIP capacitor structure includes: a first electrode plate 106, a first dielectric layer 108 and a second electrode plate 110. The first electrode plate 106 is located on the substrate 100 and wraps the support layer 104 so that the first electrode plate 106 is in a convex shape. The first dielectric layer 108 and the second electrode plate 110 are sequentially located on the convex top surface of the first electrode plate 106.

[0044] Further, the second dielectric layer 114 is located on the second electrode plate 110 and covers a portion of the top surface of the second electrode plate 110, and the third electrode plate 116 is located on the second dielectric layer 114. The capacitor formed by the third electrode plate 116 and the second electrode plate 110 is connected in parallel with the PIP capacitor structure, thereby increasing the capacitance value of the capacitor without increasing the capacitor area.

[0045] The PPM capacitor of this embodiment further includes: a dielectric layer, which is located on the substrate 100 and covers the PIP capacitor structure and the third plate 116; and a metal wiring layer, which is located on the dielectric layer and is electrically connected to the first plate 106, the second plate 110 and the third plate 116 through a plurality of electrical connectors 118. The dielectric layer includes a first dielectric layer 112 and a second dielectric layer 117, wherein the first dielectric layer 112 is located on the substrate 100 and covers the substrate 100 and the PIP capacitor structure, and the first dielectric layer 112 exposes the upper surface of the second plate 110, and the second dielectric layer 117 is located on the first dielectric layer 112 and covers the third plate 116.

[0046] The support layer 104 is insulated from the PIP capacitor structure. The support layer 104 makes the first electrode plate 106 convex and raises the height of the first electrode plate 106, that is, the thickness of the PIP capacitor structure is increased without changing the thickness of the first electrode plate 106 and the second electrode plate 110. While ensuring the thickness of the first dielectric layer 112, the upper surface of the second electrode plate 110 is exposed from the first dielectric layer 112 to form the third electrode plate 116 on the second electrode plate 110.

[0047] Figure 1 A flow chart of a method for preparing a PPM capacitor provided in this embodiment, such as Figure 1 As shown, the present invention provides a method for preparing a PPM capacitor, comprising:

[0048] Step S1: providing a substrate, and forming a support layer on the substrate, wherein the support layer covers a portion of the substrate;

[0049] Step S2: forming a PIP capacitor structure on the substrate, the PIP capacitor structure comprising a first electrode plate, a first dielectric layer and a second electrode plate, the first electrode plate being located on the substrate and wrapping the support layer so that the first electrode plate is in a convex shape, the first dielectric layer and the second electrode plate sequentially covering the convex top surface of the first electrode plate;

[0050] Step S3: forming a second dielectric layer on the second electrode plate, wherein the second dielectric layer covers a portion of the top surface of the second electrode plate;

[0051] Step S4: forming a third electrode plate on the second dielectric layer, wherein the third electrode plate covers the second dielectric layer.

[0052] Figures 2 to 9 The structural schematic diagram corresponding to the corresponding steps of the preparation method of a PPM capacitor provided in this embodiment is shown below in conjunction with the attached Figures 2 to 9 A method for preparing a PPM capacitor provided in this embodiment is described in more detail, wherein a preferred embodiment of the present invention is illustrated.

[0053] like Figure 2 As shown, a substrate 100 is provided, and the substrate 100 has a capacitor region. In order to achieve dielectric isolation between devices in an integrated single circuit, a buried oxide layer (not shown) is also formed on the substrate 100, and the buried oxide layer can eliminate parasitic latch effects; then a support layer 104 is formed on the buried oxide layer, and the support layer 104 covers a portion of the substrate 100.

[0054] In addition, the substrate 100 also has a storage area (not shown), a gate structure is formed on the storage area, and the support layer 104 is formed simultaneously with the gate structure to reduce the number of process steps. In this embodiment, the support layer 104 includes a plurality of support pillars arranged at intervals, and the support pillars include a polysilicon layer and an insulating layer covering the polysilicon layer.

[0055] In other optional embodiments, the polysilicon in the support column may also be replaced by silicon oxide, silicon nitride, etc., and the present invention is not limited to this.

[0056] like Figure 3 As shown, a first polysilicon layer 105, a first dielectric layer 108, and a second polysilicon layer 109 are sequentially formed on the substrate 100, wherein the first polysilicon layer 105 covers the support layer 104 and the substrate 100, the first dielectric layer 108 covers the first polysilicon layer 105, and the second polysilicon layer 109 covers the first dielectric layer 108. Since the first polysilicon layer 105 conformally covers the support layer 104, the first polysilicon layer 105 is in a convex shape.

[0057] Wherein, the thickness of the first polysilicon layer 105 is The thickness of the first dielectric layer 108 is The thickness of the second polysilicon layer 109 is

[0058] like Figure 4 As shown, the second polysilicon layer 109 and the first dielectric layer 108 outside the convex top surface of the first polysilicon layer 105 are etched away, and the remaining second polysilicon layer 109 forms a second electrode 110. Then, etching continues to remove a portion of the first polysilicon layer 105 on the substrate 100, retaining the convex structure of the first polysilicon layer 105, and the remaining first polysilicon layer 105 forms a first electrode 106. The first electrode 106, the first dielectric layer 108 and the second electrode 110 form a PIP capacitor structure.

[0059] The first electrode plate 106 is insulated from the support layer 104 by an insulating layer. The support layer 104 enables the first electrode plate 106 to form a convex structure without changing the thickness of the first electrode plate 106 .

[0060] like Figure 5 As shown, a first dielectric layer 112 is formed on the substrate 100 , and the first dielectric layer 112 covers the substrate 100 and the PIP capacitor structure.

[0061] like Figure 6 As shown, the first dielectric layer 112 is planarized until the upper surface of the second electrode plate 110 is exposed. The planarization process may be chemical mechanical polishing.

[0062] Specifically, Figure 5 The thickness of the first dielectric layer 112 shown in FIG. The thickness of the traditional PIP capacitor structure is generally If the upper surface of the PIP capacitor structure is to be exposed, the first dielectric layer 112 to be ground is relatively thick, which will introduce other problems during the chemical mechanical polishing process and affect the performance of the device. In this embodiment, the height of the first electrode plate 106 is raised by the support layer 104 without changing the thickness of each film layer of the PIP capacitor structure, thereby increasing the overall thickness of the PIP capacitor structure to The thickness of the first dielectric layer 112 that needs to be polished is greatly reduced, thereby reducing problems that may occur during the chemical mechanical polishing process and increasing the reliability of the semiconductor device.

[0063] like Figure 7As shown, a second dielectric layer 114 and a third electrode plate 116 are formed on the first dielectric layer 112, wherein the second dielectric layer 114 covers the second electrode plate 110 and the first dielectric layer 108, and the third electrode plate 116 covers the second dielectric layer 114. Then, a portion of the metal layer and the second dielectric layer 114 are removed by etching, and the remaining second dielectric layer 114 covers a portion of the second electrode plate 110, and the remaining third electrode plate 116 covers the second dielectric layer 114.

[0064] like Figure 8 As shown, the first dielectric layer 112 is etched to form a first opening exposing the first electrode plate 106 in the first dielectric layer 112 , and a first conductive material is filled in the first opening to form a plug 111 electrically connected to the first electrode plate 106 .

[0065] like Fig. 9 As shown, a second dielectric layer 117 is formed on the first dielectric layer 112 , the second dielectric layer 117 covers the PIP capacitor structure, the first dielectric layer 112 and the third electrode 116 , and the second dielectric layer 117 and the first dielectric layer 112 form a dielectric layer.

[0066] Further, the second dielectric layer 117 is etched to form second openings that expose the third electrode 116, the second electrode 110 and the plug 111 respectively, and a second conductive material is formed on the second dielectric layer 117. The second conductive material also fills the second opening. The portion of the second conductive material located in the second opening constitutes a plurality of electrical connectors 118. The portion of the second conductive material located on the second dielectric layer 117 constitutes a metal wiring layer. The electrical connectors 118 are electrically connected to the first electrode 106, the second electrode 110 and the third electrode 116 respectively. The metal wiring layer is electrically connected to the first electrode 106, the second electrode 110 and the third electrode 116 through the electrical connectors 118.

[0067] In the capacitor provided in this embodiment, the first electrode plate 106, the first dielectric layer 108 and the second electrode plate 110 form the PIP capacitor structure; the third electrode plate 116, the second dielectric layer 114 and the second electrode plate 110 form a metal capacitor structure, and the metal capacitor structure and the PIP capacitor structure are connected in parallel to form a PPM capacitor. The PPM capacitor adds the third electrode plate 116 on the basis of the original PIP capacitor structure. By connecting capacitors in parallel, the capacitance value of the PPM capacitor is increased without increasing the area of ​​the PIP capacitor structure.

[0068] In summary, the present invention provides a PPM capacitor and a preparation method thereof, comprising: a substrate 100, on which a support layer 104 is formed; a PIP capacitor structure, comprising a first electrode plate 106, a first dielectric layer 108 and a second electrode plate 110, wherein the first electrode plate 106 is located on the substrate 100 and wraps the support layer 104 so that the first electrode plate 106 is in a convex shape, and the first dielectric layer 108 and the second electrode plate 110 are sequentially located on the convex top surface of the first electrode plate 106; a second dielectric layer 114 is located on the second electrode plate 110 and covers a portion of the top surface of the second electrode plate 110; and a third electrode plate 116 is located on the second dielectric layer 114. By adding the third electrode plate 116, the capacitor formed by the third electrode plate 116 and the second electrode plate 110 is connected in parallel with the PIP capacitor structure, thereby increasing the capacitance value of the capacitor without increasing the size of the capacitor. In addition, the support layer 104 is formed under the first electrode plate 106 to raise the height of the PIP capacitor structure, thereby ensuring the overall thickness of the device and facilitating the contact between the PIP capacitor structure and the second dielectric layer 114; at the same time, the support layer 104 makes the thickness of the convex-shaped first electrode plate 106 consistent at all locations; the step surface of the first electrode plate 106 and the second electrode plate 110 not covered by the second dielectric layer 114 facilitate the first electrode plate 104 and the second electrode plate 110 to be led out in the subsequent process.

[0069] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. A method for preparing a PPM capacitor, characterized in that: include: Providing a substrate, and forming a support layer on the substrate, wherein the support layer covers a portion of the substrate; A PIP capacitor structure is formed on the substrate, wherein the PIP capacitor structure includes a first electrode plate, a first dielectric layer, and a second electrode plate, wherein the first electrode plate is located on the substrate and wraps the support layer so that the first electrode plate is in a convex shape, and the first dielectric layer and the second electrode plate sequentially cover the convex top surface of the first electrode plate; forming a second dielectric layer on the second electrode plate, wherein the second dielectric layer covers a portion of the top surface of the second electrode plate; forming a third electrode plate on the second dielectric layer, wherein the third electrode plate covers the second dielectric layer; Before forming the second dielectric layer and after forming the PIP capacitor structure, the method further includes: forming a first dielectric layer on the substrate, wherein the first dielectric layer covers the PIP capacitor structure and the substrate; Performing a planarization process on the first dielectric layer until the upper surface of the second electrode plate is exposed; The steps of forming the second dielectric layer and the third electrode plate include: forming a second dielectric layer and a third electrode plate in sequence on the first dielectric layer, wherein the second dielectric layer covers the first dielectric layer and the second electrode plate, and the third electrode plate covers the second dielectric layer; Part of the second dielectric layer and the third electrode plate are removed by etching, and the remaining second dielectric layer covers a part of the top surface of the second electrode plate, and the remaining third electrode plate covers the second electrode plate.

2. The method for preparing a PPM capacitor according to claim 1, characterized in that: After forming the third electrode plate, the method further includes: Etching the first dielectric layer to form a first opening exposing the step surface of the first electrode plate; Filling the first opening with a first conductive material to form a plug; forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer covers the third electrode plate, the second electrode plate and the first dielectric layer, and the second dielectric layer and the first dielectric layer form a dielectric layer; Etching the second dielectric layer to form second openings respectively exposing the second electrode plate, the third electrode plate and the plug; A second conductive material is formed on the second dielectric layer. The second conductive material also fills the second opening. The portion of the second conductive material located in the second opening constitutes a plurality of electrical connectors. The portion of the second conductive material located on the second dielectric layer constitutes a metal wiring layer. The metal wiring layer is electrically connected to the first electrode plate, the second electrode plate, and the third electrode plate through the plurality of electrical connectors.

3. The method for preparing a PPM capacitor according to claim 1, characterized in that: The substrate has a capacitor region and a storage region, a gate structure is formed in the storage region, the support layer is formed in the capacitor region, and the support layer is formed synchronously with the gate structure.

4. A PPM capacitor, characterized in that: The method for preparing a PPM capacitor according to any one of claims 1 to 3 comprises: a substrate having a support layer formed thereon; A PIP capacitor structure, comprising a first electrode plate, a first dielectric layer and a second electrode plate, wherein the first electrode plate is located on the substrate and wraps the support layer so that the first electrode plate is in a convex shape, and the first dielectric layer and the second electrode plate are sequentially located on the convex top surface of the first electrode plate; A second dielectric layer, located on the second electrode plate and covering a portion of the top surface of the second electrode plate; A third electrode plate, located on the second dielectric layer; A dielectric layer is located on the substrate and covers the PIP capacitor structure and the third electrode plate, the dielectric layer includes a first dielectric layer and a second dielectric layer, the first dielectric layer is located on the substrate, covers the substrate and the PIP capacitor structure, and the first dielectric layer exposes the upper surface of the second electrode plate, and the second dielectric layer is located on the first dielectric layer and covers the third electrode plate.

5. A PPM capacitor as claimed in claim 4, characterized in that: Also includes: The metal wiring layer is located on the dielectric layer and is electrically connected to the first electrode plate, the second electrode plate and the third electrode plate through an electrical connector.

6. A PPM capacitor as claimed in claim 4, characterized in that: The height of the support layer is 7. A PPM capacitor as claimed in claim 4, characterized in that: The supporting layer comprises a plurality of support pillars arranged at intervals, and the support pillars comprise a polysilicon layer and an insulating layer covering the polysilicon layer.

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