A signal acquisition circuit and a signal acquisition method

Abstract

The application discloses a signal acquisition circuit and a signal acquisition method. The signal acquisition circuit comprises N (N>=1) operational amplifier circuits, feedback channels, an ADC chip and a processor. The feedback channels comprise switches and resistors connected in series. At least two feedback channels are connected in parallel between the output end and the inverting input end of at least one operational amplifier circuit. The output end of the operational amplifier circuit is connected to the ADC chip. The ADC chip is used for acquiring the voltage output by the operational amplifier circuit and outputting the acquired voltage to the processor. The processor is used for calculating the current value according to the voltage output by the operational amplifier circuit, and controlling the resistance value of the feedback channel connected to the operational amplifier circuit by sending a control signal to the switch in the feedback channel according to the current value, so as to control the amplification multiple of the operational amplifier circuit. The signal acquisition circuit can reduce the cost while meeting the high precision.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of signal acquisition, in particular to a signal acquisition circuit, and a signal acquisition method. BACKGROUND

[0002] At present, many products need to achieve high-precision signal acquisition when in use. In order to achieve high-precision signal acquisition, the traditional technical solution is to use a high-precision ADC chip in the signal acquisition circuit. However, the high-precision ADC chip is relatively expensive. Although the use of the high-precision ADC chip can achieve high precision, it will increase the overall cost of the product, thereby affecting the competitiveness of the product. Therefore, reducing the cost while meeting the high precision will undoubtedly have a positive effect on the product. Therefore, how to reduce the cost while meeting the high precision has become a technical problem to be solved by the technical personnel in the field. SUMMARY

[0003] The purpose of the present application is to provide a signal acquisition circuit and a signal acquisition method, which can ensure the acquisition precision under the condition of using a low-precision ADC chip, so as to reduce the cost while meeting the high precision.

[0004] To solve the above technical problems, the present application provides a signal acquisition circuit, comprising:

[0005] N-channel operational amplifier circuits, N≥1, a feedback channel, an ADC chip and a processor; the feedback channel comprises switches and resistors connected in series; at least two feedback channels are connected in parallel between the output end and the inverting input end of at least one operational amplifier circuit; the ADC chip is connected to the output end of the operational amplifier circuit;

[0006] The ADC chip is configured to acquire the voltage output by the operational amplifier circuit and output the acquired voltage to the processor;

[0007] The processor is configured to calculate the current value according to the voltage output by the operational amplifier circuit, and control the resistance value of the feedback channel connected to the operational amplifier circuit by sending a control signal to the switch in the feedback channel according to the current value, so as to control the amplification multiple of the operational amplifier circuit.

[0008] Optionally, the signal acquisition circuit specifically comprises:

[0009] a first operational amplifier circuit and a second operational amplifier circuit;

[0010] The inverting input end of the first operational amplifier circuit is used as the input end of the signal acquisition circuit, the output end of the first operational amplifier circuit is connected with the inverting input end of the second operational amplifier circuit and the ADC chip, and the output end of the second operational amplifier circuit is connected with the ADC chip.

[0011] Optionally, the signal acquisition circuit specifically comprises:

[0012] The first feedback channel group comprises p feedback channels, and the second feedback channel group comprises q feedback channels; p is greater than or equal to 2, and q is greater than or equal to 2;

[0013] Each feedback channel of the first feedback channel group is connected in parallel between the output end and the inverting input end of the first operational amplifier circuit;

[0014] Each feedback channel of the second feedback channel group is connected in parallel between the output end and the inverting input end of the second operational amplifier circuit.

[0015] To solve the above technical problems, the application further provides a signal acquisition method, comprising:

[0016] Receiving a voltage output by an operational amplifier circuit collected by an ADC chip, and calculating a current value according to the voltage output by the operational amplifier circuit;

[0017] According to the current value, determining a target resistance value of a feedback channel connected to the operational amplifier circuit; the feedback channel is connected in parallel between the output end and the inverting input end of the operational amplifier circuit;

[0018] Controlling the resistance value of the feedback channel connected to the operational amplifier circuit to be the target resistance value, so that the amplification multiple of the operational amplifier circuit reaches a target amplification multiple.

[0019] Optionally, the determining the target resistance value of the feedback channel connected to the operational amplifier circuit according to the current value comprises:

[0020] According to the current value, determining the target resistance value of each operational amplifier circuit step by step; if the target resistance value of the operational amplifier circuit of the previous stage is the maximum, and the target resistance value and the current value still satisfy a preset condition, then determining the target resistance value of the operational amplifier circuit of the next stage; if the target resistance value of the operational amplifier circuit of the previous stage is the maximum, and the target resistance value and the current value do not satisfy the preset condition, then not determining the target resistance value of the operational amplifier circuit of the next stage and subsequent stages.

[0021] Optionally, the determining the target resistance value of each operational amplifier circuit step by step according to the current value comprises:

[0022] According to the current value, target resistance values of the first-stage operational amplifier circuit and the second-stage operational amplifier circuit are determined step by step; an output terminal of the first-stage operational amplifier circuit is connected to an inverting input terminal of the second-stage operational amplifier circuit.

[0023] Optionally, determining the target resistance value of the first-stage operational amplifier circuit according to the current value comprises:

[0024] A resistance value is selected from a first preset resistance domain, and a maximum resistance value capable of satisfying a first preset condition is taken as the target resistance value of the first-stage operational amplifier circuit.

[0025] Optionally, determining the target resistance value of the second-stage operational amplifier circuit according to the current value comprises:

[0026] A resistance value is selected from a second preset resistance domain, and a maximum resistance value capable of satisfying a second preset condition is taken as the target resistance value of the second-stage operational amplifier circuit.

[0027] Optionally, the step of selecting the resistance value from the first preset resistance domain and taking the maximum resistance value capable of satisfying the first preset condition as the target resistance value of the first-stage operational amplifier circuit comprises:

[0028] A resistance value is selected from the first preset resistance domain, and a maximum resistance value capable of satisfying I

[0029] wherein I represents the current value, VREF represents a reference voltage connected to the non-inverting input terminal of the first-stage operational amplifier circuit, and Ra represents the resistance value selected from the first preset resistance domain.

[0030] Optionally, the step of selecting the resistance value from the second preset resistance domain and taking the maximum resistance value capable of satisfying the second preset condition as the target resistance value of the second-stage operational amplifier circuit comprises:

[0031] A resistance value is selected from the second preset resistance domain, and a maximum resistance value capable of satisfying I

[0032] wherein I represents the current value, VCC represents a voltage connected to a power supply terminal of the second-stage operational amplifier circuit, VREF represents a reference voltage connected to the non-inverting input terminal of the second-stage operational amplifier circuit, R represents a resistance value connected between the output terminal of the first-stage operational amplifier circuit and the inverting input terminal of the second-stage operational amplifier circuit, Ramax represents a maximum resistance value of the first preset resistance domain, and Rb represents the resistance value selected from the second preset resistance domain.

[0033] The signal acquisition circuit provided in this application includes: N operational amplifier circuits, N≥1, a feedback channel, an ADC chip, and a processor; the feedback channel includes a switch and a resistor connected in series; at least two feedback channels are connected in parallel between the output terminal and the inverting input terminal of at least one operational amplifier circuit; the ADC chip is connected to the output terminal of the operational amplifier circuit; the ADC chip is used to acquire the voltage output by the operational amplifier circuit and output the acquired voltage to the processor; the processor is used to calculate the current value based on the voltage output by the operational amplifier circuit, and based on the current value, control the resistance value of the feedback channel connected to the operational amplifier circuit by sending a control signal to the switch in the feedback channel, so as to control the amplification factor of the operational amplifier circuit.

[0034] As can be seen, the signal acquisition circuit provided in this application has a feedback channel connected in parallel between the output terminal and the inverting input terminal of the operational amplifier circuit. The feedback channel includes a switch and a resistor. By controlling the conduction state of the feedback channel, the resistance between the output terminal and the inverting input terminal of the operational amplifier circuit can be controlled, thereby controlling the amplification factor of the operational amplifier circuit. Thus, by controlling the amplification factor of the operational amplifier circuit, the best accuracy can be achieved without exceeding the range. Even when using a low-precision ADC chip, accuracy can still be guaranteed.

[0035] The signal acquisition method provided in this application also has the above-mentioned technical effects. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 A schematic diagram of a first signal acquisition circuit provided in an embodiment of this application;

[0038] Figure 2 This is a schematic diagram of a second signal acquisition circuit provided in an embodiment of this application;

[0039] Figure 3 This is a schematic diagram of a third signal acquisition circuit provided in an embodiment of this application;

[0040] Figure 4 This is a schematic flowchart of a signal acquisition method provided in an embodiment of this application. Detailed Implementation

[0041] The core of the present application is to provide a signal acquisition circuit and a signal acquisition method, which can ensure the acquisition accuracy in the case of using a low-precision ADC chip, thereby realizing the reduction of cost while meeting high accuracy.

[0042] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in a clear and complete manner with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0043] Please refer to Figure 1 , Figure 1 A schematic diagram of a signal acquisition circuit provided by the embodiments of the present application is shown in FIG. 1. The signal acquisition circuit mainly includes: Figure 1

[0044] N operational amplifier circuits 10, N≥1, a feedback channel 20, an ADC chip 30 and a processor 40. The feedback channel 20 includes switches and resistors connected in series. At least two feedback channels 20 are connected in parallel between the output end and the inverting input end of at least one operational amplifier circuit 10. The ADC chip 30 is connected to the output end of the operational amplifier circuit 10.

[0045] The ADC chip 30 is configured to acquire the voltage output by the operational amplifier circuit 10 and output the acquired voltage to the processor 40.

[0046] The processor 40 is configured to calculate the current value according to the voltage output by the operational amplifier circuit 10, and control the resistance value of the feedback channel 20 connected to the operational amplifier circuit by sending a control signal to the switch in the feedback channel 20 according to the current value, so as to control the amplification factor of the operational amplifier circuit 10.

[0047] ​Specifically, the signal acquisition circuit provided in the application comprises one or more than one operational amplifier circuit 10, a feedback circuit, an ADC chip 30 and a processor 40. The non-inverting input end of each operational amplifier circuit 10 is connected with a reference voltage, and specifically, the reference voltage can be connected after being connected with one or more than one resistor in series. The inverting input end of the operational amplifier circuit 10 is input with a current signal, and the output end of the operational amplifier circuit 10 is connected with the ADC chip 30. At least two feedback channels 20 are connected in parallel between the inverting input end and the output end of at least one operational amplifier circuit 10. The feedback channel 20 comprises a switch and a resistor. Thus, by controlling the state of the switch, the resistance value of the resistor connected to the operational amplifier circuit 10 can be controlled, and then the amplification multiple of the operational amplifier circuit 10 can be controlled.

[0048] The current signal input into the inverting input end of the operational amplifier circuit 10 is amplified by the operational amplifier circuit 10 and then output, the ADC chip 30 connected with the output end of the operational amplifier circuit 10 acquires the voltage output by the operational amplifier circuit 10, and further transmits the voltage output by the operational amplifier circuit 10 to the processor 40, and then the processor 40 calculates the current value to be acquired according to the voltage output by the operational amplifier circuit 10. In order to achieve the best accuracy, the processor 40 will control the switch in the feedback channel 20 according to the input current, control the conduction state of the feedback channel 20, and then control the resistance between the output end and the inverting input end of the operational amplifier circuit 10, so as to change the amplification multiple of the operational amplifier circuit 10, so as to achieve the best accuracy without exceeding the range.

[0049] The processor 40 can gradually increase the amplification multiple of the operational amplifier circuit 10 by controlling the switch of the feedback channel 20 until the best accuracy is achieved without exceeding the range. In addition, the processor 40 can adjust the amplification multiple of each operational amplifier circuit 10 one by one until the best accuracy is achieved without exceeding the range.

[0050] If one operational amplifier circuit 10 is set, in order to obtain a larger amplification multiple, a larger resistor needs to be connected in parallel between the output end and the inverting input end of the operational amplifier circuit 10, and if the resistor connected in parallel between the output end and the inverting input end of the operational amplifier circuit 10 is too large, the resistance accuracy and the stability of the circuit will be affected.

[0051] Therefore, in order to obtain a larger amplification multiple, ensure the stability of the circuit and reduce the cost, in a specific embodiment, the signal acquisition circuit specifically comprises: a first operational amplifier circuit and a second operational amplifier circuit; the inverting input end of the first operational amplifier circuit is used as the input end of the signal acquisition circuit, the output end of the first operational amplifier circuit is connected with the inverting input end of the second operational amplifier circuit and the ADC chip 30, and the output end of the second operational amplifier circuit is connected with the ADC chip 30.

[0052] Specifically, referring to Figure 2 In this embodiment, the signal acquisition circuit is specifically provided with two-stage operational amplification circuits 10. The inverting input end of the first operational amplification circuit 101 serves as the input end of the entire signal acquisition circuit. The current signal flows into the inverting input end of the first operational amplification circuit 101, is amplified by the first operational amplification circuit 101, and then is amplified by the second operational amplification circuit 102. The ADC chip 30 is connected to the output end of each stage of operational amplification circuit 10 to collect the voltage output by each stage of operational amplification circuit 10.

[0053] In the case where the signal acquisition circuit is provided with two-stage operational amplification circuits 10, at least two feedback channels 20 can be connected in parallel between the output end and the inverting input end of one stage of operational amplification circuit 10, so that the amplification multiple of one stage of operational amplification circuit 10 is adjustable, while the amplification multiple of the other stage of operational amplification circuit 10 is fixed. At least two feedback channels 20 can also be connected in parallel between the output end and the inverting input end of each stage of operational amplification circuit 10, so that the amplification multiple of each stage of operational amplification circuit 10 is adjustable.

[0054] Specifically, referring to Figure 2 In a specific embodiment, the signal acquisition circuit specifically includes: a first feedback channel group 21 and a second feedback channel group 22, the first feedback channel group 21 includes p feedback channels 20, and the second feedback channel group 22 includes q feedback channels 20; p≥2, q≥2; each feedback channel 20 of the first feedback channel group 21 is connected in parallel between the output end and the inverting input end of the first operational amplification circuit 101; and each feedback channel 20 of the second feedback channel group 22 is connected in parallel between the output end and the inverting input end of the second operational amplification circuit 102.

[0055] Specifically, on the basis of the two-stage operational amplification circuits 10, the embodiment is provided with two groups of feedback channels 20, each group of feedback channels 20 including at least two feedback channels 20. The first feedback channel group 21 is connected in parallel between the output end and the inverting input end of the first operational amplification circuit 101, so that the amplification multiple of the first operational amplification circuit 101 is adjustable. The second feedback channel group 22 is connected in parallel between the output end and the inverting input end of the second operational amplification circuit 102, so that the amplification multiple of the second operational amplification circuit 102 is adjustable.

[0056] The number of feedback channels 20 included in the first feedback channel group 21 can be equal to or different from the number of feedback channels 20 included in the second feedback channel group 22. The specific number of feedback channels 20 included in the first feedback channel group 21 and the second feedback channel group 22 is not limited in the present application and can be set differently.

[0057] Based on the above embodiments, as a specific implementation, the resistance values ​​of the resistors in different feedback channels 20 are different. When any one feedback channel 20 is turned on, the amplification factor of the operational amplifier circuit 10 will be different. Thus, the processor 40 only needs to control the turn on of a single feedback channel 20 to adjust the amplification factor of the operational amplifier circuit 10.

[0058] It is understood that, in addition to the above-described embodiments, the resistances in each feedback channel 20 can also be equal. In this case, the processor 40 can control the number of conducting feedback channels 20 and thus control the resistance between the output terminal and the inverting input terminal of the operational amplifier circuit 10, thereby controlling the amplification factor of the operational amplifier circuit 10.

[0059] Furthermore, based on the above embodiments, as a specific implementation, the ADC chip 30 and the processor 40 are connected via an SPI bus or an I2C bus. In this way, the ADC chip 30 transmits the acquired voltage to the processor 40 via the SPI bus or the I2C bus.

[0060] Furthermore, based on the above embodiments, as a specific implementation, the switch in the feedback channel 20 is an analog switch. The processor 40 is connected to the analog switch via an SPI bus or an I2C bus. Thus, the processor 40 sends control signals to the analog switch in the feedback channel 20 via the SPI bus or the I2C bus.

[0061] Furthermore, based on the above embodiments, as a specific implementation method, it also includes:

[0062] A capacitor is connected in parallel between the output terminal and the inverting input terminal of the operational amplifier circuit. For example, refer to... Figure 3 As shown, a capacitor C1 is connected in parallel between the output terminal and the inverting input terminal of operational amplifier circuit U1A, and a capacitor C2 is connected in parallel between the output terminal and the inverting input terminal of operational amplifier circuit U1B.

[0063] refer to Figure 3 As shown, the following example illustrates an embodiment of current signal acquisition provided in this application, using a signal acquisition circuit comprising two stages of operational amplifier circuits, with a set of feedback channels connected in parallel between the output terminal and the inverting input terminal of each stage of operational amplifier circuit, and each set of feedback channels comprising three feedback channels:

[0064] The resistance values ​​of resistors R1, R2, and R3 are set to increase sequentially, and the resistance values ​​of resistors R4, R5, and R6 are set to increase sequentially. Among them, the resistance values ​​of R3 and R6 generally do not exceed 1MΩ.

[0065] First, controllable switches K1 and K4 are closed, switch K1 and resistor R1 in the feedback channel are turned on, resistor R1 is connected between the output end and the inverting input end of the operational amplifier circuit U1A, switch K4 and resistor R4 in the feedback channel are turned on, resistor R4 is connected between the output end and the inverting input end of the operational amplifier circuit U1B. Other feedback channels are open. At this time, the current signal flows from the inverting input end of the operational amplifier circuit U1A, is amplified by the operational amplifier circuit U1A, and the operational amplifier circuit U1A outputs a voltage Vout1_1. According to the voltage Vout1_1 output by the operational amplifier circuit U1A, the input current I=(VREF-Vout1_1) / R1 is calculated. Then, according to the input current, the number of operational amplifier circuits to be used and the amplification factor of each two-stage operational amplifier circuit are determined.

[0066] The specific determination method is as follows:

[0067] If VREF-I*R1>0, VREF-I*R2≤0, that is, VREF / R2≤I<VREF / R1, at this time, the current I=(VREF-Vout1_1) / R1 calculated by directly using the collected voltage Vout1_1 output by the operational amplifier circuit U1A is used as the result.

[0068] If VREF-I*R2>0, and VREF-I*R3≤0, that is, VREF / R3≤I<VREF / R2, then switch K1 is opened, switch K2 is controlled to be closed, switch K2 and resistor R2 in the feedback channel are turned on, resistor R2 is connected between the output end and the inverting input end of the operational amplifier circuit U1A, and then the voltage output by the operational amplifier circuit U1A is re-collected to obtain Vout1_2. According to the voltage Vout1_2 output by the operational amplifier circuit U1A at this time, the current value to be collected is calculated.

[0069] If VREF-I*R3>0, that is, I<VREF / R3 and the current I is close to VREF / R3, then switch K1 is opened, switch K3 is controlled to be closed, switch K3 and resistor R3 in the feedback channel are turned on, resistor R3 is connected between the output end and the inverting input end of the operational amplifier circuit U1A, and then the voltage output by the operational amplifier circuit U1A is re-collected to obtain Vout1_3. According to the voltage Vout1_3 output by the operational amplifier circuit U1A at this time, the current value to be collected is calculated.

[0070] If I<VREF / R3 and I is much smaller than VREF / R3, then switch K3 is kept closed, and it is considered to continue two-stage amplification.

[0071] The current is amplified by the operational amplifier circuit U1A and then passes through R7 (a resistor between the two operational amplifier circuits) and R4, and the operational amplifier circuit U1B outputs a voltage Vout2_4.

[0072] If Vout2_4 = VREF + (VREF - Vout1_3) * R4 / R7 = VREF + I*R3*R4 / R7 < VCC, that is, I < (VCC-VREF)*R7 / (R3*R4), and the current I is close to (VCC-VREF)*R7 / (R3*R4), the current value to be collected is calculated according to the voltage Vout2_4 output by the operational amplifier circuit U1B when the resistor R4 is connected.

[0073] If VREF + I*R3*R5 / R7 < VCC, and VREF + I*R3*R6 / R7 ≥ VCC, that is, (VCC-VREF)*R7 / (R3*R6) ≤ I < (VCC-VREF)*R7 / (R3*R5), the switch K4 is disconnected, the switch K5 is controlled to be closed, the switch K5 and the resistor R5 in the feedback channel are turned on, the voltage output by the operational amplifier circuit U1B is collected again, Vout2_5 is obtained, and the current value to be collected is calculated according to Vout2_5.

[0074] If VREF + I*R3*R6 / R7 < VCC, that is, I < (VCC-VREF)*R7 / (R3*R6), the switch K4 is disconnected, the switch K6 is controlled to be closed, the switch K6 and the resistor R6 in the feedback channel are turned on, the voltage output by the operational amplifier circuit U1B is collected again, Vout2_6 is obtained, and the current value to be collected is calculated according to Vout2_6.

[0075] That is, when VREF / R2 ≤ I < VREF / R1, the resistor R1 is connected to the operational amplifier circuit U1A, the voltage output by the operational amplifier circuit U1A is collected, and the current value is calculated according to the voltage output by the operational amplifier circuit U1A at this time;

[0076] When VREF / R3 ≤ I < VREF / R2, the resistor R2 is connected to the operational amplifier circuit U1A, the voltage output by the operational amplifier circuit U1A is collected, and the current value is calculated according to the voltage output by the operational amplifier circuit U1A at this time;

[0077] When I < VREF / R3 and I is close to VREF / R3, the resistor R3 is connected to the operational amplifier circuit U1A, the voltage output by the operational amplifier circuit U1A is collected, and the current value is calculated according to the voltage output by the operational amplifier circuit U1A at this time;

[0078] When I<(VCC-VREF)*R7 / (R3*R4) and I is close to (VCC-VREF)*R7 / (R3*R4), then the resistance R3 is connected to the operational amplifier circuit U1A, and the resistance R4 is connected to the operational amplifier circuit U1B, the voltage output by the operational amplifier circuit U1B is collected, and the current value is obtained by calculating the voltage output by the operational amplifier circuit U1B at this time.

[0079] When (VCC-VREF)*R7 / (R3*R6)≤I<(VCC-VREF)*R7 / (R3*R5), the resistance R3 is connected to the operational amplifier circuit U1A, and the resistance R5 is connected to the operational amplifier circuit U1B, the voltage output by the operational amplifier circuit U1B is collected, and the current value is obtained by calculating the voltage output by the operational amplifier circuit U1B at this time.

[0080] When I<(VCC-VREF)*R7 / (R3*R6), the resistance R3 is connected to the operational amplifier circuit U1A, and the resistance R6 is connected to the operational amplifier circuit U1B, the voltage output by the operational amplifier circuit U1B is collected, and the current value is obtained by calculating the voltage output by the operational amplifier circuit U1B at this time.

[0081] In summary, the signal acquisition circuit provided by the application has a feedback channel connected in parallel between the output end and the inverting input end of the operational amplifier circuit, the feedback channel includes a switch and a resistance, the size of the resistance connected between the output end and the inverting input end of the operational amplifier circuit can be controlled by controlling the conduction state of the feedback channel, so that the amplification multiple of the operational amplifier circuit is controlled, and thus by controlling the amplification multiple of the operational amplifier circuit, the best precision can be achieved without exceeding the range, and the precision can be ensured even if a low-precision ADC chip is used.

[0082] Reference Figure 4 As shown, Figure 4 A flowchart of a signal acquisition method provided by an embodiment of the application is shown, the method is applied to the processor in the signal acquisition circuit embodiment, and mainly includes the following steps.

[0083] S101: receiving the voltage output by the operational amplifier circuit collected by the ADC chip, and obtaining the current value by calculating the voltage output by the operational amplifier circuit;

[0084] S102: determining the target resistance value of the feedback channel connected to the operational amplifier circuit according to the current value; the feedback channel is connected in parallel between the output end and the inverting input end of the operational amplifier circuit;

[0085] S103: controlling the resistance value of the feedback channel connected to the operational amplifier circuit to be the target resistance value, so that the amplification multiple of the operational amplifier circuit reaches the target amplification multiple.

[0086] The target amplification factor refers to an amplification factor of the operational amplification circuit when a resistance value accessed by the operational amplification circuit is a target resistance value.

[0087] In a specific embodiment, the determining, according to the current value, of the target resistance value of the feedback channel accessing the operational amplification circuit comprises:

[0088] The target resistance value of each operational amplification circuit is determined step by step according to the current value; if the target resistance value of the operational amplification circuit of the previous stage is the maximum and the target resistance value and the current value still satisfy a preset condition, the target resistance value of the operational amplification circuit of the next stage is determined again; if the target resistance value of the operational amplification circuit of the previous stage is the maximum and the target resistance value and the current value do not satisfy the preset condition, the target resistance value of the operational amplification circuit of the next stage and each subsequent operational amplification circuit is not determined.

[0089] In the case where the operational amplification circuit comprises two or more than two paths, the target resistance value of each stage of the operational amplification circuit is determined step by step in the embodiment. If the target resistance value of the operational amplification circuit of the previous stage is the maximum and the target resistance value and the current value still satisfy a preset condition, the target resistance value of the operational amplification circuit of the next stage is determined again. If the target resistance value of the operational amplification circuit of the previous stage is the maximum and the target resistance value and the current value do not satisfy the preset condition, the target resistance value of the operational amplification circuit of the next stage and each subsequent operational amplification circuit is not determined.

[0090] On the basis of the above-mentioned embodiments, as a specific embodiment, the target resistance value of each operational amplification circuit is determined step by step according to the current value, which comprises:

[0091] The target resistance value of the first stage of the operational amplification circuit and the second stage of the operational amplification circuit is determined step by step according to the current value; the output end of the first stage of the operational amplification circuit is connected to the inverting input end of the second stage of the operational amplification circuit.

[0092] In the embodiment, the operational amplification circuit comprises two paths. In this regard, the target resistance value of the first stage of the operational amplification circuit and the second stage of the operational amplification circuit is determined step by step in the embodiment.

[0093] The way of determining the target resistance value of the first stage of the operational amplification circuit according to the current value can be:

[0094] The resistance value is selected from a first preset resistance domain, and the maximum resistance value capable of satisfying a first preset condition is taken as the target resistance value of the first stage of the operational amplification circuit.

[0095] The way of determining the target resistance value of the second stage of the operational amplification circuit according to the current value can be:

[0096] selecting a resistance value from the second preset resistance domain and taking the maximum resistance value that can satisfy the second preset condition as the target resistance value of the second stage operational amplifier circuit.

[0097] The selecting a resistance value from the first preset resistance domain and taking the maximum resistance value that can satisfy the first preset condition as the target resistance value of the first stage operational amplifier circuit can include:

[0098] selecting a resistance value from the first preset resistance domain and taking the maximum resistance value that can satisfy I

[0099] wherein I represents the current value, VREF represents a reference voltage connected to the non-inverting input terminal of the first stage operational amplifier circuit, and Ra represents the resistance value selected from the first preset resistance domain.

[0100] The selecting a resistance value from the second preset resistance domain and taking the maximum resistance value that can satisfy the second preset condition as the target resistance value of the second stage operational amplifier circuit can include:

[0101] selecting a resistance value from the second preset resistance domain and taking the maximum resistance value that can satisfy I

[0102] wherein I represents the current value, VCC represents a voltage connected to the power terminal of the second stage operational amplifier circuit, VREF represents a reference voltage connected to the non-inverting input terminal of the second stage operational amplifier circuit, R represents a resistance value connected between the output terminal of the first stage operational amplifier circuit and the inverting input terminal of the second stage operational amplifier circuit, Ramax represents the maximum resistance value of the first preset resistance domain, and Rb represents the resistance value selected from the second preset resistance domain.

[0103] Reference Figure 3 The first preset resistance domain includes R1, R2 and R3 with resistance values sequentially increasing, and the second preset resistance domain includes R4, R5 and R6 with resistance values sequentially increasing, as shown in the figure. The target resistance value of the operational amplifier circuit is determined as follows:

[0104] First, the target resistance value of the first stage operational amplifier circuit, i.e. Figure 3 the target resistance value of U1A, is determined as follows:

[0105] When VREF / R2≤I

[0106] When VREF / R3≤I<VREF / R2, the resistance R2 is the target resistance value of the first operational amplifier circuit, and the resistance R2 is connected to the first operational amplifier circuit.

[0107] When I<VREF / R3 and the difference between I and VREF / R3 is within a preset range, i.e., I is close to VREF / R3, the resistance R3 is the target resistance value of the first operational amplifier circuit, and the resistance R3 is connected to the first operational amplifier circuit.

[0108] The target resistance value of the second operational amplifier circuit is determined according to the following conditions: Figure 3 The target resistance value of U1B shown in the second embodiment is determined according to the following conditions:

[0109] When I<(VCC-VREF)*R7 / (R3*R4) and I is close to (VCC-VREF)*R7 / (R3*R4), the resistance R3 is connected to U1A, and the resistance R4 is the target resistance value of the second operational amplifier circuit, and the resistance R4 is connected to the second operational amplifier circuit.

[0110] When (VCC-VREF)*R7 / (R3*R6)≤I<(VCC-VREF)*R7 / (R3*R5), the resistance R3 is connected to U1A, and the resistance R5 is the target resistance value of the second operational amplifier circuit, and the resistance R5 is connected to the second operational amplifier circuit.

[0111] When I<(VCC-VREF)*R7 / (R3*R6), the resistance R3 is connected to U1A, and the resistance R6 is the target resistance value of the second operational amplifier circuit, and the resistance R6 is connected to the second operational amplifier circuit.

[0112] Because the situation is complex, it is impossible to enumerate and describe, and those skilled in the art should be aware that under the basic principles of the embodiments provided in the present application, there can be many examples in combination with actual situations, and without sufficient creative labor, they should all be within the scope of the present application.

[0113] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other.

[0114] The signal acquisition circuit and the signal acquisition method provided in the present application are described in detail above. In this paper, specific examples are applied to describe the principles and implementation modes of the present application. The above embodiment description is only used to help understand the method and its core idea of the present application. It should be pointed out that for ordinary skilled in the art, without departing from the principles of the present application, some improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

[0115] It is further noted that the terms "comprise", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without further restriction, exclude the existence of additional elements of the same kind in the process, method, article, or apparatus.

Claims

1. A signal acquisition circuit, characterized by comprising: The ADC chip is configured to collect the voltage output by the operational amplifier circuit and output the collected voltage to the processor. N-path operational amplifier circuit, The feedback channel comprises switches and resistors connected in series. At least two feedback channels are connected in parallel between the output end and the inverting input end of at least one operational amplifier circuit. The ADC chip is connected to the output end of the operational amplifier circuit. The processor is configured to calculate a current value according to the voltage output by the operational amplifier circuit, and control the resistance value of the feedback channel accessing the operational amplifier circuit by sending a control signal to the switch in the feedback channel, so as to control the amplification multiple of the operational amplifier circuit. The signal collection circuit specifically comprises: The first operational amplifier circuit and the second operational amplifier circuit. The inverting input end of the first operational amplifier circuit serves as the input end of the signal collection circuit, the output end of the first operational amplifier circuit is connected to the inverting input end of the second operational amplifier circuit and the ADC chip, and the output end of the second operational amplifier circuit is connected to the ADC chip. The signal collection circuit specifically comprises: Each feedback channel of the first feedback channel group is connected in parallel between the output end and the inverting input end of the first operational amplifier circuit. The first feedback channel group comprises p paths of the feedback channels, and the second feedback channel group comprises q paths of the feedback channels. ;​ Each feedback channel of the second feedback channel group is connected in parallel between the output end and the inverting input end of the second operational amplifier circuit. The signal collection circuit according to claim 1, comprising:

2. A signal acquisition method, characterized by, receiving the voltage output by the operational amplifier circuit collected by the ADC chip, and calculating a current value according to the voltage output by the operational amplifier circuit; determining a target resistance value of the feedback channel accessing the operational amplifier circuit according to the current value; the feedback channel is connected in parallel between the output end and the inverting input end of the operational amplifier circuit; controlling the resistance value of the feedback channel accessing the operational amplifier circuit to be the target resistance value, so that the amplification multiple of the operational amplifier circuit reaches a target amplification multiple. The method according to the current value, determining a target resistance value of the feedback channel accessing the operational amplifier circuit comprises:

3. The signal acquisition method of claim 2, wherein, determining the target resistance value of each operational amplifier circuit step by step according to the current value; if the target resistance value of the operational amplifier circuit of the previous stage is the maximum, and the target resistance value and the current value still satisfy a preset condition, then the target resistance value of the operational amplifier circuit of the next stage is determined again; if the target resistance value of the operational amplifier circuit of the previous stage is the maximum, and the target resistance value and the current value do not satisfy the preset condition, then the target resistance value of the operational amplifier circuit of the next stage and subsequent stages is not determined. The method according to the current value, determining a target resistance value of the feedback channel accessing the operational amplifier circuit comprises:

4. The signal acquisition method of claim 3, wherein, determining the target resistance value of the first level operational amplifier circuit and the second level operational amplifier circuit step by step according to the current value; the output end of the first level operational amplifier circuit is connected to the inverting input end of the second level operational amplifier circuit. The method according to the current value, determining a target resistance value of the first level operational amplifier circuit comprises:

5. The signal acquisition method of claim 4, wherein, selecting a resistance value from a first preset resistance domain, and taking the maximum resistance value that can satisfy a first preset condition as the target resistance value of the first level operational amplifier circuit. The method according to the current value, determining a target resistance value of the second level operational amplifier circuit comprises:

6. The signal acquisition method of claim 4, wherein, ​ The resistance value is selected from a second preset resistance domain, and a maximum resistance value capable of satisfying a second preset condition is taken as a target resistance value of the second-stage operational amplifier circuit.

7. The signal acquisition method of claim 5, wherein, The resistance value is selected from a first preset resistance domain, and a maximum resistance value capable of satisfying a first preset condition is taken as a target resistance value of the first-stage operational amplifier circuit. selecting a resistance value from the first preset resistance domain and taking the maximum resistance value capable of satisfying as the target resistance value of the first-stage operational amplifier circuit; wherein, represents the current value, represents a reference voltage to which the non-inverting input terminal of the first-stage operational amplifier circuit is connected, represents a resistance value selected from the first predetermined resistance domain.

8. The signal acquisition method of claim 6, wherein, The resistance value is selected from a second preset resistance domain, and a maximum resistance value capable of satisfying a second preset condition is taken as a target resistance value of the second-stage operational amplifier circuit. The resistance value is selected from a second preset resistance domain, and a maximum resistance value capable of satisfying a second preset condition is taken as a target resistance value of the second-stage operational amplifier circuit. selecting a resistance value from the second preset resistance domain and taking the maximum resistance value capable of satisfying the second-stage operational amplifier circuit as a target resistance value of the second-stage operational amplifier circuit; wherein, represents the current value, represents a voltage connected to a power supply terminal of the second-stage operational amplifier circuit, represents a reference voltage connected to a non-inverting input terminal of the second-stage operational amplifier circuit, represents a resistance value connected between an output terminal of the first-stage operational amplifier circuit and an inverting input terminal of the second-stage operational amplifier circuit, represents a maximum resistance value of a first preset resistance range, represents a resistance value selected from the second preset resistance range.

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