Signal sampling circuit, integrated circuit, signal sampling module and electronic equipment

Abstract

The embodiments of the present application provide a signal sampling circuit, an integrated circuit, a signal sampling module, and an electronic device. The signal sampling circuit includes: N sampling and holding circuits and M switching circuits, where N is an integer greater than or equal to 2 and M is an integer greater than or equal to 1; each sampling and holding circuit includes a signal conditioning module and a signal holding module: the signal conditioning module is used to receive a signal to be sampled, and output a conditioned signal after conditioning the signal to be sampled; the signal holding module is connected to the output end of the signal conditioning module, and is used to receive and hold the conditioned signal; the first end of at least part of the switching circuit is connected to the output end of the signal conditioning module in one sampling and holding circuit, and the second end is connected to the input end of the signal holding module in at least one other sampling and holding circuit. The signal detection circuit provided by the embodiments of the present application has the advantages of both high circuit performance and low cost.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuit design, and in particular to a signal sampling circuit, an integrated circuit, a signal sampling module, and an electronic device. Background Art

[0002] In the sensor's processing circuit, multi-phase sampling and holding is required. The traditional approach is to set up a single capacitor to sample and hold the signal of each phase in sequence, and then send it to the analog-to-digital converter (ADC) for conversion. In this approach, the capacitor needs to be reused between different sampling phases. When the capacitor is reused between different sampling phases, it needs to be reset in advance to eliminate the influence of the previously sampled signal, which increases the sampling switching time and the sampling signal settling time.

[0003] Another traditional solution is to increase the number of capacitors in the sampling circuit, making it greater than or equal to the number of sampling phases. This way, each capacitor only samples the signal of a single phase, avoiding resets during phase switching. However, this approach increases the sampling circuit area and cost. This is especially true when multiple sampling channels are used, and each channel requires multi-phase sampling, as the number of capacitors increases exponentially. Summary of the Invention

[0004] In view of the above problems, embodiments of the present application provide a signal sampling circuit, an integrated circuit, a signal sampling module, and an electronic device to solve the above technical problems.

[0005] The embodiments of the present application are implemented using the following technical solutions:

[0006] A signal sampling circuit includes N sampling and holding circuits and M switching circuits, where N is an integer greater than or equal to 2 and M is an integer greater than or equal to 1; each sampling and holding circuit includes a signal conditioning module and a signal holding module: the signal conditioning module is used to receive a signal to be sampled, condition the signal to be sampled, and output a conditioned signal; the signal holding module is connected to the output end of the signal conditioning module and is used to receive and hold the conditioned signal; a first end of at least some of the switching circuits is connected to the output end of the signal conditioning module in one sampling and holding circuit, and a second end is connected to the input end of the signal holding module in at least one other sampling and holding circuit.

[0007] An embodiment of the present application further provides an integrated circuit, comprising the above-mentioned signal sampling circuit.

[0008] An embodiment of the present application also provides a signal sampling module, comprising at least two signal generating elements for generating a signal to be sampled; and any of the above signal sampling circuits, wherein the output end of each signal generating element is respectively connected to a signal conditioning module in the signal sampling circuit.

[0009] An embodiment of the present application further provides an electronic device, comprising a device body and a signal sampling module such as any one of the above items provided in the device body.

[0010] The signal sampling circuit, integrated circuit, signal sampling module and electronic device provided by the embodiments of the present application are provided with N sampling and holding circuits and M switching circuits, wherein N is an integer greater than or equal to 2 and M is an integer greater than or equal to 1; each sampling and holding circuit includes a signal conditioning module and a signal holding module: the signal conditioning module is used to receive a signal to be sampled and output a conditioned signal after conditioning the signal to be sampled; the signal holding module is connected to the output end of the signal conditioning module and is used to receive and hold the conditioned signal; the first end of at least part of the switching circuit is connected to the output end of the signal conditioning module in one sampling and holding circuit, and the second end is connected to the input end of the signal holding module in at least one other sampling and holding circuit. The signal sampling circuit can reuse the signal holding modules in different sampling and holding circuits through the switching circuit, so that the signal sampling circuit can meet the requirements of multi-phase sampling without the need to add additional signal holding modules, and has the advantages of both high circuit performance and low cost.

[0011] These and other aspects of the present application will become more readily apparent from the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 A schematic diagram of a signal sampling circuit provided in Example 1 of the present application is shown.

[0014] Figure 2 Shown Figure 1 A structural example diagram of the signal conditioning module

[0015] Figure 3 An example of an implementation of the signal sampling circuit provided in the first embodiment of the present application is shown. Figure 1 .

[0016] Figure 4An example of an implementation of the signal sampling circuit provided in the first embodiment of the present application is shown. Figure 2 .

[0017] Figure 5 An example of an implementation of the signal sampling circuit provided in the first embodiment of the present application is shown. Figure 3 .

[0018] Figure 6 A schematic diagram of a signal sampling circuit provided in Example 2 of the present application is shown.

[0019] Figure 7 An example of an implementation of the signal sampling circuit provided in the third embodiment of the present application is shown. Figure 1 .

[0020] Figure 8 A schematic diagram of a signal sampling circuit provided in Example 3 of the present application is shown.

[0021] Figure 9 An example of an implementation of the signal sampling circuit provided in the third embodiment of the present application is shown. Figure 2 .

[0022] Figure 10 A schematic diagram of a signal sampling circuit provided in Example 4 of the present application is shown.

[0023] Figure 11 An example diagram of an implementation of the signal sampling circuit provided in the fourth embodiment of the present application is shown.

[0024] Figure 12 Shown Figure 10 A schematic diagram of the structure of a neutron switch.

[0025] Figure 13 A schematic diagram of an integrated circuit provided in Example 5 of the present application is shown.

[0026] Figure 14 A schematic diagram of a signal sampling module provided in Example 6 of the present application is shown. DETAILED DESCRIPTION

[0027] The embodiments of the present application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0028] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0029] In sensor processing circuits, multi-phase sampling and signal holding are sometimes required for sensor signals. Traditionally, a single capacitor is used to sample and hold each phase of the signal sequentially, and the signals are then fed into an analog-to-digital converter (ADC) for conversion. For example, in photoplethysmography (PPG) signal acquisition, a traditional single-channel multi-phase sampling approach involves sequentially illuminating multiple light-emitting diodes (LEDs). A photodiode (PD) sensor then converts the light signal emitted by each LED into an electrical signal. A sampling circuit then sequentially samples the electrical signals corresponding to the different light signals and holds them in a sample-and-hold capacitor. In some scenarios, ambient light sampling needs to be sampled and held before and / or after each LED is illuminated. The signals are then sequentially fed into subsequent ADCs to digitize the sampled signals. Another traditional multi-channel parallel sampling approach uses multiple PD sensors and sampling circuits to generate multiple parallel sampling signals when the LED is illuminated. Each sampling circuit is provided with a sampling and holding capacitor. In each sampling circuit, when the number of sampling and holding capacitors is greater than or equal to the number of phases of signal sampling, each sampling and holding capacitor can only hold the sampling signal of one phase; however, when the number of sampling and holding capacitors is less than the number of phases of signal sampling, each sampling circuit cannot complete signal sampling completely. One solution is to reuse some or all of the sampling and holding capacitors between different sampling phases. However, when the sampling and holding capacitors are reused between different sampling phases, the sampling and holding capacitors need to be reset in advance to eliminate the influence of the previously sampled signal. Since the sampling and holding capacitors for each sampling phase must establish the signal from zero, the sampling switching time and the establishment time of the sampling signal are increased, affecting the sampling performance. Another solution is to increase the number of sampling and holding capacitors in each sampling circuit so that the number of sampling and holding capacitors is greater than or equal to the number of sampling phases. In this way, each capacitor value is only responsible for sampling the signal of a single phase, avoiding reset during phase switching. However, increasing the sampling and holding capacitors increases the area and cost of the sampling circuit, especially when there are multiple sampling circuits, and each sampling signal needs to be sampled in multiple phases, the number of capacitors will increase exponentially.

[0030] The embodiment of the present application proposes a signal sampling circuit. The signal sampling circuit is provided with N sampling and holding circuits and M switching circuits, where N is an integer greater than or equal to 2, and M is an integer greater than or equal to 1; each sampling and holding circuit includes a signal conditioning module and a signal holding module: the signal conditioning module is used to receive the signal to be sampled, and output the conditioned signal after conditioning the signal to be sampled; the signal holding module is connected to the output end of the signal conditioning module, and is used to receive and hold the conditioned signal; the first end of at least part of the switching circuit is connected to the output end of the signal conditioning module in one sampling and holding circuit, and the second end is connected to the input end of the signal holding module in at least one other sampling and holding circuit. The signal sampling circuit can reuse the signal holding modules in different sampling and holding circuits through the switching circuit, so that the signal sampling circuit can meet the multi-phase sampling requirements without the need to add additional signal holding modules, and has the advantages of both high circuit performance and low cost.

[0031] like Figure 1 As shown, an embodiment of the present application provides a signal sampling circuit 100, comprising N sample-and-hold circuits 110 and M switch circuits 120, where N is an integer greater than or equal to 2, and M is an integer greater than or equal to 1. Each sample-and-hold circuit 110 includes a signal conditioning module 111 and a signal holding module 112. The signal conditioning module 111 is configured to receive a signal to be sampled and output a conditioned signal after conditioning the signal to be sampled. The signal holding module 112 is connected to the output of the signal conditioning module 111 and configured to receive and hold the conditioned signal. A first end of at least some of the switch circuits 120 is connected to the output of the signal conditioning module 111 in one sample-and-hold circuit 110, and a second end is connected to the input of the signal holding module 112 in at least one other sample-and-hold circuit 110.

[0032] In each sample-and-hold circuit 110, a signal conditioning module 111 receives a sampled signal output by a sensor and performs amplification, buffering, and conversion on the sampled signal. After conditioning the sampled signal, the signal conditioning module 111 outputs a conditioned signal. In the embodiment of the present application, the signal conditioning module 111 may include a current-to-voltage (IV) converter. Figure 2 A schematic diagram of the structure of the signal conditioning module 111 is shown, which may include a trans-impedance amplifier (TIA), a capacitor, and a resistor, wherein both ends of the capacitor and the resistor are connected between the input and output of the transimpedance amplifier. The signal holding module 112 is connected to the output of the signal conditioning module 111 and is used to receive and hold the conditioned signal output by the signal conditioning module 111, and simultaneously send the held conditioned signal to the analog-to-digital converter for conversion.

[0033] In one embodiment, each switch circuit 120 is connected between different sample-and-hold circuits 110 ; specifically, the two ends of the switch circuit 120 are respectively connected to the output end of the signal conditioning module 111 and the input end of the signal holding module 112 belonging to different sample-and-hold circuits 110 , thereby enabling the signal holding module 112 in one sample-and-hold circuit 110 to be reused in another sample-and-hold circuit 110 .

[0034] In one embodiment, a first end of at least a portion of the switch circuit 120 is connected to an output end of the signal conditioning module 111 in one sample and hold circuit 110 , and a second end is connected to an input end of the signal holding module 112 in at least one other sample and hold circuit 110 .

[0035] like Figure 3 As shown, this embodiment is described using an example in which the signal sampling circuit 100 includes three sample-and-hold circuits 110. That is, when N is 3, the three sample-and-hold circuits 110 may include a first sample-and-hold circuit 110a, a second sample-and-hold circuit 110b, and a third sample-and-hold circuit 110c. The first sample-and-hold circuit 110a includes a first signal conditioning module 111a and a first signal holding module 112a; the second sample-and-hold circuit 110b includes a second signal conditioning module 111b and a second signal holding module 112b; and the third sample-and-hold circuit 110c includes a third signal conditioning module 111c and a third signal holding module 112c.

[0036] Furthermore, the signal sampling circuit 100 includes three switch circuits 120, where M is 3. The three switch circuits 120 are a first switch circuit 120a, a second switch circuit 120b, and a third switch circuit 120c. The first switch circuit 120a has a first end connected to the output of the first signal conditioning module 111a, and a second end connected to the input of the second signal holding module 112b. The second switch circuit 120b has a first end connected to the output of the first signal conditioning module 111a, and a second end connected to the input of the third signal holding module 112c. The third switch circuit 120c has a first end connected to the output of the second signal conditioning module 111b, and a second end connected to the input of the third signal holding module 112c. The first switch circuit 120a, the second switch circuit 120b, and the third switch circuit 120c allow the first, second, and third signal holding modules 112a, 112b, and 112c to be multiplexed among the three sampling and holding circuits 110.

[0037] As an example, there are multiple LEDs in the PPG device, and the lighting cycle of each LED includes multiple phases. Different signal sampling circuits 110 are used to sample the electrical signals generated by the PD when different LEDs are lit. In the single-channel multi-phase sampling scenario, that is, the scenario of sampling the electrical signals of multiple phases when a single LED is lit, the same method is still used. Figure 3 For example, if the first signal sampling circuit 110a corresponds to the first LED, then when the first LED is lit, the electrical signal generated by the PD is sampled by the first signal conditioning module 111a in the first signal sampling circuit 110a. For the electrical signals of multiple phases sampled by the first signal conditioning module 111a, if, according to relevant technologies, the electrical signals of multiple phases are maintained only by the first signal holding module 112a in the first signal sampling circuit 110a, the first signal holding module 112a needs to be reset multiple times, resulting in low signal holding efficiency. The present application can reuse the signal holding modules in other signal sampling circuits through the switching circuit to maintain electrical signals of different phases when the first signal sampling circuit 110a is working, so as to reduce the number of times the first signal holding module is reset, or even eliminate the need to reset the first signal holding module, thereby improving sampling efficiency. Specifically, when sampling is performed through the first signal conditioning module 111a in the first sampling and holding circuit 110a, the second signal holding module 112b can be multiplexed by turning on the first switch circuit 120a; or the third signal holding module 112c can be multiplexed by turning on the second switch circuit 120b; or the second switch circuit 120a and the second switch circuit 120b can be multiplexed to multiplex the second signal holding module 112b and the third signal holding module 112c; so that the first sampling and holding circuit 110a does not need to reset the first signal holding module 112a or reduce the number of times the first signal holding module 112a is reset when performing multi-phase sampling, thereby saving signal establishment time, improving sampling speed, reducing system power consumption, and reducing signal crosstalk between phases.

[0038] For another example, in a motion scene, in order to provide an anti-motion interference effect, there is no need to perform single-channel multi-phase sampling, but rather multi-channel parallel sampling. In this case, the first switch circuit 120a, the second switch circuit 120b, and the third switch circuit 120c can be controlled to be turned off, so that the first sample-and-hold circuit 110a, the second sample-and-hold circuit 110b, and the third sample-and-hold circuit 110c remain independent of each other; that is, the first sample-and-hold circuit 110a, the second sample-and-hold circuit 110b, and the third sample-and-hold circuit 110c can perform three independent parallel samplings, and each signal holding module 112 does not need to be multiplexed in other sample-and-hold circuits 110.

[0039] It can be seen that the signal sampling circuit 100 can switch between multi-phase sampling and multi-channel parallel sampling. At the same time, when performing single-channel multi-phase sampling, it can also flexibly multiplex each signal holding module between any sampling and holding circuits, thereby taking into account the advantages of high sampling performance and low cost.

[0040] In some embodiments, the switch circuit 120 may connect only the output terminals of some signal conditioning modules 111 and the input terminals of some signal holding modules 112. Figure 4 As shown, the signal sampling circuit 100 includes two switch circuits 120, where M is 2. The two switch circuits 120 include a first switch circuit 120a and a second switch circuit 120b. The first switch circuit 120a is connected between the first sample-and-hold circuit 110a and the second sample-and-hold circuit 110b, while the second switch circuit 120b is connected between the first sample-and-hold circuit 110a and the third sample-and-hold circuit 110c. Specifically, the first end of the first switch circuit 120a is connected to the output of the first signal conditioning module 111a, and the second end is connected to the input of the second signal holding module 112b. The first end of the second switch circuit 120b is connected to the output of the first signal conditioning module 111a, and the second end is connected to the input of the third signal holding module 112c. The second sample-and-hold circuit 110b and the third sample-and-hold circuit 110c do not need to be connected via the switch circuit 120. Such an arrangement can ensure that the signal holding module 112 in each sampling and holding circuit 110 can be multiplexed into at least one other sampling and holding circuit 110 during single-channel multi-phase sampling to achieve high sampling performance, and can further reduce the circuit area and cost of the signal sampling circuit 100 by reducing the number of switching circuits 120.

[0041] In some embodiments, the second end of the switch circuit 120 may also be connected to a plurality of signal holding modules 112. Figure 5As shown, the signal sampling circuit 100 includes two switch circuits 120, where M is 2. The two switch circuits 120 include a first switch circuit 120a and a second switch circuit 120b. The first switch circuit 120a has a first end connected to the output of the first signal conditioning module 111a, and a second end connected to the inputs of the second signal holding module 112b and the third signal holding module 112c. The second switch circuit 120b has a first end connected to the output of the second signal conditioning module 111b, and a second end connected to the input of the third signal holding module 112c. The first switch circuit 120a enables the second signal holding module 112b and the third signal holding module 112c to be multiplexed simultaneously into the first sample-and-hold circuit 110a. This further improves the sampling performance of the signal sampling circuit 100, while reducing the number of switch circuits 120 and further reducing the circuit area and cost of the signal sampling circuit 100.

[0042] Therefore, the signal sampling circuit 100 provided in the embodiment of the present application can switch between single-channel multi-phase sampling and multi-channel parallel sampling. At the same time, when performing single-channel multi-phase sampling, each signal holding module 112 can be flexibly multiplexed between any sampling and holding circuits 110, thereby taking into account the advantages of high sampling performance and low cost.

[0043] Further, if Figure 6 As shown, each signal holding module 112 includes P holding units 1121, where P is an integer greater than or equal to 1. Of course, in some embodiments, the number of holding units 1121 in each signal holding module 112 may also be different. One end of each holding unit 1121 is connected to the output end of the signal conditioning module 111, and each holding unit 1121 is used to hold a conditioning signal sampled at a specific phase. That is, each holding unit 1121 can hold a signal of one phase. Figure 6 As shown, each signal holding module 112 includes two holding units 1121, i.e., P is 2; thus, the two holding units 1121 can hold the signals sampled twice, respectively. It is worth noting that each sample-and-hold circuit 110 can be referred to as a sampling channel, and the number of phases for each sampling channel is the number of samplings, which is related to the number of LEDs. For example, if a sample-and-hold circuit 110 needs to sample and hold the light signals of two LEDs, the number of phases for that sampling channel is 2, indicating that the sample-and-hold circuit 110 needs to sample twice, and the two holding units 1121 can hold the signals sampled twice, respectively.

[0044] Furthermore, each holding unit 1121 includes a switch 11211 and a signal storage sub-circuit 11212, wherein one end of the switch 11211 is connected to the output end of the signal conditioning module 111, and the other end is connected to the input end of the signal storage sub-circuit 11212. The switch 11211 in each holding unit 1121 can control whether the signal storage sub-circuit 11212 participates in signal holding, thereby enabling each signal holding module 112 to flexibly configure the number of holding units 1121 participating in signal holding.

[0045] In an embodiment of the present application, each signal storage subcircuit 11212 includes a capacitor C, one end of which is connected to the switch 11211, and the other end is grounded. The capacitor C can hold the signal sampled each time and send the held signal to the analog-to-digital converter for conversion. Further, each signal storage subcircuit 11212 also includes a resistor R, which is connected to the capacitor C and forms a low-pass filter. The low-pass filter can limit the noise bandwidth to improve the signal-to-noise ratio. It is worth noting that in this embodiment, only a first-order low-pass filter is used for illustration. In other embodiments, the capacitor C and resistor R in the signal storage subcircuit 11212 can also form a high-order low-pass filter. The embodiment of the present application does not limit the order of the low-pass filter. In other embodiments, a reset switch can also be provided at both ends of each capacitor C to reset the capacitor.

[0046] In some embodiments, the switch circuit 120 may include one or more sub-switches. In one embodiment, the second end of each sub-switch is connected to the second end of a switch in a holding unit. It should be understood that the first end of the sub-switch is also the first end of the switch circuit 120, and the first end of the sub-switch is connected to the output end of a signal conditioning module 111. In this case, the switch circuit 120 can multiplex each holding unit 1121 in the signal holding module 112 individually.

[0047] like Figure 7As shown, in a specific embodiment, P can be 1, N can be 2, and M can be 1. That is, the signal sampling circuit 100 may include two sample-and-hold circuits 110 and a switch circuit 120. The two sample-and-hold circuits 110 may include a first sample-and-hold circuit 110a and a second sample-and-hold circuit 110b. The switch circuit 120 may include a sub-switch. The first sample-and-hold circuit 110a includes a first signal conditioning module 111a and a first signal holding module 112a. The first signal holding module 112a includes a holding unit 1121a, which includes a switch SW1 and a capacitor C1. The first end of the switch SW1 is connected to the first signal conditioning module 111a, and the second end is connected to one end of the capacitor C1. The other end of the capacitor C1 is grounded. The second sample-and-hold circuit 110b includes a second signal conditioning module 111b and a second signal holding module 112b. The second signal holding module 112b includes a holding unit 1121b, which includes a switch SW2 and a capacitor C2. The first end of the switch SW2 is connected to the second signal conditioning module 111b, and the second end is connected to one end of the capacitor C2; the other end of the capacitor C2 is grounded. In other embodiments, a reset switch S can be connected to both ends of the capacitor C1 and the capacitor C2 to reset the capacitors C1 and C2. In this embodiment, one end of the sub-switch is connected to the output end of the first signal conditioning module 111a, and the other end is connected to the second end of the switch SW2. In this embodiment, each sampling and holding circuit 100 includes only one holding unit 1121, that is, each sampling and holding circuit 100 only supports one independent sampling phase, wherein the independent sampling phase is to hold a signal sampled once, and it does not need to hold a signal sampled multiple times multiple times, that is, there is no need to reset between two consecutive samplings. When multi-channel parallel sampling is performed, the first sample-and-hold circuit 110a and the second sample-and-hold circuit 110b can be kept independent of each other through the switch circuit 120. In this case, the first sample-and-hold circuit 110a and the second sample-and-hold circuit 110b can each support an independent sampling phase. When single-channel multi-phase sampling is performed, the holding unit 1121b in the second sample-and-hold circuit 110b can be multiplexed into the first sample-and-hold circuit 110a through the switch circuit 120. In this case, the first sample-and-hold circuit 110a increases the number of sampling phases and can support two sampling phases. This avoids the need to multiplex the holding unit 1121a in the first sample-and-hold circuit 110a during single-channel multi-phase sampling, thereby accelerating the sampling speed and improving the sampling performance.

[0048] like Figure 8As shown, in another specific embodiment, P can be an integer greater than or equal to 2, that is, each signal holding module 112 includes at least two holding units 1121. In this case, each switch circuit 120 can include P sub-switches 121, wherein the first end of each sub-switch 121 is connected to the output end of the signal conditioning module 111 in one sample-and-hold circuit 110, and the second end is connected to the input end of a signal storage sub-circuit 11212 of the signal holding module 112 in another sample-and-hold circuit 110. In other words, the second end of each sub-switch 121 is connected to the second end of a switch of the signal holding module 112 in another sample-and-hold circuit 110. The P sub-switches 121 can independently multiplex each signal storage sub-circuit 11212 in the signal holding module 112 of each sample-and-hold circuit 110, thereby improving the flexibility of multiplexing each signal storage sub-circuit 11212 in the signal holding module 112.

[0049] Specifically, if Figure 9As shown, P can be 4, N can be 2, and M can be 1. That is, the signal sampling circuit 100 may include two sample-and-hold circuits 110 and a switch circuit 120. The two sample-and-hold circuits 110 include a first sample-and-hold circuit 110a and a second sample-and-hold circuit 110b. The first sample-and-hold circuit 110a includes a first signal conditioning module 111a and a first signal holding module 112a. The first signal holding module 112a includes a holding unit 1121a1, a holding unit 1121a2, a holding unit 1121a3, and a holding unit 1121a4. The holding unit 1121a1 includes a switch SW1 and a signal storage sub-circuit 11212a1. The holding unit 1121a2 includes a switch SW2 and a signal storage sub-circuit 11212a2. The holding unit 1121a3 includes a switch SW3 and a signal storage sub-circuit 11212a3. The holding unit 1121a4 includes a switch SW4 and a signal storage sub-circuit 11212a4. Signal storage subcircuit 11212a1 includes resistor R1 and capacitor C1, signal storage subcircuit 11212a2 includes resistor R2 and capacitor C2, signal storage subcircuit 11212a3 includes resistor R3 and capacitor C3, and signal storage subcircuit 11212a4 includes resistor R4 and capacitor C4. The output end of the first signal conditioning module 111a is connected to the first ends of switches SW1, SW2, SW3, and SW4. The second end of switch SW1 is connected to one end of resistor R1, the other end of resistor R1 is connected to one end of capacitor C1, and the other end of capacitor C1 is grounded. The second end of switch SW2 is connected to one end of resistor R2, the other end of resistor R2 is connected to one end of capacitor C2, and the other end of capacitor C2 is grounded. The second end of switch SW3 is connected to one end of resistor R3, the other end of resistor R3 is connected to one end of capacitor C3, and the other end of capacitor C3 is grounded. The second end of switch SW4 is connected to one end of resistor R4, the other end of resistor R4 is connected to one end of capacitor C4, and the other end of capacitor C4 is grounded.

[0050] The second sampling and holding circuit 110b includes a second signal conditioning module 111b and a second signal holding module 112b; the second signal holding module 112b includes a holding unit 1121b1, a holding unit 1121b2, a holding unit 1121b3 and a holding unit 1121b4; and the holding unit 1121b1 includes a switch SW5 and a signal storage sub-circuit 11212b1; the holding unit 1121b2 includes a switch SW6 and a signal storage sub-circuit 11212b2; the holding unit 1121b3 includes a switch SW7 and a signal storage sub-circuit 11212b3; and the holding unit 1121b4 includes a switch SW8 and a signal storage sub-circuit 11212b4. Signal storage subcircuit 11212b1 includes resistor R5 and capacitor C5, signal storage subcircuit 11212b2 includes resistor R6 and capacitor C6, signal storage subcircuit 11212b3 includes resistor R7 and capacitor C7, and signal storage subcircuit 11212b4 includes resistor R8 and capacitor C8. The output end of second signal conditioning module 111b is connected to the first ends of switches SW5, SW6, SW7, and SW8. The second end of switch SW5 is connected to one end of resistor R5, the other end of resistor R5 is connected to one end of capacitor C5, and the other end of capacitor C5 is grounded. The second end of switch SW6 is connected to one end of resistor R6, the other end of resistor R7 is connected to one end of capacitor C7, and the other end of capacitor C7 is grounded. The second end of switch SW7 is connected to one end of resistor R7, the other end of resistor R7 is connected to one end of capacitor C7, and the other end of capacitor C7 is grounded. The second end of switch SW8 is connected to one end of resistor R8, the other end of resistor R8 is connected to one end of capacitor C8, and the other end of capacitor C8 is grounded.

[0051] The switch circuit 120 includes four sub-switches 121, namely a first sub-switch 121a, a second sub-switch 121b, a third sub-switch 121c, and a fourth sub-switch 121d. The first sub-switch 121a has one end connected to the output of the first signal conditioning module 111a and the other end connected to the second end of switch SW5. The second sub-switch 121b has one end connected to the output of the first signal conditioning module 111a and the other end connected to the second end of switch SW6. The third sub-switch 121c has one end connected to the output of the first signal conditioning module 111a and the other end connected to the second end of SW7. The fourth sub-switch 121d has one end connected to the output of the first signal conditioning module 111a and the other end connected to the second end of SW8.

[0052] In this embodiment, each sample-and-hold circuit 110 can support four independent sampling phases. The four sub-switches in the switch circuit 120 can be used to multiplex each signal storage sub-circuit in each sample-and-hold circuit 110 to other sample-and-hold circuits, enabling each sample-and-hold circuit to support four to eight independent sampling phases. Furthermore, the independent sampling phases of each sample-and-hold circuit 110 can be flexibly configured. For example, by configuring one sub-switch, one signal storage sub-circuit in the second sample-and-hold circuit 110b can be multiplexed to the first sample-and-hold circuit 110a, thereby increasing the number of independent sampling phases supported by the first sample-and-hold circuit 110a from four to five. Another example is by configuring four sub-switches, four signal storage sub-circuits 11212 in the second sample-and-hold circuit 110b can be multiplexed to the first sample-and-hold circuit 110a, thereby increasing the number of independent sampling phases supported by the first sample-and-hold circuit 110a from four to eight.

[0053] In this embodiment, the signal sampling circuit 110 can independently allocate each signal storage sub-circuit 11212 in each sample-and-hold circuit 110 to another sample-and-hold circuit 110 through flexible configuration of the sub-switches in the switch circuit 120 during single-channel multi-phase sampling. This allows each sample-and-hold circuit 110 to support 4 to 8 independent sampling phases instead of four. This eliminates the need to reuse existing signal storage sub-circuits 11212 during single-channel multi-phase sampling, nor does it require additional signal storage sub-circuits 11212, thereby improving sampling performance and saving circuit area and cost. Furthermore, when multi-channel parallel sampling is required, the switch circuit 120 can similarly maintain independent parallel sampling in each sample-and-hold circuit 110, allowing each sample-and-hold circuit 110 to support four independent sampling phases.

[0054] As another embodiment, the second end of the switch circuit 120 is connected to the first end of the switch in the holding unit 1121. In this case, the second end of the switch circuit 120 is connected to the input end of the signal holding module 112, and the entire signal holding module 112 is multiplexed, that is, all the holding units 1121 in the signal holding module 112 are multiplexed.

[0055] like Figure 10As shown, P can be an integer greater than or equal to 2, meaning that each signal holding module 112 includes at least two holding units 1121. In this case, each sample-and-hold circuit 110 may further include a switch unit 113, wherein the switch unit 113 is connected between the output of the signal conditioning module 111 in the sample-and-hold circuit 110 and the input of the signal holding module 112. The switch unit 113 can flexibly control the operation of the signal holding module 112 in each sample-and-hold circuit 110. For example, if a signal holding module 112 does not need to perform sample-and-hold, that is, is in an idle state, the switch unit 113 connected to the signal holding module 112 can be disconnected to reduce power consumption. At the same time, the idle signal holding module 112 can be multiplexed into another sample-and-hold circuit 110 via the switch circuit 120 to participate in the sample-and-hold operation of the other sample-and-hold circuit 110.

[0056] In a specific embodiment, Figure 11As shown, P can be 4, N can be 2, and M can be 1. That is, the signal sampling circuit 100 may include two sample-and-hold circuits 110 and a switch circuit 120. It is worth noting that since the switch circuit 120 reuses the entire signal holding module 112, each switch circuit 120 may include only one sub-switch. The two sample-and-hold circuits 110 may include a first sample-and-hold circuit 110a and a second sample-and-hold circuit 110b. The first sampling and holding circuit 110a includes a first signal conditioning module 111a, a first switching unit 113a and a first signal holding module 112a; wherein the first signal holding module 112a includes a holding unit 1121a1, a holding unit 1121a2, a holding unit 1121a3 and a holding unit 1121a4; and the holding unit 1121a1 includes a switch SW1, a resistor R1 and a capacitor C1; the holding unit 1121a2 includes a switch SW2, a resistor R2 and a capacitor C2; the holding unit 1121a3 includes a switch SW3, a resistor R3 and a capacitor C3; and the holding unit 1121a4 includes a switch SW4, a resistor R4 and a capacitor C4. One end of the first switch unit 113a is connected to the output end of the first signal conditioning module 111a, and the other end is simultaneously connected to the first ends of switches SW1, SW2, SW3, and SW4; a second end of switch SW1 is connected to one end of resistor R1, the other end of resistor R1 is connected to one end of capacitor C1, and the other end of capacitor C1 is grounded; a second end of switch SW2 is connected to one end of resistor R2, the other end of resistor R2 is connected to one end of capacitor C2, and the other end of capacitor C2 is grounded; a second end of switch SW3 is connected to one end of resistor R3, the other end of resistor R3 is connected to one end of capacitor C3, and the other end of capacitor C3 is grounded; a second end of switch SW4 is connected to one end of resistor R4, the other end of resistor R4 is connected to one end of capacitor C4, and the other end of capacitor C4 is grounded.

[0057] The second sampling and holding circuit 110b includes a second signal conditioning module 111b, a second switching unit 113b and a second signal holding module 112b; wherein the second signal holding module 112b includes a holding unit 1121b1, a holding unit 1121b2, a holding unit 1121b3 and a holding unit 1121b4; and the holding unit 1121b1 includes a switch SW5, a resistor R5 and a capacitor C5; the holding unit 1121b2 includes a switch SW6, a resistor R5 and a capacitor C5; the holding unit 1121b3 includes a switch SW7, a resistor R7 and a capacitor C7; and the holding unit 1121b4 includes a switch SW8, a resistor R8 and a capacitor C8. One end of the second switch unit 113b is connected to the output end of the second signal conditioning module 111b, and the other end is simultaneously connected to the first ends of switches SW5, SW6, SW7, and SW8; the second end of switch SW5 is connected to one end of resistor R5, the other end of resistor R5 is connected to one end of capacitor C5, and the other end of capacitor C5 is grounded; the second end of switch SW6 is connected to one end of resistor R6, the other end of resistor R6 is connected to one end of capacitor C6, and the other end of capacitor C6 is grounded; the second end of switch SW7 is connected to one end of resistor R7, the other end of resistor R7 is connected to one end of capacitor C7, and the other end of capacitor C7 is grounded; the second end of switch SW8 is connected to one end of resistor R8, the other end of resistor R8 is connected to one end of capacitor C8, and the other end of capacitor C8 is grounded.

[0058] The first end of the switch circuit 120 is connected to the output end of the first signal conditioning module 111a, and the other end is connected to the first ends of switches SW5, SW6, SW7, and SW8. In this embodiment, each sample-and-hold circuit 110 includes four holding units 1121, meaning that each sample-and-hold circuit 110 supports four independent sampling phases. The switch circuit 120 can be used to multiplex the four holding units 1121 in the signal holding module 112 of each sample-and-hold circuit 110 into other sample-and-hold circuits 110. For example, the four holding units 1121 in the second sample-and-hold circuit 110b can be multiplexed into the first sample-and-hold circuit 110a. Furthermore, the switch unit 113 and the switch circuit 120 allow for flexible configuration of the four holding units 1121 in the signal holding module 112 of each sample-and-hold circuit 110. For example, when the first sample-and-hold circuit 110a is operating, the switch circuit 120 and the switch unit allow the four holding units 1121 in the second sample-and-hold circuit 110b to be used for sample-and-hold, rather than the four holding units 1121 in the first sample-and-hold circuit 110a. When performing single-channel multi-phase sampling, the switch circuit 120 multiplexes the four holding units 1121 in the second signal holding module 112b of the second sample-and-hold circuit 110b into the first sample-and-hold circuit 110a, increasing the number of independent sampling phases supported by the first sample-and-hold circuit 110a from four to eight. In a specific implementation scenario, when performing multi-phase sampling on multiple LED lights during PPG signal sampling, each LED light has a different emission wavelength and spatial location. Multi-phase sampling involves sampling the signals of the multiple LED lights and an ambient light signal. Assuming there are four LED lights at different locations and / or with different emission wavelengths, each time the phase of an LED light signal is sampled, the phase of an ambient light signal is sampled. Assuming there are four LED lights at different locations and with different emission wavelengths, each time the phase of an LED light signal is sampled, the phase of an ambient light signal is sampled. This requires eight signal sampling phases. In this embodiment, the four holding units 1121 in the signal holding module 112 of the second sample-and-hold circuit 110b can be reused in the first sample-and-hold circuit 110a via the switch circuit 120. This increases the number of independent sampling phases supported by the first sample-and-hold circuit 110a from four to eight, with each holding unit 1121 corresponding to one phase of the signal. This avoids the need to reuse the four independent sampling phases originally in the first sample-and-hold circuit 110a, thereby accelerating sampling speed and improving sampling performance.

[0059] Furthermore, when performing multi-channel parallel sampling, the first sample-and-hold circuit 110a and the second sample-and-hold circuit 110b can be maintained in two independent samplings through the switch circuit 120, wherein the first sample-and-hold circuit 110a and the second sample-and-hold circuit 110b each support four independent sampling phases. In a specific implementation scenario, when sampling signals in a motion scene, in order to improve the effect of anti-motion interference, multi-channel parallel sampling can be performed. In this embodiment, the first sample-and-hold circuit 110a and the second sample-and-hold circuit 110b can be maintained in two independent parallel samplings through the switch circuit 120. Parallel sampling can improve the spatial resolution of the signal, thereby improving the effect of anti-motion interference. In this embodiment, each sample-and-hold circuit supports four independent sampling phases during parallel sampling.

[0060] Therefore, the signal sampling circuit 110 in this embodiment flexibly distributes the entire holding unit 1121 in each sampling and holding circuit 110 through the switching circuit 120. Therefore, during the single-channel multi-phase sampling process, there is no need to reuse the original holding units or add additional holding units, thereby improving sampling performance and saving circuit area and cost.

[0061] like Figure 12 As shown, in some embodiments, each sub-switch 121 in the switch circuit 120 may include a first isolating switch S1, a second isolating switch S2, and a third isolating switch S3. The first end of the first isolating switch S1, the first end of the second isolating switch S2, and the first end of the third isolating switch S3 are interconnected. The second end of the first isolating switch S1 serves as the first connection end of the sub-switch 121, the second end of the second isolating switch S2 serves as the second connection end of the sub-switch 121, and the second end of the third isolating switch S3 is grounded. These three isolating switches improve the isolation performance of the sub-switch 121 and channel isolation, further reducing crosstalk between capacitors.

[0062] The signal sampling circuit provided in the embodiment of the present application is provided with N sampling and holding circuits and M switching circuits, where N is an integer greater than or equal to 2, and M is an integer greater than or equal to 1; each sampling and holding circuit includes a signal conditioning module and a signal holding module: the signal conditioning module is used to receive the signal to be sampled, and output the conditioned signal after conditioning the signal to be sampled; the signal holding module is connected to the output end of the signal conditioning module, and is used to receive and hold the conditioned signal; the first end of at least part of the switching circuit is connected to the output end of the signal conditioning module in one sampling and holding circuit, and the second end is connected to the input end of the signal holding module in at least one other sampling and holding circuit. The signal sampling circuit can reuse the signal holding modules in different sampling and holding circuits through the switching circuit, so that the signal sampling circuit can meet the multi-phase sampling requirements without the need for additional signal holding modules, and has the advantages of both high circuit performance and low cost.

[0063] like Figure 13 As shown, an embodiment of the present application further provides an integrated circuit 200, which includes the above-mentioned signal sampling circuit.

[0064] The signal sampling circuit in the integrated circuit provided in the embodiment of the present application is provided with N sampling and holding circuits and M switching circuits, where N is an integer greater than or equal to 2, and M is an integer greater than or equal to 1; each sampling and holding circuit includes a signal conditioning module and a signal holding module: the signal conditioning module is used to receive the signal to be sampled, and output the conditioned signal after conditioning the signal to be sampled; the signal holding module is connected to the output end of the signal conditioning module, and is used to receive and hold the conditioned signal; the first end of at least part of the switching circuit is connected to the output end of the signal conditioning module in one sampling and holding circuit, and the second end is connected to the input end of the signal holding module in at least one other sampling and holding circuit. The signal sampling circuit can reuse the signal holding modules in different sampling and holding circuits through the switching circuit, so that the signal sampling circuit can meet the multi-phase sampling requirements without the need for additional signal holding modules, and has the advantages of both high circuit performance and low cost.

[0065] like Figure 14 As shown, the embodiment of the present application further provides a signal sampling module 300 , which includes at least two signal generating elements 310 and the above-mentioned signal sampling circuit 100 .

[0066] The output end of each signal generating element 310 is connected to a signal conditioning module 110 in the signal sampling circuit 100. The signal generating element 310 can detect the environmental signal and generate a signal to be sampled, and then output the signal to be sampled to the signal conditioning module 110. The environmental signal may include but is not limited to an optical signal, a pressure signal, a temperature and humidity signal, etc.

[0067] Furthermore, at least one of the at least two signal generating elements 310 is a photoelectric sensor, which can detect the LED light signal and the ambient light signal and output the LED light signal and the ambient light signal to the signal conditioning module 110 in the signal sampling circuit 100 .

[0068] The signal sampling circuit in the signal sampling module provided in the embodiments of the present application is provided with N sample-and-hold circuits and M switch circuits, where N is an integer greater than or equal to 2 and M is an integer greater than or equal to 1. Each sample-and-hold circuit includes a signal conditioning module and a signal holding module: the signal conditioning module is configured to receive a signal to be sampled, condition the signal to be sampled, and output a conditioned signal; the signal holding module is connected to the output of the signal conditioning module and is configured to receive and hold the conditioned signal; at least some of the switch circuits have a first end connected to the output of the signal conditioning module in one sample-and-hold circuit and a second end connected to the input of the signal holding module in at least one other sample-and-hold circuit. The signal sampling circuit can reuse the signal holding modules in different sample-and-hold circuits through the switch circuits, enabling the signal sampling circuit to meet multi-phase sampling requirements without requiring additional signal holding modules, thus achieving the advantages of both high circuit performance and low cost.

[0069] The embodiment of the present application further provides an electronic device, comprising a device body and the above-mentioned signal sampling module, wherein the signal sampling module is disposed in the device body.

[0070] In this embodiment, the electronic device may be, but is not limited to, a smart bracelet, a smart watch, a blood oximeter, a game controller, etc.

[0071] The signal sampling circuit in the electronic device provided in the embodiment of the present application is provided with N sampling and holding circuits and M switching circuits, where N is an integer greater than or equal to 2, and M is an integer greater than or equal to 1; each sampling and holding circuit includes a signal conditioning module and a signal holding module: the signal conditioning module is used to receive the signal to be sampled, and output the conditioned signal after conditioning the signal to be sampled; the signal holding module is connected to the output end of the signal conditioning module, and is used to receive and hold the conditioned signal; the first end of at least part of the switching circuit is connected to the output end of the signal conditioning module in one sampling and holding circuit, and the second end is connected to the input end of the signal holding module in at least one other sampling and holding circuit. The signal sampling circuit can reuse the signal holding modules in different sampling and holding circuits through the switching circuit, so that the signal sampling circuit can meet the multi-phase sampling requirements without the need to add additional signal holding modules, and has the advantages of both high circuit performance and low cost.

[0072] The above is only a preferred embodiment of the present application and does not constitute any form of limitation to the present application. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A signal sampling circuit, characterized in that: include: N sample-and-hold circuits and M switch circuits, where N is an integer greater than or equal to 2, and M is an integer greater than or equal to 1; Each of the sample-and-hold circuits comprises a signal conditioning module and a signal holding module: The signal conditioning module is used to receive the signal to be sampled, condition the signal to be sampled and output a conditioned signal; The signal holding module is connected to the output end of the signal conditioning module and is used to receive and hold the conditioned signal; each of the signal holding modules comprises: P holding units, one end of each holding unit is connected to the output end of the signal conditioning module, and each holding unit is used to hold the conditioned signal sampled at a specific phase, where P is an integer greater than or equal to 1; each holding unit comprises a switch and a signal storage subcircuit, a first end of the switch is connected to the output end of the signal conditioning module, and a second end is connected to the input end of the signal storage subcircuit in the holding unit; At least part of the switch circuit has a first end connected to an output end of a signal conditioning module in a sample-and-hold circuit, and a second end connected to an input end of a signal holding module in at least one other sample-and-hold circuit; The switching circuit is connected to the first end or the second end of the switch in the holding unit; when the switching circuit is connected to the second end of the switch in the holding unit, the switching circuit includes one or more sub-switches, and the second end of each sub-switch is connected to the second end of the switch in one of the holding units.

2. The signal sampling circuit according to claim 1, wherein: The holding unit includes a first holding unit, a second holding unit, a third holding unit, and a fourth holding unit, wherein the first holding unit includes a first switch and a first signal storage sub-circuit, the second holding unit includes a second switch and a second signal storage sub-circuit, the third holding unit includes a third switch and a third signal storage sub-circuit, and the fourth holding unit includes a fourth switch and a fourth signal storage sub-circuit; The switch circuit includes a first sub-switch, a second sub-switch, a third sub-switch, and a fourth sub-switch; wherein the first ends of the first sub-switch, the second sub-switch, the third sub-switch, and the fourth sub-switch are all connected to the output end of the signal conditioning module, the second end of the first sub-switch is connected to the second end of the first switch, the second end of the second sub-switch is connected to the second end of the second switch, the second end of the third sub-switch is connected to the second end of the third switch, and the second end of the fourth sub-switch is connected to the second end of the fourth switch.

3. The signal sampling circuit according to claim 1, wherein: The second end of the switch circuit is connected to the first end of the switch in the holding unit.

4. The signal sampling circuit according to claim 3, wherein: The holding unit includes a fifth holding unit, a sixth holding unit, a seventh holding unit, and an eighth holding unit, wherein the fifth holding unit includes a fifth switch and a fifth signal storage sub-circuit, the sixth holding unit includes a sixth switch and a sixth signal storage sub-circuit, the seventh holding unit includes a seventh switch and a seventh signal storage sub-circuit, and the eighth holding unit includes an eighth switch and an eighth signal storage sub-circuit; A first end of the switch circuit is connected to the output end of the signal conditioning module, and a second end is connected to first ends of the fifth switch, the sixth switch, the seventh switch, and the eighth switch.

5. The signal sampling circuit according to claim 3, wherein: Each of the sample-and-hold circuits further includes a switch unit connected between the output end of the signal conditioning module and the input end of the signal holding module in the sample-and-hold circuit.

6. The signal sampling circuit according to any one of claims 1 to 5, characterized in that: Each of the signal storage sub-circuits includes a capacitor, a first end of the capacitor is connected to the output end of the signal conditioning module, and a second end of the capacitor is grounded.

7. The signal sampling circuit according to claim 6, wherein: Each of the signal storage sub-circuits further includes a resistor, which is connected to the capacitor to form a low-pass filter.

8. An integrated circuit, characterized in that: The invention comprises the signal sampling circuit as described in any one of claims 1 to 7.

9. A signal sampling module, characterized in that: include: At least two signal generating elements, used to generate a signal to be sampled; as well as According to the signal sampling circuit according to any one of claims 1 to 7, the output end of each signal generating element is respectively connected to a signal conditioning module in the signal sampling circuit.

10. The signal sampling module according to claim 9, wherein: At least one of the at least two signal generating elements is a photosensor.

11. An electronic device, characterized in that: It comprises a device body and a signal sampling module as described in claim 9 or 10 above, which is arranged in the device body.

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