Analog-to-digital converter and analog-to-digital conversion method

Abstract

The present application provides an analog-to-digital converter and an analog-to-digital conversion method, which relate to the technical field of integrated circuits and can avoid the limitation of the analog-to-digital conversion accuracy of the analog-to-digital converter by the digital-to-analog converter. In the analog-to-digital converter, a sampling and holding circuit samples an analog signal to generate an analog sampling signal; a first-level comparator generates a first comparison result according to the analog sampling signal and 1 / 2 of the full-scale voltage, and the logic value corresponding to the first comparison result is the value of the first high-significant bit of the digital signal corresponding to the analog sampling signal; an n-level controller generates a control signal according to the first comparison result output by the first-level comparator to the n-th comparison result output by the n-level comparator; an n+1-level comparator generates an n+1-th comparison result according to the analog sampling signal and the control signal output by the n-level controller, and the logic value corresponding to the n+1-th comparison result is the value of the n+1-th high-significant bit of the digital signal corresponding to the analog sampling signal.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to an analog-to-digital converter and an analog-to-digital conversion method. Background Art

[0002] Analog-to-digital converter (ADC) is used to convert analog signals into digital signals. At present, most electronic devices are equipped with analog-to-digital converters. Electronic devices receive analog signals and use analog-to-digital converters to convert analog signals into digital signals, and then process the digital signals to realize various functions of electronic devices.

[0003] Among them, the commonly used analog-to-digital converter is the successive approximation register analog-to-digital converter (SAR ADC). The existing SAR ADC includes: a sampling and holding circuit, a comparator, a controller, and a digital-to-analog converter. In the process of SAR ADC converting analog signals into digital signals, the four circuit modules of the sampling and holding circuit, the comparator, the controller, and the digital-to-analog converter need to cooperate with each other, and when the accuracy of the digital-to-analog converter is 3 bits, the accuracy of the SAR ADC will also be limited to 3 bits, and when the accuracy of the digital-to-analog converter is 4 bits, the accuracy of the SAR ADC will also be limited to 4 bits. The accuracy of the digital-to-analog converter will limit the analog-to-digital conversion accuracy of the SAR ADC. Summary of the invention

[0004] The embodiments of the present application provide an analog-to-digital converter and an analog-to-digital conversion method, which can avoid the limitation of the analog-to-digital conversion accuracy of the analog-to-digital converter by the digital-to-analog converter.

[0005] In order to achieve the above objectives, this application adopts the following technical solutions:

[0006] In a first aspect, an analog-to-digital converter is provided, which includes: a sampling and holding circuit, an n+1-level comparator and an n-level controller, wherein n is a positive integer greater than or equal to 1; the sampling and holding circuit is connected to the first input terminal of each level of the comparator; the second input terminal of the n+1-th level comparator is connected to the output terminal of the n-th level controller; the input terminal of the n-th level controller is respectively connected to the output terminal of the 1st level comparator to the output terminal of the n-th level comparator; the sampling and holding circuit is configured to receive an analog signal, sample the analog signal to generate an analog sampling signal, and transmit the analog sampling signal to the first input terminal of each level of the comparator; the 1st level comparator is configured to receive an analog signal according to the analog sampling signal and 1 / 2 of the full-scale voltage, generate the first comparison result, transmit the first comparison result to the n-level controller respectively, and output the logic value corresponding to the first comparison result as the value of the first high-significant bit of the digital signal corresponding to the analog sampling signal; the n-level controller is configured to generate a control signal according to the first comparison result output by the first-level comparator to the n-th comparison result output by the n-level comparator; the n+1-level comparator is configured to generate the n+1-th comparison result according to the analog sampling signal and the control signal output by the n-level controller, and output the logic value corresponding to the n+1-th comparison result as the value of the n+1-th high-significant bit of the digital signal corresponding to the analog sampling signal. In the analog-to-digital converter, by transmitting the analog sampling signal to the first input terminal of each level of comparator, and making the first-level comparator generate the first comparison result according to the analog sampling signal and (1 / 2) of the full-scale voltage, wherein the logic value corresponding to the first comparison result is the value of the first high-significant bit of the digital signal corresponding to the analog sampling signal. Furthermore, the n-th level controller can generate a control signal according to the 1st comparison result output by the 1st level comparator to the nth comparison result output by the n-th level comparator. Among them, the n+1-th level comparator generates the n+1th comparison result according to the analog sampling signal and the control signal output by the n-th level controller, and the logic value corresponding to the n+1th comparison result is the value of the n+1th high-significant bit of the digital signal corresponding to the analog sampling signal. It can be seen that in this analog-to-digital converter, only the same number of comparators as the accuracy of the analog-to-digital converter are needed to realize the process of converting analog signals into digital signals, and there is no need to set up a digital-to-analog converter, thereby avoiding the limitation of the analog-to-digital conversion accuracy of the analog-to-digital converter by the digital-to-analog converter.

[0007] Optionally, the n-th level controller is specifically configured to determine x based on the 1st comparison result output by the 1st level comparator to the n-1th comparison result output by the n-1th level comparator, where x is a decimal number converted from a predetermined digital signal, the predetermined digital signal has n valid bits, and the most significant bit to the second least significant bit of the predetermined digital signal sequentially include the logic value corresponding to the 1st comparison result to the logic value corresponding to the n-1th comparison result, and the least significant bit of the predetermined digital signal is 1; when it is determined according to the n-th comparison result output by the n-th level comparator that the analog sampling signal is greater than (x / 2^n) of the full-scale voltage, the generated control signal is ((2x+1) / 2^(n+1)) of the full-scale voltage; or, when it is determined according to the n-th comparison result output by the n-th level comparator that the analog sampling signal is less than (x / 2^n) of the full-scale voltage, the generated control signal is ((2x-1) / 2^(n+1)) of the full-scale voltage. In this optional manner, the control signal generated by any level controller corresponds to a predetermined number of full-scale voltages, wherein the control signal generated by the n-1 level controller corresponds to (x / 2^n) of the full-scale voltage, and the n-level comparator generates an n-th comparison result based on the analog sampling signal and the (x / 2^n) of the full-scale voltage; the n-level controller can determine the value of x based on the 1st comparison result output by the 1st level comparator to the n-1th comparison result output by the n-1st level comparator, and the n-level controller can also determine that the analog sampling signal Vm is between (x / 2^n) and the full-scale voltage based on the n-th comparison result when it is determined that the analog sampling signal is greater than (x / 2^n) of the full-scale voltage. The voltage is between ((x+1) / 2^n), and the intermediate value between (x / 2^n) and ((x+1) / 2^n) is ((2x+1) / 2^(n+1)), so the nth-stage controller transmits the full-scale voltage ((2x+1) / 2^(n+1)) to the n+1th-stage comparator, so that the n+1th-stage comparator determines whether the analog sampling signal is between (x / 2^n) of the full-scale voltage and ((2x+1) / 2^(n+1)) of the full-scale voltage or between ((2x+1) / 2^(n+1)) of the full-scale voltage and ((x+1) / 2^n) of the full-scale voltage according to the analog sampling signal and ((2x+1) / 2^(n+1)).Alternatively, the nth level controller determines, based on the nth comparison result, that the analog sampling signal Vm is between ((x-1) / 2^n) of the full-scale voltage and (x / 2^n) of the full-scale voltage when determining that the analog sampling signal is less than (x / 2^n) of the full-scale voltage, and the intermediate value between ((x-1) / 2^n) and (x / 2^n) is ((2x-1) / 2^(n+1)). Therefore, the nth level controller adjusts the analog sampling signal Vm to ((2x-1) / 2^n) of the full-scale voltage. ^(n+1)) is transmitted to the n+1th comparator, so that the n+1th comparator determines whether the analog sampling signal is between ((x-1) / 2^n) of the full-scale voltage and ((2x-1) / 2^(n+1)) of the full-scale voltage or between ((2x-1) / 2^(n+1)) of the full-scale voltage and (x / 2^n) of the full-scale voltage according to the analog sampling signal and the full-scale voltage ((2x-1) / 2^(n+1)). In other words, the n+1th comparator and the nth comparator gradually approach the analog sampling signal by continuously dividing by two equal parts, and the nth comparison result generated by the nth comparator is the value of the nth most significant bit of the digital signal corresponding to the analog sampling signal Vm, and the n+1th comparison result generated by the n+1th comparator is the value of the n+1th most significant bit of the digital signal corresponding to the analog sampling signal Vm.

[0008] Optionally, the n+1th comparator is specifically configured to generate the n+1th comparison result when it is determined that the analog sampling signal is greater than the full-scale voltage ((2x+1) / 2^(n+1)) based on the analog sampling signal and the full-scale voltage ((2x+1) / 2^(n+1)), and the logic value corresponding to the n+1th comparison result is 1; or, the n+1th comparator is specifically configured to generate the n+1th comparison result when it is determined that the analog sampling signal is less than the full-scale voltage ((2x+1) / 2^(n+1)) based on the analog sampling signal and the full-scale voltage ((2x+1) / 2^(n+1)), and the logic value corresponding to the n+1th comparison result is 0. In this optional solution, the logic value corresponding to the n+1th comparison result is 1 or 0, where 0 and 1 correspond exactly to binary digits.

[0009] Optionally, the n+1th comparator is specifically configured to generate the n+1th comparison result when it is determined that the analog sampling signal is greater than the full-scale voltage ((2x-1) / 2^(n+1)) based on the analog sampling signal and the full-scale voltage ((2x-1) / 2^(n+1)), and the logic value corresponding to the n+1th comparison result is 1; or, the n+1th comparator is specifically configured to generate the n+1th comparison result when it is determined that the analog sampling signal is less than the full-scale voltage ((2x-1) / 2^(n+1)) based on the analog sampling signal and the full-scale voltage ((2x-1) / 2^(n+1)), and the logic value corresponding to the n+1th comparison result is 0. In this optional solution, the logic value corresponding to the n+1th comparison result is 1 or 0, where 0 and 1 correspond exactly to binary digits.

[0010] Optionally, the second input terminal of the first-stage comparator is connected to a bias circuit; the bias circuit is configured to receive a full-scale voltage and output (1 / 2) of the full-scale voltage to the second input terminal of the first-stage comparator. In this optional scheme, the bias circuit receives the full-scale voltage and transmits (1 / 2) of the full-scale voltage to the second input terminal of the first-stage comparator, so that the first-stage comparator of the current analog-to-digital converter generates a first comparison result based on the analog sampling signal and (1 / 2) of the full-scale voltage. The first comparison result is the value of the first high-significant bit of the digital signal corresponding to the analog sampling signal, that is, the most significant bit. Then the analog-to-digital converter sequentially obtains the value of the nth high-significant bit of the digital signal corresponding to the analog sampling signal to realize the analog-to-digital conversion function of the analog-to-digital converter.

[0011] Optionally, the first input terminal is a non-inverting input terminal of the comparator, and the second input terminal is an inverting input terminal of the comparator.

[0012] Optionally, the amplitude of the analog signal is between 0 and full-scale voltage.

[0013] In a second aspect, an analog-to-digital conversion method is provided, which includes: receiving an analog signal, sampling the analog signal to generate an analog sampling signal; generating a first comparison result based on the analog sampling signal and 1 / 2 of the full-scale voltage, and outputting a logic value corresponding to the first comparison result as the value of the first high-significant bit of the digital signal corresponding to the analog sampling signal; generating a control signal based on the first comparison result to the nth comparison result; generating an n+1th comparison result based on the analog sampling signal and the control signal, and outputting a logic value corresponding to the n+1th comparison result as the value of the n+1th high-significant bit of the digital signal corresponding to the analog sampling signal.

[0014] Optionally, a control signal is generated according to the first comparison result to the nth comparison result, specifically including: determining x according to the first comparison result to the n-1th comparison result, where x is a decimal number converted from a predetermined digital signal, the predetermined digital signal has n valid bits, and the most significant bit to the second least significant bit of the predetermined digital signal sequentially include the logic value corresponding to the first comparison result to the logic value corresponding to the n-1th comparison result, and the least significant bit of the predetermined digital signal is 1; when it is determined according to the nth comparison result that the analog sampling signal is greater than (x / 2^n) of the full-scale voltage, the generated control signal is ((2x+1) / 2^(n+1)) of the full-scale voltage; or, when it is determined according to the nth comparison result that the analog sampling signal is less than (x / 2^n) of the full-scale voltage, the generated control signal is ((2x-1) / 2^(n+1)) of the full-scale voltage.

[0015] Optionally, when it is determined that the analog sampling signal is greater than the full-scale voltage ((2x+1) / 2^(n+1)) based on the analog sampling signal and the full-scale voltage, the n+1th comparison result is generated, and the logic value corresponding to the n+1th comparison result is 1; or, when it is determined that the analog sampling signal is less than the full-scale voltage ((2x+1) / 2^(n+1)) based on the analog sampling signal and the full-scale voltage ((2x+1) / 2^(n+1)), the n+1th comparison result is generated, and the logic value corresponding to the n+1th comparison result is 0.

[0016] Optionally, when it is determined that the analog sampling signal is greater than the full-scale voltage ((2x-1) / 2^(n+1)) based on the analog sampling signal and the full-scale voltage, the n+1th comparison result is generated, and the logic value corresponding to the n+1th comparison result is 1; or, when it is determined that the analog sampling signal is less than the full-scale voltage ((2x-1) / 2^(n+1)) based on the analog sampling signal and the full-scale voltage ((2x-1) / 2^(n+1)), the n+1th comparison result is generated, and the logic value corresponding to the n+1th comparison result is 0.

[0017] Optionally, the amplitude of the analog signal is between 0 and full-scale voltage.

[0018] Among them, the technical effects brought about by any possible implementation method of the second aspect can refer to the technical effects brought about by the implementation method of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of the structure of a SAR ADC provided in an embodiment of the present application;

[0020] Figure 2A timing diagram of the SAR ADC provided in the embodiment of the present application converting an analog signal into a digital signal;

[0021] Figure 3 A schematic diagram of the structure of an analog-to-digital converter provided in an embodiment of the present application;

[0022] Figure 4 A schematic diagram of the structure of an analog-to-digital converter with a precision of 3 bits provided in an embodiment of the present application;

[0023] Figure 5 A schematic diagram of a principle of an analog-to-digital converter with a precision of 3 bits provided in an embodiment of the present application;

[0024] Figure 6 A schematic flow chart of an analog-to-digital conversion method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0026] Unless otherwise defined, all scientific and technological terms used herein have the same meaning as those known to those of ordinary skill in the art. In the present application, "at least one" refers to one or more, and "multiple" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B, which may represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B may be singular or plural. "At least one of the following (individuals)" or similar expressions thereof, refers to any combination of these items, including any combination of single items (individuals) or plural items (individuals). For example, at least one of a, b or c (individuals) may represent: a, b, c, a and b, a and c, b and c or a, b and c, where a, b and c may be single or multiple. In addition, in the embodiments of the present application, the words "first", "second", "first", "second" and the like do not limit the quantity and order.

[0027] In addition, in the present application, directional terms such as "upper" and "lower" are defined relative to the orientation of the components in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they can change accordingly according to the changes in the orientation of the components in the drawings.

[0028] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0029] Analog-to-digital converter (ADC) is used to convert analog signals into digital signals. At present, most electronic devices are equipped with analog-to-digital converters. Electronic devices receive analog signals and use analog-to-digital converters to convert analog signals into digital signals, and then process the digital signals to realize various functions of electronic devices.

[0030] Among them, the commonly used analog-to-digital converter is the successive approximation register analog-to-digital converter (SAR ADC), see Figure 1 As shown, an embodiment of the present application provides a structural schematic diagram of a SAR ADC, which includes: a sample hold circuit (sample hold devices, referred to as S / H) 101, a comparator 102, a controller 103 and a digital-to-analog converter (digital-to-analog converter, DAC) 104, the sample hold circuit 101 is coupled to the first input end of the comparator 102, the controller 103 is coupled to the output end of the comparator 102 and the input end of the digital-to-analog converter 104, and the output end of the digital-to-analog converter 104 is coupled to the second input end of the comparator 102.

[0031] Reference Figure 2 As shown, the embodiment of the present application provides a timing diagram of SAR ADC converting analog signals into digital signals. Figure 1 Before the SAR ADC shown in the figure works, it is necessary to first transmit the analog signal Vin to the sample-and-hold circuit 101, which samples the analog signal and generates an analog sampled signal Vsh. The sample-and-hold circuit 101 needs to ensure that the analog sampled signal Vsh is maintained for a predetermined time, and the predetermined time needs to ensure that the current analog-to-digital converter converts the analog sampled signal Vsh into a digital signal. Figure 2 The Vfs shown is the full-scale voltage, and the amplitude of the analog signal Vin is between 0 and the full-scale voltage Vfs. Figure 2 The illustrated analog reference signal Vdac includes an analog reference signal Vdac1 , an analog reference signal Vdac2 , and an analog reference signal Vdac3 as described below.

[0032] Combination Figure 2 As shown, in the time period t11, the sampling and holding circuit 101 samples the analog signal Vin to generate an analog sampling signal Vsh, and keeps the analog sampling signal Vsh until the end of the time period t14. In the time period t12, Figure 1 The comparator 102 shown receives an analog sampling signal Vsh transmitted from a first input terminal, and also receives an analog reference signal Vdac1 transmitted from a second input terminal. The comparator subtracts the analog sampling signal Vsh transmitted from the first input terminal from the analog reference signal Vdac1 transmitted from the second input terminal to generate a comparison result. At this time, the first input terminal is the positive input terminal, also called the positive input terminal; the second input terminal is the negative input terminal, also called the reverse input terminal. Among them, Figure 2 The accuracy of the SAR ADC shown is 3 bits (bit), so the current analog sampling signal Vsh needs to be converted into a three-bit binary digital signal, and the controller 103 generates a digital signal (100) according to the rule of setting the most significant bit (MSB) to 1 and other valid positions to 0 (here only 3 bits are used as an example, and the result of the analog-to-digital conversion is between (000-111). Of course, the accuracy of the SAR ADC may also use 4 bits (0000-1111), etc.). The controller 103 transmits the digital signal (100) to the digital-to-analog converter 104, and the digital-to-analog converter 104 converts the digital signal (100) into an analog reference signal Vdac1. The analog reference signal Vdac1 corresponds to 1 / 2 of the full-scale voltage, that is, the analog reference signal Vdac1 is (1 / 2) Vfs. Subsequently, the digital-to-analog converter 104 transmits the analog reference signal Vdac1 to the second input terminal of the comparator 102. Figure 2 As shown, since the current analog sampling signal Vsh is greater than the analog reference signal Vdac1, the comparison result output by the comparator 102 is greater than 0, which means that the most significant bit of the digital signal (100) is 1, and the analog sampling signal Vsh is between (1 / 2)Vfs and (2 / 2)Vfs.

[0033] In time period t13, Figure 1 The comparator 102 shown receives an analog sampling signal Vsh transmitted from a first input terminal and an analog reference signal Vdac2 transmitted from a second input terminal. The comparator 102 subtracts the analog sampling signal Vsh transmitted from the first input terminal from the analog reference signal Vdac2 transmitted from the second input terminal to generate a comparison result. Figure 2As shown, the controller 103 has confirmed that the most significant bit of the digital signal (100) is 1 in the time period t12, and generates a digital signal (110) according to the rule of setting the second most significant bit of the digital signal (100) to 1 and other significant bits to 0. The controller 103 transmits the digital signal (110) to the digital-to-analog converter 104, and the digital-to-analog converter 104 converts the digital signal (110) into an analog reference signal Vdac2. The analog reference signal Vdac2 corresponds to 3 / 4 of the full-scale voltage, that is, the analog reference signal Vdac1 is (3 / 4) Vfs. Subsequently, the digital-to-analog converter 104 transmits the analog reference signal Vdac2 to the second input terminal of the comparator 102. Since the current analog sampling signal Vsh is less than the analog reference signal Vdac2, the comparison result output by the comparator 102 is less than 0, indicating that the second most significant bit of the digital signal (110) is 0, and the analog sampling signal Vsh is between (2 / 4) Vfs and (3 / 4) Vfs.

[0034] In time period t14, Figure 1 The comparator 102 shown receives an analog sampling signal Vsh transmitted from a first input terminal and an analog reference signal Vdac3 transmitted from a second input terminal. The comparator subtracts the analog sampling signal Vsh transmitted from the first input terminal from the analog reference signal Vdac3 transmitted from the second input terminal to generate a comparison result. Figure 2 As shown, the controller 103 has confirmed that the second most significant bit of the digital signal (110) is 0 in the time period t13, and generates a digital signal (101) according to the rule of setting the least significant bit (LSB) to 1. The controller 103 transmits the digital signal (101) to the digital-to-analog converter 104, and the digital-to-analog converter 104 converts the digital signal (101) into an analog reference signal Vdac3. The analog reference signal Vdac2 corresponds to 5 / 8 of the full-scale voltage, that is, the analog reference signal Vdac1 is (5 / 8) Vfs. Subsequently, the digital-to-analog converter 104 transmits the analog reference signal Vdac3 to the second input terminal of the comparator 102. Since the current analog sampling signal Vsh is greater than the analog reference signal Vdac3, the comparison result output by the comparator 102 is greater than 0, which means that the least significant bit of the digital signal (101) is 1, and the analog sampling signal Vsh is between (5 / 8) Vfs and (6 / 8) Vfs.

[0035] After the above time period t11 to time period t14 ends, the controller 103 can determine the value of each valid bit of the digital signal converted from the current analog sampling signal Vsh, and can determine that the digital signal corresponding to the current analog sampling signal Vsh is (101). When the above SAR ADC performs analog-to-digital conversion, the analog sampling signal sampled each time must be compared and the value is determined in order from the highest bit to the lowest bit, which requires the four circuit modules of the sampling and holding circuit 101, the comparator 102, the controller 103 and the digital-to-analog converter 104 to cooperate with each other, and when the accuracy of the digital-to-analog converter 104 is 3 bits (bit), the accuracy of the SAR ADC will also be limited to 3 bits, and when the accuracy of the digital-to-analog converter 104 is 4 bits, the accuracy of the SAR ADC will also be limited to 4 bits. The accuracy of the digital-to-analog converter will limit the analog-to-digital conversion accuracy of the SAR ADC.

[0036] In order to avoid the limitation of the analog-to-digital conversion accuracy of the analog-to-digital converter by the digital-to-analog converter, refer to Figure 3 As shown, an embodiment of the present application provides an analog-to-digital converter, which includes: a sampling and holding circuit 31, an n+1-level comparator 32 ( Figure 3 The comparator 32 shown includes a comparator 32-1, a comparator 32-2, a comparator 32-n and a comparator 32-n+1) and an n-stage controller 33 ( Figure 3 The controller 33 shown includes a controller 33-1, a controller 33-n-1 and a controller 33-n); the sampling and holding circuit 31 is connected to the first input terminal of each level of the comparator 32; the second input terminal of the comparator 32-n+1 is connected to the output terminal of the controller 33-n, wherein n is a positive integer greater than or equal to 1; the input terminal of the controller 33-n is respectively connected to the output terminal of the comparator 32-1 to the output terminal of the comparator 32-n.

[0037] The sampling and holding circuit 31 is configured to receive an analog signal Vin, sample the analog signal to generate an analog sampling signal Vm, and transmit the analog sampling signal Vm to the first input terminal of each level of comparator 32. Exemplarily, after receiving the analog signal Vin, the sampling and holding circuit needs to sample the analog signal Vin to generate an analog sampling signal Vm, and transmit the analog sampling signal Vm to the first input terminal of each level of comparator 32, so that each level of comparator 32 compares the current analog sampling signal Vm. The amplitude of the analog signal Vin is between 0 and the full-scale voltage Vfs, and the sampling and holding circuit 31 needs to ensure that the sampled analog sampling signal Vm is maintained for a predetermined time, which is greater than or equal to the time consumed by the analog-to-digital converter to convert the analog sampling signal Vm into a digital signal.

[0038] Comparator 32-1 is configured to generate a first comparison result based on the analog sampling signal and 1 / 2 of the full-scale voltage, transmit the first comparison result to the n-stage controller respectively, and output the logic value corresponding to the first comparison result as the value of the first high-significant bit of the digital signal corresponding to the analog sampling signal.

[0039] Among them, each level of comparator 32 usually subtracts the analog sampling signal Vm transmitted from its first input terminal from the full-scale voltage (x / 2^n) transmitted from the second input terminal to generate the nth comparison result. And the comparison result of each level of comparator 32 usually corresponds to two logic values, one logic value is 1 (also called high level), and the other logic value is 0 (also called low level). In the first type of comparator, the logic value corresponding to the comparison result is 1, indicating that the analog sampling signal Vm is greater than the full-scale voltage (x / 2^n), and the logic value corresponding to the comparison result is 0, indicating that the analog sampling signal Vm is less than or equal to the full-scale voltage (x / 2^n); in the second type of comparator, the logic value corresponding to the comparison result is 1, indicating that the analog sampling signal Vm is greater than or equal to the full-scale voltage (x / 2^n), and the logic value corresponding to the comparison result is 0, indicating that the analog sampling signal Vm is less than the full-scale voltage (x / 2^n). In the third comparator, the logic value corresponding to the comparison result is 1, indicating that the analog sampling signal Vm is greater than the full-scale voltage (x / 2^n), and the logic value corresponding to the comparison result is 0, indicating that the analog sampling signal Vm is less than the full-scale voltage (x / 2^n). In the embodiment of the present application, the comparator 32 used is to subtract the full-scale voltage (x / 2^n) transmitted by the second input terminal from the analog sampling signal Vm transmitted by the first input terminal to generate the nth comparison result, wherein the first input terminal is also referred to as the non-inverting input terminal of the comparator, the second input terminal is also referred to as the inverting input terminal of the comparator, and the logic value corresponding to the nth comparison result is 1, indicating that the analog sampling signal Vm is greater than the full-scale voltage (x / 2^n), and the logic value corresponding to the nth comparison result is 0, indicating that the analog sampling signal Vm is less than the full-scale voltage (x / 2^n). Of course, the first comparator or the second comparator mentioned above can also be used, and the embodiment of the present application does not limit this.

[0040] In addition, the comparator 32-1 can determine whether the current analog sampling signal Vm is between 0 and 1 / 2 of the full-scale voltage Vfs, or between 1 / 2 of the full-scale voltage Vfs and the full-scale voltage Vfs, based on the first comparison result generated by the analog sampling signal Vm and 1 / 2 of the full-scale voltage Vfs. When the analog sampling signal Vm is greater than 1 / 2 of the full-scale voltage Vfs, the logic value corresponding to the generated first comparison result is 1, indicating that the current analog sampling signal Vm is between 1 / 2 of the full-scale voltage Vfs and the full-scale voltage Vfs; when the analog sampling signal Vm is less than 1 / 2 of the full-scale voltage Vfs, the logic value corresponding to the generated first comparison result is 0, indicating that the current analog sampling signal Vm is between 0 and 1 / 2 of the full-scale voltage Vfs. Then, the logic value corresponding to the first comparison result is the value of the first high-significant bit (that is, the most significant bit) of the digital signal corresponding to the analog sampling signal.

[0041] The controller 33 - n is configured to generate a control signal according to the first comparison result outputted from the comparator 32 - 1 to the nth comparison result outputted from the comparator 32 - n.

[0042] Specifically, the controller 33-n is configured to determine x based on the first comparison result output by the comparator 32-1 to the n-1th comparison result output by the comparator 32-n-1, where x is a decimal number converted from a predetermined digital signal, the predetermined digital signal has n valid bits, and the most significant bit to the second least significant bit of the predetermined digital signal sequentially include the logic value corresponding to the first comparison result to the logic value corresponding to the n-1th comparison result, and the least significant bit of the predetermined digital signal is 1; when it is determined according to the nth comparison result output by the comparator 32-n that the analog sampling signal is greater than (x / 2^n) of the full-scale voltage, the generated control signal is ((2x+1) / 2^(n+1)) of the full-scale voltage; or, when it is determined according to the nth comparison result output by the comparator 32-n that the analog sampling signal is less than (x / 2^n) of the full-scale voltage, the generated control signal is ((2x-1) / 2^(n+1)) of the full-scale voltage.

[0043] Exemplarily, the control signal generated by any level controller corresponds to a predetermined number of full-scale voltages, and from the above content, it can be seen that the control signal generated by the n-1th level controller corresponds to (x / 2^n) of the full-scale voltage, and the nth level comparator generates the nth comparison result based on the analog sampling signal and the full-scale voltage (x / 2^n).

[0044] Moreover, x is a decimal number converted from a predetermined digital signal, the predetermined digital signal has n valid bits, the most significant bit to the second least significant bit of the predetermined digital signal sequentially include the logic value corresponding to the first comparison result to the logic value corresponding to the n-1th comparison result, and the least significant bit of the predetermined digital signal is 1. This means that x must be an odd number, and x is less than 2^n, which means that the value of x is 1, 3, 5...2^n-3, 2^n-1. Among them, there are a total of (2^n / 2) positive odd numbers between 0 and 2^n, and when the comparator 32-n generates the nth comparison result according to the analog sampling signal Vm and the full-scale voltage (x / 2^n), there are 2 logical values ​​corresponding to the nth comparison result, which means that the comparator 32-n can determine a total of (2^n / 2)*2, that is, 2^n situations, which means that the comparator 32-n divides the full-scale voltage into 2^n equally spaced ranges, the first equally spaced range is 0 to (1 / 2^n) of the full-scale voltage, the second equally spaced range is (1 / 2^n) of the full-scale voltage to (2 / 2^n) of the full-scale voltage, the third equally spaced range is (2 / 2^n) of the full-scale voltage to (3 / 2^n) of the full-scale voltage... and so on, the interval between two adjacent equally spaced ranges is (1 / 2^n) of the full-scale voltage.

[0045] Wherein, when x is 1, the comparator 32-n determines whether the analog sampling signal Vm is between the first equally spaced range of 0 and (1 / 2^n) of the full-scale voltage, or between the second equally spaced range of (1 / 2^n) of the full-scale voltage and (2 / 2^n) of the full-scale voltage. When the analog sampling signal Vm is greater than (1 / 2^n) of the full-scale voltage, the logic value corresponding to the nth comparison result generated by the comparator 32-n is 1, and the comparator 32-n determines that the analog sampling signal Vm is between the second equally spaced range of (1 / 2^n) of the full-scale voltage and (2 / 2^n) of the full-scale voltage; when the analog sampling signal Vm is less than (1 / 2^n) of the full-scale voltage, the logic value corresponding to the nth comparison result generated by the comparator 32-n is 0, and the comparator 32-n determines that the analog sampling signal Vm is between the first equally spaced range of 0 and (1 / 2^n) of the full-scale voltage.

[0046] When x is 3, the comparator 32-n determines whether the analog sampling signal Vm is between (2 / 2^n) and (3 / 2^n) of the full-scale voltage in the third equally spaced range, or between (3 / 2^n) and (4 / 2^n) of the full-scale voltage in the fourth equally spaced range. When the analog sampling signal Vm is greater than (3 / 2^n) of the full-scale voltage, the logic value corresponding to the nth comparison result generated by the comparator 32-n is 1, and the comparator 32-n determines that the analog sampling signal Vm is between (3 / 2^n) and (4 / 2^n) of the full-scale voltage in the fourth equally spaced range; when the analog sampling signal Vm is less than (3 / 2^n), the logic value corresponding to the nth comparison result generated by the comparator 32-n is 0, and the comparator 32-n determines that the analog sampling signal Vm is between (2 / 2^n) and (3 / 2^n) of the full-scale voltage in the third equally spaced range.

[0047] By analogy, the comparator 32 - n generates the value of the nth most significant bit of the digital signal corresponding to the analog sampling signal Vm corresponding to the nth comparison result.

[0048] Then, when the controller 33-n determines that the analog sampling signal is greater than (x / 2^n) of the full-scale voltage according to the nth comparison result, it means that the current analog sampling signal is between (x / 2^n) of the full-scale voltage and ((x+1) / 2^n) of the full-scale voltage. Then the comparator 33-n+1 needs to divide the range between (x / 2^n) of the full-scale voltage and ((x+1) / 2^n) of the full-scale voltage into two equally spaced ranges, and then determine which of the two equally spaced ranges the analog sampling signal Vm is in. The intermediate value of (x / 2^n) and ((x+1) / 2^n) is (((x / 2^n)+((x+1) / 2^n)) / 2), that is, ((2x+1) / 2^(n+1)), so the control signal generated by the controller 33-n is ((2x+1) / 2^(n+1)) of the full-scale voltage.

[0049] When the controller 33-n determines that the analog sampling signal is less than (x / 2^n) of the full-scale voltage according to the nth comparison result, it means that the current analog sampling signal is between ((x-1) / 2^n) of the full-scale voltage and (x / 2^n) of the full-scale voltage. Then the comparator 33-n+1 needs to divide the range between ((x-1) / 2^n) of the full-scale voltage and (x / 2^n) of the full-scale voltage into two equally spaced ranges, and then determine which of the two equally spaced ranges the analog sampling signal Vm is in. The intermediate value between ((x-1) / 2^n) and (x / 2^n) is ((((x-1) / 2^n)+(x / 2^n)) / 2), that is, ((2x-1) / 2^(n+1)), so the control signal generated by the controller 33-n is ((2x-1) / 2^(n+1)) of the full-scale voltage.

[0050] That is to say, the n+1th comparator and the nth comparator gradually approach the analog sampling signal by continuously dividing the signal into two equal parts.

[0051] Exemplarily, when n is 3, 2^n is 8, and taking the logical value corresponding to the first comparison result as 1, the logical value corresponding to the second comparison result as 0, and the logical value corresponding to the third comparison result as 1 as an example, at this time, the predetermined digital signal is (101), and the decimal number converted from the predetermined digital signal (101) is 5, and the controller 33-3 determines that the value of x is 5. Moreover, the logic value corresponding to the third comparison result is 1, indicating that the analog sampling signal Vm is greater than (5 / 8) of the full-scale voltage, that is, the analog sampling signal Vm is between (5 / 8) of the full-scale voltage and (6 / 8) of the full-scale voltage. Then, the comparator 32-4 needs to divide the range from (5 / 8) of the full-scale voltage to (6 / 8) of the full-scale voltage into two equally spaced ranges, wherein the first equally spaced range is from (5 / 8) of the full-scale voltage to (13 / 16) of the full-scale voltage, and the second equally spaced range is from (13 / 16) of the full-scale voltage to (6 / 8) of the full-scale voltage. The comparator 32-4 then determines in which of the two equally spaced ranges the analog sampling signal Vm is located. Therefore, the comparator 32-4 needs to generate the n+1th comparison result according to the analog sampling signal Vm and the full-scale voltage (13 / 16), where n is 3, x is 5, ((2x-1) / 2^(n+1)) is ((2*5+1) / (2^(3+1))), which is (13 / 16). This means that the control signal generated by the controller 33-3 is the full-scale voltage (13 / 16), and the controller 33-3 transmits the full-scale voltage (13 / 16) to the comparator 32-4. So that the comparator 32-4 can generate the fourth comparison result according to the analog sampling signal Vm and the control signal.

[0052] Exemplarily, when n is 4, 2^n is 16, and the logic value corresponding to the first comparison result is 0, the logic value corresponding to the second comparison result is 0, the logic value corresponding to the third comparison result is 1, and the logic value corresponding to the fourth comparison result is 0, at this time, the predetermined digital signal is (0011), and the decimal number converted from the predetermined digital signal (0011) is 3, and the controller 33-4 determines that the value of x is 3. Moreover, the logic value corresponding to the fourth comparison result is 0, indicating that the analog sampling signal Vm is less than (3 / 16) of the full-scale voltage, that is, the analog sampling signal Vm is between (2 / 16) of the full-scale voltage and (3 / 16) of the full-scale voltage. Then, the comparator 32-5 needs to divide the range from (2 / 16) of the full-scale voltage to (3 / 16) of the full-scale voltage into two equally spaced ranges, wherein the first equally spaced range is from (2 / 16) of the full-scale voltage to (5 / 32) of the full-scale voltage, and the second equally spaced range is from (5 / 32) of the full-scale voltage to (3 / 16) of the full-scale voltage. The comparator 32-5 then determines which of the two equal parts the analog sampling signal Vm is in. Therefore, the comparator 32-5 needs to generate the n+1th comparison result according to the analog sampling signal Vm and the (5 / 32) of the full-scale voltage, where n is 3, x is 5, ((2x-1) / 2^(n+1)) is ((2*3-1) / (2^(4+1))), which is (5 / 32), which means that the control signal generated by the controller 33-4 is the (5 / 32) of the full-scale voltage, and the controller 33-4 transmits the (5 / 32) of the full-scale voltage to the comparator 32-5. So that the comparator 32-5 can generate the fifth comparison result according to the analog sampling signal and the (5 / 32) of the full-scale voltage.

[0053] The comparator 32-n+1 is configured to generate the n+1th comparison result according to the analog sampling signal Vm and the control signal output by the controller 33-n, and output the logic value corresponding to the n+1th comparison result as the value of the n+1th high-significant bit of the digital signal corresponding to the analog sampling signal.

[0054] Among them, the control signal generated by any level of controller corresponds to a predetermined number of full-scale voltages, and when the comparator 32-n+1 receives a control signal output by the controller 33-n as ((2x+1) / 2^(n+1)) of the full-scale voltage, the comparator 32-n+1, ​​based on the analog sampling signal and the full-scale voltage ((2x+1) / 2^(n+1)), determines that the analog sampling signal is greater than ((2x+1) / 2^(n+1)) of the full-scale voltage, generates the n+1th comparison result, and the logic value corresponding to the n+1th comparison result is 1; or, the comparator 32-n+1, ​​based on the analog sampling signal and the full-scale voltage ((2x+1) / 2^(n+1)), determines that the analog sampling signal is less than ((2x+1) / 2^(n+1)) of the full-scale voltage, generates the n+1th comparison result, and the logic value corresponding to the n+1th comparison result is 0.

[0055] When comparator 32-n+1 receives a control signal output by controller 33-n that is a full-scale voltage of ((2x-1) / 2^(n+1)), comparator 32-n+1 determines, based on the analog sampling signal and the full-scale voltage of ((2x-1) / 2^(n+1)), that the analog sampling signal is greater than ((2x-1) / 2^(n+1)) of the full-scale voltage, and generates the n+1th comparison result, and the logic value corresponding to the n+1th comparison result is 1; or, when comparator 32-n+1 determines, based on the analog sampling signal and the full-scale voltage of ((2x-1) / 2^(n+1)), that the analog sampling signal is less than ((2x-1) / 2^(n+1)) of the full-scale voltage, it generates the nth comparison result, and the logic value corresponding to the n+1th comparison result is 0.

[0056] The logic value corresponding to the (n+1)th comparison result is the value of the (n+1)th most significant bit of the digital signal corresponding to the analog sampling signal.

[0057] In the analog-to-digital converter, the analog sampling signal is transmitted to the first input terminal of each level of comparator, and the first level comparator generates the first comparison result according to the analog sampling signal and (1 / 2) of the full-scale voltage, wherein the logic value corresponding to the first comparison result is the value of the first high-significant bit of the digital signal corresponding to the analog sampling signal. In addition, the n-level controller can generate a control signal according to the first comparison result output by the first level comparator to the n-th comparison result output by the n-level comparator. Among them, the n+1-level comparator generates the n+1-th comparison result according to the analog sampling signal and the control signal output by the n-level controller, and the logic value corresponding to the n+1-th comparison result is the value of the n+1-th high-significant bit of the digital signal corresponding to the analog sampling signal. It can be seen that in the analog-to-digital converter, only the same number of comparators as the accuracy of the analog-to-digital converter are needed to realize the process of converting the analog signal into a digital signal, and no digital-to-analog converter is required, thereby avoiding the limitation of the digital-to-analog converter on the analog-to-digital conversion accuracy of the analog-to-digital converter.

[0058] In other embodiments, each level of comparator 32 can generate the nth comparison result by subtracting the analog sampling signal Vm transmitted from the first input terminal from the full-scale voltage (x / 2^n) transmitted from the second input terminal, wherein the second input terminal is also referred to as the non-inverting input terminal of the comparator, and the first input terminal is also referred to as the inverting input terminal of the comparator. And the comparison result of each level of comparator 32 usually corresponds to two logic values, one logic value is 1 (also called high level), and the other logic value is 0 (also called low level). In the fourth type of comparator, the logic value corresponding to the comparison result is 1, indicating that the full-scale voltage (x / 2^n) is greater than the analog sampling signal Vm, and the logic value corresponding to the comparison result is 0, indicating that the full-scale voltage (x / 2^n) is less than or equal to the analog sampling signal Vm; in the fifth type of comparator, the logic value corresponding to the comparison result is 1, indicating that the full-scale voltage (x / 2^n) is greater than or equal to the analog sampling signal Vm, and the logic value corresponding to the comparison result is 0, indicating that the full-scale voltage (x / 2^n) is less than the analog sampling signal Vm. In the sixth comparator, the logic value corresponding to the comparison result is 1, indicating that the full-scale voltage (x / 2^n) is greater than the analog sampling signal Vm, and the logic value corresponding to the comparison result is 0, indicating that the full-scale voltage (x / 2^n) is less than the analog sampling signal Vm. Then, the logic value corresponding to the comparison result of the comparator 32-n is taken inversely, that is, the value of the nth most significant bit of the digital signal corresponding to the current analog sampling signal.

[0059] Specifically, refer to Figure 4 As shown, an embodiment of the present application provides an analog-to-digital converter, the accuracy of which is 3 bits (bit), that is, the analog sampling signal in the analog-to-digital converter can be converted into 3-bit binary data. Figure 5 As shown, Figure 5The schematic diagram of the analog-to-digital converter provided in the embodiment of the present application. In addition, the amplitude of the current analog signal Vin is between 0 and the full-scale voltage Vfs.

[0060] Reference Figure 4 As shown, the sampling and holding circuit 42 is connected to the first input terminal of the comparator 42-1, the first input terminal of the comparator 42-2 and the first input terminal of the comparator 42-3, the second input terminal of the comparator 42-1 receives 1 / 2 of the full-scale voltage, that is, (1 / 2) Vfs, the controller 43-1 is connected to the output terminal of the comparator 42-1 and the second input terminal of the comparator 42-2, and the controller 43-2 is connected to the output terminal of the comparator 42-1, the output terminal of the comparator 42-2 and the second input terminal of the comparator 42-3.

[0061] Figure 4 The analog-to-digital conversion accuracy of the analog-to-digital converter in is 3 bits. Figure 4 The analog-to-digital converter shown has 3 levels of comparators and 2 levels of controllers. In other embodiments, the analog-to-digital conversion accuracy of the analog-to-digital converter is 3 bits, and the analog-to-digital converter has 3 levels of comparators and 3 levels of controllers. The controller 43-3 is connected to the output end of the comparator 42-1, the output end of the comparator 42-2, and the output end of the comparator 42-3.

[0062] It should be noted that when the precision of the analog-to-digital converter is 4 bits, there are 4-level comparators and 3-level controllers in the analog-to-digital converter, or there are 4-level comparators and 4-level controllers in the analog-to-digital converter; when the precision of the analog-to-digital converter is 5 bits, there are 5-level comparators and 4-level controllers in the analog-to-digital converter, or there are 5-level comparators and 5-level controllers in the analog-to-digital converter…

[0063] When the analog-to-digital converter converts an analog signal into a digital signal, first, the sampling and holding circuit 41 receives the analog signal Vin, samples the analog signal to generate an analog sampling signal Vm, and transmits the analog sampling signal Vm to the first input terminal of the comparator 42-1, the first input terminal of the comparator 42-2, and the first input terminal of the comparator 42-3, and the sampling and holding circuit 41 needs to ensure that the current analog sampling signal Vm is maintained for a predetermined time length, which is greater than or equal to the time consumed by the analog-to-digital converter to convert the analog sampling signal Vm into a digital signal.

[0064] The comparator 42-1 generates a first comparison result based on the analog sampling signal Vm and 1 / 2 of the full-scale voltage Vfs, that is, (1 / 2)Vfs. If the analog sampling signal Vm is greater than 1 / 2 of the full-scale voltage, the logic value corresponding to the first comparison result generated by the comparator 42-1 is 1, and it is determined that the analog sampling signal is between (1 / 2)Vfs and (2 / 2)Vfs; if the analog sampling signal Vm is less than (1 / 2)Vfs, the logic value corresponding to the first comparison result generated by the comparator 42-1 is 0, and it is determined that the analog sampling signal is between 0 and (1 / 2)Vfs. Since the comparator 42-1 compares the analog sampling signal Vm with (1 / 2)Vfs, the logic value corresponding to the first comparison result generated by the comparator 42-1 is the value of the first most significant bit of the digital signal corresponding to the analog sampling signal Vm, that is, the value of the most significant bit. The comparator 42 - 1 is connected to a bias circuit, which receives a full-scale voltage and transmits 1 / 2 of the full-scale voltage to a second input terminal of the comparator 42 - 1 .

[0065] The controller 43-1 generates a control signal according to the first comparison result output by the comparator 42-1 to the nth comparison result output by the comparator 42-n, and the current n is 1, which means that the controller 43-1 generates a control signal according to the first comparison result output by the comparator 42-1. The controller 43-1 determines x according to the first comparison result output by the comparator 42-1 to the n-1th comparison result output by the comparator 42-n-1, where x is a decimal number converted from a predetermined digital signal, the predetermined digital signal has n bits, the most significant bit to the second least significant bit of the predetermined digital signal sequentially include the logic value corresponding to the first comparison result to the logic value corresponding to the n-1th comparison result, and the least significant bit of the predetermined digital signal is 1. Since the current n is 1, there is no n-1th comparison result, and the predetermined digital signal also has only 1 bit, so the predetermined digital signal is (1), and the decimal value corresponding to the predetermined digital signal (1) is 1, and the controller 43-1 determines that x is 1. When the controller 43-1 determines that the analog sampling signal is greater than (1 / 2) of the full-scale voltage according to the first comparison result, the generated control signal is ((2*1+1) / 2^(1+1)) of the full-scale voltage, that is, 3 / 4 of the full-scale voltage Vfs. The controller 43-1 transmits (3 / 4) Vfs to the second input terminal of the comparator 42-2. Figure 5 The comparator 42-2a shown receives (3 / 4) Vfs transmitted from the second input terminal of the controller 43-1; or, when it is determined according to the first comparison result that the analog sampling signal is less than (1 / 2) of the full-scale voltage, the generated control signal is ((2*1-1) / 2^(1+1)) of the full-scale voltage, that is, 1 / 4 of the full-scale voltage Vfs, and the controller 43-1 transmits (1 / 4) Vfs to the second input terminal of the comparator 42-2, referring to Figure 5 The comparator 42 - 2 b shown receives (1 / 4) Vfs transmitted from the second input terminal of the controller 43 - 1 .

[0066] The comparator 42-2 generates a second comparison result according to the analog sampling signal Vm and the control signal output by the controller 43-1. If the control signal transmitted from the controller 43-1 to the second input terminal of the comparator 42-2 is (1 / 4) Vfs. Figure 5 As shown, the comparator 42-2b generates a second comparison result according to the analog sampling signal Vm and (1 / 4) Vfs. If the analog sampling signal Vm is greater than (1 / 4) Vfs, the logic value corresponding to the second comparison result generated by the comparator 42-2b is 1, and it is determined that the analog sampling signal is between (1 / 4) Vfs and (2 / 4) Vfs; if the analog sampling signal Vm is less than (1 / 4) Vfs, the logic value corresponding to the second comparison result generated by the comparator 42-2b is 0, and it is determined that the analog sampling signal is between 0 and (1 / 4) Vfs. Since the comparator 42-2b compares the analog sampling signal Vm and (1 / 4) Vfs, the logic value corresponding to the second comparison result generated by the comparator 42-2b is the value of the second most significant bit of the digital signal corresponding to the analog sampling signal Vm.

[0067] The comparator 42-2 generates a second comparison result according to the analog sampling signal Vm and the control signal output by the controller 43-1. If the control signal transmitted from the controller 43-1 to the second input terminal of the comparator 42-2 is (3 / 4) Vfs, Figure 5 As shown, the comparator 42-2a generates a second comparison result according to the analog sampling signal Vm and (3 / 4)Vfs. If the analog sampling signal Vm is greater than (3 / 4)Vfs, the logic value corresponding to the second comparison result generated by the comparator 42-2a is 1, and it is determined that the analog sampling signal is between (3 / 4)Vfs and (4 / 4)Vfs; if the analog sampling signal Vm is less than (3 / 4)Vfs, the logic value corresponding to the second comparison result generated by the comparator 42-2a is 0, and it is determined that the analog sampling signal is between (2 / 4)Vfs and (3 / 4)Vfs. Since the comparator 42-2a compares the analog sampling signal Vm and (3 / 4)Vfs, the logic value corresponding to the second comparison result generated by the comparator 42-2a is the value of the second most significant bit of the digital signal corresponding to the analog sampling signal Vm.

[0068] The controller 43-2 generates a control signal based on the first comparison result output by the comparator 42-1 to the nth comparison result output by the comparator 42-n, and the current n is 2, which means that the controller 43-2 generates a control signal based on the first comparison result output by the comparator 42-1 to the second comparison result output by the comparator 42-2. The controller 43-2 determines x based on the first comparison result output by the comparator 42-1 to the n-1th comparison result output by the comparator 42-n-1, where x is a decimal number converted from a predetermined digital signal, the predetermined digital signal has n bits, and the most significant bit to the second least significant bit of the predetermined digital signal sequentially include the logic value corresponding to the first comparison result to the logic value corresponding to the n-1th comparison result, and the least significant bit of the predetermined digital signal is 1. Where n-1 is 1, and the logic value corresponding to the comparison result is 1 or 0, which means that the predetermined digital signal is (11) or the predetermined digital signal is (01). When the predetermined digital signal is 11, the decimal value corresponding to the predetermined digital signal (11) is 3, referring to Figure 5 As shown, the controller 43-2a determines that x is 3. When the controller 43-2a determines that the analog sampling signal is greater than (3 / 4)Vfs according to the second comparison result, the generated control signal is ((2*3+1) / 2^(2+1)) of the full-scale voltage, that is, (7 / 8)Vfs. The controller 43-2a transmits (7 / 8)Vfs to the second input terminal of the comparator 42-3. Figure 5 The comparator 42-3a shown receives (7 / 8)Vfs transmitted from the second input terminal of the controller 43-2a; or, when it is determined according to the second comparison result that the analog sampling signal is less than (3 / 4)Vfs, the generated control signal is ((2*3-1) / 2^(2+1)) of the full-scale voltage, that is, (5 / 8)Vfs, and the controller 43-2a transmits (5 / 8)Vfs to the second input terminal of the comparator 42-3, referring to Figure 5 The comparator 42 - 3 b shown receives (5 / 8) Vfs transmitted from the second input terminal of the controller 43 - 2 a .

[0069] When the predetermined digital signal is 01, the decimal value corresponding to the predetermined digital signal (01) is 1. Figure 5 As shown, the controller 43-2b determines that x is 1. And when the controller 43-2b determines that the analog sampling signal is greater than (1 / 4)Vfs according to the second comparison result, the generated control signal is ((2*1+1) / 2^(2+1)) of the full-scale voltage, that is, (3 / 8)Vfs. The controller 43-2b transmits (3 / 8)Vfs to the second input terminal of the comparator 42-3, referring to Figure 5The comparator 42-3c shown receives (3 / 8)Vfs transmitted from the second input terminal of the controller 43-2b; or, when it is determined according to the second comparison result that the analog sampling signal is less than (1 / 4)Vfs, the generated control signal is ((2*3-1) / 2^(2+1)) of the full-scale voltage, that is, (1 / 8)Vfs, and the controller 43-2b transmits (1 / 8)Vfs to the second input terminal of the comparator 42-3, referring to Figure 5 The comparator 42 - 3 d shown receives (1 / 8) Vfs transmitted from the second input terminal of the controller 43 - 2 b.

[0070] Exemplarily, the controller 43-2 can be implemented using a 2-4 decoder circuit. When the controller 43-2 is implemented using a 2-4 decoder circuit, the first comparison result transmitted by the comparator 42-1 is transmitted to the first input terminal of the 2-4 decoder, and the second comparison result transmitted by the comparator 42-2 is transmitted to the second input terminal of the 2-4 decoder. In addition, the 2-4 decoder is configured to generate a control signal of (7 / 8) Vfs when determining that the first comparison result inputted at the first input terminal corresponds to a logic value of 1 and the second comparison result inputted at the second input terminal corresponds to a logic value of 1, and transmit (7 / 8) Vfs to the comparator 42-3; the 2-4 decoder is configured to generate a control signal of (5 / 8) Vfs when determining that the first comparison result inputted at the first input terminal corresponds to a logic value of 1 and the second comparison result inputted at the second input terminal corresponds to a logic value of 0, and transmit (5 / 8) Vfs to the comparator 42- 3; The 24 decoder is configured to generate a control signal of (3 / 8) Vfs when determining that the first comparison result input at the first input terminal corresponds to a logic value of 0 and the second comparison result input at the second input terminal corresponds to a logic value of 1, and transmit (3 / 8) Vfs to the comparator 42-3; The 24 decoder is configured to generate a control signal of (1 / 8) Vfs when determining that the first comparison result input at the first input terminal corresponds to a logic value of 0 and the second comparison result input at the second input terminal corresponds to a logic value of 0, and transmit (1 / 8) Vfs to the comparator 42-3.

[0071] The comparator 42-3 generates a third comparison result according to the analog sampling signal Vm and the control signal output by the controller 43-2. ​​If the control signal transmitted from the controller 43-2 to the second input terminal of the comparator 42-3 is (7 / 8) Vfs, Figure 5As shown, the comparator 42-3a generates a third comparison result according to the analog sampling signal Vm and (7 / 8)Vfs. If the analog sampling signal Vm is greater than (7 / 8)Vfs, the logic value corresponding to the third comparison result generated by the comparator 42-3a is 1, and it is determined that the analog sampling signal is between (7 / 8)Vfs and (8 / 8)Vfs. In summary, the digital signal corresponding to the analog sampling signal Vm is (111); if the analog sampling signal Vm is less than (7 / 8)Vfs, the logic value corresponding to the third comparison result generated by the comparator 42-3a is 0, and it is determined that the analog sampling signal is between (6 / 8)Vfs and (7 / 8)Vfs. In summary, the digital signal corresponding to the analog sampling signal Vm is (110).

[0072] The comparator 42-3 generates a third comparison result according to the analog sampling signal Vm and the control signal output by the controller 43-2. ​​If the control signal transmitted from the controller 43-2 to the second input terminal of the comparator 42-3 is (5 / 8) Vfs, Figure 5 As shown, the comparator 42-3b generates a third comparison result according to the analog sampling signal Vm and (5 / 8)Vfs. If the analog sampling signal Vm is greater than (5 / 8)Vfs, the logic value corresponding to the third comparison result generated by the comparator 42-3b is 1, and it is determined that the analog sampling signal is between (5 / 8)Vfs and (6 / 8)Vfs. In summary, the digital signal corresponding to the analog sampling signal Vm is (101); if the analog sampling signal Vm is less than (5 / 8)Vfs, the logic value corresponding to the third comparison result generated by the comparator 42-3b is 0, and it is determined that the analog sampling signal is between (4 / 8)Vfs and (5 / 8)Vfs. In summary, the digital signal corresponding to the analog sampling signal Vm is (100).

[0073] The comparator 42-3 generates a third comparison result according to the analog sampling signal Vm and the control signal output by the controller 43-2. ​​If the control signal transmitted from the controller 43-2 to the second input terminal of the comparator 42-3 is (3 / 8) Vfs, Figure 5As shown, the comparator 42-3c generates a third comparison result according to the analog sampling signal Vm and (3 / 8)Vfs. If the analog sampling signal Vm is greater than (3 / 8)Vfs, the logic value corresponding to the third comparison result generated by the comparator 42-3c is 1, and it is determined that the analog sampling signal is between (3 / 8)Vfs and (4 / 8)Vfs. In summary, the digital signal corresponding to the analog sampling signal Vm is (011); if the analog sampling signal Vm is less than (3 / 8)Vfs, the logic value corresponding to the third comparison result generated by the comparator 42-3c is 0, and it is determined that the analog sampling signal is between (2 / 8)Vfs and (3 / 8)Vfs. In summary, the digital signal corresponding to the analog sampling signal Vm is (010).

[0074] The comparator 42-3 generates a third comparison result according to the analog sampling signal Vm and the control signal output by the controller 43-2. ​​If the control signal transmitted from the controller 43-2 to the second input terminal of the comparator 42-3 is (1 / 8) Vfs, Figure 5 As shown, the comparator 42-3d generates a third comparison result according to the analog sampling signal Vm and (1 / 8)Vfs. If the analog sampling signal Vm is greater than (1 / 8)Vfs, the logic value corresponding to the third comparison result generated by the comparator 42-3d is 1, and it is determined that the analog sampling signal is between (1 / 8)Vfs and (2 / 8)Vfs. In summary, the digital signal corresponding to the analog sampling signal Vm is (001); if the analog sampling signal Vm is less than (1 / 8)Vfs, the logic value corresponding to the third comparison result generated by the comparator 42-3d is 0, and it is determined that the analog sampling signal is between (0 / 8)Vfs and (1 / 8)Vfs. In summary, the digital signal corresponding to the analog sampling signal Vm is (000).

[0075] Exemplarily, the embodiment of the present application also provides an analog-to-digital conversion method, referring to Figure 6 As shown, the analog-to-digital conversion method includes the following steps:

[0076] 601. Receive an analog signal, and sample the analog signal to generate an analog sampled signal.

[0077] Exemplarily, the received analog signal cannot be directly converted into a binary digital signal, and it is necessary to sample the analog signal to generate multiple analog sampling signals, and convert each of the multiple analog sampling signals into a binary digital signal.

[0078] 602. Generate a first comparison result according to the analog sampling signal and 1 / 2 of the full-scale voltage.

[0079] Among them, according to the first comparison result generated by the analog sampling signal Vm and 1 / 2 of the full-scale voltage Vfs, it can be determined whether the current analog sampling signal Vm is between 0 and 1 / 2 of the full-scale voltage Vfs, or between 1 / 2 of the full-scale voltage Vfs and the full-scale voltage Vfs. When the analog sampling signal Vm is greater than 1 / 2 of the full-scale voltage Vfs, the logic value corresponding to the generated first comparison result is 1, indicating that the current analog sampling signal Vm is between 1 / 2 of the full-scale voltage Vfs and the full-scale voltage Vfs; when the analog sampling signal Vm is less than 1 / 2 of the full-scale voltage Vfs, the logic value corresponding to the generated first comparison result is 0, indicating that the current analog sampling signal Vm is between 0 and 1 / 2 of the full-scale voltage Vfs. Then, the logic value corresponding to the first comparison result is the value of the first high-significant bit (that is, the most significant bit) of the digital signal corresponding to the analog sampling signal.

[0080] 603. Generate a control signal according to the first comparison result to the nth comparison result.

[0081] Specifically, x is determined according to the first comparison result to the n-1th comparison result, where x is a decimal number converted from a predetermined digital signal, the predetermined digital signal has n valid bits, and the most significant bit to the second least significant bit of the predetermined digital signal sequentially include the logic value corresponding to the first comparison result to the logic value corresponding to the n-1th comparison result, and the least significant bit of the predetermined digital signal is 1; when it is determined according to the nth comparison result that the analog sampling signal is greater than (x / 2^n) of the full-scale voltage, the generated control signal is ((2x+1) / 2^(n+1)) of the full-scale voltage; or, when it is determined according to the nth comparison result that the analog sampling signal is less than (x / 2^n) of the full-scale voltage, the generated control signal is ((2x-1) / 2^(n+1)) of the full-scale voltage.

[0082] From the above, it can be known that the control signal corresponds to a predetermined value of the full-scale voltage, wherein the nth comparison result is generated according to the analog sampling signal and (x / 2^n) of the full-scale voltage.

[0083] Moreover, x is a decimal number converted from a predetermined digital signal, the predetermined digital signal has n valid bits, the most significant bit to the second least significant bit of the predetermined digital signal sequentially include the logic value corresponding to the first comparison result to the logic value corresponding to the n-1th comparison result, and the least significant bit of the predetermined digital signal is 1. This means that x must be an odd number, and x is less than 2^n, which means that the value of x is 1, 3, 5...2^n-3, 2^n-1. Among them, there are a total of (2^n / 2) positive odd numbers between 0 and 2^n, and when the nth comparison result is generated according to the analog sampling signal Vm and the full-scale voltage (x / 2^n), there are 2 logical values ​​corresponding to the nth comparison result, which means that a total of (2^n / 2)*2, that is, 2^n situations can be determined, which means that the full-scale voltage is divided into 2^n equally spaced ranges, the first equally spaced range is 0 to (1 / 2^n) of the full-scale voltage, the second equally spaced range is (1 / 2^n) of the full-scale voltage to (2 / 2^n) of the full-scale voltage, the third equally spaced range is (2 / 2^n) of the full-scale voltage to (3 / 2^n) of the full-scale voltage... and so on, the interval between two adjacent equally spaced ranges is (1 / 2^n) of the full-scale voltage.

[0084] Among them, when x is 1, it is determined whether the analog sampling signal Vm is between the first equally spaced range of 0 and the full-scale voltage (1 / 2^n), or between the second equally spaced range of the full-scale voltage (1 / 2^n) and the full-scale voltage (2 / 2^n). When the analog sampling signal Vm is greater than (1 / 2^n) of the full-scale voltage, the logic value corresponding to the generated nth comparison result is 1, and it can be determined that the analog sampling signal Vm is between the second equally spaced range of the full-scale voltage (1 / 2^n) and the full-scale voltage (2 / 2^n); when the analog sampling signal Vm is less than (1 / 2^n) of the full-scale voltage, the logic value corresponding to the generated nth comparison result is 0, and it can be determined that the analog sampling signal Vm is between the first equally spaced range of 0 and the full-scale voltage (1 / 2^n).

[0085] When x is 3, it is determined whether the analog sampling signal Vm is between (2 / 2^n) and (3 / 2^n) of the full-scale voltage in the third equally spaced range, or between (3 / 2^n) and (4 / 2^n) of the full-scale voltage in the fourth equally spaced range. When the analog sampling signal Vm is greater than (3 / 2^n) of the full-scale voltage, the logic value corresponding to the generated nth comparison result is 1, and it can be determined that the analog sampling signal Vm is between (3 / 2^n) and (4 / 2^n) of the full-scale voltage in the fourth equally spaced range; when the analog sampling signal Vm is less than (3 / 2^n), the logic value corresponding to the generated nth comparison result is 0, and it can be determined that the analog sampling signal Vm is between (2 / 2^n) and (3 / 2^n) of the full-scale voltage in the third equally spaced range.

[0086] By analogy, the value of the nth most significant bit of the digital signal corresponding to the analog sampling signal Vm corresponding to the nth comparison result is generated.

[0087] Then, when it is determined according to the nth comparison result that the analog sampling signal is greater than (x / 2^n) of the full-scale voltage, it means that the current analog sampling signal is between (x / 2^n) of the full-scale voltage and ((x+1) / 2^n) of the full-scale voltage. Then, it is necessary to divide the range between (x / 2^n) of the full-scale voltage and ((x+1) / 2^n) of the full-scale voltage into two equally spaced ranges, and then determine which of the two equally spaced ranges the analog sampling signal Vm is in. The intermediate value between (x / 2^n) and ((x+1) / 2^n) is (((x / 2^n)+((x+1) / 2^n)) / 2), that is, ((2x+1) / 2^(n+1)), so the generated control signal is ((2x+1) / 2^(n+1)) of the full-scale voltage.

[0088] When it is determined that the analog sampling signal is less than (x / 2^n) of the full-scale voltage according to the nth comparison result, it means that the current analog sampling signal is between ((x-1) / 2^n) of the full-scale voltage and (x / 2^n) of the full-scale voltage. Then, it is necessary to divide the range between ((x-1) / 2^n) of the full-scale voltage and (x / 2^n) of the full-scale voltage into two equally spaced ranges, and then determine which of the two equally spaced ranges the analog sampling signal Vm is in. The middle value of ((x-1) / 2^n) and (x / 2^n) is ((((x-1) / 2^n)+(x / 2^n)) / 2), that is, ((2x-1) / 2^(n+1)), so the generated control signal is ((2x-1) / 2^(n+1)) of the full-scale voltage.

[0089] That is to say, the nth comparison result and the (n+1)th comparison result gradually approach the analog sampling signal by continuously dividing into two equal parts.

[0090] For example, when n is 3, 2^n is 8, and the logic value corresponding to the first comparison result is 1, the logic value corresponding to the second comparison result is 0, and the logic value corresponding to the third comparison result is 1, at this time, the predetermined digital signal is (101), and the decimal number converted from the predetermined digital signal (101) is 5, so it can be determined that the value of x is 5. Moreover, the logic value corresponding to the third comparison result is 1, which indicates that the analog sampling signal Vm is greater than (5 / 8) of the full-scale voltage, that is, the analog sampling signal Vm is between (5 / 8) of the full-scale voltage and (6 / 8) of the full-scale voltage. Therefore, it is necessary to divide the range from (5 / 8) of the full-scale voltage to (6 / 8) of the full-scale voltage into two equally spaced ranges, wherein the first equally spaced range is from (5 / 8) of the full-scale voltage to (13 / 16) of the full-scale voltage, and the second equally spaced range is from (13 / 16) of the full-scale voltage to (6 / 8) of the full-scale voltage, and then determine in which of the two equally spaced ranges the analog sampling signal Vm is located. Therefore, it is necessary to generate the n+1th comparison result according to the analog sampling signal Vm and the full-scale voltage (13 / 16), where n is 3, x is 5, ((2x-1) / 2^(n+1)) is ((2*5+1) / (2^(3+1))), which is (13 / 16). This means that the generated control signal is (13 / 16) of the full-scale voltage, and the fourth comparison result can be generated according to the analog sampling signal Vm and the control signal.

[0091] For example, when n is 4, 2^n is 16, and the logical value corresponding to the first comparison result is 0, the logical value corresponding to the second comparison result is 0, the logical value corresponding to the third comparison result is 1, and the logical value corresponding to the fourth comparison result is 0, at this time, the predetermined digital signal is (0011), and the decimal number converted from the predetermined digital signal (0011) is 3, so it can be determined that the value of x is 3. Moreover, the logic value corresponding to the fourth comparison result is 0, indicating that the analog sampling signal Vm is less than (3 / 16) of the full-scale voltage, that is, the analog sampling signal Vm is between (2 / 16) of the full-scale voltage and (3 / 16) of the full-scale voltage. Therefore, it is necessary to divide the range from (2 / 16) of the full-scale voltage to (3 / 16) of the full-scale voltage into two equally spaced ranges, wherein the first equally spaced range is from (2 / 16) of the full-scale voltage to (5 / 32) of the full-scale voltage, and the second equally spaced range is from (5 / 32) of the full-scale voltage to (3 / 16) of the full-scale voltage, and then determine which of the two equal parts the analog sampling signal Vm is in. Therefore, it is necessary to generate the n+1th comparison result based on the analog sampling signal Vm and (5 / 32) of the full-scale voltage, where n is 3, x is 5, ((2x-1) / 2^(n+1)) is ((2*3-1) / (2^(4+1))), which is (5 / 32), which means that the generated control signal is (5 / 32) of the full-scale voltage. The fifth comparison result can be generated based on the analog sampling signal and (5 / 32) of the full-scale voltage.

[0092] 604. Generate an (n+1)th comparison result according to the analog sampling signal and the control signal.

[0093] Specifically, when it is determined that the analog sampling signal is greater than the full-scale voltage ((2x+1) / 2^(n+1)) based on the analog sampling signal and the full-scale voltage, the n+1th comparison result is generated, and the logic value corresponding to the n+1th comparison result is 1; or, when it is determined that the analog sampling signal is less than the full-scale voltage ((2x+1) / 2^(n+1)) based on the analog sampling signal and the full-scale voltage ((2x+1) / 2^(n+1)), the n+1th comparison result is generated, and the logic value corresponding to the n+1th comparison result is 0.

[0094] When it is determined according to the analog sampling signal and the full-scale voltage ((2x-1) / 2^(n+1)) that the analog sampling signal is greater than the full-scale voltage ((2x-1) / 2^(n+1)), the n+1th comparison result is generated, and the logic value corresponding to the n+1th comparison result is 1; or, when it is determined according to the analog sampling signal and the full-scale voltage ((2x-1) / 2^(n+1)) that the analog sampling signal is less than the full-scale voltage ((2x-1) / 2^(n+1)), the nth comparison result is generated, and the logic value corresponding to the n+1th comparison result is 0.

[0095] The logic value corresponding to the (n+1)th comparison result is the value of the (n+1)th most significant bit of the digital signal corresponding to the analog sampling signal.

[0096] In the above embodiments, the description of each embodiment has different emphases. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0097] Although the present application has been described in conjunction with specific features and embodiments thereof, it is obvious that various modifications and combinations may be made thereto without departing from the spirit and scope of the present application. Accordingly, this specification and the drawings are merely exemplary illustrations of the present application as defined by the appended claims, and are deemed to have covered any and all modifications, variations, combinations or equivalents within the scope of the present application. Obviously, those skilled in the art may make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. An analog-to-digital converter, characterized in that: include: A sampling and holding circuit, an n+1-level comparator and an n-level controller, wherein n is a positive integer greater than or equal to 1; the sampling and holding circuit is connected to the first input terminal of each level of the comparator; The second input end of the comparator of the n+1th stage is connected to the output end of the controller of the nth stage; The input end of the controller of the nth stage is respectively connected to the output end of the comparator of the first stage to the output end of the comparator of the nth stage; The sample-and-hold circuit is configured to receive an analog signal, sample the analog signal to generate an analog sampling signal, and transmit the analog sampling signal to the first input terminal of each stage of the comparator; The comparator of the first stage is configured to generate a first comparison result according to the analog sampling signal and 1 / 2 of the full-scale voltage, transmit the first comparison result to the n-stage controller respectively, and output the logic value corresponding to the first comparison result as the value of the first high-significant bit of the digital signal corresponding to the analog sampling signal; The controller of the nth stage is configured to generate a control signal according to the first comparison result output by the comparator of the first stage to the nth comparison result output by the comparator of the nth stage; The comparator of the n+1th stage is configured to generate an n+1th comparison result according to the analog sampling signal and the control signal output by the controller of the nth stage, and output the logic value corresponding to the n+1th comparison result as the value of the n+1th high-significant bit of the digital signal corresponding to the analog sampling signal; Among them, the controller of the nth level is specifically configured to determine x according to the 1st comparison result output by the comparator of the 1st level to the n-1th comparison result output by the comparator of the n-1th level, wherein x is a decimal number converted from a predetermined digital signal, the predetermined digital signal has n valid bits, and the most significant bit to the second least significant bit of the predetermined digital signal sequentially include the logic value corresponding to the 1st comparison result to the logic value corresponding to the n-1th comparison result, and the least significant bit of the predetermined digital signal is 1; when it is determined according to the nth comparison result output by the comparator of the nth level that the analog sampling signal is greater than (x / 2^n) of the full-scale voltage, the control signal generated is ((2x+1) / 2^(n+1)) of the full-scale voltage; or, when it is determined according to the nth comparison result output by the comparator of the nth level that the analog sampling signal is less than (x / 2^n) of the full-scale voltage, the control signal generated is ((2x-1) / 2^(n+1)) of the full-scale voltage.

2. The analog-to-digital converter according to claim 1, characterized in that The comparator of the n+1th level is specifically configured to generate an n+1th comparison result when it is determined that the analog sampling signal is greater than ((2x+1) / 2^(n+1)) of the full-scale voltage according to the analog sampling signal and ((2x+1) / 2^(n+1)) of the full-scale voltage, and the logic value corresponding to the n+1th comparison result is 1; Alternatively, the comparator at the n+1th level is specifically configured to generate an n+1th comparison result when it is determined that the analog sampling signal is less than ((2x+1) / 2^(n+1)) of the full-scale voltage based on the analog sampling signal and ((2x+1) / 2^(n+1)) of the full-scale voltage, and the logic value corresponding to the n+1th comparison result is 0.

3. The analog-to-digital converter according to claim 1, characterized in that: The comparator of the n+1th level is specifically configured to generate an n+1th comparison result when it is determined that the analog sampling signal is greater than ((2x-1) / 2^(n+1)) of the full-scale voltage according to the analog sampling signal and ((2x-1) / 2^(n+1)) of the full-scale voltage, and the logic value corresponding to the n+1th comparison result is 1; Alternatively, the comparator at the n+1th level is specifically configured to generate an n+1th comparison result when it is determined that the analog sampling signal is less than ((2x-1) / 2^(n+1)) of the full-scale voltage based on the analog sampling signal and ((2x-1) / 2^(n+1)) of the full-scale voltage, and the logic value corresponding to the n+1th comparison result is 0.

4. The analog-to-digital converter according to claim 1, characterized in that: The second input terminal of the comparator of the first stage is connected to a bias circuit; The bias circuit is configured to receive the full-scale voltage and output (1 / 2) of the full-scale voltage to the second input terminal of the first-stage comparator.

5. The analog-to-digital converter according to claim 1, characterized in that: The first input terminal is a non-inverting input terminal of the comparator, and the second input terminal is an inverting input terminal of the comparator.

6. The analog-to-digital converter according to claim 1, characterized in that: The amplitude of the analog signal is between 0 and the full-scale voltage.

7. An analog-to-digital conversion method, characterized in that: include: receiving an analog signal, and sampling the analog signal to generate an analog sampling signal; Generate a first comparison result according to the analog sampling signal and 1 / 2 of the full-scale voltage, and output a logic value corresponding to the first comparison result as the value of the first most significant bit of the digital signal corresponding to the analog sampling signal; Generate a control signal according to the first comparison result to the nth comparison result; Generate an n+1th comparison result according to the analog sampling signal and the control signal, and output a logic value corresponding to the n+1th comparison result as a value of an n+1th high-significant bit of a digital signal corresponding to the analog sampling signal; The step of generating a control signal according to the first comparison result to the nth comparison result specifically includes: According to the first comparison result to the n-1th comparison result, x is determined, wherein x is a decimal number converted from a predetermined digital signal, the predetermined digital signal has n valid bits, and the most significant bit to the second least significant bit of the predetermined digital signal sequentially include the logic value corresponding to the first comparison result to the logic value corresponding to the n-1th comparison result, and the least significant bit of the predetermined digital signal is 1; when it is determined according to the nth comparison result that the analog sampling signal is greater than (x / 2^n) of the full-scale voltage, the generated control signal is ((2x+1) / 2^(n+1)) of the full-scale voltage; or, when it is determined according to the nth comparison result that the analog sampling signal is less than (x / 2^n) of the full-scale voltage, the generated control signal is ((2x-1) / 2^(n+1)) of the full-scale voltage.

8. The analog-to-digital conversion method according to claim 7, characterized in that: When it is determined that the analog sampling signal is greater than ((2x+1) / 2^(n+1)) of the full-scale voltage according to the analog sampling signal and ((2x+1) / 2^(n+1)) of the full-scale voltage, an n+1th comparison result is generated, and a logic value corresponding to the n+1th comparison result is 1; Alternatively, when it is determined that the analog sampling signal is less than ((2x+1) / 2^(n+1)) of the full-scale voltage based on the analog sampling signal and ((2x+1) / 2^(n+1)) of the full-scale voltage, an n+1th comparison result is generated, and the logic value corresponding to the n+1th comparison result is 0.

9. The analog-to-digital conversion method according to claim 7, characterized in that: When it is determined that the analog sampling signal is greater than ((2x-1) / 2^(n+1)) of the full-scale voltage according to the analog sampling signal and ((2x-1) / 2^(n+1)) of the full-scale voltage, an n+1th comparison result is generated, and a logic value corresponding to the n+1th comparison result is 1; Alternatively, when it is determined that the analog sampling signal is less than ((2x-1) / 2^(n+1)) of the full-scale voltage based on the analog sampling signal and ((2x-1) / 2^(n+1)) of the full-scale voltage, an n+1th comparison result is generated, and the logic value corresponding to the n+1th comparison result is 0.

10. The analog-to-digital conversion method according to claim 7, characterized in that: The amplitude of the analog signal is between 0 and the full-scale voltage.

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