A decoder hardware architecture for concatenated RS and BCH codes

Abstract

This application provides a decoder hardware architecture for concatenated RS and BCH codes, comprising a BCH decoding module, a first deinterleaver, an RS decoding module, and a multiplexer. The BCH decoding module and the RS decoding module employ the same target total parallelism and the same target clock frequency. This application offers the following advantages: the decoding hardware architecture enables the decoding of concatenated RS and BCH codes in ultra-high-speed communication networks of 800Gbps, 1600Gbps, and above, while simultaneously meeting the requirements of commercial applications for extremely high speed, small size, and low power consumption in decoders.

Description

Technical Field

[0001] This invention relates to the field of optical communication encoding and decoding technology, and in particular to a decoder hardware architecture for concatenated RS and BCH codes. Background Technology

[0002] Currently, optical communication networks are the world's primary communication carrier, boasting advantages such as high transmission speed, long transmission distance, strong anti-interference capabilities, and low loss. However, in long-distance communication, data transmission may suffer from loss or errors due to factors such as attenuation and crosstalk. Therefore, data is typically encoded before transmission to ensure the effectiveness and reliability of data transmission. Today, the amount of data generated and transmitted worldwide is rapidly increasing. To achieve ultra-high-speed optical communication, current research has focused on optical communication network bandwidths reaching 800 Gbps, and even 1600 Gbps.

[0003] In current ultra-high-speed optical communication systems, the concatenated coding scheme of RS (Reed-Solomon) codes and BCH (Bose–Chaudhuri–Hocquenghem) codes has attracted widespread attention. RS codes are a forward error-correcting channel code with a corresponding independent RS decoder, while BCH codes are linear block codes in a finite field with a corresponding independent BCH decoder. Typically, a demultiplexer (DEMUX) is used to demultiplex the received individual data, outputting the data in parallel to the RS encoder for RS encoding. Then, the data is interleaved by an interleaver and output to the BCH encoder for BCH encoding, thus achieving the concatenated coding of RS and BCH codes.

[0004] However, there is currently no corresponding decoder hardware architecture for the concatenated encoding scheme of RS code and BCH code to implement the decoding of concatenated RS code and BCH code. Summary of the Invention

[0005] To address the technical issue of the lack of a corresponding decoder hardware architecture for current RS and BCH code concatenated encoding schemes, this application provides a decoder hardware architecture for RS and BCH code concatenated codes, used to implement the decoding of RS and BCH code concatenated codes.

[0006] The first aspect of this application provides a decoder hardware architecture for concatenated RS and BCH codes, including a BCH decoding module, a first deinterleaver, an RS decoding module, and a multiplexer.

[0007] The BCH decoding module is used to receive data to be decoded and perform BCH decoding on the data to be decoded; the first deinterleaver is used to receive data output by the BCH decoding module and perform deinterleaving; the RS decoding module is used to receive data output by the first deinterleaver and perform RS decoding; the multiplexer is used to receive data output by the RS decoding module and combine it into a single output; the BCH decoding module and the RS decoding module adopt the same target total parallelism and the same target clock frequency.

[0008] Optionally, the BCH decoding module includes 32m or 80m BCH decoders, where m is a positive integer.

[0009] Optionally, the RS decoding module includes 2n RS decoders, where n is a positive integer.

[0010] Optionally, the target total parallelism is 1280, meaning 1280 bits are received per cycle; the target clock frequency is... Where a and b are positive integers, and a≥b; the clock period required for the BCH decoding module and the RS decoding module to receive one concatenated code is the target reception period, which is a positive integer greater than or equal to 9; the average decoding clock period for the corresponding data in a concatenated code calculated by the BCH decoding module and the RS decoding module is the target decoding period, which is a positive integer greater than or equal to 9.

[0011] Optionally, the target total parallelism is 1440, meaning 1440 bits are received per cycle; the target clock frequency is... The clock cycles required for each of the BCH decoding module and the RS decoding module to receive one concatenated code are defined as the target reception period, which is a positive integer greater than or equal to 8. The average decoding clock cycle calculated by the BCH decoding module and the RS decoding module for the corresponding data in one concatenated code is defined as the target decoding period, which is also a positive integer greater than or equal to 8.

[0012] Optionally, the target total parallelism is 1920, meaning 1920 bits are received per cycle; the target clock frequency is... Where a and b are positive integers, and a≥b; the clock period required for the BCH decoding module and the RS decoding module to receive one concatenated code is the target reception period, which is a positive integer greater than or equal to 6; the average decoding clock period for the corresponding data in a concatenated code calculated by the BCH decoding module and the RS decoding module is the target decoding period, which is a positive integer greater than or equal to 6.

[0013] Optionally, the BCH decoding module adopts a hard-decision decoding method.

[0014] Optionally, the BCH decoding module adopts a soft-decision decoding method.

[0015] Optionally, the upper limit of the number of bits inverted for each codeword in the soft-decision decoding formula can be set to 4, 5 or 6 to reduce hardware consumption.

[0016] Optionally, each of the RS decoders includes a second corrector computation unit, multiple key equation solving units, at least one Qian search and Forney operator computation unit, and a second random access memory; each key equation solving unit operates in ping-pong mode; the Qian search and Forney operator units interface with the output of the key equation solving units in an overlapping mode.

[0017] This application provides a decoder hardware architecture for concatenated RS and BCH codes, comprising a BCH decoding module, a first deinterleaver, an RS decoding module, and a multiplexer. The BCH decoding module and the RS decoding module employ the same target total parallelism and the same target clock frequency. This application offers the following advantages: the decoding hardware architecture enables the decoding of concatenated RS and BCH codes in ultra-high-speed communication networks of 800Gbps, 1600Gbps, and above, while simultaneously meeting the requirements of commercial applications for extremely high speed, small size, and low power consumption in decoders. Attached Figure Description

[0018] Figure 1 This is a schematic diagram showing the results of the concatenated coding scheme of RS(544,514) code and BCH(360,340) code in a 1600Gbps optical communication system.

[0019] Figure 2 This is a schematic diagram showing the result of the concatenated coding scheme of RS(544,514) code and BCH(144,136) code in a 1600Gbps optical communication system.

[0020] Figure 3 This is a schematic diagram of a decoder hardware architecture disclosed in an embodiment of this application;

[0021] Figure 4 This is a schematic diagram of an internal unit structure of a decoder hardware architecture disclosed in an embodiment of this application;

[0022] Figure 5 This is a partial schematic diagram of another internal unit structure of a decoder hardware architecture disclosed in an embodiment of this application;

[0023] Figure 6This is a partial schematic diagram of another internal unit structure of a decoder hardware architecture disclosed in an embodiment of this application;

[0024] Figure 7 This is a partial schematic diagram of another internal unit structure of a decoder hardware architecture disclosed in an embodiment of this application;

[0025] Figure 8 This is a partial schematic diagram of another internal unit structure of a decoder hardware architecture disclosed in an embodiment of this application;

[0026] Figure 9 This is a schematic diagram illustrating the application of a decoder hardware architecture disclosed in this application to the encoding and decoding process of a 1600Gbps optical communication system. Detailed Implementation

[0027] To facilitate the explanation of the technical solution of this application, a brief introduction will first be given to the concatenated encoding scheme of RS code and BCH code involved in this application.

[0028] Taking a 1600Gbps optical communication system as an example, this paper introduces two encoding schemes that concatenate RS codes and BCH codes.

[0029] The first method uses concatenated encoding of RS(544,514) and BCH(360,340) codes. The outer code of the concatenated code contains two complete RS(544,514) codewords. Specifically, each codeword has 544 code elements and 514 information code elements; one code element is one symbol (1 symbol = 10 bits). The inner code uses BCH(360,340), where each BCH codeword contains 340 bits of source information and 20 bits of parity. One concatenated code requires 32 BCH(360,340) codewords. The total length of the concatenated code is 360 bits * 32 = 11520 bits. The specific concatenation scheme is attached. Figure 1 As shown, Ra0 and Rb0 represent the first code elements of the first RS code and the second RS code, respectively, and so on. The 32 BCH codes are encoded in the column direction, with the parity bit placed after the data matrix, and the encoded data is output row by row.

[0030] The second method uses concatenated RS(544,514) and BCH(144,136) codes. The outer code is the same as in the first scheme, using two RS(544,514) codes. The inner code uses BCH(144,136) codes, where one BCH codeword contains 136 bits of source information and 8 bits of parity, requiring 80 BCH(144,136) codewords. The specific concatenation scheme is as follows... Figure 2As shown, Ra0 and Rb0 represent the first code elements of the first RS code and the second RS code, respectively, and so on. The 80 BCH codes are encoded in the column direction, with the parity bit placed after the data matrix, and the encoded data is output row by row.

[0031] In hardware implementation, the received single-channel data is first converted into two parallel channels using a multiplexer, and then output to two RS encoders in the same cycle. After interleaving, the data is output to 32 or 80 BCH encoders for BCH encoding, thus realizing the concatenated encoding of RS code and BCH code.

[0032] It should be noted that by simply halving the system clock frequency, the concatenated coding scheme for 1600Gbps optical communication systems described above can be transformed into a concatenated coding scheme for 800Gbps optical communication systems.

[0033] The aforementioned concatenated coding scheme does not yet have a corresponding decoder hardware architecture for decoding concatenated RS and BCH codes.

[0034] To address the technical issue that there is currently no corresponding decoder hardware architecture for concatenated RS and BCH codes, this application discloses a decoder hardware architecture for concatenated RS and BCH codes through the following embodiments, which can realize the decoding of concatenated RS and BCH codes; furthermore, it can meet the requirements of commercial applications for extremely high speed, small area and low power consumption of the decoder.

[0035] To facilitate the explanation of the technical solution of this application, some concepts involved in this application are first explained below. In the decoder hardware architecture described in this application, the clock period required for the BCH decoding module and the RS decoding module to receive corresponding data in a concatenated code is the target reception period, and the average decoding clock period calculated by the BCH decoding module and the RS decoding module in a concatenated code is the target decoding period.

[0036] One embodiment of this application discloses a decoder hardware architecture for a concatenated encoding scheme of RS code and BCH code in a 1600Gbps optical communication network, such as... Figure 3 As shown. The decoder hardware architecture includes a BCH decoding module, a first deinterleaver, an RS decoding module, and a multiplexer.

[0037] The BCH decoding module is used to receive data to be decoded and to perform BCH decoding on the data to be decoded.

[0038] Furthermore, when the decoder hardware architecture is applied to the decoding of concatenated RS(544, 514) codes and BCH(360, 340) codes, the BCH decoding module contains 32m BCH decoders, where m is a positive integer; furthermore, when the decoder hardware architecture is applied to the decoding of concatenated RS(544, 514) codes and BCH(144, 136) codes, the BCH decoding module contains 80m BCH decoders.

[0039] The first deinterleaver is used to receive data output by the BCH decoding module and perform deinterleaving.

[0040] The RS decoding module is used to receive the data output by the first deinterleaver and perform RS decoding.

[0041] Furthermore, the RS decoding module contains 2n decoders, where n is a positive integer.

[0042] The multiplexer is used to receive the data output by the RS decoding module and combine it into a single output.

[0043] The BCH decoding module and the RS decoding module employ the same target total parallelism and the same target clock frequency. The number of bits received per cycle in the decoder hardware architecture is defined as the target total parallelism.

[0044] The decoder hardware architecture disclosed in this embodiment, which is applied to concatenated RS and BCH codes, has the following beneficial effects: the decoder hardware architecture can realize the decoding of concatenated RS and BCH codes in ultra-high-speed communication networks of 800Gbps, 1600Gbps and above, and can simultaneously meet the requirements of extremely high speed, small area and low power consumption of decoders in commercial applications.

[0045] In the first embodiment of this example, the BCH decoding module of the decoder hardware architecture disclosed for the concatenated encoding scheme of RS(544, 514) code and BCH(360, 340) code includes 32 BCH decoders, and the RS decoding module includes 2 RS decoders.

[0046] The first embodiment discloses three sets of parallel computing frameworks that meet the decoding requirements of a 1600Gbps optical communication system.

[0047] See Figure 4 This is a schematic diagram of the internal unit structure of a decoder hardware architecture that implements the first set of parallel computing frameworks in the first implementation method.

[0048] In a 1600Gbps optical communication system, the rate at which received data, after transcoding, encoding, demodulation, and deinterleaving, is input to the decoder is: 1600Gbps × 66 / 64 × 257 / 264 × 288 / 257 = 1800Gbps. In the first set of parallel computing frameworks of the first embodiment, the target total parallelism of the BCH decoding module and the RS decoding module is selected as 1280, that is, 1280 bits are received per cycle.

[0049] At this time, the clock frequency of each BCH decoder is f′B CH =1800Gbps / 1280b=1.40625GHz, the data received by each BCH decoder in each cycle is 1280 / 32=40 bits, the cycle for receiving a complete concatenated codeword is 360 / 40=9, and the average decoding clock cycle for calculating the corresponding data in a concatenated code is also 9.

[0050] In practical applications, the clock frequency f′ of the BCH decoder BCH =1.40625GHz is an optimal case. In this embodiment, setting the target clock frequency of the BCH decoder to fBCH is sufficient to meet the decoding requirements. Specifically, Where a and b are positive integers, and a ≥ b. Similarly, 9 is the optimal reception period for receiving a complete concatenated codeword, and 9 is the optimal average decoding clock period for calculating the corresponding data in a concatenated code. In practical applications, combined with the clock frequency of the designed decoder, setting the target reception period of the BCH decoder to a positive integer greater than or equal to 9 and the target decoding period to a positive integer greater than or equal to 9 can satisfy the decoding requirements.

[0051] In the first set of parallel computing frameworks of the first embodiment, the operation of the decoder hardware architecture is described using the optimal clock frequency as the target clock frequency, the optimal number of reception cycles as the target reception cycle, and the optimal average decoding clock cycle as the target decoding cycle. Those skilled in the art can obtain decoder hardware architectures for other situations without inventive effort by referring to the decoder hardware architecture disclosed in this embodiment.

[0052] Each BCH decoder outputs 340 bits of data. For ease of hardware implementation, the BCH decoding result is output over 9 cycles. In the first cycle, each BCH decoder outputs 20 bits, and in the subsequent 8 cycles, each outputs 40 bits. The maximum throughput per cycle for each BCH decoder is TP1 = 1.40625 GHz * 40 bits = 56.25 Gbps. The maximum throughput per cycle for the BCH decoding module is TP1. BCH=TP1*32=1800Gbps.

[0053] In hardware implementation, the first deinterleaver is a bit selector. During the decoding process, the first deinterleaver receives the output of 32*340 bits from the BCH decoding module. Following the reverse of the encoding interleaving method, every 10 bits form a group of symbols needed to construct the RS decoder, resulting in 32*340 / 10 / 2 = 544 symbols.

[0054] The input of the RS decoder uses the same target clock frequency as the BCH decoder, i.e., f. RS =1.40625GHz. The target reception period and target decoding period of the RS decoder are set to be the same as those of the BCH decoding module, i.e., 9 periods. In the first period, each RS decoder inputs 32*20 / 2 = 320 bits, and in the following 8 periods, each RS decoder inputs 32*40 / 2 = 640 bits, i.e., each RS decoder inputs 5440 bits, or 544 symbols. After decoding by the RS decoder, each RS decoder outputs 514 symbols. The maximum throughput of each RS decoder per period is TP2 = 1.40625GHz * 640 bits = 900Gbps, and the maximum throughput of the RS decoding module per period is TP2 = 1.40625GHz * 640 bits = 900Gbps. BCH =TP1*2=1800Gbps.

[0055] The multiplexer receives 2*514 symbols output from the RS decoding module and combines them into 10280 bits of data for output. The throughput of the entire hardware architecture is TP = 10280 bits * 1.40625 GHz / 9 = 10280 bits * 1.40625 GHz / 9 = 1606.25 Gbps.

[0056] In summary, the concatenated encoding and decoding of RS(544,514) and BCH(360,340) codes are achieved. Furthermore, the throughput of the described hardware architecture meets the throughput requirements of a 1600Gbps optical communication system, and the throughput of the BCH decoding module is consistent with that of the RS decoding module, eliminating the need for complex designs such as gearboxes during data transmission. Therefore, the decoder hardware architecture has low complexity, meeting the requirements of extremely high speed, small area, and low power consumption in commercial applications.

[0057] Furthermore, within the first set of parallel computing frameworks, the internal unit structure of the decoder hardware architecture and the corresponding decoding process are as follows:

[0058] The 32 BCH decoders in the BCH decoding module have different internal unit architectures depending on the selected decoding method. The BCH decoder using hard-decision decoding includes a first corrector calculation unit and a direct equation solving unit. The BCH decoder using soft-decision decoding includes a test codeword generation unit, multiple first corrector calculation units, multiple direct equation solving units, a final codeword determination unit, and a first random access memory.

[0059] The BCH decoder employing a hard-decision decoding method receives 40 bits of data per cycle and updates the BCH corrector in real time through the first corrector calculation unit to obtain the coefficients of the polynomial equation at the error location.

[0060] The direct solution unit is used to directly solve for the error positions of the BCH code, outputs the error-corrected codeword, and ends the BCH decoding process.

[0061] Figure 4 The decoder hardware architecture shown is the internal unit structure of the BCH decoding module using the hard-decision decoding method.

[0062] The first corrector calculation unit and the direct equation solving unit can be used in conjunction with a soft-decision decoding algorithm. In this embodiment, the Chase II decoding algorithm is used to achieve the effect of soft decoding. That is, the BCH decoder can add a test codeword generation unit, add a final codeword judgment unit, add a first random access memory, and use multiple first corrector calculation units and multiple direct equation solving units to achieve the effect of soft decoding. Figure 5 It is the internal unit structure of a single BCH decoder when using the soft-decision decoding method.

[0063] When combined with the Chase II decoding algorithm, the upper limit of the number of bits flipped per codeword can be limited to reduce the complexity of the decoder hardware architecture.

[0064] Furthermore, in practical applications, the soft-decision decoding algorithm limits the upper limit of the number of bits flipped per codeword, typically to 4, 5, or 6, which reduces the complexity of the hardware architecture while ensuring decoding capability. In this embodiment, the upper limit of the number of bits flipped per codeword in the soft-decision algorithm is limited to 5.

[0065] Compared to the hard-decision decoding method, the soft-decision decoding method has a lower decoding error rate and stronger decoding capability, but its computational complexity is about 10 times higher, making it suitable for scenarios with high decoding capability requirements. The hard-decision decoding method has low computational complexity, fast computation speed, and small hardware implementation area, making it suitable for scenarios with high requirements for decoding speed and hardware area.

[0066] In this embodiment, each RS decoder includes a second corrector computation unit, at least two key equation solving units, at least one Qian search and Forney operator computation unit, and a second random access memory.

[0067] Each RS decoder receives 64 symbols per target reception cycle, with the first 32 symbols of the first target reception cycle padded with zeros to ensure that the RS decoder receives the same number of symbols in each target reception cycle.

[0068] The second corrector calculation unit of each RS decoder performs real-time calculation of 30 RS correctors for each RS decoder based on the position of the error bit in the BCH decoder, and updates the RS correctors in real time to obtain the coefficients of the error position polynomial equation and the error numerical polynomial equation.

[0069] The key equation solving units operate in a ping-pong mode; depending on the number of key equation solving units selected, each key equation solving unit completes all calculations within a minimum of 18 cycles. Each key equation solving unit is used to calculate the error location polynomial equation and the error numerical polynomial equation.

[0070] Ping-pong mode is a processing technique frequently used in data flow control. Its key feature is the seamless, uninterrupted delivery of buffered data to the data processing unit through the rhythmic switching between input selection and output units. Viewing ping-pong mode as a single module, its input and output data flows are continuous and uninterrupted. Therefore, ping-pong mode is ideal for pipelined processing of input data, achieving seamless buffering and processing. Furthermore, ping-pong mode can save buffer space, enabling seamless data buffering with a smaller buffer size, eliminating the need for large-scale data buffering at once.

[0071] In this embodiment, the critical equation solving unit uses an improved iBM (inversionless Berlekamp-Massey) iterative algorithm to solve the critical equation. The BM iterative algorithm, proposed by Berlekamp-Massey in 1966, has been continuously improved and has become a mature algorithm for solving critical equations.

[0072] It should be noted that if those skilled in the art implement the technical solution of this invention, and the key equation solving unit uses the ordinary iBM algorithm, four key equation solving units need to work in ping-pong mode to meet the decoding speed requirements.

[0073] The Qian search and Forney operator calculation units are used to correct codewords based on the error position polynomial and error numerical polynomial obtained from the key equation solving unit. The corrected codeword is then output, and the RS decoding process ends.

[0074] When one of the aforementioned Qian search and Forney operator computation units is deployed, the Qian search and Forney operator computation unit completes all calculations within 9 cycles and alternately interfaces with the outputs of the two aforementioned key equation solving units. For example... Figure 4 As shown.

[0075] When two of the aforementioned money search and Forney operator computation units are arranged, as follows: Figure 6 As shown, the two Qian search and Forney operator computation units operate in an overlapping mode, with each Qian search and Forney operator computation unit completing all calculations within 18 cycles and interfacing with the output of a fixed key equation solving unit.

[0076] Among them, the overlapping mode is a parallel processing structure when the computing unit processes data. It controls multiple identical computing units through time-division multiplexing, which can achieve the effect of frame interleaving, thereby improving the circuit computing efficiency and saving computing resources.

[0077] Both of the above-described methods of connecting the Qian search and Forney operator computation units with the key equation solving unit can meet the decoding speed requirements.

[0078] The second random access memory is used by the RS decoder to store intermediate data during the calculation process.

[0079] In the second set of parallel computing frameworks in this embodiment, the target total parallelism of the BCH decoding module and the RS decoding module is selected as 1440, that is, 1440 bits are received per cycle.

[0080] At this time, the clock frequency of the BCH decoder is f′ BCH=1800Gbps / 1440b=1.25GHz. Each BCH decoder receives 1440 / 32=45 bits of data per cycle. The cycle for receiving a complete concatenated codeword is 360 / 45=8. The average decoding clock cycle for the corresponding data in a concatenated code is calculated to be 8.

[0081] In practical applications, the clock frequency f′ of the BCH decoder BCH =1.25GHz is an optimal case. In this embodiment, setting the target clock frequency of the BCH decoder to fBCH is sufficient to meet the decoding requirements. Specifically, Where a and b are positive integers, and a≥b. Similarly, 8 is the optimal reception period for receiving a complete concatenated codeword, and 8 is also the optimal average decoding clock period for calculating the corresponding data in a concatenated code. In practical applications, setting the target reception period of the BCH decoder to a positive integer greater than or equal to 8 and the target decoding period to a positive integer greater than or equal to 9 can satisfy the decoding requirements.

[0082] In the second set of parallel computing frameworks of the first embodiment, the operation of the decoder hardware architecture is described using the optimal clock frequency as the target clock frequency, the optimal number of reception cycles as the target reception cycle, and the optimal average decoding clock cycle as the target decoding cycle. Those skilled in the art can obtain decoder hardware architectures for other situations without inventive effort by referring to the decoder hardware architecture disclosed in this embodiment.

[0083] Each BCH decoder outputs 340 bits of data. For ease of hardware implementation, the BCH decoding result is output over 8 cycles. The first cycle outputs 25 bits per BCH decoder, and the subsequent 7 cycles each output 45 bits. The maximum throughput of each BCH decoder per cycle is TP1 = 1.25 GHz * 45 bits = 56.25 Gbps. The maximum throughput of the BCH decoding module per cycle is TP1. BCH =TP1*32=1800Gbps.

[0084] The function implemented by the first deinterleaver is consistent with the setting of the first deinterleaver in the first set of parallel computing frameworks.

[0085] The input of the RS decoder uses the same target clock frequency as the BCH decoder, i.e., f. RS=1.25GHz. In the first target reception cycle, the input to each RS decoder is 25 * 32 / 2 = 400 bits. In the subsequent seven target reception cycles, the input is 32 * 45 / 2 = 720 bits, meaning each RS decoder has an input of 5400 bits, or 544 symbols. After decoding by the RS decoder, each RS decoder outputs 514 symbols. The maximum throughput of each RS decoder per cycle is TP2 = 1.25GHz * 720 bits = 900Gbps, and the maximum throughput of the RS decoding module per cycle is TPBCH = TP1 * 2 = 1800Gbps.

[0086] The multiplexer receives 2*514 symbols output from the RS decoding module and combines them into 10280 bits of data for output. The throughput of the entire hardware architecture per cycle is TP = 10280 bits * 1.25 GHz / 8 = 10280 bits * 1.25 GHz / 8 = 1606.25 Gbps.

[0087] In summary, the decoding of the concatenated encoding of RS(544, 514) code and BCH(360, 340) code is achieved. Furthermore, this achieves the same beneficial effects as described in the first set of parallel computing frameworks in the first embodiment.

[0088] Under the second set of parallel computing frameworks, the decoding process of the decoder hardware architecture is as follows:

[0089] The BCH decoding module comprises 32 BCH decoders, each with a different internal unit architecture depending on the selected decoding method. Each of the 32 BCH decoders in the BCH decoding module receives 45 bits of data per cycle; the workflow of each BCH decoder is the same as that of the BCH decoders in the first set of parallel computing architectures.

[0090] Each RS decoder includes a second calibrator computation unit, at least two key equation solving units, at least one Qian search and Forney operator computation unit, and a second random access memory; each RS decoder in the RS module receives 72 symbols per target reception cycle, wherein the first 32 symbols of the first target reception cycle are padded with zeros to ensure that the same number of symbols are received in each target reception cycle.

[0091] The function implemented by the second calibrator computing unit is the same as that implemented by the second calibrator computing unit under the first set of parallel computing frameworks.

[0092] The key equation solving units operate in a ping-pong mode, and each key equation solving unit completes all calculations within at least 16 cycles, depending on the number of key equation solving units selected. The solving algorithm selected by the key equation solving units is the same as that in the first set of parallel computing frameworks.

[0093] The Qian search and Furni operator calculation unit is used to correct the codeword based on the error position polynomial and error numerical polynomial obtained by the key equation solving unit; the corrected codeword is output and the RS decoding process ends.

[0094] When one of the Qian search and Forney operator computation units is deployed, the Qian search and Forney operator computation unit completes all calculations within 8 cycles and alternately interfaces with the outputs of the two key equation solving units.

[0095] When arranging the two money search and Forney operator computation units, as follows: Figure 6 As shown, the two Qian search and Forni operator computation units operate in an overlapping mode, with each Qian search and Forni operator computation unit completing all calculations within 16 cycles and interfacing with the output of a fixed key equation solving unit.

[0096] Both of the above-described methods of connecting the Qian search and Forney operator computation units with the key equation solving unit can meet the decoding speed requirements.

[0097] The second random access memory is used by the RS decoder to store intermediate data during the calculation process.

[0098] In the third set of parallel computing frameworks in this embodiment, the target total parallelism of the BCH decoding module and the RS decoding module is selected as 1920, that is, 1920 bits are received per cycle.

[0099] At this time, the target clock frequency of each BCH decoder is f′. BCH =1800Gbps / 1920b=0.9375GHz, the data received by each BCH decoder in each cycle is 1920 / 32=60 bits, the cycle for receiving a complete concatenated codeword is 360 / 60=6, and the average decoding clock cycle for the corresponding data in a concatenated code is 6.

[0100] In practical applications, the clock frequency f′ of the BCH decoder BCH =0.9375GHz is an optimal case. In this embodiment, the target clock frequency of the BCH decoder is set to f. BCH This will satisfy the decoding requirements. Specifically, Where a and b are positive integers, and a≥b. Similarly, 6 is the optimal reception period for receiving a complete concatenated codeword, and 6 is also the optimal average decoding clock period for calculating the corresponding data in a concatenated codeword. In practical applications, setting the target reception period of the BCH decoder to a positive integer greater than or equal to 6 and the target decoding period to a positive integer greater than or equal to 6 can satisfy the decoding requirements.

[0101] In the third set of parallel computing frameworks of the first embodiment, the operation of the decoder hardware architecture is described using the optimal clock frequency as the target clock frequency, the optimal number of reception cycles as the target reception cycle, and the optimal average decoding clock cycle as the target decoding cycle. Those skilled in the art can obtain decoder hardware architectures for other situations without inventive effort by referring to the decoder hardware architecture disclosed in this embodiment.

[0102] Each BCH decoder outputs 340 bits of data. For ease of hardware implementation, the BCH decoding result is output over 6 cycles. In the first cycle, each BCH decoder outputs 40 bits, and in the subsequent 5 cycles, each outputs 60 bits. The maximum throughput per cycle for each BCH decoder is TP1 = 0.9375 GHz * 60 bits = 56.25 Gbps. The maximum throughput per cycle for the BCH decoding module is TP1. BCH =TP1*32=1800Gbps.

[0103] At this time, the function implemented by the first deinterleaver is consistent with the setting of the first deinterleaver in the first set of parallel computing frameworks.

[0104] The input of the RS decoder uses the same target clock frequency as the BCH decoder, i.e., fR. S =0.9375GHz. The target number of cycles for the RS decoder is set to be the same as the target number of cycles for the BCH decoding module, i.e., 6 cycles. In the first cycle, each RS decoder inputs 32*40 / 2 = 640 bits. In the subsequent 5 cycles, each RS decoder inputs 32*40 / 2 = 960 bits, meaning each RS decoder inputs 5440 bits, or 544 symbols. After decoding, each RS decoder outputs 514 symbols. The maximum throughput per cycle for each RS decoder is TP2 = 0.9375GHz * 960 bits = 900Gbps, and the maximum throughput per cycle for the RS decoding module is TPBCH = TP1 * 2 = 1800Gbps.

[0105] The multiplexer receives 2*514 symbols output from the RS decoding module and combines them into 10280 bits of data for output. The throughput of the entire hardware architecture per cycle is TP = 10280 bits * 0.9375 GHz / 6 = 10280 bits * 0.9375 GHz / 6 = 1606.25 Gbps.

[0106] In summary, the decoding of the concatenated encoding of RS(544, 514) code and BCH(360, 340) code is achieved. Furthermore, this achieves the same beneficial effects as described in the first set of parallel computing frameworks in the first embodiment.

[0107] Furthermore, the throughput of the BCH decoding module per cycle is TP. BCH =0.9375GHz*60bits*32=1800Gbps, and the throughput of the RS decoding module per cycle is TPRs=0.9375GHz*960bits*2=1800Gbps; consistent with the beneficial effects described in the first set of parallel computing frameworks in the first embodiment.

[0108] Under the third set of parallel computing frameworks, the decoding process of the decoder hardware architecture is as follows:

[0109] The BCH decoding module comprises 32 BCH decoders, each with a different internal unit architecture depending on the selected decoding method. Each of the 32 BCH decoders in the BCH decoding module receives 60 bits of data per cycle; the workflow of each BCH decoder is the same as that of the BCH decoders in the first set of parallel computing architectures.

[0110] Each of the RS decoders includes a second corrector computation unit, at least three key equation solving units, at least one Qian search and Forney operator computation unit, and a second random access memory.

[0111] Each RS decoder receives 96 symbols per cycle, with the first 32 symbols of the first cycle padded with zeros to ensure that the RS decoder receives the same number of symbols in each cycle.

[0112] The calculation process of the second corrector calculation unit of each RS decoder is the same as that of the second corrector calculation unit in the first set of parallel computing frameworks.

[0113] The key equation solving units operate in a ping-pong mode, and each key equation completes all calculations within at least 18 cycles, depending on the number of key equation solving units selected.

[0114] It should be noted that when those skilled in the art implement the third set of parallel computing frameworks of the first embodiment of the present invention, if the key equation solving unit uses the ordinary iBM algorithm, it is necessary to use 5 key equation solving units to work in ping-pong mode to meet the decoding speed requirements.

[0115] The Qian search and Forney operator calculation units are used to correct codewords based on the error position polynomial and error numerical polynomial obtained from the key equation solving unit. The corrected codeword is then output, and the RS decoding process ends.

[0116] like Figure 7 As shown, when one of the Qian search and Forney operator computation units is deployed, the Qian search and Forney operator computation unit completes all calculations within 6 cycles and alternately interfaces with the outputs of the 3 key equation solving units.

[0117] like Figure 8 As shown, when three of the aforementioned Qian search and Forni operator computation units are arranged, the three Qian search and Forni operator computation units operate in an overlapping mode. Each of the aforementioned Qian search and Forni operator computation units completes all calculations within 18 cycles and interfaces with the output of a fixed key equation solving unit.

[0118] Both of the above-described methods of connecting the Qian search and Forney operator computation units with the key equation solving unit can meet the decoding speed requirements.

[0119] The second random access memory is used by the RS decoder to store intermediate data during the calculation process.

[0120] The second embodiment of this invention discloses a decoder hardware architecture for a concatenated encoding scheme of RS(544, 514) code and BCH(144, 136) code. The BCH decoding module includes 80 BCH decoders, and the RS decoding module includes 2 RS decoders.

[0121] In the second embodiment of this example, three parallel computing frameworks are disclosed for the concatenated coding scheme of RS(544, 514) code and BCH(144, 136) code, which meet the decoding requirements of the decoder in a 1600Gbps optical communication system.

[0122] In the first set of parallel computing frameworks of the second implementation, the target total parallelism of the BCH decoding module and the RS decoding module is selected as 1280.

[0123] At this time, the target clock frequency of each BCH decoder is f′. BCH=1.40625GHz, each BCH decoder receives 1280 / 80 = 16 bits of data per cycle, and the number of cycles for receiving a complete concatenated codeword is 144 / 16 = 9.

[0124] Referring to the first set of parallel computing frameworks in the first embodiment, the target period frequency of the BCH decoder Where a and b are positive integers, and a≥b; the target reception period of the BCH decoder is set to a positive integer greater than or equal to 9, and the target decoding period is set to a positive integer greater than or equal to 9 to meet the decoding requirements.

[0125] In the first set of parallel computing frameworks of the second embodiment, the operation of the decoder hardware architecture is described using the optimal clock frequency as the target clock frequency, the optimal number of reception cycles as the target reception cycle, and the optimal average decoding clock cycle as the target decoding cycle. Those skilled in the art can obtain decoder hardware architectures for other situations without inventive effort by referring to the decoder hardware architecture disclosed in this embodiment.

[0126] Each BCH decoder outputs 136 bits of data. For ease of hardware implementation, the BCH decoding result is output over 9 cycles. In the first cycle, each BCH decoder outputs 8 bits, and the subsequent 8 cycles each output 16 bits. The maximum throughput per cycle for each BCH decoder is TP1 = 1.40625 GHz * 16 bits = 22.5 Gbps. The maximum throughput per cycle for the BCH decoding module is TP1. BCH =TP1*80=1800Gbps.

[0127] In hardware implementation, the first deinterleaver is a bit selector. During the decoding process in this embodiment, the first deinterleaver receives 80*136 bits of output from the BCH decoding module. Following the reverse of the encoding interleaving method, every 10 bits form a group of symbols needed to construct the RS decoder, resulting in 80*136 / 10 / 2 = 544 symbols.

[0128] The input of the RS decoder uses the same target clock frequency as the BCH decoder, i.e., f. Rs=1.40625GHz. The target reception period and target decoding period of the RS decoder are set to be the same as those of the BCH decoding module, i.e., 9 periods. In the first period, each RS decoder inputs 80*8 / 2 = 320 bits, and in the following 8 periods, each RS decoder inputs 80*16 / 2 = 640 bits, i.e., each RS decoder inputs 5440 bits, or 544 symbols. After decoding by the RS decoder, each RS decoder outputs 514 symbols. The maximum throughput of each RS decoder per period is TP2 = 1.40625GHz * 640 bits = 900Gbps, and the maximum throughput of the RS decoding module per period is TPBCH = TP1 * 2 = 1800Gbps.

[0129] The multiplexer receives 2*514 symbols output from the RS decoding module and combines them into 10280 bits of data for output. The throughput of the entire hardware architecture per cycle is TP = 10280 bits * 1.40625 GHz / 9 = 10280 bits * 1.40625 GHz / 9 = 1606.25 Gbps.

[0130] In summary, the decoding of concatenated encoding of RS(544, 514) code and BCH(144, 136) code is achieved. Furthermore, this achieves the same beneficial effects as described in the first set of parallel computing frameworks in the first embodiment.

[0131] Based on the first set of parallel computing frameworks in the first embodiment disclosed in this application, the specific decoding process of the first set of parallel computing frameworks in the second embodiment can be easily derived, and will not be repeated here. It is particularly important to note that in the second embodiment, because the number of bits received per target cycle by each BCH decoder is relatively less than that in the first embodiment, when the direct equation solving unit and the Qian search unit in the BCH decoder combine a soft decision algorithm during the calculation process, limiting the upper limit of the number of bits inverted per codeword to 4 can balance decoding capability and hardware architecture complexity.

[0132] In the second set of parallel computing frameworks in the second implementation, the target total parallelism of the BCH decoding module and the RS decoding module is selected as 1440.

[0133] At this time, the target clock frequency of each BCH decoder is f′. BCH =1.25GHz, each BCH decoder receives 1440 / 80 = 18 bits of data per cycle, and the target number of cycles for receiving a complete concatenated codeword is 144 / 18 = 8.

[0134] Referring to the second set of parallel computing frameworks in the first embodiment, the target period frequency of the BCH decoder is... Where a and b are positive integers, and a≥b; the target number of the BCH decoder can be set to a positive integer greater than or equal to 8 to meet the decoding requirements.

[0135] In the second set of parallel computing frameworks of the second embodiment, the operation of the decoder hardware architecture is described using the optimal clock frequency as the target clock frequency, the optimal number of reception cycles as the target reception cycle, and the optimal average decoding clock cycle as the target decoding cycle. Those skilled in the art can obtain decoder hardware architectures for other situations without inventive effort by referring to the decoder hardware architecture disclosed in this embodiment.

[0136] Each BCH decoder outputs 136 bits of data. For ease of hardware implementation, the BCH decoding result is output over 8 cycles. In the first cycle, each BCH decoder outputs 10 bits, and in the subsequent 7 cycles, each outputs 18 bits. The maximum throughput of each BCH decoder per cycle is TP1 = 1.25 GHz * 18 bits = 22.5 Gbps. The maximum throughput of the BCH decoding module per cycle is TP1. BCH =TP1*80=1800Gbps.

[0137] The function implemented by the first deinterleaver is consistent with the setting of the first deinterleaver in the first set of parallel computing frameworks.

[0138] The input of the RS decoder uses the same target clock frequency as the BCH decoder, i.e., f. Rs =1.25GHz. The target reception period and target decoding period of the RS decoder are set to be the same as those of the BCH decoding module, i.e., 8 periods. In the first period, each RS decoder inputs 80*10 / 2 = 400 bits, and in the following 7 periods, each RS decoder inputs 80*18 / 2 = 640 bits, i.e., each RS decoder inputs 5440 bits, or 544 symbols. After decoding by the RS decoder, each RS decoder outputs 514 symbols. The maximum throughput of each RS decoder per period is TP2 = 1.25GHz * 720 bits = 900Gbps, and the maximum throughput of the RS decoding module per period is TP2 = 1.25GHz * 720 bits = 900Gbps. BCH =TP1*2=1800Gbps.

[0139] The multiplexer receives 2*514 symbols output from the RS decoding module and combines them into 10280 bits of data for output. The throughput of the entire hardware architecture per cycle is TP = 10280 bits * 1.25 GHz / 8 = 10280 bits * 1.25 GHz / 8 = 1606.25 Gbps.

[0140] In summary, the decoding of concatenated encoding of RS(544, 514) code and BCH(144, 136) code is achieved. Furthermore, this achieves the same beneficial effects as described in the first set of parallel computing frameworks in the first embodiment.

[0141] Based on the second set of parallel computing frameworks in the first embodiment disclosed in this application, the specific decoding process of the second set of parallel computing frameworks in the second embodiment can be easily derived, and will not be repeated here.

[0142] In the third set of parallel computing frameworks in the second embodiment, the target total parallelism of the BCH decoding module and the RS decoding module is selected as 1920.

[0143] At this time, the target clock frequency of each BCH decoder is f′. BCH =0.9375GHz, each BCH decoder receives 1920 / 80 = 24 bits of data per cycle, and the target number of cycles to receive a complete concatenated codeword is 144 / 25 = 6.

[0144] Referring to the third set of parallel computing frameworks in the first embodiment, the target period frequency of the BCH decoder Where a and b are positive integers, and a≥b; the target number of cycles of the BCH decoder is set to a positive integer greater than or equal to 6.

[0145] In the third set of parallel computing frameworks of the second embodiment, the operation of the decoder hardware architecture is described using the optimal clock frequency as the target clock frequency, the optimal number of reception cycles as the target reception cycle, and the optimal average decoding clock cycle as the target decoding cycle. Those skilled in the art can obtain decoder hardware architectures for other situations without inventive effort by referring to the decoder hardware architecture disclosed in this embodiment.

[0146] Each BCH decoder outputs 136 bits of data. For ease of hardware implementation, the BCH decoding result is output over 6 cycles. In the first cycle, each BCH decoder outputs 16 bits, and in the subsequent 5 cycles, each outputs 24 bits. The maximum throughput of each BCH decoder per cycle is TP1 = 0.9375 GHz * 24 bits = 22.5 Gbps. The maximum throughput of the BCH decoding module per cycle is TP1. BCH =TP1*80=1800Gbps.

[0147] The function implemented by the first deinterleaver is consistent with the setting of the first deinterleaver in the first set of parallel computing frameworks.

[0148] The input of the RS decoder uses the same target clock frequency as the BCH decoder, i.e., f. RS =0.9375GHz. The target reception period and target decoding period of the RS decoder are set to be the same as those of the BCH decoding module, i.e., 6 periods. In the first period, each RS decoder inputs 80*16 / 2 = 640 bits, and in the following 5 periods, each RS decoder inputs 80*24 / 2 = 960 bits, i.e., each RS decoder inputs 5440 bits, or 544 symbols. After decoding by the RS decoder, each RS decoder outputs 514 symbols. The maximum throughput of each RS decoder per period is TP2 = 0.9375GHz * 960 bits = 900Gbps, and the maximum throughput of the RS decoding module per period is TP2 = 0.9375GHz * 960 bits = 900Gbps. BCH =TP1*2=1800Gbps.

[0149] The multiplexer receives 2*514 symbols output from the RS decoding module and combines them into 10280 bits of data for output. The throughput of the entire hardware architecture per cycle is TP = 10280 bits * 0.9375 GHz / 6 = 10280 bits * 0.9375 GHz / 6 = 1606.25 Gbps.

[0150] In summary, the decoding of the concatenated encoding of RS(544,514) code and BCH(144,136) code is achieved. Furthermore, this achieves the same beneficial effects as described in the first set of parallel computing frameworks in the first embodiment.

[0151] Based on the third set of parallel computing frameworks in the first embodiment disclosed in this application, the specific decoding process of the third set of parallel computing frameworks in the second embodiment can be easily derived, and will not be repeated here.

[0152] Both the first and second embodiments are decoder hardware architectures for 1600Gbps optical communication systems. It should be noted that a decoder hardware architecture for 800Gbps optical communication systems can be implemented simply by halving the system clock frequency. Those skilled in the art can easily implement a decoder hardware architecture for 800Gbps optical communication systems based on the two embodiments of this example, and will not be elaborated further here.

[0153] Figure 9 The diagram illustrates the application of the decoder hardware architecture described in this application to the encoding and decoding process of a 1600Gbps optical communication system, taking the concatenated encoding and decoding of RS(544,514) code and BCH(360,340) code as an example.

[0154] See Figure 9 Taking a parallel computing framework with a parallelism of 1280 as an example, in a 1600Gbps optical communication system, the lane port (Ethernet data exchange standard packet, the data size transmitted by one lane port is 66 bits) is still used. First, 2*80*66=10560 bits of data enters the 256b / 257b transcoder and is converted to 10280 bits. The 256b / 257b transcoder has an input throughput of 1650Gbps and an output throughput of 1606.25Gbps.

[0155] The data then enters the encoder, where it first passes through a demultiplexer to convert the 10280 bits of data into two parallel 5140-bit numbers, which are output to two RS encoders in the same cycle. These two RS encoders encode the data into 2*544 symbols, which are then interleaved into 32*340 bits by a first interleaver. Finally, the data is encoded into 32*360 bits by 32 BCH encoders, completing the concatenated encoding. Each RS encoder and BCH encoder completes one concatenated code encoding within 9 cycles. Each RS encoder has a parallel output of 640 bits per cycle, a clock frequency of 1.40625 GHz, and a throughput of 900 Gbps. Each BCH encoder has a parallel output of 40 bits per cycle, a clock frequency of 1.40625 GHz, and a throughput of 56.25 Gbps.

[0156] The data then passes through a second interleaver and modulator to become data suitable for transmission. After being transmitted through the channel, it passes through a demodulator and a second deinterleaver to deinterleave the data into 32*360 bits and transmit it to the receiving end. The channel throughput during transmission is 1800Gbps.

[0157] At the receiving end, the data is first processed by a decision before being output to the decoder.

[0158] In the decoder, the data is first decoded into 32*340 bits by 32 BCH decoders, then deinterleaved into 2*544 symbols by the first deinterleaver, then decoded into 2*514 symbols by two RS decoders, and finally combined into 10280 bits by a multiplexer to complete the decoding. Each RS decoder and BCH decoder completes the decoding of one concatenated code within 9 cycles. Each BCH decoder operates at a parallel capacity of 40 bits per cycle, with a clock frequency of 1.40625 GHz and a throughput of 56.25 Gbps. Each RS decoder operates at a parallel capacity of 640 bits per cycle, with a clock frequency of 1.40625 GHz and a throughput of 900 Gbps.

[0159] The decoded data is passed through a 256b / 257b reverse transcoder to obtain the final decoded data bits; wherein the input throughput of the 256b / 257b reverse transcoder is 1606.25Gbps and the output throughput is 1650Gbps.

[0160] Those skilled in the art can Figure 9 A schematic diagram of the encoding and decoding process of the hardware architecture with parallelism of 1440 and 1920 applied to a 1600 Gbps optical communication system can be easily obtained, and will not be described in detail here.

[0161] It should be noted that by simply halving the clock frequency of the decoder hardware architecture, a schematic diagram of the encoding and decoding process of applying the decoder hardware architecture described in this application to an 800Gbps optical communication system can be obtained, which will not be elaborated here.

[0162] As can be seen from the above technical solutions, the decoder hardware architecture for concatenated RS and BCH codes provided in this application includes the BCH decoding module, the first deinterleaver, the RS decoding module, and the multiplexer. The BCH decoding module receives data to be decoded and performs BCH decoding on the data. The first deinterleaver receives data output from the BCH decoding module and performs deinterleaving. The RS decoding module receives data output from the first deinterleaver and performs RS decoding. The multiplexer receives data output from the RS decoding module and combines it into a single data output. The BCH decoding module and the RS decoding module use the same target total parallelism and the same target clock frequency. Based on the decoder hardware architecture for concatenated RS and BCH codes provided in this application, the decoding of concatenated RS and BCH codes in ultra-high-speed communication networks of 800Gbps, 1600Gbps, and above can be realized, and it can simultaneously meet the requirements of extremely high speed, small area, and low power consumption for decoders in commercial applications.

[0163] For the same or similar parts among the various embodiments in this specification, please refer to each other.

Claims

1. A decoder hardware architecture for concatenated RS and BCH codes, characterized in that, It includes a BCH decoding module, a first deinterleaver, an RS decoding module, and a multiplexer; The BCH decoding module is used to receive data to be decoded and to perform BCH decoding on the data to be decoded. The first deinterleaver is used to receive data output by the BCH decoding module and perform deinterleaving; The RS decoding module is used to receive the data output by the first deinterleaver and perform RS decoding. The multiplexer is used to receive the data output by the RS decoding module and combine it into a single output; The BCH decoding module and the RS decoding module use the same target total parallelism and the same target clock frequency for decoding; The target total parallelism is 1280, meaning 1280 bits are received per cycle; the target clock frequency is... Where a and b are positive integers, and a ≥ b; the clock period required for each of the BCH decoding module and the RS decoding module to receive corresponding data in a concatenated code is the target reception period, which is a positive integer greater than or equal to 9; the average decoding clock period calculated by the BCH decoding module and the RS decoding module for corresponding data in a concatenated code is the target decoding period, which is a positive integer greater than or equal to 9; or, The target total parallelism is 1440, meaning 1440 bits are received per cycle; the target clock frequency is... The clock cycles required for each of the BCH decoding module and the RS decoding module to receive corresponding data in a concatenated code are defined as the target reception period, which is a positive integer greater than or equal to 8. The average decoding clock cycle calculated by the BCH decoding module and the RS decoding module for corresponding data in a concatenated code is defined as the target decoding period, which is also a positive integer greater than or equal to 8. The target total parallelism is 1920, meaning 1920 bits are received per cycle; the target clock frequency is... Where a and b are positive integers, and a≥b; the clock period required for the BCH decoding module and the RS decoding module to receive the corresponding data in a concatenated code is the target reception period, which is a positive integer greater than or equal to 6; the average decoding clock period for the BCH decoding module and the RS decoding module to calculate the corresponding data in a concatenated code is the target decoding period, which is a positive integer greater than or equal to 6.

2. The decoder hardware architecture for concatenated RS and BCH codes according to claim 1, characterized in that, The BCH decoding module contains 32m or 80m BCH decoders, where m is a positive integer.

3. The decoder hardware architecture for concatenated RS and BCH codes according to claim 1, characterized in that, The RS decoding module contains 2n RS decoders, where n is a positive integer.

4. The decoder hardware architecture for concatenated RS and BCH codes according to claim 2, characterized in that, The BCH decoding module uses a hard-decision decoding method.

5. The decoder hardware architecture for concatenated RS and BCH codes according to claim 2, characterized in that, The BCH decoding module uses a soft-decision decoding method.

6. The decoder hardware architecture for a concatenated RS code and BCH code according to claim 5, characterized in that, The upper limit of the number of bits reversed in each codeword in the soft-decision decoding method is set to 4, 5 or 6.

7. The decoder hardware architecture for a concatenated RS code and BCH code according to claim 3, characterized in that, Each RS decoder includes a second corrector computation unit, multiple key equation solving units, at least one Qian search and Forney operator computation unit, and a second random access memory; Each of the key equation solving units operates in ping-pong mode; The Qian search and Forney operator units are interfacing with the output of the key equation solving unit in an overlapping mode.

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