Defer cache status updates

Abstract

Disclosed is a method of deferring an update of a cache state in a non-speculative cache memory in a processor-based system in response to a speculative data request until the speculative data request becomes non-speculative. An update of at least one cache state in the cache memory caused by the data request is deferred until the data request becomes non-speculative. Thus, the cache state in the cache memory is not updated for a request caused by an incorrect prediction. Deferring an update of the cache state in the cache memory may include deferring storage of received speculatively requested data in a primary data array of the cache memory as a result of a cache miss until the data request becomes non-speculative. The received speculatively requested data may first be stored in a speculative buffer memory associated with the cache memory, and then subsequently stored in the primary data array if the data request becomes non-speculative.

Description

Technical Field

[0001] The technology of the present disclosure relates to processor-based systems that employ a central processing unit (CPU) (also referred to as a "processor"), and more particularly to cache memory in a processor-based system for storing or "caching" copies of information in main memory for faster access by the processor. Background Art

[0002] A central processing unit (CPU) (also referred to as a "processor") performs computing tasks for various applications. Conventional processors include one or more processor cores (also referred to as "CPU cores"). The processor executes computer program instructions ("instructions") (also referred to as "software instructions") extracted from an instruction memory. The processor executes instructions extracted from the memory based on the instruction type and data operands to perform operations and generate results. The results may be provided as inputs to be consumed by another instruction and / or stored as data in a data memory. Instruction and data memory may be provided in a main memory as part of a processor-based system including a processor. Instruction and data memory may also be provided in the form of a cache memory. For example, a data cache memory includes or "caches" a smaller copy of data stored in the main memory to allow the processor to access the data faster. A cache memory system includes one or more cache memories organized in a hierarchy between the processor and the main memory. Data migrates between the main memory and different levels of cache memories based on cache hits and misses. If a processor requests data that is not stored in any level of cache memory (i.e., a cache miss), the data is retrieved from the main memory and stored in cache memories at each level. If a subsequent request for the same data results in a cache hit (ie, the data is requested before it is evicted from the levels of cache memory), the data is provided to the processor from the cache memory rather than having to re-fetch the data from main memory.

[0003] Data retrieved from a higher level cache memory or main memory due to a cache miss in a lower level cache memory is temporarily stored in a dedicated structure, which is called a fill buffer in the lower level cache memory. The fill buffer is also called a miss status holding register (MSHR). The fill buffer of the cache memory acts as a temporary storage area for incoming data to be stored in the cache memory until a cache entry in the cache memory becomes available to store the incoming data. The cache memory will evict existing cache entries in the data array of the cache memory based on an eviction policy such as the least recently used to make room for new incoming data as a result of a cache miss. A cache miss to a lower level cache memory may result in a data request (i.e., a read request) to the next higher level cache memory, which has already stored the requested data in its data array or is still stored in the fill buffer before being stored in the cache data array. In either case, in response to a request for data from a lower level cache memory, the requested data contained in the fill buffer or the data array of the higher level cache memory may be provided to the lower level cache memory. The cache memory may retain incoming data in its fill buffer and not store the data in its data array until the fill buffer becomes full, because incoming requests for data may be fulfilled from both the fill buffer and the data array.

[0004] The processor can adopt the instruction pipeline as a processing technique, thereby can increase the throughput of the computer instruction being executed by splitting the processing of each instruction into a series of steps. These steps are executed in an execution pipeline consisting of multiple stages. However, structural risks may occur in the instruction pipeline, wherein the next instruction cannot be executed without causing an erroneous calculation result. For example, control risk may occur due to the execution of the control flow instruction that causes the precise interruption in the processor. An example of a control flow instruction that may cause control risk is a conditional branch instruction. The conditional branch instruction can redirect the flow path of the instruction execution based on the condition evaluated when the condition of the control branch instruction is executed. A method for maximizing processor performance involves using a prediction circuit to speculatively predict the result of the condition of the conditional branch instruction before the conditional branch instruction is executed. In this way, younger ("younger") instructions that follow the predicted flow path of the conditional branch instruction can be extracted and also processed in the instruction pipeline, rather than stopping until the branch condition is resolved when the conditional branch instruction is executed. When the conditional branch instruction finally reaches the execution stage of the instruction pipeline and is executed, the result target address of the conditional branch instruction is verified by comparing the result target address of the conditional branch instruction with the target address predicted when the conditional branch instruction was extracted before. If the predicted target address matches the actual target address, it means that a correct prediction has been made, and no delay will be generated in the execution of the instruction, because when the conditional branch instruction reaches the execution stage of the instruction pipeline, the subsequent instructions at the target address will be correctly extracted and already exist in the instruction pipeline. However, if the predicted target address does not match the actual target address, a branch hazard of misprediction will occur in the instruction pipeline, resulting in an accurate interruption. As a result, an error prediction recovery process is performed, so that instructions younger than the conditional branch instruction in the instruction pipeline are refreshed and the instruction pipeline extraction unit is redirected to extract new instructions starting from the target address, resulting in delays and performance degradation.

[0005] Even though misprediction recovery involves flushing instructions younger than the conditional branch instruction in the mispredicted flow path, and then fetching and processing instructions in the correct flow path, the processing of the younger instructions in the wrong flow path may still cause data to be brought into the cache memory due to cache misses. This may lead to security issues in the form of leakage. For example, a malicious attacker process executed in a processor may include code that loads a large amount of data from memory, causing the data to fill the shared cache to start the cache memory. The attacker process may also start the branch prediction circuit to force a mispredicted speculative prediction of the conditional branch instruction in the victim process that is executed later. The load instructions in the mispredicted flow path following the conditional branch instruction in the victim process cause the processor to load data into the cache memory, even though these load instructions will be flushed later when the conditional branch instruction is executed and its condition is resolved. This may cause some of the data in the cache memory started by the attacker process to be evicted from the cache memory by the load instructions in the wrong flow path in the victim process. When the attacker process is executed again after the victim process is disconnected, the attacker process can determine which of its launched data are evicted from the cache memory. This information can provide information about the data addresses accessed by the victim process.

[0006] The above security issues can be solved by providing (multiple) non-shared speculative buffers outside the shared cache memory to store load data from the processing of speculatively processed load instructions. The speculatively loaded data from the processing of the speculatively processed load instructions to the speculative buffer can still be provided to the consumer instructions, depending on the speculatively processed load instructions. When the load instruction that causes data to be speculatively loaded into the speculative buffer is executed and becomes non-speculative, if the speculative prediction is correct, the speculative request can be reissued non-speculatively. If the speculative prediction is wrong, the speculative request for the data will not be reissued, thereby preventing the speculatively loaded data from being installed in the cache memory. In this way, the data will not be loaded into the cache memory due to the processing of the incorrectly speculated load instruction. However, up to twice (2X) data requests will be issued to load the data into the processor, which is inefficient. Summary of the invention

[0007] Aspects disclosed herein include: in response to a speculative data request, postponing a cache state update in a non-speculative cache memory in a processor-based system until the speculative data request becomes non-speculative. The processor-based system includes a processor, which may include one or more processor cores, which execute computer software instructions to perform operations based on load data stored in a main memory. The processor-based system also includes a cache memory system, which includes one or more private and / or shared cache memories organized in a hierarchy between the processor and the main memory. Each cache memory has a cache replacement policy that manages which data in its cache entries will be evicted to a higher level cache memory or main memory to make room to store new data requests (i.e., load / read requests). As a result of speculatively predicting the condition of a conditional flow control instruction (e.g., a conditional branch instruction), a load-based instruction ("load instruction") speculatively processed by a processor causes a data request to be made to the cache memory system. However, if it is determined that the condition of the conditional flow control instruction has been mispredicted during execution, the speculatively processed load-based instruction can be refreshed. However, previous data requests to the cache memory system that resulted from the processing of speculative load-based instructions that are no longer valid are made to the cache memory system. If such data requests are allowed to cause other cached data in the cache memory system to be evicted, this may result in cache pollution. This may also result in security issues. For example, a malicious attacker process may learn information about data accessed by a victim process based on erroneous speculative data loaded into the cache memory system. The malicious attacker process may enable the cache memory system with its own data and enable the control prediction circuit to make an erroneous prediction for conditional flow control instructions in the victim process, resulting in erroneous speculative data being loaded into the cache memory system. The attacker application may learn information about the victim process based on which enabled victim data in the cache memory system is replaced with the erroneous speculative data to be loaded into the cache memory system.

[0008] In this regard, in an exemplary aspect disclosed herein, at least one cache state in a cache memory is delayed from being updated in the cache memory in response to a received data request until the data request becomes non-speculative. In this way, the cache memory is not updated based on a data request generated by an incorrect prediction that should not be issued when an incorrect prediction occurs, and thus the cache memory is a non-speculative cache memory. In this way, cache pollution can be reduced. As another example, an attacker process cannot obtain data access information about a victim process executed in a processor by initiating an incorrect prediction in a control prediction circuit, which incorrect prediction causes a data request to be issued by the victim process, thereby causing a speculative change in the cache state in the cache memory. If a data request that is not parsed as non-speculative can change the cache state in the cache memory, the attacker application can understand the data access of the victim process by understanding the changed cache state in the cache memory.

[0009] In one exemplary aspect, a deferral of cache state updates in a cache memory is provided by not initially storing received speculative requested data in a cache entry in a primary data array of a cache memory received from a higher level memory as a result of a cache miss of the cache memory. Instead, the received speculative requested data is first stored in a speculative buffer memory that is not in the primary data array of the cache memory. For example, the speculative buffer memory may be a fill cache circuit in the cache memory that acts as a temporary storage area for the requested data to be stored until a cache entry in the primary data array of the cache memory becomes available to store the incoming data. If the load instruction that caused the data request being requested becomes non-speculative, the speculative requested data stored in the speculative buffer memory is stored in an available cache entry in the primary data array of the cache memory. A new data request does not have to be issued by a processor to the cache memory system in order for the speculative requested data stored in the speculative buffer memory to be stored in a cache entry in the cache memory in response to the data request becoming non-speculative.

[0010] In another exemplary aspect, when a data request issued from a processor to a cache memory in a cache memory system is contained in a cache entry in a primary data array of the cache memory, a cache hit occurs. Since the speculatively requested data is already contained in a cache entry of the primary data array in the cache memory, the speculatively requested data in the hit cache entry in the primary data array in the cache memory is returned to the requesting party in the processor. However, the update of the replacement cache state of the cache entry in the primary data array containing the speculatively requested data can be postponed until the load instruction that initiated the data request for the data becomes non-speculative. For example, therefore, a replacement strategy for the primary data array of the cache memory will not be executed based on a replacement cache state that has been changed for the cache entry of the primary data array containing the speculatively requested data due to the data request in case the data request is refreshed due to a prediction error.

[0011] In another exemplary aspect, if a data request issued from a processor to a cache memory is not contained in a primary data array, but is contained in a speculative buffer memory associated with the cache memory, the speculatively requested data in the speculative buffer memory is also returned to the requestor in the processor as a cache hit. By not writing the speculatively requested data to a cache entry in the primary data array of the cache memory until the data request becomes non-speculative, an update of the cache state for the speculatively requested data is deferred. In addition, as an example, an update of a replacement cache state for the speculatively requested data is automatically deferred until a new data request for the same data results in a cache hit in the primary data array of the cache memory, as discussed above.

[0012] In this regard, in an exemplary aspect, a non-speculative cache memory in a processor-based system is provided. The non-speculative cache memory includes a main data array, the main data array includes a plurality of cache entries, each of the plurality of cache entries is configured to store cache data of data associated with a memory address in a memory system of the processor-based system. The non-speculative cache memory also includes a speculative buffer memory, the speculative buffer memory includes a plurality of buffer entries, each of the plurality of buffer entries includes a data entry configured to store cache data associated with a memory address in the memory system. The non-speculative cache memory also includes a cache controller, the cache controller is configured to receive a data request including a target address and an instruction identification (ID) from a requester, the instruction identification (ID) identifying a load instruction, the load instruction including a target address processed by a processor in the processor-based system. The cache controller is also configured to search the main data array for a cache entry associated with the target address of the data request. The cache controller is also configured to search the speculative buffer memory for a buffer entry associated with the target address of the data request. The cache controller is further configured to send a data response to the data request to the requestor based on the cache data associated with the target address in the primary data array and the cache data in the cache entry associated with the target address in the speculative buffer memory. The cache controller is further configured to receive a commit indicator including an instruction ID of a non-speculative instruction. The cache controller is further configured to update a cache state of a cache entry associated with the target address of the data request in the primary data array in response to the received instruction ID in the commit indicator indicating that the load instruction of the data request is non-speculative.

[0013] In another exemplary aspect, a method for updating cache state in a non-speculative cache memory in a processor-based system is provided. The method includes receiving a data request including a target address and an instruction ID from a requester, the instruction ID identifying a load instruction, the load instruction including a target address processed by a processor in the processor-based system. The method also includes: searching a cache entry associated with the target address of the data request in a plurality of cache entries in a main data array, each of the plurality of cache entries being configured to store cache data associated with a memory address in a memory system of the processor-based system. The method also includes: searching a cache entry associated with the target address of the data request in a plurality of cache entries in a speculative buffer memory, each of the plurality of cache entries being configured to store cache data associated with a memory address in the memory system. The method also includes: sending a data response to the data request to the requester based on the cache entry associated with the target address in the main data array and the cache data in the buffer entry associated with the target address in the speculative buffer memory. The method also includes: receiving a commit indicator including an instruction ID of a non-speculative instruction. The method further includes updating a cache state of a cache entry in the primary data array associated with a target address of the data request in response to the received instruction ID in the commit indicator indicating that the load instruction of the data request is non-speculative.

[0014] After reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings, those skilled in the art will be able to understand the scope of the present disclosure and implement additional aspects thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0016] Figure 1 is a diagram of an exemplary processor-based system including a processor configured to issue memory requests (i.e., data read and data write requests) to a memory system including a cache memory system and a main memory, wherein at least one cache memory in the cache memory system is configured to, in response to receiving a data request from the processor, defer updating of a cache state until the data request becomes non-speculative;

[0017] Figure 2 can be included in Figure 1a diagram of exemplary instruction processing circuitry in a processor of and including one or more instruction pipelines for processing computer instructions for execution, wherein the instruction processing circuitry includes control flow prediction circuitry configured to speculatively predict conditions of conditional flow control instructions fetched and processed by the instruction processing circuitry;

[0018] Figure 3 yes Figure 1 A schematic diagram of an exemplary non-speculative cache memory in a cache memory system in;

[0019] Figure 4 It is shown Figure 3 a flow chart of an exemplary process of a cache controller in a cache memory in a cache memory that defers updating of a cache state of data for a received speculative data request and updates the deferred cache state in a primary data array for data associated with the data request in response to the data request becoming non-speculative;

[0020] Figure 5A Shows Figure 1 a processor in the cache memory system issuing a data request resulting in a cache hit in a primary data array of the cache memory, wherein a cache controller of the cache memory allocates an entry associated with a load instruction processed by the processor generating the data request in a speculative access recording (SAR) circuit for recording a cache state update deferral for a cache entry in the primary data array storing the speculatively requested data;

[0021] Figure 5B Shows Figure 3 a cache memory in which a non-speculative indicator is received from a processor indicating that a load instruction processed by the processor has become non-speculative, and a cache controller in the cache memory accesses a recorded cache state update deferral associated with the load instruction that has become non-speculative, so that a cache state of a cache entry in a primary data array storing speculative requested data is updated;

[0022] Fig. 6A Shows Figure 1 a processor in the cache memory system issuing a data request to the cache memory system, resulting in a cache miss in a primary data array of the cache memory, and an entry allocated in a speculative access recording (SAR) circuit configured to store an index associated with an instruction associated with the data request to a cache entry in a speculative buffer memory allocated to store cache data requested by the data to record a cache state update deferral for the data request;

[0023] Figure 6B Shows Figure 3 a cache memory in the processor receiving a non-speculative indicator from the processor indicating that a load instruction processed by the processor has become non-speculative, and in response, a cache controller in the cache memory accessing a recorded cache state update deferral associated with a load instruction in the speculative buffer memory, the load instruction being indexed by an entry in the SAR circuit associated with the instruction associated with the data request, to update a cache state of a cache entry in a primary data array storing the requested data;

[0024] FIG. 7A to FIG. 7D Shows Figure 1 An example of a processor in a cache memory system issuing a data request to cause a cache hit and a cache miss in a primary data array of the cache, and an example process of deferring an update of a cache state for cache data in the primary data array associated with the data request by using a SAR circuit configured to index a dummy fill buffer circuit, and the dummy fill buffer circuit is configured to index a speculative buffer memory to record the deferred cache state update for use in updating the cache state associated with the data request when the data request becomes non-predictive;

[0025] Figure 8 is a block diagram of an exemplary processor-based system including a processor configured to issue memory requests to a memory system including a cache memory system and a main memory, wherein the cache memory system includes at least one cache memory, including but not limited to Figure 1 , 3 , FIG. 5A to FIG. 5B , FIG. 6A to FIG. 6B and FIG. 7A to FIG. 7D A cache memory in the processor is configured to defer updating of a cache state in response to receiving a data request from a processor until the data request becomes non-speculative. DETAILED DESCRIPTION

[0026] Aspects disclosed herein include deferring cache state updates in non-speculative cache memories in a processor-based system in response to speculative data requests until the speculative data requests become non-speculative. The processor-based system includes a processor, which may include one or more processor cores that execute computer software instructions to perform operations based on loaded data stored in a main memory. The processor-based system also includes a cache memory system, which includes one or more private and / or shared cache memories organized in a hierarchy between the processor and the main memory. Each cache memory has a cache replacement policy that manages which data in its cache entries will be evicted to a higher level cache memory or main memory to make room to store new data requests (i.e., load / read requests). Load-based instructions ("load instructions") speculatively processed by a processor as a result of speculatively predicting a condition of a conditional flow control instruction (e.g., a conditional branch instruction) result in a data request being made to the cache memory system. In an exemplary aspect disclosed herein, at least one cache state in the cache memory is deferred from being updated in the cache memory in response to a received data request until the data request becomes non-speculative. As such, the cache memory is not updated based on data requests resulting from mispredictions that should not have been issued when a misprediction occurred, and thus the cache memory is a non-speculative cache memory.

[0027] In this way, cache pollution can be reduced. As another example, an attacker process cannot obtain data access information about a victim process executing in a processor by initiating a misprediction in a control prediction circuit, which misprediction causes the victim process to issue a data request that results in speculatively changing a cache state in a cache memory. If a data request that is not resolved as non-speculative can change a cache state in a cache memory, the attacker application can learn about the data access of the victim process by learning about the changed cache state in the cache memory.

[0028] Figure 11 is a diagram of an exemplary processor-based system 100 that includes a central processing unit (CPU) or processor 102 that is configured to issue memory requests (i.e., data read and data write requests) to a memory system 104 that includes a cache memory system 106 and a main memory 108. For example, the main memory 108 may be a dynamic random access memory (DRAM) provided in a separate DRAM chip. The processor 102 includes one or more respective CPU cores 110(1) to 110(N), where “N” is a positive integer representing the number of CPU cores included in the processor 102. The processor 102 may be packaged in an integrated circuit (IC) chip 112. The cache memory system 106 includes one or more cache memories 114(1) to 114(X), which may be in different hierarchies in the processor-based system 100, the different hierarchies being logically located between the CPU cores 110(1) to 110(N) and the main memory 108, where "X" is a positive integer representing the number of CPU cores included in the processor 102. The cache memories store or cache a subset of data contained in the main memory 108 to provide faster access to data in the main memory 108 to the CPU cores 110(1) to 110(N) for fulfilling data requests. The memory controller 116 controls access to the main memory 108.

[0029] For example, the CPU core 110(1) to the CPU core 110(N) as a requesting device may issue a data request 118 to read data in response to processing a load instruction. The data request 118 includes a target address of the data to be read from the memory. The data request 118 may also include an instruction identification (ID) that identifies the instruction that causes the CPU core 110(1) to the CPU core 110(N) to issue the data request 118. Using the CPU core 110(1) as an example, if the requested data is not in the private cache memory 114(1) (which may be considered as a first level (L1) cache memory) (i.e., a cache miss to the cache memory 114(1)), in this example, the private cache memory 114(1) sends the data request 118 to the shared cache memory 114(X) shared by all the CPU cores 110(1) to the CPU core 110(N) via the interconnect bus 117, and the shared cache memory 114(X) may be a (3) level cache memory. Other shared cache memories 114(2), 114(3) that the processor 102 shares with only a subset of the CPU cores 110(1) to 110(N) may also be considered as level 2 (2) cache memories. If not contained in any cache memory 114(1) to 114(X), the requested data is ultimately retrieved from the cache memory 114(1) to 114(X) or main memory 108. Data received by a cache memory 114(1) to 114(X) from a higher level cache memory 114(1) to 114(X) or main memory 108 due to a cache miss causes the receiving cache memory 114(1) to 114(N) to evict the cached data to a higher level memory to make room for the new cached data. Each cache memory 114(1) to cache memory 114(X) has a cache replacement policy that manages which of its cache data will be evicted to a higher level cache memory 114(1) to cache memory 114(X) or main memory 108 to make room to store new cache data in response to a data request 118 that resulted in a cache miss.

[0030] Figure 2 The instruction processing circuit 200 provided in the CPU core 110 is shown. The CPU core 110 may be Figure 1 The CPU core 110(1) to the CPU core 110(N) in any processor 102 in the embodiment of the present invention may be a CPU core 110(1) to a CPU core 110(N) in any processor 102 in the embodiment of the present invention. For example, the instruction processing circuit 200 includes one or more instruction pipelines 10 to 110. N , the one or more instruction pipelines I0 to instruction pipeline IN The computer instruction 202F is used to process the extracted computer instruction 202F, which is extracted by the instruction fetch circuit 204 from a series of instructions 202 stored in the instruction cache memory 206 or the instruction memory 208 for execution. The instruction cache memory 206 may be provided as part of the cache memory 114 (1) to the cache memory 114 (X) Figure 1 The instruction memory 208 may be provided in the cache memory system 106 of the processor-based system 100. Figure 1 The instruction fetch circuit 204 is configured to fetch the instruction 202F to one or more instruction pipelines 10 to 10 before the instruction 202F reaches the execution circuit 212 for execution. N The fetch instruction 202F is provided as the instruction stream 210 to be pre-processed in the instruction processing circuit 200. Instruction pipeline I0 to instruction pipeline I N Different processing circuits or stages across the instruction processing circuitry 200 are provided to pre-process and process the fetch instruction 202F in a series of steps that may be performed concurrently prior to execution of the fetch instruction 202F by the execution circuitry 212 to increase throughput.

[0031] Continue to refer Figure 2 The instruction processing circuit 200 includes an instruction decoding circuit 214, which is configured to decode the extracted instruction 202F extracted by the instruction extraction circuit 204 into a decoded instruction 202D to determine the instruction type and the required action. The decoded instruction 202D is placed in the instruction pipeline I0 to the instruction pipeline I N The decoded instruction 202D is then passed to one or more instruction pipelines and is subsequently provided to a renaming circuit 216 in the instruction processing circuit 200 to determine whether any register names in the decoded instruction 202D need to be renamed to break any register dependencies that would prevent parallel or out-of-order processing. The renaming circuit 216 is configured to call a register mapping table (RMT) 218 ​​to rename logical source register operands and / or write target register operands of the decoded instruction 202D to available physical registers 220(1) to physical registers 220(X) (P0, P1, . . . , P2) in a physical register file (PRF) 222. X ). RMT 218 includes a plurality of mapping entries, each of which is mapped to a corresponding logical register R0 to a logical register R PThe mapping entry is configured to store information in the form of an address pointer to a physical register 220(1)-220(X) in a physical register file (PRF) 222. Each physical register 220(1)-220(X) in the PRF 222 contains a data entry configured to store data for decoding a source and / or destination register operand of the instruction 202D.

[0032] The instruction processing circuit 200 also includes a register access (RACC) circuit 224 configured to access logical registers R0 to R1 in the RMT 218 based on the source register operand mapped to the decoded instruction 202D. P The RACC circuit 224 is configured to access the physical registers 220(1) to 220(X) in the PRF 222 using the mapping entries of the instruction processing circuit 200 to retrieve the generated value from the executed instruction 202E in the execution circuit 212. The RACC circuit 224 is also configured to provide the generated value retrieved from the executed decoded instruction 202E as the source register operand of the decoded instruction 202D to be executed. In addition, in the instruction processing circuit 200, the scheduler circuit 226 is provided between the instruction pipelines I0 to I1. N The scheduler circuit 226 sends a signal to the execution circuit 212 that is ready to be executed in execution lanes L0 to L1. K Write circuitry 228 is also provided in instruction processing circuitry 200 to write or commit the resulting value from the executed instruction 202E back to a memory, such as PRF 222, cache memory system 106, or main memory 108.

[0033] Continue to refer Figure 2 The instruction processing circuit 200 further includes a flow control prediction circuit 230. The flow control prediction circuit 230 is configured to speculatively predict the result of a condition of an extracted conditional flow control instruction 202F, such as a conditional branch instruction, which controls whether a taken or not taken path in the instruction control flow path of the instruction stream 210 is extracted to the instruction pipeline I0 to the instruction pipeline I1. N In this way, the condition of the fetched conditional flow control instruction 202F does not have to be resolved when executed by the execution circuitry 212 before the instruction processing circuitry 200 can continue to process the speculatively fetched instruction 202F. The prediction made by the flow control prediction circuitry 230 may be provided to the instruction fetch circuitry 204 as prediction information 232 for use by the instruction fetch circuitry 204 in determining the next instruction 202 to fetch.

[0034] However, if, when conditional flow control instruction 202F is executed in execution circuitry 212, it is determined that the condition of conditional flow control instruction 202F has been mispredicted, then speculative fetch instructions 202F fetched after conditional flow control instruction 202F and processed in instruction processing circuitry 202 are flushed because these instructions should not be processed. Instruction processing circuitry 202 returns to the state that existed before conditional flow control instruction 202F was processed. The speculative fetch instructions 202F that are flushed in response to a misprediction may have included load-based instructions ("load instructions") that are directed to the instruction processing circuitry 202. Figure 1 102, a cache memory system 106 in a processor-based system 100 in FIG. 100 issues a speculative data request 118. If such a speculative data request 118 results in a cache miss, data is evicted from the cache memory system 106 to make room for data responses to any such speculative data requests 118. This may result in cache pollution. This may also result in security issues. For example, a malicious attacker process executing in the processor 102 may learn information about data accessed by a victim process executing in the processor 102 based on erroneous speculative data loaded into the cache memory system 106. The malicious attacker process may enable the cache memory system 106 with its own data and enable the flow control prediction circuit 230 to make an incorrect prediction for the conditional flow control instruction 202F in the victim process, thereby causing erroneous speculative data to be loaded into the cache memory system 106. The attacking application may learn information about the victim process based on which enabled victim data in the cache memory system 106 is replaced with the incorrectly speculative data to be loaded into the cache memory system 106 .

[0035] At this point, Figure 1 One or more of the cache memories 114(1) through 114(X) in the cache memory system 106 of the processor-based system 100 may be configured as non-speculative cache memories. The non-speculative cache memories are configured to defer updating of a cache state of a cache entry for a received data request 118 until the data request becomes non-speculative. For example, Figure 3 Shows Figure 1 An example of a cache memory 114 in a processor-based system 100 in FIG. 1 is shown in FIG. 1 , which is configured to be non-speculative. Figure 3As shown, the non-speculative cache memory 114 includes a cache controller 300, which is a circuit configured to control the operation of the non-speculative cache memory 114, including processing a data request 118 for accessing cache data stored in the non-speculative cache memory 114, providing a data response 302 of cache data to the requester, filling a request 304 in response to a cache miss for the received data request 118 to obtain cache data from a higher level memory, and filling a response 306 with cache data received from a higher level memory in response to the fill request 304.

[0036] The non-speculative cache memory 114 also includes a main data array 308, which includes a plurality of cache entries 310(0) to 310(M), each of which is configured to store Figure 1Cache data 314(0) to cache data 314(M) stored at memory addresses associated with corresponding tags 312(0) to tags 312(M) in the memory system 104. The non-speculative cache memory 114 also includes a tag array 311 configured to store a plurality of tags 312(0) to tags 312(M) corresponding to corresponding cache entries 310(0) to cache entries 310(M). The primary data array 308 may also include a cache replacement state 315(0) to cache entry 315(M) in each corresponding cache entry 310(0) to cache entry 310(M) to indicate a replacement state for the associated cache entry 310(0) to cache entry 310(M), which is used by the cache controller 300 to determine which cache entry 310(0) to cache entry 310(M) to evict when new data for the non-speculative data request 118 needs to be stored in the primary data array 308. The primary data array 308 may also include a valid indicator 316(0) to cache entry 316(M) in each corresponding cache entry 310(0) to cache entry 310(M) to indicate whether the cache data 314(0) to cache data 314(M) is valid. The non-speculative cache memory 114 in this example also includes a speculative buffer memory 318, which includes a plurality of buffer entries 320(0) to 320(B), each of which is configured to store cache data 324(0) to 324(B) stored at a memory address associated with a corresponding buffer tag 322(0) to 322(B) in the memory system 104. The non-speculative cache memory 114 also includes a tag array 323, which is configured to store the buffer tags 322(0) to 322(B) associated with the corresponding buffer entries 320(0) to 320(B). For example, the speculative buffer memory 318 can be a fill buffer for the non-speculative cache memory 114, which acts as a temporary storage area for incoming data in the fill response 306 issued in response to the fill request 304 to be stored in the non-speculative cache memory 114 until cache entries 310(0) to 310(M) in the main data array 308 become available to store the incoming data.

[0037] Continue to refer Figure 3, the speculative cache memory 318 also includes instruction identifiers (IDs) 326(0) to 326(B) in each corresponding cache entry 320(0) to 320(B) to store the instruction IDs of the load instructions that issued the data request 118 to the non-speculative cache memory 114 to track whether and when the data request 118 becomes non-speculative. The cache controller 300 is configured to update the cache state associated with the data request 118 in the cache entries 310(0) to 310(M) in the main data array 308 associated with the data request 118 after the instruction that caused the data request 118 to be issued becomes non-speculative in the processor 102. As will be discussed in more detail below, the cache controller 300 is configured to allocate the buffer entries 320(0) to 320(B) in the speculative cache memory 318 in response to the received data request 118. Cache controller 300 is configured to initially update respective speculative indicators (NS) 330 ( 0 ) through 330 (B) using the speculative state in each cache entry 320 ( 0 ) through 320 (B) for the received data request 118 as speculation. Each of the cache entries 320(0) to 320(B) in the speculative cache memory 318 further includes an in-cache indicator 332(0) to 332(B) indicating whether the data for the associated cache entry 320(0) to 320(B) is stored in the cache entry 310(0) to 310(M) in the main data array 308 and a valid indicator 334(0) to 334(B) indicating whether the cache entry 320(0) to 320(B) is valid. The non-speculative cache memory 114 is configured to receive a commit indicator 328 containing an instruction ID of a non-speculative instruction issued by the processor 102. The cache controller 300 may use the received instruction ID in the commit indicator 328 to search for instruction ID 326(0) to instruction ID 326(B) in the speculative buffer memory 318 to update the corresponding non-speculative indicator (NS) 330(0) to non-speculative indicator 330(B) in each cache entry 320(0) to cache entry 320(B). The cache controller 300 may then update the cache status of the data of the associated data request 118 in cache entries 310(0) to cache entries 310(M) in the main data array 308 in response to the non-speculative indicator (NS) 330(0) to non-speculative indicator 330(B) for the data request 118 becoming non-speculative.

[0038] For example, if based on Figure 2 The load instruction 202D speculatively processed by the control flow prediction in the processor 102 in the Figure 3 When a data request 118 for data is issued to the non-speculative cache memory 114 in the cache memory 300, the cache controller 300 is configured to search the tags 312(0) to 312(M) in the cache entries 310(0) to 310(M) associated with the target address of the data request 118 in the tag array 311 to determine whether the data for the data request 118 exists. The cache controller 300 is also configured to search the buffer tags 322(0) to 322(B) corresponding to the buffer entries 320(0) to 320(B) associated with the target address of the data request 118 in the tag array 323 in the speculative buffer memory 318 to determine whether the data for the data request 118 exists in the speculative buffer memory 318. If a cache miss occurs in which the data for the data request 118 is not present in the primary data array 308 or in the speculative buffer memory 318, the cache controller 300 issues a fill request 304 for the data from the higher level memory and receives the requested data as a fill response 306. The cache controller 300 may be configured to defer updating of the cache state for the data request 118 by not initially storing the received data in the fill response 306 for the data request 118 in cache entries 310(0) to 310(M) in the primary data array 308. Instead, the received data for the data request 118 may first be stored as cache data 324(0) to 324(B) in the allocated buffer entries 320(0) to 320(B) in the speculative buffer memory 318 so as not to pollute the primary data array 308 with the speculative data. When data request 118 becomes non-speculative, as indicated by the instruction ID in commit indicator 328 that matches instruction ID 326(0) to instruction ID 326(B) in buffer entries 320(0) to 320(B) in speculative buffer memory 318, cache controller 300 may cause data for data request 118 to be stored in allocated cache entries 310(0) to 310(M) in main data array 308.

[0039] In another example, a cache hit occurs when the target address of the data request 118 corresponds to the matching tags 312(0) to 312(M) in the tag array 311 in the non-speculative cache memory 114. This indicates that the data for the data request 118 has been contained in the cache entries 310(0) to 310(M) corresponding to the matching tags 312(0) to 312(M) in the main data array 308. The cache data 314(0) to 314(M) for the data request 118 stored in the corresponding cache entries 310(0) to 310(M) are returned to the requester in the processor 102 as the data response 302. However, the updating of cache replacement states 315(0) to 315(M) of cache entries 310(0) to 310(M) having cache data 314(0) to 314(M) for data request 118 may be postponed until data request 118 becomes non-speculative. Thus, for example, the replacement policy of non-speculative cache memory 114 will not be executed based on replacement cache states for cache entries 310(0) to 310(M) in main data array 308 that are changed by speculative data request 118, which may be flushed in processor 102 due to an invalid update of the cache state caused by a misprediction.

[0040] In another example, if a data request 118 is issued from the processor 102, and the non-speculative cache memory 114 is not included in the cache entries 310(0) to 310(M) in the main data array 308, but is included in the cache entries 320(0) to 320(B) in the speculative buffer memory 318, then the corresponding cache data 324(0) to 324(B) for the data request 118 are returned to the requester in the processor 102 as the data response 302. However, the cache controller 300 can be configured to postpone the update of the cache state for the data request 118 by not storing the data in the speculative buffer memory 318 for the data request 118 in the cache entries 310(0) to 310(M) in the main data array 308, so as to prevent the speculative data from polluting the main data array 308. When data request 118 becomes non-speculative, as indicated by the instruction ID in commit indicator 328 matching instruction ID 326(0) to instruction ID 326(B) in buffer entries 320(0) to 320(B) in speculative buffer memory 318, cache controller 300 may cause data for data request 118 to be stored in allocated cache entries 310(0) to 310(M) in main data array 308. Thus, as another example, if a later cache hit occurs on such allocated cache entries 310(0) to cache entries 310(M) for a new subsequent data request 118, then the update of the cache replacement states 315(0) to cache replacement states 315(M) of cache entries 310(0) to cache entries 310(M) in the main data array 308 having cache data 314(0) to cache data 314(M) for the data request 118 will be postponed until the data request 118 becomes non-speculative, as discussed above for the cache hit of the main data array 308.

[0041] Figure 4 It is shown Figure 3 Flowchart of an exemplary process 400 for a cache controller 300 in a non-speculative cache memory 114 in FIG. 1 that defers updating of a cache state of data for received speculative data requests 118 . Figure 4 The process 400 also includes updating the deferred cache state in the primary data array 308 for data associated with the data request 118 in response to the data request 118 becoming non-speculative. Figure 4 The process 400 will be combined Figure 3 The non-speculative cache memory 114 in Figure 1 and Figure 2 In this regard, the non-speculative cache memory 114 receives a data request 118 from a requestor including a target address and an instruction identifier (ID) that identifies a load instruction (ID) that is processed by the processor 102 and includes the target address. Figure 4 Cache controller 300 searches tag array 311 for tags 312(0) to 312(M) associated with the target address of data request 118 ( Figure 4 Cache controller 300 also searches speculative cache memory 318 for cache tags 322(0) to 322(B) associated with the target address of data request 118 ( Figure 4 Cache controller 300 sends data response 302(B) to data request 118 to requestor in processor 102 based on cache entries 310(0) to 310(M) in primary data array 308 being associated with the target address and buffer tags 322(0) to 322(B) in tag array 323 in speculative buffer memory 318 being associated with the target address of data request 118. Figure 4 4. Cache controller 300 receives commit indicator 328 (block 408 in FIG. 4 ) including an instruction ID of a non-speculative instruction. Figure 4 In response to the received instruction ID in the commit indicator 328 indicating that the load instruction of the data request 118 is non-speculative, the cache controller 300 updates the cache states ( 0 ) to 310 (M) of the cache entries in the main data array 308 associated with the target address of the data request 118. Figure 4 412 in FIG.

[0042] As will be discussed in more detail below, the non-speculative cache memory 114 may also include a speculative access record (SAR) circuit 336 to track whether data associated with a data request 118 that is not yet known to be non-speculative is contained in the main data array 308 or the speculative buffer memory 318. As described above, the data for the received data request 118 may have been contained in the main data array 308 resulting in a cache hit, may have been contained in the speculative buffer memory 318 also resulting in a cache hit, or may not be contained in either resulting in a cache miss. In the event of a cache miss, buffer entries 320(0) to 320(B) for storing the data of the data request 118 are allocated in the speculative buffer memory 318. Therefore, the data for the data request 118 may be stored in the main data array 308 or the speculative buffer memory 318. In response to receiving a commit indicator 328 indicating an instruction ID of an instruction that has been committed by the processor 102, the cache controller 300 requires a method for determining whether data associated with a data request 118 issued as a result of an instruction matching the instruction ID is stored in the primary data array 308 or in the speculative buffer memory 318 so that the cache state can be updated. If the data associated with the committed instruction identified by the instruction ID in the commit indicator 328 is stored in the primary data array 308, the cache controller 300 needs to update the cache states of cache entries 310(0) to 310(M) in the primary data array 308 that store data for the committed data request 118. If data associated with the commit instruction identified by the instruction ID in the commit indicator 328 is stored in the speculative buffer memory 318, the cache controller 300 needs to update the non-speculative indicators (NS) 330(0) to the non-speculative indicators 330(B) of the buffer entries 320(0) to 320(B) in the speculative buffer memory 318. The cache controller 300 updates the non-speculative indicators (NS) 330(0) to the non-speculative indicators 330(B) of the buffer entries 320(0) to 320(B) associated with the non-speculative instruction ID so that the data associated with the committed data request 118 is written to the main data array 308 as non-speculative data.

[0043] In this regard, Figure 3As shown, the non-speculative cache memory 114 includes a SAR circuit 336 configured to store SAR entries 338(0) to SAR entries 338(S) associated with corresponding instruction IDs 340(0) to 340(S). When a data request 118 is received, the cache controller 300 allocates the SAR entries 338(0) to SAR entries 338(S) allocated in the SAR circuit 336 and associated with the instruction ID of the instruction that issued the data request 118. If data associated with the instruction identified by the instruction ID of the received data request 118 is already stored in cache entries 310(0) to cache entry 310(M) in the main data array 308, then the main data array (MDA) index 342(0) to main data array 342(S) for the allocated SAR entry 338(0) to SAR entry 338(S) is updated using the index to the cache entry 310(0) to cache entry 310(M) in the main data array 308 containing the data for the data request 118. If the data associated with the instruction identified by the instruction ID of the received data request 118 is not stored in cache entries 310(0) to 310(M) of the main data array 308, but is stored in buffer entries 320(0) to 320(B) in the speculative buffer memory 318, then the speculative cache (SB) indexes 344(0) to 344(S) for the allocated SAR entries 338(0) to SAR entries 338(S) are updated using the indexes to the buffer entries 320(0) to 320(B) in the speculative buffer memory 318 that contain the data for the data request 118. If the data associated with the instruction identified by the instruction ID of the received data request 118 is not stored in cache entries 310(0) to 310(M) in the main data array 308 or cache entries 320(0) to 320(B) in the speculative buffer memory 318 that caused the cache miss, then the speculative buffer (SB) indexes 344(0) to 344(S) for the allocated SAR entries 338(0) to SAR entries 338(S) are updated using the indexes to the buffer entries 320(0) to 320(B) in the speculative buffer memory 318 that contain the data for the received data request 118 from the fill response 306 from the higher level memory in response to the fill request 304. As described above, allocating SAR entry 338(0) to SAR entry 338(S) in SAR circuit 336 for data request 118 allows cache controller 300 to determine whether it is necessary to update the cache state of data associated with data request 118 that has been made non-speculative in main data array 308 or speculative buffer memory 318.

[0044] To illustrate an example of using the SAR circuit 336 by the non-speculative cache memory 114 to track recorded speculative data requests and to be able to defer updates to cache states in the non-speculative cache memory 114 until the data requests become non-speculative, an example is provided. Figure 5A and 5B . Figure 5A Shows Figure 1 The processor 102 in the non-speculative cache memory 114 issues a data request 118 including an instruction ID and a target address, which is received by the non-speculative cache memory 114, resulting in a cache hit in the primary data array 308 of the non-speculative cache memory 114. In this example, in the data request 118, the instruction ID identifying the processing instruction that caused the data request 118 to be issued is instruction ID 1. The cache controller 300 in the non-speculative cache memory 114 is configured to search the primary data array 308 and the speculative buffer memory 318 to search for data corresponding to the target address of the data request 118. In this example, the data corresponding to the target address of the data request 118 is contained in the primary data array 308, resulting in a cache hit. The data for the data request 118 in the primary data array 308 is returned to the requester in the processor 102 as a data response 302. However, the instruction identified by instruction ID 1 that causes the data request 118 to be issued is considered speculative until a commit indicator 328 indicating otherwise is received by the non-speculative cache memory 114, as previously discussed. The cache controller 300 in the non-speculative cache memory 114 is configured to, at Figure 5A The SAR circuit 336 shown allocates a SAR entry 338 (1) associated with instruction ID 1 to record the deferral of the cache status update for the data request 118 in the main data array 308. Figure 5AAs shown, instruction ID 1 is stored in instruction ID 340(1) of SAR entry 338(1). Since data request 118 results in a cache hit to primary data array 308 in non-speculative cache memory 114, cache set / way "12 / 4" of cache entry 310(0) to cache entry 310(M) in primary data array 308 containing data for data request 118 is stored in MDA index 342(1). At this point, cache controller 300 can later locate cache entry 310(0) to cache entry 310(M) in primary data array 308 based on MDA index 342(1) to update its cache state when instruction ID 1 is indicated as being committed according to received commit indicator 328. Note that a null value is stored in SB index 344(1) for SAR entry 338(1) because the data for data request 118 is in primary data array 308 and not in speculative buffer memory 318. Note that in this example, SAR entry 338(0) records the location of the data for previous data request 118 in SB index 344(0) corresponding to entry 1 in speculative buffer memory 318. It should also be noted that the allocated SAR entry 338(0) through SAR entry 338(S) may optionally be augmented by cache controller 300 with information related to deferred cache replacement policy updates. For example, SAR entry 338(0) through SAR entry 338(S) may be marked as most recently used (MRU) entries in a least recently used (LRU) cache replacement policy.

[0045] Figure 5B Shows Figure 5A In the example of processor 102 receiving commit indicator 328 identifying instruction ID 1 as being committed. In response, cache controller 300 is configured to search SAR circuit 336 to determine whether SAR entry 338 includes instruction ID 1 in instruction ID 340(0) to instruction ID 340(S) to indicate that the update of the cache state of data request 118 associated with instruction ID 1 is deferred. Figure 5AAs shown and previously described, in this example, instruction ID 1 is included in SAR entry 338(1) in response to the received data request 118 resulting from the processing of instruction ID 1. Cache controller 300 is configured to, in response to determining that instruction ID 1 is included in SAR entry 338(1), update cache entries 310(0) through 310(M) in primary data array 308 indexed by MDA index 342(1) to cache replace state 315(0) through cache replace state 315(M). This is because, based on the received commit indicator 328, cache entries 310(0) through 310(M) in primary data array 308 indexed by MDA index 342(1) for the instruction ID are no longer speculative. In response to receiving the commit indicator 328 indicating that instruction ID 1 is committed to make room to record the deferred cache update status of future received data requests 118, the cache controller 300 may deallocate the SAR entry 338(1).

[0046] To illustrate an example of using the SAR circuit 336 and the speculative buffer memory 318 in the non-speculative cache memory 114 to track recorded speculative data requests and to be able to defer updates to the cache state in the non-speculative cache memory 114 until the data request becomes non-speculative, an example is provided. Fig. 6A and 6B . Fig. 6A Shows Figure 1 The processor 102 in the non-speculative cache memory 114 issues a data request 118 including an instruction ID and a target address, which is received by the non-speculative cache memory 114, resulting in a cache miss to the primary data array 308 and the speculative buffer memory 318. In this example, the instruction ID in the data request 118 identifying the processing instruction that caused the issuance of the data request 118 is instruction ID 7. The cache controller 300 in the non-speculative cache memory 114 is configured to search the primary data array 308 and the speculative buffer memory 318 for data corresponding to the target address of the data request 118. As previously discussed, in this example, the data corresponding to the target address of the data request 118 is neither contained in the primary data array 308 nor in the speculative buffer memory 318 of the non-speculative cache memory 114. The instruction identified by instruction ID 1 that caused the issuance of the data request 118 is considered speculative until a commit indicator 328 indicating otherwise is received by the non-speculative cache memory 114.

[0047] The cache controller 300 in the non-speculative cache memory 114 is configured to Fig. 6AAn available cache entry 320(7) is allocated in the speculative cache memory 318, which in this example is index 7. This allows the cache controller 300 to retrieve and install data for the data request 118 associated with instruction ID 1 and stored in the speculative cache memory 318 in a speculative state in response to the fill response 306 received from the higher level memory in the main data array 308 when the data request 118 becomes non-speculative. In this example, the cache in-cache indicator 332(7) in the buffer entry 320(7) is set to "0", which indicates that the data associated with the received data request 118 is not contained in the main data array 308. In this example, the non-speculative indicator 330(7) for the buffer entry 320(7) is set to "0" to indicate the speculative state. In this example, the valid indicator 334(7) is set to "1" to indicate that the buffer entry 320(7) is valid. If no cache entries 320(0) to 320(B) are available in the speculative cache memory 318, the cache controller 300 may be configured to send a retry indicator as a data response 302 to the requestor in the processor 102 to instruct the requestor to retry the data request 118 at a later time. This provides more time for the data request 118 having the recorded deferred cache state updates stored in the speculative cache memory 318 to become non-speculative, which will cause its corresponding cache entry 320(0) to 320(B) to be used and / or reallocated, as described below with respect to Figure 6B discussed in more detail.

[0048] Reference again Fig. 6A The cache controller 300 in the non-speculative cache memory 114 is also configured to allocate a SAR entry 338(0) associated with instruction ID 1 in the SAR circuit 336 to record the deferral of the cache state update in the main data array 308 for the data request 118. Fig. 6AAs shown, instruction ID 1 is stored in instruction ID 340(0) of SAR entry 338(0). Since data request 118 results in a cache miss, MDA index 342(0) contains a null value because data for data request 118 is not stored in main data array 308. In this example, SB index "7" is stored in SB index 344(0) to point to buffer entry 320(7) allocated in speculative buffer memory 318, which records the speculative state of data request 118 associated with instruction ID 1. At this point, cache controller 300 can later search for instruction ID 1 in SAR circuit 336 when its associated data request 118 becomes non-speculative to determine buffer entry 320(0) to buffer entry 320(B) to update its corresponding speculative indicator 330(7) to a non-speculative state. Note that for SAR entry 338(1), a null value is stored in MDA index 342(0) because the data for data request 118 is not contained in main data array 308. Cache controller 300 is configured to write data for data request 118 associated with instruction ID contained in buffer entry 320(0) to buffer entry 320(B) in speculative buffer memory 318 with speculative indicator 330(7) as a non-speculative state. Figure 6B Shows Fig. 6A 1 receives an example of a commit indicator 328 identifying instruction ID 1 as being committed. In response, cache controller 300 is configured to search SAR circuit 336 to determine whether SAR entry 338 includes instruction ID 1 in instruction ID 340(0) through instruction ID 340(S) to indicate that an update of the cache state of the data request 118 associated with instruction ID 1 is deferred. In this example, instruction ID 1 is included in SAR entry 338(0) in response to the received data request 118 resulting from the processing of instruction ID 1, as shown in FIG. Fig. 6AAs shown and previously described. The cache controller 300 is configured to, in response to determining that instruction ID 1 is contained in SAR entry 338(0), consult SB index 344(0) to determine buffer entry 320(0) to buffer entry 320(B) associated with instruction ID 1. In this example, index "7" is stored in SB index 344(0) to point to buffer entry 320(7) in speculative buffer memory 318. Non-speculative indicator 330(7) is set to a non-speculative state, "1" in this example. In this manner, cache controller 300 can write data associated with data request 118 for instruction ID 1 recorded in buffer entry 320(7) in main data array 308. The cache controller 300 may wait to write the data request 118 for instruction ID 1 recorded in the buffer entry 320(7) in the primary data array 308 until a new buffer entry 320(0) to buffer entry 320(B) needs to be allocated in the speculative buffer memory 318 and there are no empty buffer entries 320(0) to buffer entry 320(B). The data associated with the data request 118 for instruction ID 1 may remain in the buffer entry 320(7) because subsequent data requests 118 for the same data based on their target addresses may be implemented as cache hits from the speculative buffer memory 318, as described above. When the cache controller 300 writes the data associated with the data request 118 for instruction ID 1 recorded in the buffer entry 320(7) in the primary data array 308, the in-cache indicator 332(7) will be set to indicate that the data is stored in the primary data array 308 according to the "1" indicator. Therefore, when the cache controller 300 needs to allocate new buffer entries 320(0) to 320(B) in the speculative buffer memory 318 for the new data request 118, the cache controller 300 may search for buffer entries 320(0) to 320(B) whose in-cache indicators are set to "1" in this example. This indicates that the data for buffer entries 320(0) to 320(B) has been written to the main data array 308 as non-speculative data, and therefore the associated buffer entries 320(0) to 320(B) may be deallocated and / or reallocated.

[0049] about Figure 3 SAR circuit 336 and speculative buffer memory 318 in Figure 6BIn the example of updating the speculative state of the tracking data request 118 to the non-speculative state, the instruction ID becoming non-speculative will eventually trigger the cache controller 300 to write the data for the data request 118 associated with the instruction ID into the main data array 308. As described above, the buffer entries 320(0) to 320(B) and their associated mapping SAR entries 338(0) to 338(S) for the instruction ID that has become non-speculative in the speculative buffer memory 318 will be deallocated in the speculative buffer memory 318 to make them available for another data request 118. However, other instruction IDs may be allocated in the SAR entries 338(0) to 338(S) in the SAR circuit 336, which are mapped to the same buffer entries 320(0) to 320(M) in the speculative buffer memory 318. For example, multiple data requests 118 may have the same target address. If a buffer entry 320(0) to a buffer entry 320(M) in the speculative buffer memory 318 that is mapped to a plurality of SAR entries 338(0) to SAR entries 338(S) is deallocated, the remaining SAR entries 338(0) to SAR entries 338(S) in the speculative buffer memory 318 that are mapped to the same buffer entry 320(0) to SAR entries 320(M) will not be aware that the buffer entry 320(0) to buffer entry 320(M) to which it points has been deallocated. Therefore, the instruction ID associated with such a SAR entry 338(0) to SAR entry 338(S) that later becomes non-speculative will lose its mapping to the speculative buffer memory 318, making it impossible to update the associated cache state. As discussed below, one approach to addressing this problem is to provide another level of indirect mapping between the SAR circuit 336 and the speculative buffer memory 318.

[0050] The SAR circuit 336 discussed above for tracking the speculative status of data requests 118 received by the non-speculative cache memory 114 may also be used in conjunction with a virtual fill buffer (VFB) circuit. As described below, the virtual fill buffer (VFB) circuit may be used to map SAR entries 338(0) to SAR entries 338(S) to buffer entries 320(0) to 320(B) in the speculative buffer memory 318. The VFB circuit may be used to track whether data associated with buffer entries 320(0) to 320(B) in the speculative buffer memory 318 becomes non-speculative and is written to the main data array 308 so that other instruction IDs may remain mapped to the VFB circuit. The VFB circuit can track whether the buffer entries 320(0) to 320(B) in the speculative buffer memory 318 associated with the remaining instruction IDs mapped from the SAR circuit 336 to the VFB circuit have been written to the main data array 308, so that cache status updates for such other mapped instruction IDs can be directly updated to the main data array 308 because the associated buffer entries 320(0) to 320(B) mapped thereto in the speculative buffer memory 318 will be deallocated.

[0051] Note, refer again Figure 3 The non-speculative cache memory 114 in Fig. 6A and 6B, when cache entries 310(0) to 310(M) are evicted from the primary data array 308 by the cache controller 300, the cache controller 300 may also update the cache entries 320(0) to 320(B) in the speculative buffer memory 318. For example, if a particular cache entry 310(0) to 310(M) in the primary data array 308 (e.g., by its set / way) is identified as a victim entry to be evicted by the cache controller 300, the cache controller 300 may be configured to search the cache entries 320(0) to 320(B) to determine whether there are any cache entries 320(0) to 320(B) in the speculative buffer memory 318 that correspond to the evicted cache entry 310(0) to 310(M). If so, such corresponding cache entry(s) 320(0)-320(B) may be invalidated by setting their corresponding valid indicators 334(0)-334(B) to an invalid state (e.g., to a "0" state). In this manner, if a new data request 118 is received in the non-speculative cache memory 114 with a target address corresponding to the evicted cache entry 310(0)-310(M), which would result in a cache miss to the primary data array 308, a cache hit would not erroneously occur in the speculative cache memory 318. In this regard, FIG. 7A to FIG. 7D Shows Figure 1 1. An example of a processor 102 in FIG. 10 issuing a data request 118 received by a non-speculative cache memory 114 in a cache memory system 106. In this example, the non-speculative cache memory includes an alternate SAR circuit 700 that can be mapped to entries in a virtual fill buffer (VFB) circuit 708 that is mapped to the speculative buffer memory 318 for tracking speculative data requests 118 and updating the cache status of such requests in the primary data array 308 when they become non-speculative. In this example, as Fig. 7AAs shown, three (3) data requests 118 are made to the non-speculative cache memory 114 identified by three (3) instruction IDs (instruction IDs 1, 4, and 8). The cache controller in the non-speculative cache memory 114 is configured to search the primary data array 308 and the speculative buffer memory 318 for data corresponding to the target addresses of the three data requests 118. In this example, the data corresponding to the target address of the data request 118 for instruction ID 1 is not contained in the primary data array 308 or the speculative buffer memory 318 of the non-speculative cache memory 114, resulting in a cache miss. The cache controller 300 performs a cache miss in a manner similar to Figure 3 The SAR circuit 336 Fig. 7A SAR entry 702(0) is allocated in SAR circuit 700 shown in FIG. 1 . Instruction ID 1 is stored in instruction ID 704(0) in SAR entry 702(0). Cache controller 300 also allocates SAR entry 702(0) in SAR circuit 700 shown in FIG. 1 . Fig. 7A 1. As shown, a VFB entry 710(7) is allocated in the VFB circuit 708. An index "7" corresponding to the allocated VFB entry 710(7) is stored in the VFB index 706(0) in the SAR circuit 700 to map the SAR entry 702(0) for instruction ID 1 to the VFB entry 710(7) in the VFB circuit 708. The in-cache indicator 714(7) in the SAR entry 702(7) is set to the data associated with the data request 118 initiated from instruction ID 1 that is not present in the primary data array 308 because the data request 118 associated with instruction ID 1 resulted in a cache miss. Therefore, the MDA index 716(7) in the VFB entry 710(7) is set to "0" or a null value because it does not point to a location in the primary data array 308. However, the speculative buffer (SB) index 718 ( 7 ) in the VFB circuit 708 is set to “4” to map the VFB entry 710 ( 7 ) to the buffer entry 320 ( 4 ) in the speculative buffer memory 318 , which contains the data of the allocated buffer entry 320 ( 4 ) in the speculative buffer memory 318 received from the fill response 306 .

[0052] The cache controller 300 in the non-speculative cache memory 114 is also configured to search the primary data array 308 and the speculative buffer memory 318 for data corresponding to the target address of the data request 118 for instruction IDs 4 and 8. In this example, both searches result in cache hits to the speculative buffer memory 318 because these instructions have the same target address as the data request 118 for instruction ID 1, and the cache controller 300 has already filled this data from the fill response 306 into the cache entry 320(4) in the speculative buffer memory 318. Therefore, both SAR entries 702(0) and 702(2) with instruction IDs 1 and 7 in instruction IDs 704(0) and 704(2) are also mapped to VFB index "7" in their corresponding VFB indexes 706(0), 706(2). Thus, providing VFB circuit 708 allows multiple SAR entries (SAR entry 702(1) to SAR entry 702(2) in this example) to be mapped to the same VFB index, which can be mapped to buffer entry 320(0) to buffer entry 320(B) in speculative buffer memory 318 to provide another level of indirect mapping.

[0053] Note also that, as an option, when the current SAR entry 702(0) to SAR entry 702(S) in the SAR circuit 700 is allocated in response to the new data request 118, if there is an older SAR entry 702(0) to SAR entry 702(S) pointing to the same VFB entry 710 in the VFB circuit 708, the current SAR entry 702(0) to SAR entry 702(S) may be folded into the older SAR entry 702(0) to SAR entry 702(S). The current SAR entry 702(0) to SAR entry 702(S) may replace the older SAR entry 702(0) to SAR entry 702(S) or be ignored so that the new SAR entry 702(0) to SAR entry 702(S) is not allocated. For example, in Figure 7B In the SAR circuit 700 in FIG. 7 , if both SAR entries 702(0) and 702(1) are associated with instruction ID 1, then both SAR entries 702(0) and 702(1) can be provided as one SAR entry 702 because both point to the same VFB entry 710(7). Figure 7BAs shown, the non-speculative cache memory 114 in this example receives the commit indicator 328 for instruction ID 1 to indicate that instruction ID 1 has been committed in the processor 102, and therefore the data associated with the data request 118 for instruction ID 1 in the cache entry 320(4) in the speculative cache memory 318 is now non-speculative. At this point, the cache controller 300 changes the NS indicator 330(4) for the cache entry 320(4) to "1" to indicate that the entry is non-speculative. In addition, as shown in FIG. Figure 7C As shown, cache controller 300 also changes in cache entry 320(4) in cache to "1" to indicate that data associated with data request 118 for instruction ID 1 is included in primary data array 308 in response to data being received from higher level memory in data response 302. When cache entry 320(4) is evicted, cache entry 320(4) is reclaimed based on its NS indicator 330(4) indicating that the data is being received from higher level memory. Figure 7C In the non-speculative state shown, cache controller 300 may write data associated with data request 118 for instruction ID 1 recorded in cache entry 320(4) in primary data array 308. Fig.7D As shown, instruction IDs 4 and 8 in SAR entries 702(0), 702(1) mapped to VFB entry 710(7) can use in-cache indicator 714(7) and MDA index 716(7) to know the locations of cache entries 310(0) to 310(M) to be updated when instruction IDs 4 and 8 become non-speculative. Therefore, if cache controller 300 deallocates buffer entry 320(4) before instruction IDs 4 and 8 become non-speculative, VFB circuit 708 saves the information needed to update the cache state of data for data request 118 associated with instruction IDs 4 and 8 in primary data array 308 using in-cache indicator 714(7) and MDA index 716(7).

[0054] Note that for any of the above examples, the NS indicators 330(0) to NS indicators 330(B) in the speculative buffer memory 318 in the non-speculative cache memory 114 may be further used by the cache controller 300 to influence the order in which the buffer entries 320(0) to 320(B) are evicted from the speculative buffer memory 318. Recall that when evicting the buffer entries 320(0) to 320(B), if the NS indicators 330(0) to NS indicators 330(B) are set to a non-speculative state for the buffer entries 320(0) to 320(B), the corresponding data for the buffer entries 320(0) to 320(B) will be written to the main memory 108, otherwise, the buffer entries 320(0) to 320(B) are discarded. Assuming a basic fill buffer replacement strategy (e.g., FIFO, LRU, PLRU, MRU, random, SRRIP, DRRIP, etc.), an optional enhanced replacement strategy may be adopted. If the NS indicators 330(0) to NS indicators 330(B) of all buffer entries 320(0) to 320(B) are marked as non-speculative states, the cache controller 300 may adopt the basic replacement strategy to replace the buffer entries 320(0) to 320(B). If the NS indicators 330(0) to NS indicators 330(B) for one buffer entry 320(0) to 320(B) are marked as non-speculative states, such buffer entry 320(0) to 320(B) may be replaced first. If NS indicators 330(0) to NS indicators 330(B) for more than one buffer entry 320(0) to buffer entry 320(B) are marked as a non-speculative state, the basic replacement policy can be applied to all buffer entries 320(0) to NS indicators 330(B) having NS indicators 330(0) to NS indicators 330(B) marked as a non-speculative state. If all of the cache entries 320(0) to 320(B) have NS indicators 330(0) to NS indicators 330(B) marked as speculative, any of the following replacement strategies may be employed, as examples: a basic replacement strategy, selecting the most recently used (MRU) cache entry 320(0) to 320(B), selecting the least recently used (LRU) cache entry 320(0) to 320(B), selecting the last inserted cache entry 320(0) to 320(B), selecting the first inserted cache entry 320(0) to 320(B), and selecting a random cache entry 320(0) to 320(B). A combination of the above replacement strategies may be selected based on additional meta-information about the cache line requester (e.g., MRU if it may be flushed, LRU if it is streaming, etc.).

[0055] In addition, in the case where the non-speculative cache memory 114 can receive data requests 118 from multiple CPU cores 110(1) to CPU core 110(N), the SAR circuit 336, 700 can be implemented to maintain a record of all data accesses for the data request 118 and identify the CPU core 110(0) to CPU core 110(N) as the requestor. The VFB circuit 708 can be shared among multiple CPU cores 110(1) to CPU core 110(N). In response to the data request 118, the non-speculative cache memory 114 can be configured to send back a commit identifier to allow the target commit message of the CPU core 110(1) to CPU core 110(N) to be sent to the non-speculative cache memory 114(1) to the non-speculative cache memory 114(X). This can reduce Figure 1 In the embodiment of the present invention, the processor 102 can transmit instruction commit information bundles to reduce the traffic on the interconnect bus 117 between the CPU cores 110(0) to the CPU cores 110(N) and the cache memories 114(1) to the cache memories 114(X). In addition, the processor 102 can also send bundle messages of instruction commit information to reduce the traffic on the interconnect bus 117, instead of sending one commit message for each non-speculative data request 118. The instruction commit information bundle can be explicit, where each instruction ID for the data request 118 is specified in the bundle message, or implicit, where the instruction ID implies that all instruction IDs lower than the non-speculative instruction ID are also non-speculative.

[0056] Figure 8 8 is a block diagram of an exemplary processor-based system 800 that includes a processor 802 (eg, a microprocessor) that includes instruction processing circuitry 804. For example, the processor-based system 800 may be Figure 1 The processor-based system 100 in FIG. 8 is shown in FIG. 8A . For example, the instruction processing circuit 804 may be Figure 2800. The processor-based system 800 may be one or more circuits included in an electronic board, such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing board, a mobile device, or any other device, and may represent, for example, a server or a user's computer. In this example, the processor-based system 800 includes a processor 802. The processor 802 represents one or more general-purpose processing circuits, such as a microprocessor, a central processing unit, and the like. More specifically, the processor 802 may be an EDGE instruction set microprocessor, or other processor that implements an instruction set that supports explicit consumer naming for transmitting production values ​​generated by the execution of producer instructions. The processor 802 is configured to execute the processing logic in the instruction for performing the operations and steps discussed herein. In this example, the processor 802 includes an instruction cache 808 for temporary fast access memory storage of instructions accessible by the instruction processing circuit 804. Instructions extracted or pre-fetched from a memory (such as from a main memory 810 via a system bus 812) are stored in the instruction cache 808. Instruction processing circuitry 804 is configured to process instructions fetched into instruction cache 808 and process the instructions for execution.

[0057] The processor 802 may include a local cache memory 814 to store cached data in the main memory 810. A cache memory 816 external to the processor 802 may also be provided between the local cache memory 814 and the main memory 810 to provide a cache memory system 818. The cache memories 814, 816 in the cache memory system 818 may include Figure 1 , 3 , FIG. 5A to FIG. 5B , FIG. 6A to FIG. 6B and FIG. 7A to FIG. 7D Any of cache memories 114 ( 1 ) to cache memories 114 (X) in the embodiment of the present invention and configured to defer updating a cache state in response to receiving a data request from processor 802 until the data request becomes non-speculative.

[0058] The processor 802 and the main memory 810 are coupled to a system bus 812 and may be coupled to peripheral devices included in the processor-based system 800. As is well known, the processor 800 communicates with these other devices by exchanging address, control, and data information via the system bus 812. For example, the processor 802 may transmit a bus transaction request to a memory controller 819 in the main memory 810 as an example of a slave device. Although Figure 8810 , but multiple system buses 812 may be provided, each of which constitutes a different structure. In this example, the memory controller 819 is configured to provide a memory access request to a memory array 820 in the main memory 810. The memory array 820 includes an array of storage bit cells for storing data. As non-limiting examples, the main memory 810 may be a read-only memory (ROM), a flash memory, a dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM)), and a static memory (e.g., a flash memory, a static random access memory (SRAM), etc.).

[0059] Other devices may be connected to the system bus 812. Figure 8 As shown, for example, these devices may include a main memory 810, one or more input devices 822, one or more output devices 824, a modem 826, and one or more display controllers 828. The (multiple) input devices 822 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The (multiple) output devices 824 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. The modem 826 may be any device configured to allow data to be exchanged with the network 830. The network 830 may be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), Bluetooth TM The modem 826 may be configured to support any type of communication protocol desired. The processor 802 may also be configured to access the display controller 828 via the system bus 812 to control information sent to one or more displays 832. The display(s) 832 may include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.

[0060] Figure 8 The processor-based system 800 in FIG. 8 may include an instruction set 834 to be executed by the processor 802 for any application desired according to the instructions. The instructions 834 may be stored in the main memory 810, the processor 802, and / or the instruction cache 808 as examples of non-transitory computer-readable media 836. The instructions 834 may also reside completely or at least partially within the main memory 810 and / or within the processor 802 during its execution. The instructions 834 may also be transmitted or received over the network 830 via the modem 826, so that the network 830 includes the computer-readable medium 836.

[0061] Although the computer-readable medium 836 is shown as a single medium in the exemplary embodiment, the term "computer-readable medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more instruction sets. The term "computer-readable medium" should also be considered to include any medium that can store, encode, or carry an instruction set executed by a processing device and cause the processing device to perform any one or more methods of the embodiments disclosed herein. Therefore, the term "computer-readable medium" should be understood to include, but is not limited to, solid-state memories, optical media, and magnetic media.

[0062] The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be composed of hardware components or may be embodied in machine executable instructions, which may be used to cause a general or special purpose processor programmed with the instructions to perform the steps. Alternatively, the steps may be performed by a combination of hardware and software.

[0063] The embodiments disclosed herein may be provided as a computer program product or software, which may include a machine-readable medium (or computer-readable medium) having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform a process according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes: a machine-readable storage medium (e.g., a ROM, a random access memory ("RAM"), a disk storage medium, an optical storage medium, a flash memory device, etc.), etc.

[0064] Unless otherwise specifically noted and as is clear from the foregoing discussion, it should be understood that throughout this specification, discussions using terms such as "processing," "computing," "determining," "displaying," and the like refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission, or display devices.

[0065] The algorithms and displays presented herein have no inherent relevance to any particular computer or other device. Various systems can be used together with the program according to the teachings herein, or it may prove convenient to construct a more specialized device to perform the required method steps. The required structure of various these systems will be clear from the above description. In addition, the embodiments described herein are not described with reference to any specific programming language. It should be understood that a variety of programming languages ​​can be used to implement the teachings of the embodiments described herein.

[0066] Those skilled in the art will further understand that the various illustrative logical blocks, modules, circuits, and algorithms described in conjunction with the embodiments disclosed herein may be implemented as electronic hardware, instructions stored in a memory or another computer-readable medium and executed by a processor or other processing device, or a combination of the two. As an example, the components of the distributed antenna system described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein may be any type and size of memory and may be configured to store any type of desired information. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functions. How such functions are implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. A technician may implement the described functions in different ways for each specific application, but such implementation decisions should not be interpreted as causing a deviation from the scope of the present embodiment.

[0067] The various illustrative logical blocks, modules, and circuits described in conjunction with the embodiments disclosed herein may be implemented or executed with a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. In addition, the controller may be a processor. The processor may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration).

[0068] The embodiments disclosed herein may be embodied in hardware and in instructions stored in hardware, and may reside in, for example, RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integrated with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. In an alternative, the processor and storage medium may reside in a remote station, a base station, or a server as discrete components.

[0069] It should also be noted that the operational steps described in any exemplary embodiment herein are described to provide examples and discussions. The described operations can be performed in many different sequences that are different from the sequences shown. In addition, the operations described in a single operational step can actually be performed in a plurality of different steps. In addition, one or more operational steps discussed in the exemplary embodiment can be combined. It will also be understood by those skilled in the art that information and signals can be represented using any variety of processes and technologies. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that can be used as reference in the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0070] Unless otherwise expressly stated, it is by no means intended that any method set forth herein be interpreted as requiring that its steps be performed in a particular order. Therefore, if a method claim does not actually recite the order in which its steps are followed, or if the steps are not otherwise specifically stated in the claims or specification to be limited to a particular order, it is by no means intended that any particular order can be inferred. It is clear to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the present invention. Since modifications, combinations, sub-combinations, and variations of the disclosed embodiments that incorporate the spirit and essence of the present invention can be conceived by those skilled in the art, the present invention should be interpreted as including all content within the scope of the appended claims and their equivalents.

Claims

1. A non-speculative cache memory in a processor-based system, comprising: a primary data array comprising a plurality of cache entries each configured to store cache data associated with a memory address in a memory system of the processor-based system; a speculative cache memory comprising a plurality of cache entries, each of the plurality of cache entries comprising: a data entry configured to store cache data associated with a memory address in the memory system; and A cache controller configured to: receiving a data request including a target address and an instruction identification ID from a requester, the instruction identification identifying a load instruction, the load instruction including the target address to be processed by a processor in the processor-based system; searching the primary data array for a cache entry associated with the target address of the data request; searching, in the speculative cache memory, a cache entry associated with the target address of the data request; sending a data response to the data request to the requester based on cache data in the primary data array associated with the target address and cache data in a buffer entry in the speculative cache memory associated with the target address; receiving a commit indicator comprising an instruction ID of a non-speculative instruction; and In response to the instruction ID received in the commit indicator indicating that the load instruction of the data request is non-speculative: A cache state of a cache entry in the primary data array associated with the target address of the data request is updated.

2. The non-speculative cache memory of claim 1 , wherein: The cache controller is further configured to determine whether a cache entry in the primary data array is associated with the target address of the data request; and In response to a cache entry in the primary data array being associated with the target address of the data request, the cache controller is configured to send the data response to the data request to the requester, the data response including cache data in the cache entry in the primary data array having the target address associated with the target address of the data request.

3. The non-speculative cache memory of claim 2 , wherein the cache controller is configured to, in response to the instruction ID received in the commit indicator indicating that the load instruction of the data request is non-speculative, update the cache state, the cache state comprising a cache replacement state of the cache entry in the primary data array associated with the target address of the data request.

4. The non-speculative cache memory according to claim 3, further comprising a speculative access record SAR circuit, the SAR circuit being configured to store SAR entries including an instruction ID entry and a main data array entry; The cache controller is further configured to: In response to a cache entry in the primary data array being associated with the target address of the data request, the cache controller is further configured to: allocating a SAR entry in the SAR circuit, the SAR entry comprising an instruction ID entry and a primary data array entry, the instruction ID entry comprising the instruction ID of the load instruction of the data request, the primary data array entry comprising an index to a cache entry in the primary data array associated with the target address of the data request; and In response to the instruction ID received in the commit indicator indicating that the load instruction of the data request is non-speculative: determining whether the received instruction ID is contained in an instruction ID entry in a SAR entry in the SAR circuit; and In response to determining that the received instruction ID is contained in a SAR entry in the SAR circuit, updating the cache replacement state of the cache entry in the primary data array, the cache replacement state corresponding to the index in the primary data array entry in the SAR entry containing the received instruction ID.

5. The non-speculative cache memory of claim 2 , wherein the cache controller is further configured to, in response to a cache entry in the primary data array not being associated with the target address of the data request: determining whether a cache entry in the speculative cache memory is associated with the target address of the data request; and In response to a buffer entry in the speculative buffer memory being associated with the target address of the data request, the cache controller is configured to send the data response to the data request to the requester, the data response including cache data in the buffer entry in the speculative buffer memory having the target address associated with the target address of the data request.

6. The non-speculative cache memory of claim 5 , wherein the cache controller is further configured to: in response to the instruction ID received in the commit indicator indicating that the load instruction of the data request is non-speculative, The cache data in the cache entry in the speculative cache memory having the target address associated with the target address of the data request is written to a cache entry in the primary data array.

7. The non-speculative cache memory of claim 6 , wherein the cache controller is further configured to: in response to the received instruction ID in the commit indicator indicating that the load instruction of the data request is non-speculative: The cache state is updated, the cache state comprising a cache replacement state of the cache entry in the primary data array associated with the target address of the data request.

8. The non-speculative cache memory of claim 6, further comprising a speculative access record (SAR) circuit configured to store SAR entries, the SAR entries comprising an instruction ID entry and a speculative cache memory index entry; The cache controller is further configured to: In response to a buffer entry in the speculative buffer memory being associated with the target address of the data request: allocating a SAR entry in the SAR circuit, the SAR entry comprising an instruction ID entry and a speculative buffer memory index entry, the instruction ID entry comprising the instruction ID of the load instruction of the data request, the speculative buffer memory index entry comprising an index to a buffer entry in the speculative buffer memory associated with the target address of the data request; as well as In response to the instruction ID received in the commit indicator indicating that the load instruction of the data request is non-speculative: determining whether the received instruction ID is contained in an instruction ID entry in a SAR entry in the SAR circuit; as well as In response to determining that the received instruction ID is contained in a SAR entry in the SAR circuit, a cache replacement state of the cache entry in the primary data array associated with the target address of the data request is updated.

9. The non-speculative cache memory of claim 6, wherein: Each cache entry in the speculative cache memory further includes a non-speculative indicator indicating whether the cache entry is non-speculative; and The cache controller is further configured to: In response to a buffer entry in the speculative buffer memory being associated with the target address of the data request: A non-speculative indicator in the cache entry in the speculative buffer memory associated with the target address of the data request is set to a speculative state.

10. The non-speculative cache memory of claim 9, wherein the cache controller is further configured, in response to the received instruction ID in the commit indicator indicating that the load instruction of the data request is non-speculative: The non-speculative indicator in the cache entry in the speculative buffer memory associated with the target address of the data request is set to a non-speculative state.

11. The non-speculative cache memory of claim 5, wherein the cache controller is further configured to, in response to a cache entry in the speculative cache memory not being associated with the target address of the data request: sending the data request to a next higher level memory in the processor-based system; receiving data for the data request from the next higher level memory; determining whether a cache entry in the speculative cache memory is available for storing cache data; as well as In response to determining that a buffer entry in the speculative buffer memory is available for storing cache data, the data received from the next higher level memory for the data request is written to an available buffer entry in the speculative buffer memory and an available buffer entry associated with the target address of the data request.

12. The non-speculative cache memory of claim 11, wherein the cache controller is further configured to, in response to determining that a cache entry in the speculative cache memory is not available to store cache data, send a retry indicator to the requestor to retry the data request.

13. The non-speculative cache memory of claim 11 , wherein the cache controller is configured, in response to the received instruction ID in the commit indicator indicating that the load instruction of the data request is non-speculative: The cache state of the cache entry in the primary data array associated with the target address of the data request is updated by being configured to write data for the data request in the cache entry in the speculative buffer memory associated with the target address of the data request to the cache entry in the primary data array associated with the target address of the data request.

14. The non-speculative cache memory of claim 13, wherein the cache controller is further configured to select a buffer entry from the plurality of buffer entries in the speculative cache memory to be evicted from the speculative cache memory based on a speculative state in a non-speculative indicator of a corresponding buffer entry.

15. The non-speculative cache memory of claim 14, wherein the cache controller is configured to select the cache entry to be evicted from the speculative cache memory according to a first replacement policy if all of the non-speculative indicators of the respective cache entries indicate a non-speculative state.

16. The non-speculative cache memory of claim 15 , wherein the cache controller is configured to select the cache entry to be evicted from the speculative cache memory according to a second replacement policy different from the first replacement policy if all of the non-speculative indicators of the respective cache entries indicate a speculative state.

17. The non-speculative cache memory of claim 11, wherein: Each cache entry in the speculative cache memory further includes: a non-speculative indicator indicating whether the cache entry is non-speculative; and The cache controller is further configured to: In response to a buffer entry in the speculative buffer memory being associated with the target address of the data request: setting a non-speculative indicator in the cache entry in the speculative buffer memory associated with the target address of the data request to a speculative state; In response to the instruction ID received in the commit indicator indicating that the load instruction of the data request is non-speculative: setting the non-speculative indicator in the cache entry in the speculative cache memory associated with the target address of the data request to a non-speculative state; and In response to the non-speculative indicator in the cache entry associated with the target address of the data request in the speculative buffer memory being set to a non-speculative state: The cache state of the cache entry in the primary data array associated with the target address of the data request is updated by being configured to write data for the data request in the cache entry in the speculative buffer memory associated with the target address of the data request to the cache entry in the primary data array associated with the target address of the data request.

18. The non-speculative cache memory of claim 17, further comprising a speculative access record SAR circuit configured to store SAR entries, the SAR entries comprising an instruction ID entry and a speculative cache memory index entry; The cache controller is further configured to: In response to a cache entry in the speculative cache memory being unassociated with the target address of the data request: allocating a SAR entry in the SAR circuit, the SAR entry comprising an instruction ID entry storing the instruction ID of the load instruction of the data request and the speculative buffer memory index entry storing an index to a buffer entry in the speculative buffer memory associated with the target address of the data request; and In response to the instruction ID received in the commit indicator indicating that the load instruction of the data request is non-speculative: determining, based on an index in the speculative buffer memory index entry in the SAR entry in the SAR circuit having an instruction ID including the received instruction ID, that the buffer entry in the speculative buffer memory associated with the target address of the data request is set to a non-speculative state; The cache controller is configured to: The non-speculative indicator in the determined ones of the buffer entries in the speculative buffer memory associated with the target address of the data request is set to a non-speculative state.

19. The non-speculative cache memory of claim 18, wherein each SAR entry in the SAR circuit further comprises a central processing unit (CPU) core ID entry configured to store a CPU core ID, the CPU core ID identifying a requestor of a received data request further comprising the CPU core ID as the requestor; The cache controller is further configured to, in response to the cache entry in the speculative cache memory being unassociated with the target address of the data request, store the CPU core ID in the received data request in the CPU core ID entry of the SAR entry allocated in the SAR circuit.

20. The non-speculative cache memory of claim 19, wherein the cache controller is further configured to, in response to the cache entry in the speculative cache memory being unassociated with the target address of the data request, send a cache ID identifying the non-speculative cache memory to a requesting CPU.

21. The non-speculative cache memory of claim 19, wherein the cache controller is further configured to: receiving a commit indicator from a requesting CPU, the commit indicator comprising a plurality of instruction IDs, each of the instruction IDs identifying a load instruction for a non-speculative data request; and For each of the plurality of instruction IDs received where the commit indicator indicates that the load instruction of the data request is non-speculative, determining that the buffer entry in the speculative buffer memory associated with the target address of the data request is set to a non-speculative state based on an index in the speculative buffer memory index entry in the SAR entry in the SAR circuit having an instruction ID including the received instruction ID.

22. The non-speculative cache memory of claim 21 , wherein in response to the instruction ID received in the commit indicator indicating that the load instruction of the data request is non-speculative, the cache controller is further configured to: determining any instruction ID stored in any instruction ID entry in the SAR entries in the SAR circuit that is younger than the received instruction ID; and The non-speculative indicator in the SAR entry having an instruction ID in its instruction ID entry that is younger than the received instruction ID is set to a non-speculative state.

23. The non-speculative cache memory of claim 22 , wherein the cache controller is further configured to, in response to determining that any instruction ID stored in any instruction ID entry in the SAR entries in the SAR circuit is younger than the received instruction ID, de-allocate the SAR entry in the SAR circuit having an instruction ID in its instruction ID entry that is younger than the received instruction ID.

24. The non-speculative cache memory of claim 17, further comprising: a speculative access record SAR circuit configured to store SAR entries, the SAR entries including an instruction ID entry and a virtual fill buffer VFB index entry; as well as A VFB circuit is configured to store VFB entries, wherein the VFB entries include instruction ID entries and VFB index entries; The cache controller is further configured to: In response to a cache entry in the speculative cache memory not being associated with the target address of the data request: allocating a VFB entry in the VFB circuit, the VFB entry comprising an instruction ID entry and a VFB index entry, the instruction ID entry comprising the instruction ID of the load instruction of the data request, the VFB index entry comprising an index to a buffer entry in the speculative buffer memory associated with the target address of the data request; as well as allocating SAR entries in the SAR circuit, the SAR entries including the instruction ID entry and the VFB index entry, the instruction ID entry storing the instruction ID of the load instruction of the data request and the VFB index entry storing an index to a VFB entry in the VFB circuit having an instruction ID entry containing the instruction ID; as well as In response to the instruction ID received in the commit indicator indicating that the load instruction of the data request is non-speculative: determining a VFB entry in the VFB circuit having an instruction ID entry containing the indexed instruction ID based on an index in the VFB index in a SAR entry in the SAR circuit having an instruction ID entry containing the received instruction ID; and determining the buffer entry in the speculative buffer memory associated with the target address of the data request that is set to a non-speculative state based on an index in the VFB index entry in the determined VFB entry in the VFB circuit; The cache controller is configured to: The non-speculative indicator in the determined ones of the buffer entries in the speculative buffer memory associated with the target address of the data request is set to a non-speculative state.

25. The non-speculative cache memory of claim 24, wherein the cache controller is further configured, in response to allocating the SAR entry in the SAR circuit: determining whether another SAR entry included in the SAR circuit includes the instruction ID in its instruction ID entry and the VFB index entry in its VFB entry; and In response to determining that the other SAR entry is included in the SAR circuit, the SAR entry in the SAR circuit is deallocated.

26. The non-speculative cache memory of claim 1, wherein the cache controller is further configured to evict a cache entry in the speculative cache memory in response to a cache entry in the primary data array corresponding to a memory address corresponding to the cache entry being evicted.

27. A method of updating cache state in a non-speculative cache memory in a processor-based system, comprising: receiving a data request including a target address and an instruction identification ID from a requester, the instruction identification ID identifying a load instruction, the load instruction including the target address to be processed by a processor in the processor-based system; searching, in a primary data array, a cache entry of a plurality of cache entries associated with the target address of the data request, the plurality of cache entries each configured to store cache data associated with a memory address in a memory system of the processor-based system; searching, in a speculative cache memory, a cache entry of a plurality of cache entries associated with the target address of the data request, the plurality of cache entries each configured to store cache data associated with a memory address in the memory system; sending a data response to the data request to the requester based on the cache entry in the primary data array associated with the target address and the cache data in the cache entry in the speculative cache memory associated with the target address; receiving a commit indicator, the commit indicator comprising an instruction ID of a non-speculative instruction; as well as In response to the instruction ID received in the commit indicator indicating that the load instruction of the data request is non-speculative, updating a cache state of a cache entry in the primary data array associated with the target address of the data request.

28. The method according to claim 27: Also includes: determining whether a cache entry in the primary data array is associated with the target address of the data request; as well as Comprising: in response to a cache entry in the main data array being associated with the target address of the data request, sending the data response to the data request to the requester, the data response including cache data in the cache entry in the main data array having the target address associated with the target address of the data request.

29. The method according to claim 28, comprising: In response to the instruction ID received in the commit indicator indicating that the load instruction of the data request is non-speculative, updating the cache state, the cache state including a cache replacement state of the cache entry in the primary data array associated with the target address of the data request.

30. The method of claim 28, further comprising: In response to a cache entry in the primary data array not being associated with the target address of the data request: determining whether a cache entry in the speculative cache memory is associated with the target address of the data request; and In response to a buffer entry in the speculative buffer memory being associated with the target address of the data request, sending the data response to the data request to the requester, the data response including cache data in the buffer entry in the speculative buffer memory having the target address associated with the target address of the data request.

31. The method of claim 30, further comprising: In response to the instruction ID received in the commit indicator indicating that the load instruction of the data request is non-speculative, writing the cache data in the cache entry in the speculative buffer memory having the target address associated with the target address of the data request to a cache entry in the primary data array.

32. The method according to claim 31, comprising: In response to the instruction ID received in the commit indicator indicating that the load instruction of the data request is non-speculative, updating the cache state, the cache state including a cache replacement state of the cache entry in the primary data array associated with the target address of the data request.

33. The method of claim 30, further comprising: In response to a cache entry in the speculative cache memory being unassociated with the target address of the data request: sending the data request to a next higher level memory in the processor-based system; receiving data for the data request from the next higher level memory; determining whether a cache entry in the speculative cache memory is available for storing cache data; as well as In response to determining that a buffer entry in the speculative buffer memory is available for storing cache data, the data received from the next higher level memory for the data request is written to an available buffer entry in the speculative buffer memory associated with the target address of the data request.

34. The method of claim 33, further comprising: In response to determining that a cache entry in the speculative cache memory is not available to store cache data, a retry indicator is sent to the requestor to retry the data request.

35. The method of claim 33, comprising: In response to the instruction ID received in the commit indicator indicating that the load instruction of the data request is non-speculative, updating the cache state of the cache entry in the primary data array associated with the target address of the data request, comprising: Data for the data request in the cache entry associated with the target address of the data request in the speculative cache memory is written to a cache entry associated with the target address of the data request in the primary data array.

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