Constant slice header parameters signaled at higher syntax levels for video codecs

Abstract

An example device includes a memory configured to store video data and one or more processors implemented in circuitry and communicatively coupled to the memory. The one or more processors are configured to determine whether a maximum number of merge candidates for a slice of the video data is equal to a first value. The one or more processors are configured to infer a value of a first syntax element to be equal to a second value based at least in part on the maximum number of merge candidates for the slice being equal to the first value, the first syntax element indicating the maximum number of merge candidates and the maximum number of merge candidates for a non-rectangular codec mode. The one or more processors are further configured to decode the slice based on the maximum number of merge candidates and the first syntax element.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Application No. 16 / 948,084, filed on September 2, 2020, which claims the benefit of U.S. Provisional Application No. 62 / 896,459, filed on September 5, 2019, each of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to video encoding and video decoding. Background Art

[0003] Digital video capabilities can be incorporated into a wide range of devices, including digital televisions, digital direct broadcast systems, wireless broadcast systems, personal digital assistants (PDAs), laptop or desktop computers, tablet computers, e-book readers, digital cameras, digital recording devices, digital media players, video game devices, video game consoles, cellular or satellite radio telephones, so-called "smart phones", video teleconferencing devices, video streaming devices, etc. Digital video devices implement video codec technologies, such as those described in the standards defined by the following: MPEG-2; MPEG-4; ITU-T H.263; ITU-T H.264 / MPEG-4 Part 10; Advanced Video Codec (AVC); ITU-T H.265 / High Efficiency Video Codec (HEVC), and extensions of such standards. By implementing such video codec technologies, video devices can more efficiently send, receive, encode, decode, and / or store digital video information.

[0004] Video coding techniques include spatial (intra-picture) prediction and / or temporal (inter-picture) prediction to reduce or remove redundancy inherent in video sequences. For block-based video codecs, video slices (e.g., video pictures or portions of video pictures) may be partitioned into video blocks, which may also be referred to as codec tree units (CTUs), codec units (CUs), and / or codec nodes. Video blocks in an intra-coded (I) slice of a picture are encoded using spatial prediction relative to reference samples in neighboring blocks in the same picture. Video blocks in an inter-coded (P or B) slice of a picture may use spatial prediction relative to reference samples in neighboring blocks in the same picture, or temporal prediction relative to reference samples in other reference pictures. Pictures may be referred to as frames, and reference pictures may be referred to as reference frames. Summary of the Invention

[0005] Generally, this disclosure describes techniques for video codecs and, more specifically, describes signaling techniques at the picture parameter set (PPS) and slice header levels. The disclosed signaling techniques can avoid conflicting syntax elements and reduce signaling overhead when compared to certain codec standards.

[0006] In one example, a method includes determining, by one or more processors, whether a maximum number of merge candidates for a slice of video data is equal to a first value; inferring, by the one or more processors, a value of a first syntax element to be equal to a second value based at least in part on the maximum number of merge candidates for the slice being equal to the first value, the first syntax element indicating the maximum number of merge candidates and a maximum number of merge candidates for a non-rectangular codec mode; and decoding, by the one or more processors, the slice based on the maximum number of merge candidates and the first syntax element.

[0007] In another example, a device includes a memory configured to store video data and one or more processors implemented in circuitry and communicatively coupled to the memory, the one or more processors configured to: determine whether a maximum number of merge candidates for a slice of the video data is equal to a first value; infer a value of a first syntax element to be equal to a second value based at least in part on the maximum number of merge candidates for the slice being equal to the first value, the first syntax element indicating the maximum number of merge candidates and the maximum number of merge candidates for a non-rectangular codec mode; and decode the slice based on the maximum number of merge candidates and the first syntax element.

[0008] In another example, an apparatus includes means for determining whether a maximum number of merge candidates for a slice of video data is equal to a first value; means for inferring a value of a first syntax element to be equal to a second value based at least in part on the maximum number of merge candidates for the slice being equal to the first value, the first syntax element indicating the maximum number of merge candidates and the maximum number of merge candidates for a non-rectangular codec mode; and means for decoding the slice based on the maximum number of merge candidates and the value of the first syntax element.

[0009] In another example, a non-transitory computer-readable storage medium having instructions stored thereon that, when executed by one or more processors, cause the one or more processors to determine whether a maximum number of merge candidates for a slice of video data is equal to a first value; infer a value of a first syntax element to be equal to a second value based at least in part on the maximum number of merge candidates for the slice being equal to the first value, the first syntax element indicating the maximum number of merge candidates and the maximum number of merge candidates for a non-rectangular codec mode; and decode the slice based on the maximum number of merge candidates and the first syntax element.

[0010] The details of one or more examples are set forth in the accompanying drawings and the description below.Other features, objects, and advantages will be apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a block diagram illustrating an example video encoding and decoding system that may perform the techniques of this disclosure.

[0012] Figure 2A and Figure 2B is a conceptual diagram illustrating an example quadtree binary tree (QTBT) structure and a corresponding codec tree unit (CTU).

[0013] Figure 3 is a block diagram illustrating an example video encoder that may perform the techniques of this disclosure.

[0014] Figure 4 is a block diagram illustrating an example video decoder that may perform the techniques of this disclosure.

[0015] Figure 5 is a flow chart illustrating a signaling technique according to the present disclosure.

[0016] Figure 6 is a flow chart illustrating a method of encoding video data.

[0017] Figure 7 is a flow chart illustrating a method of decoding video data. DETAILED DESCRIPTION

[0018] Some video codec standards may allow for conflicting signaling. When a video decoder receives conflicting syntax elements, it may be unable to determine how to decode the video data. Additionally, a video encoder may waste signaling bandwidth by signaling a syntax element that may conflict with another syntax element.

[0019] According to the technology of the present disclosure, a video decoder can infer the value of one syntax element based on the value of another syntax element. In this way, conflicting syntax elements can be avoided and signaling notification bandwidth can be saved. For example, a video decoder can determine whether the value of a first syntax element indicating the maximum number of merge candidates is equal to a first value. The video decoder can infer the value of the first syntax element to be equal to a second value based at least in part on the value of the first syntax element being equal to the first value, the first syntax element indicating the maximum number of merge candidates and the maximum number of merge candidates for a non-rectangular codec mode. The video decoder can decode the video data based on the value of the first syntax element and the first syntax element. As used herein, a non-rectangular codec mode is a codec mode that uses a geometric shape other than a rectangle or a square. An example of a non-rectangular codec mode is a triangle mode.

[0020] Figure 1 1 is a block diagram illustrating an example video encoding and decoding system 100 that can perform the techniques of the present disclosure. The techniques of the present disclosure generally relate to encoding and decoding (encoding and / or decoding) video data. Generally, video data includes any data used to process video. Thus, video data can include original unencoded video, encoded video, decoded (e.g., reconstructed) video, and video metadata, such as signaling data.

[0021] like Figure 1 As shown, in this example, video encoding and decoding system 100 includes a source device 102 that provides encoded video data for decoding and display by a destination device 116. Specifically, source device 102 provides the video data to destination device 116 via a computer-readable medium 110. Source device 102 and destination device 116 may include any of a variety of devices, such as mobile devices (e.g., notebook (i.e., laptop) computers, tablet computers, telephone handsets such as smartphones, cameras, digital media players, etc.), desktop computers, set-top boxes, televisions, display devices, video game consoles, video streaming devices, etc. In some cases, source device 102 and destination device 116 may be equipped for wireless communication and, therefore, may be referred to as wireless communication devices.

[0022] exist Figure 1In the example of , source device 102 includes a video source 104, a memory 106, a video encoder 200, and an output interface 108. Destination device 116 includes an input interface 122, a video decoder 300, the memory 120, and a display device 118. According to the present disclosure, the video encoder 200 of source device 102 and the video decoder 300 of destination device 116 can be configured to apply techniques for new signaling notification methods at the picture parameter set (PPS) and slice header levels. Thus, source device 102 represents an example of a video encoding device, while destination device 116 represents an example of a video decoding device. In other examples, the source device and destination device can include other components or arrangements. For example, source device 102 can receive video data from an external video source such as an external camera. Similarly, destination device 116 can interface with an external display device rather than including an integrated display device.

[0023] like Figure 1 The illustrated video encoding and decoding system 100 is merely an example. Generally, any digital video encoding and / or decoding device can implement the techniques for the new signaling method at the PPS and slice header level. The source device 102 and the destination device 116 are merely examples of such codec devices, where the source device 102 generates encoded and decoded video data for transmission to the destination device 116. This disclosure refers to a "codec" device as a device that performs encoding and / or decoding of data. Thus, the video encoder 200 and the video decoder 300 represent examples of codec devices, specifically, examples of a video encoder and a video decoder, respectively. In some examples, the source device 102 and the destination device 116 can operate in a substantially symmetrical manner, such that each of the source device 102 and the destination device 116 includes video encoding and decoding components. Thus, the video encoding and decoding system 100 can support one-way or two-way video transmission between the source device 102 and the destination device 116, for example, for video streaming, video playback, video broadcasting, or video telephony.

[0024] Typically, video source 104 represents a source of video data (i.e., original, unencoded video data) and provides a continuous series of pictures (also referred to as "frames") of video data to video encoder 200, which encodes the data for these pictures. Video source 104 of source device 102 may include a video capture device such as a video camera, a video archive containing previously captured original video, and / or a video feed interface for receiving video from a video content provider. As a further alternative, video source 104 may generate computer graphics-based data as source video, or a combination of live video, archived video, and computer-generated video. In each case, video encoder 200 encodes the captured, pre-captured, or computer-generated video data. Video encoder 200 may rearrange the pictures from the received order (sometimes referred to as "display order") into a codec order for encoding and decoding. Video encoder 200 may generate a bitstream comprising encoded video data. Source device 102 may then output the encoded video data onto computer-readable medium 110 via output interface 108 for receipt and / or retrieval by, for example, input interface 122 of destination device 116 .

[0025] Memory 106 of source device 102 and memory 120 of destination device 116 represent general purpose memory. In some examples, memory 106 and memory 120 can store raw video data, e.g., raw video from video source 104 and raw, decoded video data from video decoder 300. Additionally or alternatively, memory 106 and memory 120 can store software instructions executable by, for example, video encoder 200 and video decoder 300, respectively. Although memory 106 and memory 120 are shown separately from video encoder 200 and video decoder 300 in this example, it should be understood that video encoder 200 and video decoder 300 can also include internal memory for functionally similar or equivalent purposes. Furthermore, memory 106 and memory 120 can store, for example, encoded video data output from video encoder 200 and input to video decoder 300. In some examples, portions of memory 106 and memory 120 can be allocated as one or more video buffers, e.g., to store raw, decoded, and / or encoded video data.

[0026] The computer-readable medium 110 can represent any type of medium or device capable of transmitting encoded video data from the source device 102 to the destination device 116. In one example, the computer-readable medium 110 represents a communication medium that enables the source device 102 to send the encoded video data directly to the destination device 116 in real time, for example, via a radio frequency network or a computer-based network. According to a communication standard such as a wireless communication protocol, the output interface 108 can modulate a transmission signal including the encoded video data, and the input interface 122 can demodulate the received transmission signal. The communication medium can include any wireless or wired communication medium, such as a radio frequency (RF) spectrum or one or more physical transmission lines. The communication medium can form part of a packet-based network such as a local area network, a wide area network, or a global network such as the Internet. The communication medium can include routers, switches, base stations, or any other equipment that may be useful in facilitating communication from the source device 102 to the destination device 116.

[0027] In some examples, source device 102 may output the encoded data from output interface 108 to storage device 112. Similarly, destination device 116 may access the encoded data from storage device 112 via input interface 122. Storage device 112 may include any of a variety of distributed or locally accessed data storage media, such as a hard drive, Blu-ray disc, DVD, CD-ROM, flash memory, volatile or non-volatile memory, or any other suitable digital storage medium for storing encoded video data.

[0028] In some examples, source device 102 may output the encoded video data to a file server 114 or another intermediate storage device that may store the encoded video generated by source device 102. Destination device 116 may access the stored video data from file server 114 via streaming or downloading. File server 114 may be any type of server device capable of storing encoded video data and transmitting this encoded video data to destination device 116. File server 114 may represent a web server (e.g., for a website), a file transfer protocol (FTP) server, a content delivery network device, or a network attached storage (NAS) device. Destination device 116 may access the encoded video data from file server 114 via any standard data connection, including an internet connection. This may include a wireless channel (e.g., a Wi-Fi connection), a wired connection (e.g., a digital subscriber line (DSL), a cable modem, etc.), or a combination of both, suitable for accessing the encoded video data stored on file server 114. File server 114 and input interface 122 may be configured to operate according to a streaming transmission protocol, a download transmission protocol, or a combination thereof.

[0029] The output interface 108 and the input interface 122 may represent wireless transmitters / receivers, modems, wired networking components (e.g., Ethernet cards), wireless communication components operating according to any of the various IEEE 802.11 standards, or other physical components. In examples where the output interface 108 and the input interface 122 include wireless components, the output interface 108 and the input interface 122 may be configured to communicate data, such as encoded video data, according to a cellular communication standard such as 4G, 4G-LTE (Long Term Evolution), LTE-Advanced, 5G, etc. In certain examples where the output interface 108 includes a wireless transmitter, the output interface 108 and the input interface 122 may be configured to communicate data, such as encoded video data, according to other wireless standards such as the IEEE 802.11 specifications, the IEEE 802.15 specifications (e.g., ZigBee TM ),Bluetooth TM Standards, etc.) to transfer data, such as encoded video data. In some examples, source device 102 and / or destination device 116 may include respective system-on-chip (SoC) devices. For example, source device 102 may include a SoC device for performing functionality attributed to video encoder 200 and / or output interface 108, while destination device 116 may include a SoC device for performing functionality attributed to video decoder 300 and / or input interface 122.

[0030] The techniques of the present disclosure may be applied to support video encoding and decoding for any of a variety of multimedia applications such as over-the-air television broadcasting, cable television transmission, satellite television transmission, Internet streaming video transmission such as Dynamic Adaptive Streaming over HTTP (DASH), digital video encoded onto a data storage medium, decoding of digital video stored on a data storage medium, or other applications.

[0031] The input interface 122 of the destination device 116 receives an encoded video bitstream from the computer-readable medium 110 (e.g., a communication medium, a storage device 112, a file server 114, etc.). The encoded video bitstream may include signaling information defined by the video encoder 200 and also used by the video decoder 300, such as syntax elements with values ​​describing characteristics and / or processing of video blocks or other coded units (e.g., slices, pictures, groups of pictures, sequences, etc.). The display device 118 displays decoded pictures of the decoded video data to a user. The display device 118 may represent any of a variety of display devices, such as a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, or another type of display device.

[0032] although Figure 1Although not shown, in some examples, the video encoder 200 and the video decoder 300 can each be integrated with an audio encoder and / or an audio decoder and can include appropriate MUX-DEMUX units or other hardware and / or software to process the multiplexed stream including both audio and video in a common data stream. If applicable, the MUX-DEMUX unit can conform to the ITU H.223 multiplexer protocol or other protocols such as the User Datagram Protocol (UDP).

[0033] The video encoder 200 and the video decoder 300 can each be implemented as any of a variety of suitable encoder and / or decoder circuits, such as one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), discrete logic, software, hardware, firmware, or any combination thereof. When the technology is partially implemented in software, the device can store instructions for the software in a suitable non-transitory computer-readable medium and execute these instructions in hardware using one or more processors to perform the technology of the present disclosure. Each of the video encoder 200 and the video decoder 300 can be included in one or more encoders or decoders, any of which can be integrated as part of a combined encoder / decoder (CODEC) in the corresponding device. The device including the video encoder 200 and / or the video decoder 300 can include an integrated circuit, a microprocessor, and / or a wireless communication device, such as a cellular phone.

[0034] The video encoder 200 and the video decoder 300 can operate according to a video codec standard, such as ITU-T H.265, also known as High Efficiency Video Coding (HEVC), or its extensions, such as the multi-view and / or scalable video codec extensions. Alternatively, the video encoder 200 and the video decoder 300 can operate according to other private or industry standards, such as ITU-T H.266, also known as Versatile Video Codec (VVC). At the 15th meeting of the Joint Video Experts Group (JVET) of ITU-T SG 16WP 3 and ISO / IEC JTC 1 / SC 29 / WG 11: Gothenburg, SE, July 3-12, 2019, JVET-O2001-vE, Bross et al. described a draft of the VVC standard in “Versatile Video Coding (Draft 6)” (hereinafter referred to as “VVC Draft 6”). At the 19th meeting of the Joint Video Experts Group (JVET) of ITU-T SG 16WP 3 and ISO / IEC JTC 1 / SC 29 / WG 11: by teleconference, June 22-July 1, 2020, JVET-S2001-vA, Bross et al. described a newer draft of the VVC standard in "Versatile Video Coding (Draft 10)" (hereinafter referred to as "VVC Draft 10"). However, the technology of this disclosure is not limited to any particular codec standard.

[0035] Typically, the video encoder 200 and the video decoder 300 can perform block-based encoding and decoding of pictures. The term "block" generally refers to a structure that includes data to be processed (e.g., encoded, decoded, or otherwise used in the encoding and / or decoding process). For example, a block can include a two-dimensional matrix of samples of luma and / or chroma data. Typically, the video encoder 200 and the video decoder 300 can encode and decode video data represented in a YUV (e.g., Y, Cb, Cr) format. That is, rather than encoding and decoding red, green, and blue (RGB) data for samples of a picture, the video encoder 200 and the video decoder 300 can encode and decode luma and chroma components, where the chroma components can include both red-hued and blue-hued chroma components. In some examples, the video encoder 200 converts the received RGB formatted data to a YUV representation before encoding, and the video decoder 300 converts the YUV representation to an RGB format. Alternatively, a pre-processing unit and a post-processing unit (not shown) can perform these conversions.

[0036] The present disclosure may generally refer to encoding and decoding of pictures (e.g., encoding and decoding), which is intended to include the process of encoding or decoding the data of a picture. Similarly, the present disclosure may refer to encoding and decoding of a block of a picture as including the process of encoding or decoding the data for the block, such as prediction and / or residual encoding and decoding. A coded video bitstream typically includes a series of values ​​for syntax elements that indicate encoding and decoding decisions (e.g., codec mode) and the partitioning of the picture into blocks. Therefore, references to encoding and decoding a picture or block should generally be understood to refer to encoding and decoding the values ​​for the syntax elements that form the picture or block.

[0037] HEVC defines various blocks, including codec units (CUs), prediction units (PUs), and transform units (TUs). According to HEVC, a video codec (such as the video encoder 200) partitions a codec tree unit (CTU) into CUs according to a quadtree structure. That is, the video codec partitions the CTU and CU into four equal non-overlapping squares, and each node of the quadtree has zero or four child nodes. A node without child nodes may be referred to as a "leaf node," and the CU of such a leaf node may include one or more PUs and / or one or more TUs. The video codec may further partition the PUs and TUs. For example, in HEVC, the residual quadtree (RQT) represents the partitioning of the TUs. In HEVC, PU represents inter-frame prediction data, and TU represents residual data. An intra-predicted CU includes intra-frame prediction information, such as an intra-frame mode indication.

[0038] As another example, the video encoder 200 and the video decoder 300 can be configured to operate according to VVC. According to VVC, a video codec (such as the video encoder 200) partitions a picture into multiple codec tree units (CTUs). The video encoder can partition the CTU according to a tree structure such as a quadtree-binary tree (QTBT) structure or a multi-type tree (MTT) structure. The QTBT structure removes the concept of multiple partitioning types, such as the separation between CU, PU, ​​and TU of HEVC. The QTBT structure includes two levels: a first level partitioned according to quadtree partitioning, and a second level partitioned according to binary tree partitioning. The root node of the QTBT structure corresponds to the CTU. The leaf nodes of the binary tree correspond to the codec units (CUs).

[0039] In the MTT partitioning structure, blocks can be partitioned using quadtree (QT) partitioning, binary tree (BT) partitioning, and one or more types of ternary tree (TT) (also known as ternary tree (TT)) partitioning. A ternary tree or ternary tree partitioning is a partitioning in which a block is split into three sub-blocks. In some examples, the ternary tree or ternary tree partitioning divides the block into three sub-blocks instead of dividing the original block through the center. The partitioning types in MTT (e.g., QT, BT, and TT) can be symmetric or asymmetric.

[0040] In some examples, the video encoder 200 and the video decoder 300 may use a single QTBT structure or MTT structure to represent each of the luma component and the chroma components, while in other examples, the video encoder 200 and the video decoder 300 may use two or more QTBT structures or MTT structures, such as one QTBT / MTT structure for the luma component and another QTBT / MTT structure for the two chroma components (or two QTBT / MTT structures for corresponding chroma components).

[0041] The video encoder 200 and the video decoder 300 can be configured to use quadtree segmentation, QTBT segmentation, MTT segmentation, or other segmentation structures according to HEVC. For the purpose of explanation, the description of the technology of the present disclosure is presented with respect to QTBT segmentation. However, it should be understood that the technology of the present disclosure can also be applied to video codecs configured to use quadtree segmentation or other types of segmentation.

[0042] Blocks (e.g., CTUs or CUs) can be grouped in various ways within a picture. As an example, a brick can refer to a rectangular area of ​​a CTU row within a particular slice in a picture. A slice can be a rectangular area of ​​a CTU within a particular slice column and a particular slice row in a picture. A slice column refers to a rectangular area of ​​a CTU with a height equal to the height of the picture and a width specified by a syntax element (e.g., such as in a picture parameter set). A slice row refers to a rectangular area of ​​a CTU with a height specified by a syntax element (e.g., such as in a picture parameter set) and a width equal to the width of the picture.

[0043] In some examples, a slice can be partitioned into multiple bricks, where each brick can include one or more CTU rows within the slice. A slice that is not partitioned into multiple bricks can also be referred to as a brick. However, a brick that is a proper subset of a slice cannot be referred to as a slice.

[0044] Bricks in a picture can also be arranged in slices. A slice can be an integer number of bricks of a picture that can be contained exclusively in a single Network Abstraction Layer (NAL) unit. In some examples, a slice includes a contiguous sequence of complete bricks of multiple complete slices or just one slice.

[0045] This disclosure may use "NxN" and "N by N" interchangeably to refer to the sample dimensions of a block (such as a CU or other video block) in terms of the vertical and horizontal dimensions, for example, 16x16 samples or 16 by 16 samples. Typically, a 16x16 CU will have 16 samples in the vertical direction (y=16) and 16 samples in the horizontal direction (x=16). Likewise, an NxN CU typically has N samples in the vertical direction and N samples in the horizontal direction, where N represents a non-negative integer value. The samples in a CU may be arranged in rows and columns. Furthermore, a CU does not necessarily need to have the same number of samples in the horizontal direction as in the vertical direction. For example, a CU may include NxM samples, where M is not necessarily equal to N.

[0046] The video encoder 200 encodes video data representing prediction and / or residual information and other information for a CU. The prediction information indicates how the CU will be predicted to form a prediction block for the CU. The residual information typically represents the sample-by-sample difference between the samples of the CU before encoding and the prediction block.

[0047] To predict a CU, the video encoder 200 may typically form a prediction block for the CU through inter-frame prediction or intra-frame prediction. Inter-frame prediction typically refers to predicting a CU based on data from a previously coded picture, while intra-frame prediction typically refers to predicting a CU based on previously coded data from the same picture. To perform inter-frame prediction, the video encoder 200 may use one or more motion vectors to generate a prediction block. The video encoder 200 may typically perform a motion search to identify a reference block that closely matches the CU, for example, based on the difference between the CU and the reference block. The video encoder 200 may calculate a difference metric using the sum of absolute differences (SAD), the sum of squared differences (SSD), the mean absolute difference (MAD), the mean squared difference (MSD), or other such difference calculations to determine whether the reference block closely matches the current CU. In some examples, the video encoder 200 may use unidirectional prediction or bidirectional prediction to predict the current CU.

[0048] Some examples of VVC also provide an affine motion compensation mode, which can be considered an inter-frame prediction mode. In affine motion compensation mode, the video encoder 200 can determine two or more motion vectors representing non-translational motion such as: zooming in or out, rotation, perspective motion, or other irregular motion types.

[0049] To perform intra prediction, the video encoder 200 may select an intra prediction mode to generate a prediction block. Certain examples of VVC provide sixty-seven intra prediction modes, including various directional modes, as well as a planar mode and a DC mode. Typically, the video encoder 200 selects an intra prediction mode that describes a neighboring sample of a current block (e.g., a block of a CU) to predict the sample of the current block based on it. Assuming that the video encoder 200 encodes and decodes CTUs and CUs in raster scan order (from left to right, from top to bottom), such samples may typically be located above, above and to the left of, or to the left of the current block in the same picture as the current block.

[0050] The video encoder 200 encodes data indicating the prediction mode for the current block. For example, for inter-frame prediction mode, the video encoder 200 may encode data indicating which of various available inter-frame prediction modes to use, as well as motion information for the corresponding mode. For example, for unidirectional or bidirectional inter-frame prediction, the video encoder 200 may encode motion vectors using advanced motion vector prediction (AMVP) or merge mode. For affine motion compensation mode, the video encoder 200 may use a similar mode to encode motion vectors.

[0051] After predicting a block, such as after intra-frame prediction or inter-frame prediction of the block, the video encoder 200 can calculate residual data for the block. The residual data, such as a residual block, represents the sample-by-sample difference between the block and a prediction block for the block formed using the corresponding prediction mode. The video encoder 200 can apply one or more transforms to the residual block to produce transformed data in a transform domain rather than a sample domain. For example, the video encoder 200 can apply a discrete cosine transform (DCT), an integer transform, a wavelet transform, or a conceptually similar transform to the residual video data. Additionally, the video encoder 200 can apply a secondary transform, such as a mode-dependent non-separable secondary transform (MDNSST), a signal-dependent transform, a Karhunen-Loeve transform (KLT), etc., after the primary transform. The video encoder 200 generates transform coefficients after applying one or more transforms.

[0052] As described above, after any transform used to generate transform coefficients, the video encoder 200 can perform quantization on the transform coefficients. Quantization generally refers to a process in which transform coefficients are quantized to potentially reduce the amount of data used to represent the transform coefficients, thereby providing further compression. By performing the quantization process, the video encoder 200 can reduce the bit depth associated with some or all of the transform coefficients. For example, the video encoder 200 can round down an n-bit value to an m-bit value during quantization, where n is greater than m. In some examples, to perform quantization, the video encoder 200 can perform a bitwise right shift of the value to be quantized.

[0053] After quantization, the video encoder 200 may scan the transform coefficients to produce a one-dimensional vector from the two-dimensional matrix including the quantized transform coefficients. The scan may be designed to place higher energy (and therefore lower frequency) transform coefficients at the front of the vector and lower energy (and therefore higher frequency) transform coefficients at the back of the vector. In some examples, the video encoder 200 may scan the quantized transform coefficients using a predefined scan order to produce a serialized vector and then entropy encode the quantized transform coefficients of the vector. In other examples, the video encoder 200 may perform adaptive scanning. After scanning the quantized transform coefficients to form a one-dimensional vector, the video encoder 200 may entropy encode the one-dimensional vector, for example, according to context-adaptive binary arithmetic coding (CABAC). The video encoder 200 may also entropy encode values ​​for syntax elements that describe metadata associated with the encoded video data for use by the video decoder 300 when decoding the video data.

[0054] To perform CABAC, the video encoder 200 may assign context within a context model to a symbol to be transmitted. The context may relate to, for example, whether the neighboring values ​​of the symbol are zero values. The probability determination may be based on the context assigned to the symbol.

[0055] The video encoder 200 may further generate block-based syntax data, picture-based syntax data, and sequence-based syntax data, for example, in a picture header, a block header, a slice header, or other syntax data such as a sequence parameter set (SPS), a picture parameter set (PPS), or a video parameter set (VPS) to the video decoder 300. The video decoder 300 may also decode such syntax data to determine how to decode the corresponding video data.

[0056] In this way, the video encoder 200 can generate a bitstream that includes coded video data, such as syntax elements describing the partitioning of a picture into blocks (e.g., CUs) and prediction and / or residual information for the blocks. Ultimately, the video decoder 300 can receive the bitstream and decode the coded video data.

[0057] In general, the video decoder 300 performs a process that is inverse to that performed by the video encoder 200 to decode the encoded video data of the bitstream. For example, the video decoder 300 may use CABAC to decode values ​​for syntax elements in the bitstream in a manner substantially similar to, but inverse to, the CABAC encoding process of the video encoder 200. The syntax elements may define information about the partitioning of a picture into CTUs, and the partitioning of each CTU according to a corresponding partitioning structure, such as a QTBT structure, to define CUs of the CTU. The syntax elements may further define prediction and residual information for a block (e.g., a CU) of video data.

[0058] The residual information may be represented by, for example, quantized transform coefficients. The video decoder 300 may inverse quantize and inverse transform the quantized transform coefficients of the block to reproduce a residual block for the block. The video decoder 300 uses the signaled prediction mode (intra-frame or inter-frame prediction) and related prediction information (e.g., motion information for inter-frame prediction) to form a prediction block for the block. The video decoder 300 may then combine the prediction block and the residual block (on a sample-by-sample basis) to reproduce the original block. The video decoder 300 may perform additional processing, such as performing a deblocking process to reduce visual artifacts along block boundaries.

[0059] According to the techniques of this disclosure, in one example, a method includes: determining, by one or more processors, whether a maximum number of merge candidates for a slice of video data is equal to a first value; inferring, by the one or more processors, a value of a first syntax element to be equal to a second value based at least in part on the maximum number of merge candidates for the slice being equal to the first value, the first syntax element indicating the maximum number of merge candidates and the maximum number of merge candidates for a non-rectangular codec mode; and decoding the slice based on the maximum number of merge candidates and the value of the first syntax element.

[0060] According to the techniques of this disclosure, in another example, a device includes a memory configured to store video data and one or more processors implemented in circuitry and communicatively coupled to the memory, the one or more processors configured to: determine whether a maximum number of merge candidates for a slice of the video data is equal to a first value; infer a value of a first syntax element to be equal to a second value based at least in part on the maximum number of merge candidates for the slice being equal to the first value, the first syntax element indicating the maximum number of merge candidates and the maximum number of merge candidates for a non-rectangular codec mode; and decode the slice based on the maximum number of merge candidates and the first syntax element.

[0061] According to the techniques of this disclosure, in another example, a non-transitory computer-readable storage medium includes instructions stored thereon that, when executed by one or more processors, cause the one or more processors to: determine whether a maximum number of merge candidates for a slice of video data is equal to a first value; infer a value of a first syntax element to be equal to a second value based at least in part on the maximum number of merge candidates for the slice being equal to the first value, the first syntax element indicating the maximum number of merge candidates and the maximum number of merge candidates for a non-rectangular codec mode; and decode the slice based on the maximum number of merge candidates and the first syntax element.

[0062] In accordance with the techniques of this disclosure, in another example, a device includes means for determining whether a maximum number of merge candidates for a slice of video data is equal to a first value; means for inferring a value of a first syntax element to be equal to a second value based at least in part on the maximum number of merge candidates for the slice being equal to the first value, the first syntax element indicating the maximum number of merge candidates and the maximum number of merge candidates for a non-rectangular codec mode; and means for decoding the slice based on the maximum number of merge candidates and the value of the first syntax element.

[0063] The present disclosure may generally refer to "signaling" certain information, such as syntax elements. The term "signaling" may generally refer to the communication of values ​​for syntax elements and / or other data used to decode encoded video data. That is, video encoder 200 may signal values ​​for syntax elements in a bitstream. Typically, signaling involves generating values ​​in the bitstream. As described above, source device 102 may transmit the bitstream to destination device 116 in substantially real time or in non-real time, such as may occur when syntax elements are stored on storage device 112 for later retrieval by destination device 116.

[0064] Figure 2A and Figure 2Bis a conceptual diagram illustrating an example quadtree binary tree (QTBT) structure 130, and a corresponding codec tree unit (CTU) 132. Solid lines represent quadtree splits, while dashed lines indicate binary tree splits. In each split (i.e., non-leaf) node of the binary tree, a flag is signaled to indicate which split type (i.e., horizontal or vertical) is used, where in this example, 0 indicates horizontal splitting and 1 indicates vertical splitting. For quadtree splitting, there is no need to indicate the split type because the quadtree node splits the block horizontally and vertically into 4 equally sized sub-blocks. Accordingly, the video encoder 200 can encode and the video decoder 300 can decode syntax elements (such as split information) for the region tree level (i.e., solid lines) of the QTBT structure 130 and syntax elements (such as split information) for the prediction tree level (i.e., dashed lines) of the QTBT structure 130. The video encoder 200 may encode and the video decoder 300 may decode video data, such as prediction and transform data, for the CU represented by the terminal leaf node of the QTBT structure 130 .

[0065] generally, Figure 2B The CTU 132 may be associated with parameters defining the sizes of blocks corresponding to nodes at the first and second levels in the QTBT structure 130. These parameters may include a CTU size (expressed in samples), a minimum quadtree size (MinQTSize, representing the minimum allowed quadtree leaf node size), a maximum binary tree size (MaxBTSize, representing the maximum allowed binary tree root node size), a maximum binary tree depth (MaxBTDepth, representing the maximum allowed binary tree depth), and a minimum binary tree size (MinBTSize, representing the minimum allowed binary tree leaf node size).

[0066] The root node of the QTBT structure corresponding to the CTU can have four child nodes at the first level of the QTBT structure, each of which can be split according to quadtree partitioning. That is, the nodes at the first level are leaf nodes (no child nodes) or have four child nodes. The example of the QTBT structure 130 represents such nodes as parent nodes and child nodes including solid lines for branching. If the nodes at the first level are not larger than the maximum allowed binary tree root node size (MaxBTSize), these nodes can be further split by the corresponding binary tree. The binary tree splitting of a node can be iterated until the node obtained by the split reaches the minimum allowed binary tree leaf node size (MinBTSize) or the maximum allowed binary tree depth (MaxBTDepth). The example of the QTBT structure 130 represents such nodes as having dotted lines for branching. The binary tree leaf nodes are called coding units (CUs), which are used for prediction (e.g., intra-picture or inter-picture prediction) and transformation without any further partitioning. As described above, CUs can also be referred to as "video blocks" or "blocks."

[0067] In one example of a QTBT partitioning structure, the CTU size is set to 128×128 (luminance sample and two corresponding 64×64 chroma samples), MinQTSize is set to 16×16, MaxBTSize is set to 64×64, MinBTSize (for both width and height) is set to 4, and MaxBTDepth is set to 4. Quadtree partitioning is first applied to the CTU to generate quadtree leaf nodes. Quadtree leaf nodes can have sizes from 16×16 (i.e., MinQTSize) to 128×128 (i.e., CTU size). If the leaf quadtree node is 128×128, it will not be further split by the binary tree because the size exceeds MaxBTSize (i.e., 64×64 in this example). Otherwise, the leaf quadtree node will be further split by the binary tree. Therefore, the quadtree leaf node is also the root node of the binary tree and has a binary tree depth of 0. When the binary tree depth reaches MaxBTDepth (4 in this example), no further splitting is allowed. When a binary tree node has a width equal to MinBTSize (4 in this example), this means that no further horizontal splitting is allowed. Similarly, a binary tree node with a height equal to MinBTSize means that no further vertical splitting is allowed for the binary tree node. As described above, the leaf nodes of the binary tree are called CUs and are further processed according to prediction and transformation without the need for further splitting.

[0068] Figure 3 is a block diagram illustrating an example video encoder 200 that may perform the techniques of this disclosure. Figure 3This is provided for purposes of explanation and should not be construed as limiting the techniques broadly illustrated and described in this disclosure. For purposes of explanation, this disclosure describes video encoder 200 in the context of video codec standards such as the HEVC video codec standard and the developing H.266 video codec standard. However, the techniques of this disclosure are not limited to these video codec standards and are generally applicable to video encoding and decoding.

[0069] exist Figure 3 In the example of FIG, the video encoder 200 includes a video data memory 230, a mode selection unit 202, a residual generation unit 204, a transform processing unit 206, a quantization unit 208, an inverse quantization unit 210, an inverse transform processing unit 212, a reconstruction unit 214, a filter unit 216, a decoded picture buffer (DPB) 218, and an entropy coding unit 220. Any or all of the video data memory 230, the mode selection unit 202, the residual generation unit 204, the transform processing unit 206, the quantization unit 208, the inverse quantization unit 210, the inverse transform processing unit 212, the reconstruction unit 214, the filter unit 216, the DPB 218, and the entropy coding unit 220 may be implemented in one or more processors or processing circuits. Moreover, the video encoder 200 may include additional or alternative processors or processing circuits to perform these and other functions.

[0070] The video data memory 230 may store video data to be encoded by the components of the video encoder 200. The video encoder 200 may receive video data from, for example, the video source 104 ( Figure 1 ) receives video data stored in video data memory 230. DPB 218 can act as a reference picture memory for storing reference video data used to predict subsequent video data by the video encoder 200. Video data memory 230 and DPB 218 can be formed by any of a variety of memory devices, such as dynamic random access memory (DRAM) (including synchronous DRAM (SDRAM)), magnetoresistive RAM (MRAM), resistive RAM (RRAM), or other types of memory devices. Video data memory 230 and DPB 218 can be provided by the same memory device or separate memory devices. In various examples, video data memory 230 can be located on-chip with other components of the video encoder 200, as shown, or off-chip relative to those components.

[0071] In this disclosure, references to video data memory 230 should not be construed as limited to memory internal to video encoder 200, unless specifically described as such, or memory external to video encoder 200, unless specifically described as such. Rather, references to video data memory 230 should be understood as reference memory that stores video data received by video encoder 200 for encoding (e.g., video data for a current block to be encoded). Figure 1 The memory 106 may also provide temporary storage for outputs from the various units of the video encoder 200 .

[0072] Figure 3 The various units are illustrated to aid in understanding the operations performed by the video encoder 200. These units can be implemented as fixed-function circuits, programmable circuits, or a combination thereof. Fixed-function circuits refer to circuits that provide a specific function and are preset on the operations that can be performed. Programmable circuits refer to circuits that can be programmed to perform various tasks and provide flexible functionality in the operations that can be performed. For example, a programmable circuit can execute software or firmware so that the programmable circuit operates in a manner defined by the instructions of the software or firmware. Fixed-function circuits can execute software instructions (e.g., to receive parameters or output parameters), but the type of operations performed by the fixed-function circuits is generally immutable. In some examples, one or more of the units can be different circuit blocks (fixed-function or programmable), while in some examples, one or more of the units can be integrated circuits.

[0073] The video encoder 200 may include an arithmetic logic unit (ALU), an elementary function unit (EFU), a digital circuit, an analog circuit, and / or a programmable core formed by a programmable circuit. In an example where the operation of the video encoder 200 is performed using software executed by a programmable circuit, the memory 106 ( Figure 1 ) may store instructions (eg, object code) for software that video encoder 200 receives and executes, or another memory (not shown) within video encoder 200 may store such instructions.

[0074] The video data memory 230 is configured to store received video data. The video encoder 200 may retrieve a picture of video data from the video data memory 230 and provide the video data to the residual generation unit 204 and the mode selection unit 202. The video data in the video data memory 230 may be original video data to be encoded.

[0075] The mode selection unit 202 includes a motion estimation unit 222, a motion compensation unit 224, and an intra prediction unit 226. The mode selection unit 202 may include additional functional units for performing video prediction according to other prediction modes. As an example, the mode selection unit 202 may include a palette unit, an intra-block copy unit (which may be part of the motion estimation unit 222 and / or the motion compensation unit 224), an affine unit, a linear model (LM) unit, and the like.

[0076] The mode selection unit 202 typically coordinates multiple encoding passes to test combinations of encoding parameters and the resulting rate-distortion values ​​for such combinations. The encoding parameters may include the partitioning of CTUs into CUs, the prediction mode for a CU, the transform type for the residual data of a CU, the quantization parameter for the residual data of a CU, etc. The mode selection unit 202 may ultimately select a combination of encoding parameters that has a better rate-distortion value than other tested combinations.

[0077] The video encoder 200 may partition a picture retrieved from the video data memory 230 into a series of CTUs and encapsulate one or more CTUs into a slice. The mode selection unit 202 may partition the CTUs of the picture according to a tree structure, such as a QTBT structure or the quadtree structure of HEVC described above. As described above, the video encoder 200 may form one or more CUs by partitioning the CTUs according to the tree structure. Such CUs may also be generally referred to as "video blocks" or "blocks." In some examples, the mode selection unit 202 may partition the CTUs according to a non-rectangular encoding mode. In such cases, the mode selection unit 202 may partition the CTUs using geometric shapes other than rectangular or square shapes. For example, the mode selection unit 202 may partition the CTUs using a triangular pattern.

[0078] Typically, the mode select unit 202 also controls its components (e.g., the motion estimation unit 222, the motion compensation unit 224, and the intra prediction unit 226) to generate a prediction block for the current block (e.g., the current CU, or the overlapping portion of the PU and TU in HEVC). For inter prediction of the current block, the motion estimation unit 222 may perform a motion search to identify one or more closely matching reference blocks in one or more reference pictures (e.g., one or more previously coded pictures stored in the DPB 218). Specifically, the motion estimation unit 222 may calculate values ​​indicating how similar the potential reference blocks are to the current block, for example, based on the sum of absolute differences (SAD), sum of squared differences (SSD), mean absolute difference (MAD), mean squared difference (MSD), etc. The motion estimation unit 222 may typically perform these calculations using the sample-by-sample differences between the current block and the reference block under consideration. The motion estimation unit 222 may identify the reference block with the lowest of these calculated values, indicating the reference block that most closely matches the current block.

[0079] Motion estimation unit 222 may form one or more motion vectors (MVs) that define the position of a reference block in a reference picture relative to the current block in the current picture. Motion estimation unit 222 may then provide the motion vectors to motion compensation unit 224. For example, for unidirectional inter prediction, motion estimation unit 222 may provide a single motion vector, while for bidirectional inter prediction, motion estimation unit 222 may provide two motion vectors. Motion compensation unit 224 may then use the motion vectors to generate a prediction block. For example, motion compensation unit 224 may use the motion vectors to retrieve data for the reference block. As another example, if the motion vectors have fractional sample precision, motion compensation unit 224 may interpolate values ​​for the prediction block based on one or more interpolation filters. Furthermore, for bidirectional inter prediction, motion compensation unit 224 may retrieve data for two reference blocks identified by the corresponding motion vectors and combine the retrieved data, for example, by sample-by-sample averaging or weighted averaging.

[0080] As another example, for intra prediction or intra prediction codecs, the intra prediction unit 226 can generate a prediction block based on samples adjacent to the current block. For example, for directional mode, the intra prediction unit 226 can generally mathematically combine the values ​​of the adjacent samples and pad these calculated values ​​in a defined direction across the current block to produce the prediction block. As another example, for DC mode, the intra prediction unit 226 can calculate the average of the adjacent samples of the current block and generate the prediction block so that each sample of the prediction block includes this average.

[0081] Mode selection unit 202 provides the prediction block to residual generation unit 204. Residual generation unit 204 receives the original, unencoded version of the current block from video data memory 230 and the prediction block from mode selection unit 202. Residual generation unit 204 calculates the sample-by-sample difference between the current block and the prediction block. The resulting sample-by-sample difference defines a residual block for the current block. In some examples, residual generation unit 204 may also determine the difference between the sample values ​​in the residual block to generate the residual block using residual differential pulse code modulation (RDPCM). In some examples, residual generation unit 204 may be formed using one or more subtractor circuits that perform binary subtraction.

[0082] In the example where the mode select unit 202 partitions the CU into PUs, each PU may be associated with a luma prediction unit and a corresponding chroma prediction unit. The video encoder 200 and the video decoder 300 may support PUs of various sizes. As described above, the size of a CU may refer to the size of the luma codec block of the CU, and the size of a PU may refer to the size of the luma prediction unit of the PU. Assuming that the size of a particular CU is 2N×2N, the video encoder 200 may support PUs of size 2N×2N or N×N for intra prediction, and symmetric PUs of size 2N×2N, 2N×N, N×2N, N×N, or similar sizes for inter prediction. The video encoder 200 and the video decoder 300 may also support asymmetric partitioning for PUs of size 2N×nU, 2N×nD, nL×2N, and nR×2N for inter prediction.

[0083] In an example where the mode selection unit 202 does not further partition a CU into PUs, each CU may be associated with a luma codec block and a corresponding chroma codec block. As described above, the size of a CU may refer to the size of the luma codec block of the CU. The video encoder 200 and the video decoder 300 may support CUs of size 2N×2N, 2N×N, or N×2N.

[0084] For other video codecs such as intra-block copy mode codecs, affine mode codecs, and linear model (LM) mode codecs, as examples, the mode selection unit 202 generates a prediction block for the current block being encoded via the corresponding unit associated with the codec. In some examples, such as palette mode codecs, the mode selection unit 202 may not generate a prediction block, but instead generate syntax elements indicating how to reconstruct the block based on the selected palette. In such modes, the mode selection unit 202 may provide these syntax elements to the entropy coding unit 220 for encoding.

[0085] As described above, the residual generation unit 204 receives video data for a current block and a corresponding prediction block. The residual generation unit 204 then generates a residual block for the current block. To generate the residual block, the residual generation unit 204 calculates the sample-by-sample difference between the prediction block and the current block.

[0086] The transform processing unit 206 applies one or more transforms to the residual block to generate a block of transform coefficients (referred to herein as a "transform coefficient block"). The transform processing unit 206 may apply various transforms to the residual block to form the transform coefficient block. For example, the transform processing unit 206 may apply a discrete cosine transform (DCT), a directional transform, a Karl-Lof transform (KLT), or a conceptually similar transform to the residual block. In some examples, the transform processing unit 206 may perform multiple transforms on the residual block, for example, a primary transform and a secondary transform, such as a rotation transform. In some examples, the transform processing unit 206 does not apply a transform to the residual block.

[0087] The quantization unit 208 may quantize the transform coefficients in the transform coefficient block to produce a quantized transform coefficient block. The quantization unit 208 may quantize the transform coefficients of the transform coefficient block according to a quantization parameter (QP) value associated with the current block. The video encoder 200 (e.g., via the mode selection unit 202) may adjust the degree of quantization applied to the transform coefficient block associated with the current block by adjusting the QP value associated with the CU. Quantization may introduce a loss of information, and therefore, the quantized transform coefficients may have lower precision than the original transform coefficients produced by the transform processing unit 206.

[0088] The inverse quantization unit 210 and the inverse transform processing unit 212 may apply inverse quantization and inverse transform, respectively, to the quantized transform coefficient block to reconstruct a residual block from the transform coefficient block. The reconstruction unit 214 may generate a reconstructed block corresponding to the current block (albeit potentially with some degree of distortion) based on the reconstructed residual block and the prediction block generated by the mode selection unit 202. For example, the reconstruction unit 214 may add samples of the reconstructed residual block to corresponding samples from the prediction block generated by the mode selection unit 202 to generate the reconstructed block.

[0089] Filter unit 216 may perform one or more filter operations on the reconstructed block. For example, filter unit 216 may perform a deblocking operation to reduce blocking artifacts along the edges of the CU. In some examples, the operations of filter unit 216 may be skipped.

[0090] The video encoder 200 stores the reconstructed block in the DPB 218. For example, in examples where the operation of the filter unit 216 is not required, the reconstruction unit 214 can store the reconstructed block to the DPB 218. In examples where the operation of the filter unit 216 is required, the filter unit 216 can store the filtered reconstructed block to the DPB 218. The motion estimation unit 222 and the motion compensation unit 224 can retrieve a reference picture formed by the reconstructed (and possibly filtered) block from the DPB 218 to perform inter-frame prediction on blocks of subsequently encoded pictures. In addition, the intra-frame prediction unit 226 can use the reconstructed block of the current picture in the DPB 218 to perform intra-frame prediction on other blocks in the current picture.

[0091] In general, entropy coding unit 220 may entropy encode syntax elements received from other functional components of video encoder 200. For example, entropy coding unit 220 may entropy encode quantized transform coefficient blocks from quantization unit 208. As another example, entropy coding unit 220 may entropy encode prediction syntax elements (e.g., motion information for inter-frame prediction or intra-frame mode information for intra-frame prediction) from mode selection unit 202. Entropy coding unit 220 may perform one or more entropy encoding operations on syntax elements, another example of video data, to generate entropy-encoded data. For example, entropy coding unit 220 may perform a context-adaptive variable length coding (CAVLC) operation, a CABAC operation, a variable-to-variable (V2V) length coding operation, a syntax-based context-adaptive binary arithmetic coding (SBAC) operation, a probability interval partitioning entropy (PIPE) coding operation, an exponential-Golomb coding operation, or another type of entropy coding operation on the data. In some examples, entropy coding unit 220 may operate in a bypass mode in which syntax elements are not entropy encoded.

[0092] The video encoder 200 may output a bitstream including entropy-encoded syntax elements required for reconstructing blocks of a slice or picture. Specifically, the entropy encoding unit 220 may output a bitstream.

[0093] The operations described above are described with respect to blocks. Such descriptions should be understood as operations for luma codec blocks and / or chroma codec blocks. As described above, in some examples, the luma codec blocks and chroma codec blocks are the luma and chroma components of a CU. In some instances, the luma codec blocks and chroma codec blocks are the luma and chroma components of a PU.

[0094] In some examples, operations performed with respect to luma codec blocks do not need to be repeated for chroma codec blocks. As an example, the operations used to identify the motion vector (MV) and reference picture for a luma codec block do not need to be repeated for identifying the MV and reference picture for a chroma codec block. Specifically, the MV for a luma codec block can be scaled to determine the MV for a chroma block, while the reference picture can be the same. As another example, the intra prediction process can be the same for luma and chroma codec blocks.

[0095] The video encoder 200 represents an example of a device configured to encode video data, including a memory configured to store the video data, and one or more processing units implemented in circuitry and configured to: determine a maximum number of merge candidates for a slice of the video data; determine a second value of a first syntax element based on the maximum number of merge candidates for the slice, the first syntax element indicating the maximum number of merge candidates and the maximum number of merge candidates for a non-rectangular codec mode; and encode the video data based on the maximum number of merge candidates and the first syntax element.

[0096] Figure 4 is a block diagram illustrating an example video decoder 300 that may perform the techniques of this disclosure. Figure 4 This is provided for purposes of explanation and is not intended to limit the techniques broadly illustrated and described in this disclosure. For purposes of explanation, this disclosure describes a video decoder 300 based on techniques of VVC and HEVC. However, the techniques of this disclosure may be performed by video codec devices configured for other video codec standards.

[0097] exist Figure 4 In the example of FIG, the video decoder 300 includes a codec picture buffer (CPB) memory 320, an entropy decoding unit 302, a prediction processing unit 304, an inverse quantization unit 306, an inverse transform processing unit 308, a reconstruction unit 310, a filter unit 312, and a decoded picture buffer (DPB) 314. Any or all of the CPB memory 320, the entropy decoding unit 302, the prediction processing unit 304, the inverse quantization unit 306, the inverse transform processing unit 308, the reconstruction unit 310, the filter unit 312, and the DPB 314 may be implemented in one or more processors or processing circuits. Moreover, the video decoder 300 may include additional or alternative processors or processing circuits to perform these and other functions.

[0098] The prediction processing unit 304 includes a motion compensation unit 316 and an intra prediction unit 318. The prediction processing unit 304 may include additional units for performing prediction according to other prediction modes. As an example, the prediction processing unit 304 may include a palette unit, an intra block copy unit (which may be part of the motion compensation unit 316), an affine unit, a linear model (LM) unit, and the like. In other examples, the video decoder 300 may include more, fewer, or different functional components.

[0099] The CPB memory 320 may store video data, such as an encoded video bitstream, to be decoded by components of the video decoder 300. The video data stored in the CPB memory 320 may be, for example, received from the computer-readable medium 110 ( Figure 1 ). The CPB memory 320 may include a CPB that stores coded video data (e.g., syntax elements) from the coded video bitstream. Similarly, the CPB memory 320 may store video data other than syntax elements for coded or decoded pictures, such as temporary data representing outputs from various units of the video decoder 300. The DPB 314 typically stores decoded pictures, which the video decoder 300 may output and / or use as reference video data when decoding subsequent data or pictures of the coded video bitstream. The CPB memory 320 and the DPB 314 may be formed from any of a variety of memory devices, such as DRAM (including SDRAM), MRAM, RRAM, or other types of memory devices. The CPB memory 320 and the DPB 314 may be provided by the same memory device or separate memory devices. In various examples, the CPB memory 320 may be located on-chip with other components of the video decoder 300, or off-chip relative to those components.

[0100] Additionally or alternatively, in some examples, video decoder 300 may retrieve the video from memory 120 ( Figure 1 ) to retrieve the encoded and decoded video data. That is, memory 120 may store data as discussed above in conjunction with CPB memory 320. Likewise, when some or all of the functionality of video decoder 300 is implemented in software to be executed by processing circuitry of video decoder 300, memory 120 may store instructions to be executed by video decoder 300.

[0101] Figure 4 The various units shown in FIG3 are illustrated to aid in understanding the operations performed by the video decoder 300. These units may be implemented as fixed function circuits, programmable circuits, or a combination thereof. Figure 3Similarly, fixed-function circuits refer to circuits that provide a specific function and are preset in the operations that can be performed. Programmable circuits refer to circuits that can be programmed to perform various tasks and provide flexible functionality in the operations that can be performed. For example, a programmable circuit can execute software or firmware so that the programmable circuit operates in a manner defined by the instructions of the software or firmware. Fixed-function circuits can execute software instructions (for example, to receive parameters or output parameters), but the type of operations performed by the fixed-function circuits is generally immutable. In some examples, one or more of the units can be different circuit blocks (fixed-function or programmable), while in some examples, one or more of the units can be integrated circuits.

[0102] The video decoder 300 may include an ALU, an EFU, digital circuits, analog circuits, and / or a programmable core formed by programmable circuits. In examples where the operation of the video decoder 300 is performed by software executed on the programmable circuits, on-chip or off-chip memory may store instructions (e.g., object code) of the software that the video decoder 300 receives and executes.

[0103] Entropy decoding unit 302 may receive encoded video data from the CPB and entropy decode the video data to reproduce syntax elements. Prediction processing unit 304, inverse quantization unit 306, inverse transform processing unit 308, reconstruction unit 310, and filter unit 312 may generate decoded video data based on syntax elements extracted from the bitstream.

[0104] Typically, the video decoder 300 reconstructs a picture on a block-by-block basis. The video decoder 300 may perform a reconstruction operation on each block individually (where the block currently being reconstructed, ie, decoded, may be referred to as a "current block").

[0105] The entropy decoding unit 302 may entropy decode syntax elements defining the quantized transform coefficients of the quantized transform coefficient block, as well as transform information such as a quantization parameter (QP) and / or (one or more) transform mode indications. The inverse quantization unit 306 may use the QP associated with the quantized transform coefficient block to determine a degree of quantization and, similarly, determine a degree of inverse quantization for the inverse quantization unit 306 to apply. The inverse quantization unit 306 may, for example, perform a bitwise left shift operation to inverse quantize the quantized transform coefficients. The inverse quantization unit 306 may thereby form a transform coefficient block comprising the transform coefficients.

[0106] After inverse quantization unit 306 forms a transform coefficient block, inverse transform processing unit 308 may apply one or more inverse transforms to the transform coefficient block to generate a residual block associated with the current block. For example, inverse transform processing unit 308 may apply an inverse DCT, an inverse integer transform, an inverse Karl-Lof transform (KLT), an inverse rotational transform, an inverse directional transform, or another inverse transform to the coefficient block.

[0107] Furthermore, prediction processing unit 304 generates a prediction block based on the prediction information syntax elements entropy decoded by entropy decoding unit 302. In some instances, prediction processing unit 304 may infer values ​​for certain syntax elements. For example, prediction processing unit 304 may determine whether a maximum number of merge candidates for a slice of video data is equal to 2. The maximum number of merge candidates for a slice of video data may be related to the merge candidates. Based at least in part on the maximum number of merge candidates for a slice of video data being equal to 2, prediction processing unit 304 may infer a value for a first syntax element to be equal to 0. For example, prediction processing unit 304 may determine whether the value of MaxNumMergeCand is equal to 2, and based on the value of MaxNumMergeCand being equal to 2, infer a value of max_num_merge_cand_minus_max_num_triangle_cand to be equal to 0.

[0108] For example, if the prediction information syntax element indicates that the current block is inter-predicted, the motion compensation unit 316 may generate a prediction block. In this case, the prediction information syntax element may indicate a reference picture in the DPB 314 from which the reference block is retrieved, and a motion vector that identifies the position of the reference block in the reference picture relative to the position of the current block in the current picture. The motion compensation unit 316 may generally generate a prediction block in the same manner as the prediction information syntax element indicates that the current block is inter-predicted ... Figure 3 ) and the inter-frame prediction process is performed in a manner basically similar to the described method.

[0109] As another example, if the prediction information syntax element indicates that the current block is intra-predicted, the intra-prediction unit 318 may generate a prediction block according to the intra-prediction mode indicated by the prediction information syntax element. Again, the intra-prediction unit 318 may generally generate a prediction block in the same manner as the intra-prediction unit 226 ( Figure 3 The intra prediction process is performed in a substantially similar manner as described above. The intra prediction unit 318 can retrieve data of neighboring samples for the current block from the DPB 314.

[0110] The reconstruction unit 310 may reconstruct the current block using the prediction block and the residual block. For example, the reconstruction unit 310 may add samples of the residual block to corresponding samples of the prediction block to reconstruct the current block.

[0111] The filter unit 312 may perform one or more filter operations on the reconstructed block. For example, the filter unit 312 may perform a deblocking operation to reduce blocking artifacts along the edges of the reconstructed block. The operations of the filter unit 312 need not be performed in all examples.

[0112] The video decoder 300 may store the reconstructed block in the DPB 314. For example, in examples where the operation of the filter unit 312 is not performed, the reconstruction unit 310 may store the reconstructed block to the DPB 314. In examples where the operation of the filter unit 312 is performed, the filter unit 312 may store the filtered reconstructed block to the DPB 314. As described above, the DPB 314 may provide reference information to the prediction processing unit 304, such as samples of the current picture for intra prediction and samples of previously decoded pictures for subsequent motion compensation. Moreover, the video decoder 300 may output a decoded picture (e.g., decoded video) from the DPB 314 for use in, for example, Figure 1 Subsequent presentation on a display device such as display device 118.

[0113] In this manner, the video decoder 300 represents an example of a video decoding device, including a memory configured to store video data, and one or more processing units implemented in circuitry and configured to: determine whether a maximum number of merge candidates for a slice of video data is equal to a first value; infer a value of a first syntax element to be equal to a second value based at least in part on the maximum number of merge candidates for the slice being equal to the first value, the first syntax element indicating the maximum number of merge candidates and the maximum number of merge candidates for a non-rectangular codec mode; and decode the slice based on the maximum number of merge candidates and the first syntax element.

[0114] This document discloses a signaling method for PPS and slice headers. The technology disclosed in this document can be applied to the Multi-Video Codec Standard and other future video codec standards.

[0115] Video codec standards include ITU-T H.261, ISO / IEC MPEG-1 Visual, ITU-T H.262 or ISO / IEC MPEG-2 Visual, ITU-T H.263, ISO / IEC MPEG-4 Visual, and ITU-T H.264 (also known as ISO / IEC MPEG-4 AVC), including its Scalable Video Codec (SVC) and Multi-view Video Codec (MVC) extensions. Furthermore, the Joint Collaboration Team on Video Codecs (JCT-VC) of the ITU-T Video Coding Experts Group (VCEG) and the ISO / IEC Moving Picture Experts Group (MPEG), as well as the Joint Collaboration Team on 3D Video Codec Extensions (JCT-3V), have recently developed a new video codec standard, High Efficiency Video Codec (HEVC) or ITU-T H.265, including its Range and Screen Content Codec extensions, 3D Video Codec (3D-HEVC), Multi-view Extension (MV-HEVC), and Scalable Extension (SHVC). In 2016, MPEG and ITU-T VCEG formed the Joint Exploratory Video Team (JVET) to explore and develop new video codec tools for the next-generation video codec standard called Versatile Video Codec (VVC). Versatile Video Codec Working Draft (WD) 6 can be downloaded at JVET-O2001. The reference software is called the VVC Test Model (VTM). The sections of VVC Draft 6 Version 14 discussed in this disclosure are excerpted in Table 1 below. The video encoder 200 can generate parameters such as those listed below, and the video decoder 300 can decode the parameters to determine how to decode the corresponding video data.

[0116]

[0117]

[0118]

[0119]

[0120]

[0121] Table 1

[0122] The PPS flag constant_slice_header_params_enabled_flag is used to specify that at least one syntax element is constant in the slice header of the slices involved in the PPS. However, if the video codec implements VVC draft 6, problems may arise if the values ​​of syntax elements such as max_num_merge_cand_minus_max_num_triangle_cand are constant, but the value of six_minus_max_num_merge_cand is not. This disclosure describes signaling techniques that address these issues. This disclosure also describes signaling techniques that may include bit-saving improvements.

[0123] This disclosure includes several techniques that can improve signaling at the PPS level and slice header level. These techniques can involve codec modes that use geometric shapes other than rectangular blocks (e.g., non-rectangular codec modes), for example, codec modes that use triangles or other non-rectangular shapes. At least one of the following proposed techniques or a combination of at least two of the following proposed techniques can be applied to VVC Draft 6.

[0124] For example, when reusing a regular merge list for constructing a non-rectangular codec mode merge list (such as a triangle merge list), if the maximum number of triangle merge candidates (e.g., MaxNumTriangleMergeCand) is greater than the value of MaxNumMergeCand (the maximum number of merge candidates), there may not be enough candidates (e.g., fewer than a predetermined threshold). Therefore, VVC draft 6 restricts the value of MaxNumTriangleMergeCand to be equal to or less than MaxNumMergeCand, and if MaxNumMergeCand is equal to 1, it is restricted to zero. If the value of pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1 is greater than 0 and the value of pps_six_minus_max_num_merge_cand_plus1 is equal to 0, MaxNumTriangleMergeCand is determined in the PPS and is constant in the slice header of the slices involved in the PPS, but multiple MaxNumMergeCand values ​​are derived in the slice header for each slice. If the value of MaxNumMergeCand in some slices is less than the constant value of MaxNumTriangleMergeCand, problems may occur. Because the value of MaxNumTriangleMergeCand depends on the value of MaxNumMergeCand, for example, MaxNumTriangleMergeCand <= MaxNumMergeCand, according to the technology of the present disclosure, if six_minus_max_num_merge_cand is signaled in the slice header, the video encoder 200 may also signal max_num_merge_cand_minus_max_num_triangle_cand in the slice header. The video encoder 200 may signal max_num_merge_cand_minus_max_num_triangle_cand and six_minus_max_num_merge_cand in the slice header and encode the corresponding video data, and the video decoder 300 may parse these syntax elements to determine how to decode the corresponding video data. For this example, the syntax changes to VVC Draft 6 Version 14 are in the following Table 2, <add> and< / add> Described between.

[0125]

[0126]

[0127]

[0128] Table 2

[0129] Another solution is disclosed herein to address the issues discussed above. According to the techniques of this disclosure, even if pps_six_minus_max_num_merge_cand_plus1 is equal to 0, the value of pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1 is allowed to be greater than 0. In this case, the value of MaxNumTriangleMergeCand is MaxNumMergeCand-max_num_merge_cand_minus_max_num_triangle_cand and even if MaxNumMergeCand is greater than or equal to 2, the value of MaxNumTriangleMergeCand may be less than 2. If MaxNumTriangleMergeCand is less than 2, the video encoder 200 and / or the video decoder 300 may reset MaxNumTriangleMergeCand to be equal to 2. The syntax changes to VVC draft 6 version 14 for Proposal 1.2 are shown in the following Table 3, <add> and< / add> Described between.

[0130]

[0131]

[0132]

[0133] Table 3

[0134] In VVC draft 6, if pps_six_minus_max_num_merge_cand_plus1 is equal to 5, MaxNumMergeCand is derived as 2, and in this case, pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1 must be zero or one. In VVC draft 6, when max_num_merge_cand_minus_max_num_triangle_cand is present, for example, when MaxNumMergeCand is greater than or equal to 2, the value of MaxNumTriangleMergeCand may be in the range of 2 to MaxNumMergeCand (inclusive). More specifically, if pps_six_minus_max_num_merge_cand_plus1 is equal to 5, MaxNumTriangleMergeCand may be a constant value of 2. According to the techniques of this disclosure, if pps_six_minus_max_num_merge_cand_plus1 is equal to 5, then the video decoder 300 may infer pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1 to be 1. For this example, the syntax changes to VVC Draft 6 version 14 are in the following Table 4, <add> and< / add> Described between.

[0135]

[0136]

[0137]

[0138] Table 4

[0139] In another example, according to the techniques of this disclosure, the video decoder 300 may determine whether the maximum number of merge candidates for a slice of video data is equal to a first value. The video decoder 300 may infer, based at least in part on the maximum number of merge candidates for the slice being equal to the first value, that the value of a first syntax element is equal to a second value, the first syntax element indicating the maximum number of merge candidates and the maximum number of merge candidates for a non-rectangular codec mode. The video decoder 300 may decode the slice based on the maximum number of merge candidates and the first syntax element. In some instances, for video data to which the first syntax element applies, the value of the first syntax element is equal to the maximum number of merge candidates minus the maximum number of merge candidates for the non-rectangular codec mode. In some examples, the first value is 2 and the second value is 0. In some examples, the non-rectangular codec mode is a triangular mode.

[0140] In some examples, the video decoder 300 may determine whether the value of a second syntax element indicating a maximum number of merge candidates is equal to a third value. The video decoder 300 may infer, based at least in part on the value of the second syntax element being equal to the third value, that the value of a third syntax element is equal to a fourth value, the third syntax element indicating the maximum number of merge candidates and the maximum number of merge candidates for non-rectangular codec mode. In some examples, for video data to which the second syntax element applies, the value of the second syntax element is equal to 6 minus the maximum number of merge candidates plus 1, and the second syntax element is in a picture parameter set, and wherein for video data to which the third syntax element applies, the value of the third syntax element is equal to the maximum number of merge candidates minus the maximum number of merge candidates for non-rectangular codec mode plus 1, and the third syntax element is in a picture parameter set. In some examples, the third value is 5, and the fourth value is 0. In some examples, the video decoder 300 may determine whether the third syntax element exists. In some examples, the video decoder 300 may determine whether the value of a fourth syntax element is equal to 1, the fourth syntax element indicating whether a parameter in a slice header is constant. In some examples, inferring the value of the third syntax element is further based on the absence of the third syntax element and the value of the fourth syntax element being equal to 1.

[0141] For example, if MaxNumMergeCand is equal to 2, the video decoder 300 may infer max_num_merge_cand_minus_max_num_triangle_cand to be 0. If pps_six_minus_max_num_merge_cand_plus1 is equal to 5, the video decoder 300 may further infer pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1 to be 0. For this example, the syntax changes to VVC Draft 6 version 14 are shown in Table 5 below, using <add> and< / add> The additional parts shown between and <delete> and< / delete> The deleted parts shown between are described.

[0142]

[0143]

[0144]

[0145]

[0146]

[0147] Form 5

[0148] The value of MaxNumMergeCand is derived from the slice header for different slices, and therefore various values ​​exist for MaxNumMergeCand in the slice header. When the value of MaxNumMergeCand differs, pps_max_num_merge_cand_minus_max_num_triangle_cand_minus1 may not be limited to the range of 0 to MaxNumMergeCand (inclusive). According to the techniques of this disclosure, a new parameter, PpsMaxNumMergeCand, may be added at the PPS level to distinguish it from another similar parameter, MaxNumMergeCand, at the slice header level. PpsMaxNumMergeCand is derived from 7-pps_six_minus_max_num_merge_cand_plus1 and is used to derive another PPS syntax element, pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1, to limit the value of pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1 to the range of 0 to PpsMaxNumMergeCand-1. The video encoder 200 can generate PpsMaxNumMergeCand and pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1 and limit the value of pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1 to the range of 0 to PpsMaxNumMergeCand-1, and encode the corresponding video data. The video decoder 300 can parse these syntax elements to determine how to decode the corresponding video data. The syntax changes to VVC draft 6 version 14 are shown in Table 6 below. <add> and< / add> Described between.

[0149]

[0150]

[0151] Table 6

[0152] In another example, according to the techniques of this disclosure, the value of pps_six_minus_max_num_merge_cand_plus1 can be used directly to limit the value of pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1. For example, the video encoder 200 can limit the value of pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1 to a range of 0 to 6 - pps_six_minus_max_num_merge_cand_plus1 and encode the corresponding video data, and the video decoder 300 can parse these syntax elements to determine how to decode the corresponding video data. The syntax changes to VVC Draft 6 Version 14 are shown in the following Table 7, <change> and< / change> Described between.

[0153]

[0154] Form 7

[0155] Figure 5 is a flow chart illustrating a signaling technique according to the present disclosure. The video decoder 300 may determine whether a maximum number of merge candidates for a slice of video data is equal to a first value (330). For example, the first value may be equal to 2 and the video decoder 300 may determine whether MaxNumMergeCand is equal to 2.

[0156] The video decoder 300 may infer a value of the first syntax element to be equal to a second value based at least in part on the maximum number of merge candidates for the slice being equal to the first value (332). For example, the second value may be 0, and the video decoder 300 may infer a value of the first syntax element (such as max_num_merge_cand_minus_max_num_triangle_cand) to be equal to 0 based on the maximum number of merge candidates for the slice being equal to 2.

[0157] In some examples, the first syntax element indicates a maximum number of merge candidates and a maximum number of merge candidates for a non-rectangular codec mode. For example, for video data to which the first syntax element applies, the value of the first syntax element can be equal to the maximum number of merge candidates minus the maximum number of merge candidates for the non-rectangular codec mode.

[0158] The video decoder 300 may decode the slice based on the maximum number of merge candidates and the first syntax element (334). In some instances, the video decoder 300 may also determine whether the value of the second syntax element indicating the maximum number of merge candidates is equal to a third value, and infer the value of the third syntax element to be equal to a fourth value based at least in part on the value of the second syntax element being equal to the third value. In some examples, the third syntax element indicates the maximum number of merge candidates and the maximum number of merge candidates for non-rectangular coding mode. In some examples, the third value is 5. In some examples, the fourth value is 0. In some examples, for video data to which the second syntax element applies, the value of the second syntax element is equal to 6 minus the maximum number of merge candidates plus 1. In some examples, the second syntax element is pps_six_minus_max_num_merge_cand_plus1. In some instances, for video data to which the third syntax element applies, the value of the third syntax element is equal to the maximum number of merge candidates minus the maximum number of merge candidates for non-rectangular coding mode plus 1. In some examples, the third syntax element is pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1.

[0159] In some examples, the video decoder 300 may determine whether a third syntax element is present. For example, the video decoder 300 may determine whether pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1 is present in the PPS. In some instances, the video decoder 300 may determine whether a value of a fourth syntax element is equal to 1. For example, the video decoder 300 may determine whether a value of constant_slice_header_params_enabled_flag is equal to 1. The video decoder 300 may further infer that the value of the third syntax element is 0 based on the absence of the third syntax element and the value of the fourth syntax element being 1. For example, the video decoder 300 may further infer that the value of pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1 is 0 based on the absence of pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1 and the value of constant_slice_header_params_enabled_flag being 1.

[0160] Figure 61 is a flowchart illustrating an example method for encoding a current block. The current block may include a current CU. Although relative to the video encoder 200 ( Figure 1 and Figure 3 ), but it should be understood that other devices may be configured to perform the same Figure 6 A similar approach to the one in the previous section.

[0161] In this example, initially, the video encoder 200 predicts a current block (350). For example, the video encoder 200 may form a prediction block for the current block. The video encoder 200 may then calculate a residual block for the current block (352). To calculate the residual block, the video encoder 200 may calculate the difference between the original, unencoded block of the current block and the prediction block. The video encoder 200 may then transform and quantize the coefficients of the residual block (354). Next, the video encoder 200 may scan the quantized transform coefficients of the residual block (356). During or after the scan, the video encoder 200 may entropy encode the transform coefficients (358). For example, the video encoder 200 may encode the transform coefficients using CAVLC or CABAC. The video encoder 200 may then output entropy encoded data for the block (360).

[0162] Figure 7 is a flowchart illustrating an example method for decoding a current block of video data. The current block may include a current CU. Although with respect to the video decoder 300 ( Figure 1 and Figure 4 ), but it should be understood that other devices may be configured to perform the same Figure 7 A similar approach to the one in the previous section.

[0163] The video decoder 300 may receive entropy-encoded data for a current block, such as entropy-encoded data corresponding to entropy-encoded prediction information for the current block and coefficients of a residual block (370). The video decoder 300 may entropy decode the entropy-encoded data to determine prediction information for the current block and reproduce coefficients of the residual block (372). The video decoder 300 may predict the current block (374), for example, using an intra-prediction or inter-prediction mode as indicated by the prediction information for the current block, to calculate a prediction block for the current block. The video decoder 300 may then inverse scan the reproduced coefficients (376) to create a block of quantized transform coefficients. The video decoder 300 may then inverse quantize and inverse transform the transform coefficients to produce a residual block (378). The video decoder 300 may ultimately decode the current block by combining the prediction block and the residual block (380).

[0164] According to the techniques of this disclosure, a video encoder and a video decoder may avoid conflicting syntax elements and may save signaling overhead.

[0165] This disclosure includes the following examples.

[0166] Example 1. A method for decoding video data, the method comprising:

[0167] Determining, by one or more processors, whether a maximum number of merge candidates for a slice of video data is equal to a first value; inferring, by the one or more processors, a value of a first syntax element to be equal to a second value based at least in part on the maximum number of merge candidates for the slice being equal to the first value, the first syntax element indicating the maximum number of merge candidates and the maximum number of merge candidates for a non-rectangular codec mode; and decoding the slice based on the maximum number of merge candidates and the value of the first syntax element.

[0168] Example 2. The method of Example 1, wherein for video data to which the first syntax element applies, a value of the first syntax element is equal to the maximum number of merge candidates minus the maximum number of merge candidates for a non-rectangular codec mode.

[0169] Example 3. The method of Example 1 or 2, further comprising determining whether a non-rectangular codec mode is enabled.

[0170] Example 4. The method of any combination of Examples 1-3, wherein the first value is 2 and the second value is 0.

[0171] Example 5. The method of any combination of Examples 1-4, wherein the non-rectangular encoding / decoding mode is a triangular mode.

[0172] Example 6. A method as any combination of Examples 1-5, further comprising: determining, by one or more processors, whether a value of a second syntax element indicating a maximum number of merge candidates is equal to a third value; inferring, by one or more processors, that a value of a third syntax element is equal to a fourth value based at least in part on the value of the second syntax element being equal to the third value, wherein the third syntax element indicates the maximum number of merge candidates and the maximum number of merge candidates for a non-rectangular coding mode.

[0173] Example 7. The method of Example 6, wherein for video data to which the second syntax element applies, the value of the second syntax element is equal to 6 minus the maximum number of merge candidates plus 1, and the second syntax element is in a picture parameter set, and wherein for video data to which the first syntax element applies, the value of the third syntax element is equal to the maximum number of merge candidates minus the maximum number of merge candidates for non-rectangular codec mode plus 1, and the third syntax element is in a picture parameter set.

[0174] Example 8. The method of Example 6 or 7, wherein the third value is 5 and the fourth value is 0.

[0175] Example 9. A method as in any combination of Examples 6-8, further comprising: determining, by one or more processors, whether a third syntax element exists; and determining, by one or more processors, whether a value of a fourth syntax element is equal to 1, the fourth syntax element indicating whether a parameter in the slice header is a constant, wherein inferring the value of the third syntax element is further based on the absence of the third syntax element and the value of the fourth syntax element being equal to 1.

[0176] Example 10. The method of any combination of Examples 1-9, further comprising displaying the decoded video data on a display device.

[0177] Example 11. A method for encoding and decoding video data, the method comprising: determining, by one or more processors, a first syntax element, the first syntax element being associated with a merge candidate; determining, by one or more processors and based on the first syntax element, a second syntax element; and encoding and decoding the video data, by one or more processors and based on the first syntax element and the second syntax element.

[0178] Example 12. The method of Example 11, wherein determining the second syntax element comprises: determining whether the first syntax element is signaled in a slice header; and based on the first syntax element being signaled in the slice header, determining the second syntax element in the slice header, wherein for video data to which the first syntax element applies, the value of the first syntax element is equal to 6 minus a maximum number of merge candidates, and for video data to which the second syntax element applies, the value of the second syntax element is equal to the maximum number of merge candidates minus a maximum number of triangle candidates.

[0179] Example 13. The method of Example 11, wherein determining the second syntax element comprises: determining whether a value of the first syntax element is greater than 0; determining whether a value of the second syntax element is less than 2; and resetting the value of the second syntax element to 2 based on the value of the first syntax element being greater than 0 and the value of the second syntax element being less than 2, wherein for video data to which the first syntax element applies, the value of the first syntax element is equal to the maximum number of merge candidates minus the maximum number of triangle candidates plus 1, the first syntax element is in a picture parameter set, and wherein for video data to which the second syntax element applies, the value of the second syntax element is equal to the maximum number of triangle merge candidates.

[0180] Example 14. The method of Example 11, wherein determining the second syntax element comprises: determining whether a value of the first syntax element is equal to 5; and based on the value of the first syntax element being equal to 5, inferring a value of the second syntax element to be equal to 1, wherein for video data to which the first syntax element applies, the value of the first syntax element is equal to 6 minus a maximum number of merge candidates plus 1, the first syntax element is in a picture parameter set, and wherein for video data to which the second syntax element applies, the value of the second syntax element is equal to the maximum number of merge candidates minus a maximum number of triangle candidates plus 1.

[0181] Example 15. The method of Example 11, wherein determining the second syntax element comprises: determining whether the value of the first syntax element is equal to 5; and based on the value of the first syntax element being 5, inferring the value of the second syntax element to be 0.

[0182] Example 16. The method of Example 15, wherein for video data to which the first syntax element applies, the value of the first syntax element is equal to 6 minus the maximum number of merge candidates plus 1, and the first syntax element is in a picture parameter set, and wherein for video data to which the second syntax element applies, the value of the second syntax element is equal to the maximum number of merge candidates minus the maximum number of triangle candidates plus 1, and the second syntax element is in a picture parameter set.

[0183] Example 17. The method of any of Examples 15-16, further comprising:

[0184] Determining, by the one or more processors, whether the value of the third syntax element is equal to 2; and inferring, by the one or more processors and based on the value of the third syntax element being equal to 2, the value of the fourth syntax element to be 0.

[0185] Example 18. The method of Example 17, wherein for video data to which the first syntax element applies, the value of the third syntax element is equal to a maximum number of merge candidates, and for video data to which the second syntax element applies, the value of the fourth syntax element is equal to the maximum number of merge candidates minus a maximum number of triangle candidates.

[0186] Example 19. A method as described in any of Examples 17-18, wherein determining the second syntax element includes: determining whether the second syntax element exists; determining whether the value of a fifth syntax element is equal to 1, the fifth syntax element indicating whether a parameter in the slice header is a constant; and based on the second syntax element not existing and the value of the fifth syntax element being equal to 1, inferring the value of the second syntax element to be equal to 0.

[0187] Example 20. The method of Example 11, wherein determining the second syntax element comprises: determining whether a value of the first syntax element is greater than or equal to 1; and based on the value of the first syntax element being greater than or equal to 1, determining that the second syntax element is equal to 7 minus the first syntax element, wherein for video data to which the first syntax element applies, the value of the first syntax element is equal to 6 minus a maximum number of merge candidates plus 1, and wherein for video data to which the second syntax element applies, the value of the second syntax element is equal to the maximum number of merge candidates, and the second syntax element is in a picture parameter set.

[0188] Example 21. The method of Example 11, wherein determining the second syntax element comprises: determining a value of 6 minus the value of the first syntax element; and limiting the value of the second syntax element to a range of values ​​from 0 to 6 minus the value of the first syntax element, wherein for video data to which the first syntax element applies, the value of the first syntax element is equal to 6 minus the maximum number of merge candidates plus 1, and wherein for video data to which the second syntax element applies, the value of the second syntax element is equal to the maximum number of merge candidates minus the maximum number of triangle candidates plus 1.

[0189] Example 22. A method of encoding and decoding video data, the method comprising: determining whether six_minus_max_num_merge_cand is to be signaled in a slice header; if six_minus_max_num_merge_cand is to be signaled in the slice header, also signaling max_num_merge_cand_minus_max_num_triangle_cand in the slice header; and encoding and decoding the video data based on six_minus_max_num_merge_cand and max_num_merge_cand_minus_max_num_triangle_cand.

[0190] Example 23. The method of Example 22, further comprising: determining whether pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1 is present and constant_slice_header_params_enabled_flag is equal to one; and if pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1 is not present and constant_slice_header_params_enabled_flag is equal to one, inferring pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1 to be equal to zero.

[0191] Example 24. A method of encoding and decoding video data, the method comprising: determining whether MaxNumTriangleMergeCand is less than two; if MaxNumTriangleMergeCand is less than two, resetting MaxNumTriangleMergeCand to be equal to two; and encoding and decoding the video data based on MaxNumTriangleMergeCand and MaxNumTriangleMergeCand.

[0192] Example 25. The method of Example 24, further comprising: determining whether pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1 is greater than zero; and if pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1 is greater than zero and MaxNumTriangleMergeCand is less than two, resetting MaxNumTriangleMergeCand to equal two.

[0193] Example 26. A method of encoding and decoding video data, the method comprising: determining whether pps_six_minus_max_num_merge_cand_plus1 is equal to five; if pps_six_minus_max_num_merge_cand_plus1 is equal to five, inferring pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1 to be one; and

[0194] The video data is encoded and decoded based on pps_six_minus_max_num_merge_cand_plus1 and pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1.

[0195] Example 27. The method of Example 26, further comprising: determining whether constant_slice_header_params_enabled_flag is equal to one; and if pps_six_minus_max_num_merge_cand_plus1 is equal to five and constant_slice_header_params_enabled_flag is equal to one, inferring pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1 to be one.

[0196] Example 28. The method of Example 26 or 27, further comprising: if pps_six_minus_max_num_merge_cand_plus1 is not equal to five, inferring pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1 to be zero.

[0197] Example 29. A method of encoding and decoding video data, the method comprising: determining whether pps_six_minus_max_num_merge_cand_plus1 is equal to five; if pps_six_minus_max_num_merge_cand_plus1 is equal to five, inferring pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1 to be zero; determining whether MaxNumMergeCand is equal to two; if MaxNumMergeCand is equal to two; inferring max_num_merge_cand_minus_max_num_triangle_cand to be zero; and encoding and decoding the video data based on pps_six_minus_max_num_merge_cand_plus1, pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1, MaxNumMergeCand, and max_num_merge_cand_minus_max_num_triangle_cand.

[0198] Example 30. The method of Example 29, further comprising: determining whether pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1 does not exist and the constant slice header parameter enable flag is equal to one; and if pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1 does not exist and the constant slice header parameter enable flag is equal to one, inferring pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1 to be zero.

[0199] Example 31. The method of Example 29 or 30, further comprising: determining whether max_num_merge_cand_minus_max_num_triangle_cand exists, whether sps_triangle_enabled_flag is equal to one, and whether MaxNumMergeCand is equal to two; if max_num_merge_cand_minus_max_num_triangle_cand does not exist, sps_triangle_enabled_flag is equal to one and MaxNumMergeCand is equal to two, setting MaxNumTriangleMergeCand equal to two.

[0200] Example 32. A method of encoding and decoding video data, the method comprising: generating a PpsMaxNumMergeCand parameter in a picture parameter set (PPS); and encoding and decoding the video data based on the PpsMaxNumMergeCand parameter.

[0201] Example 33. The method of Example 32, wherein generating the PpsMaxNumMergeCand parameter comprises subtracting pps_six_minus_max_num_merge_cand_plus1 from seven.

[0202] Example 34. The method of Example 32 or 33, further comprising: determining whether pps_six_minus_max_num_merge_cand_plus1 is greater than or equal to one; and if pps_six_minus_max_num_merge_cand_plus1 is greater than or equal to one, generating the PpsMaxNumMergeCand parameter comprises subtracting pps_six_minus_max_num_merge_cand_plus1 from seven.

[0203] Example 35. The method of any combination of Examples 32-34, further comprising: determining whether MaxNumMergeCand exists; and if MaxNumMergeCand does not exist, inferring MaxNumMergeCand to be equal to the PpsMaxNumMergeCand parameter.

[0204] Example 36. A method of encoding and decoding video data, the method comprising: limiting a value of pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1 based on a value of pps_six_minus_max_num_merge_cand_plus1; and encoding and decoding the video data based on pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1 and pps_six_minus_max_num_merge_cand_plus1.

[0205] Example 37. The method of Example 36, wherein the value of pps_max_num_merge_cand_minus_max_num_triangle_cand_plus1 is restricted to a range of zero to six - pps_six_minus_max_num_merge_cand_plus1.

[0206] Example 38. The method of any of Examples 1-37, wherein encoding and decoding includes decoding.

[0207] Example 39. The method of any of Examples 1-37, wherein encoding and decoding includes encoding.

[0208] Example 40. An apparatus for encoding and decoding video data, the apparatus comprising one or more components for performing the method of any of Examples 1-39.

[0209] Example 41. The apparatus of Example 40, wherein the one or more components include one or more processors implemented in circuitry.

[0210] Example 42. The apparatus of any of Examples 40 and 41, further comprising a memory for storing video data.

[0211] Example 43. The apparatus of any of Examples 40-42, further comprising a display configured to display the decoded video data.

[0212] Example 44. The device of any of Examples 40-43, wherein the device comprises one or more of a camera, a computer, a mobile device, a broadcast receiver device, or a set-top box.

[0213] Example 45. The device of any of Examples 40-44, wherein the device comprises a video decoder.

[0214] Example 46. The device of any of Examples 40-45, wherein the device comprises a video encoder.

[0215] Example 47. A computer-readable storage medium having instructions stored thereon, which, when executed, cause one or more processors to perform the method of any of Examples 1-39.

[0216] It should be appreciated that, depending on the example, certain actions or events of any of the techniques described herein may be performed in a different sequence, may be added, combined, or omitted entirely (e.g., not all described actions or events are necessary for practice of the techniques). Moreover, in some examples, actions or events may be performed concurrently, such as through multithreading, interrupt handling, or multiple processors, rather than sequentially.

[0217] In one or more examples, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored or transmitted as one or more instructions or code on a computer-readable medium and executed by a hardware-based processing unit. Computer-readable media may include computer-readable storage media, which corresponds to tangible media such as data storage media; or communication media, including any medium that facilitates the transfer of a computer program from one place to another, for example, according to a communication protocol. In this manner, computer-readable media may generally correspond to (1) non-transitory tangible computer-readable storage media or (2) communication media such as signals or carrier waves. Data storage media may be any available media that can be accessed by one or more computers or one or more processors to retrieve instructions, codes, and / or data structures for implementing the techniques described in this disclosure. A computer program product may include computer-readable media.

[0218] As an example and not limitation, such computer-readable storage media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage or other magnetic storage devices, flash memory, or any other medium that can be used to store required program code in the form of instructions or data structures and that can be accessed by a computer. Similarly, any connection is appropriately referred to as a computer-readable medium. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, microwaves are used to send instructions from a website, server, or other remote source, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of medium. However, it should be understood that computer-readable storage media and data storage media do not include connection, carrier wave, signal, or other transient media, but are for non-transient, tangible storage media. Disk and optical disk used herein include compact disk (CD), laser disk, optical disk, digital versatile disk (DVD), floppy disk, and blue disc, wherein disks typically reproduce data magnetically, while optical disks reproduce data optically with lasers. The combination of the above items should also be included in the scope of computer-readable media.

[0219] Instructions may be executed by one or more processors such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Accordingly, the terms "processor" and "processing circuitry" as used herein may refer to any of the aforementioned structures or any other structure suitable for implementing the techniques described herein. Additionally, in some aspects, the functionality described herein may be provided within dedicated hardware and / or software modules configured for encoding and decoding, or incorporated into a combined codec. Similarly, the technology may be fully implemented in one or more circuits or logic elements.

[0220] The technology of the present disclosure can be implemented in various devices or apparatuses, including wireless handheld devices, integrated circuits (ICs) or IC sets (e.g., chipsets). Various components, modules, or units are described in this disclosure to emphasize the functional aspects of devices configured to perform the disclosed technology, but do not necessarily need to be implemented by different hardware units. More specifically, as described above, the various units can be combined in a codec hardware unit or provided by a collection of interoperable hardware units including one or more processors as described above in combination with appropriate software and / or firmware.

[0221] Various examples have been described. These and other examples are within the scope of the following claims.

Claims

1. A method for decoding video data, wherein the video data includes one or more slices, the one or more slices including a first slice, the method comprising: determining, by one or more processors, whether a maximum number of merge candidates for the first stripe is equal to two; inferring, by the one or more processors, a value of a first syntax element equal to zero based at least in part on the maximum number of merge candidates for the first slice being equal to two, the value of the first syntax element being equal to the maximum number of merge candidates minus a maximum number of merge candidates for a non-rectangular codec mode for the video data to which the first syntax element applies; as well as The first slice is decoded based on the maximum number of merge candidates for the first slice and a value of the first syntax element. 2 . The method of claim 1 , further comprising determining whether the non-rectangular codec mode is enabled. The method of claim 1 , wherein the non-rectangular encoding / decoding mode is a triangular mode.

4. The method of claim 1 , further comprising: Determining, by the one or more processors, that the non-rectangular encoding and decoding mode is enabled and that the maximum number of merge candidates is equal to 2; as well as Based on determining that the non-rectangular codec mode is enabled and the maximum number of merge candidates is equal to 2, determining that the maximum number of merge candidates for the non-rectangular codec mode is equal to 2.

5. The method according to claim 1, wherein The one or more stripes are greater than one in number, and the one or more stripes include a second stripe, the method further comprising: receiving, based on a determination by the one or more processors that the maximum number of merge candidates for the second slice of the video data is greater than two and the non-rectangular codec mode is enabled, an instance of the first syntax element, the instance indicating, for a second slice of video data to which the instance of the first syntax element applies, the maximum number of merge candidates minus a maximum number of merge candidates for the non-rectangular codec mode; The second slice is decoded based on the maximum number of merge candidates for the second slice and a value of the instance of the first syntax element.

6. The method of claim 1 , further comprising: The decoded video data is displayed on a display device.

7. An apparatus for decoding video data, the video data comprising one or more slices, the one or more slices comprising a first slice, the apparatus comprising: a memory configured to store the video data; as well as one or more processors implemented in circuitry and communicatively coupled to the memory, the one or more processors configured to: Determining whether the maximum number of merge candidates for the first stripe is equal to two; inferring a value of a first syntax element to be equal to zero based at least in part on the maximum number of merge candidates for the first slice being equal to two, the value of the first syntax element being equal to the maximum number of merge candidates minus a maximum number of merge candidates for a non-rectangular codec mode for the video data to which the first syntax element applies; as well as The first slice is decoded based on a maximum number of merge candidates for the first slice and the first syntax element.

8. The device of claim 7, wherein the one or more processors are further configured to determine whether the non-rectangular codec mode is enabled.

9. The apparatus of claim 7, wherein the non-rectangular encoding / decoding mode is a triangular mode.

10. The apparatus of claim 7, wherein the one or more processors are further configured to: Determining that the non-rectangular codec mode is enabled and the maximum number of merge candidates is equal to 2; and Based on determining that the non-rectangular codec mode is enabled and the maximum number of merge candidates is equal to 2, determining that the maximum number of merge candidates for the non-rectangular codec mode is equal to 2.

11. The apparatus of claim 7, wherein: The number of the one or more stripes is greater than one, and the one or more stripes include a second stripe, the one or more processors are further configured to: receiving, based on a determination that the maximum number of merge candidates for the second slice of the video data is greater than two and the non-rectangular codec mode is enabled, an instance of the first syntax element, the instance indicating, for a second slice of video data to which the instance of the first syntax element applies, the maximum number of merge candidates minus a maximum number of merge candidates for the non-rectangular codec mode; The second slice is decoded based on the maximum number of merge candidates for the second slice and a value of the instance of the first syntax element.

12. The device of claim 7, further comprising a display device configured to display the video data.

13. The device of claim 7, wherein the device comprises a wireless communication device.

14. A non-transitory computer-readable storage medium having stored thereon instructions for decoding video data, the video data comprising one or more slices, the one or more slices comprising a first slice, the instructions, when executed by one or more processors, causing the one or more processors to: Determining whether the maximum number of merge candidates for the first stripe is equal to two; inferring a value of a first syntax element to be equal to zero based at least in part on the maximum number of merge candidates for the first slice being equal to two, the value of the first syntax element being equal to the maximum number of merge candidates minus a maximum number of merge candidates for a non-rectangular codec mode for the video data to which the first syntax element applies; as well as The first slice is decoded based on a maximum number of merge candidates for the first slice and the first syntax element.

15. An apparatus for decoding video data, the video data comprising one or more slices, the one or more slices comprising a first slice, the apparatus comprising: means for determining whether a maximum number of merge candidates for the first stripe is equal to two; means for inferring a value of a first syntax element equal to zero based at least in part on the maximum number of merge candidates for the first slice being equal to two, the value of the first syntax element being equal to the maximum number of merge candidates minus a maximum number of merge candidates for a non-rectangular codec mode for the video data to which the first syntax element applies; as well as Means for decoding the first slice based on a maximum number of merge candidates for the first slice and a value of the first syntax element.

Images