A Method for Measuring Insertion Loss of QFN Package Housing

Abstract

The present invention provides a method for testing the insertion loss of a QFN package. The method involves extracting and replicating the pattern and structure of a high-frequency I / O transmission line twice on a processing layout of the QFN package, and designing a test dummy chip so that the patterns and structures of the two high-frequency I / O transmission lines are mirror images of each other and connected in series. The test dummy chip and the QFN package are manufactured using the same materials and processes, and are manufactured from the same layout and batch. An insertion loss value detection instrument is used to connect the two ends of the transmission line on the manufactured test dummy chip via a connecting assembly to perform insertion loss value detection. The insertion loss value is then divided by two to obtain the insertion loss value of the high-frequency I / O transmission line of a single QFN package. The method utilizes the process characteristics of full-panel array mass production of QFN packages and the characteristic that the insertion loss of two homogeneous transmission lines connected in series is doubled. The high-frequency I / O transmission line of the QFN package is replicated twice and mirrored in series to produce a test dummy chip, which serves as an insertion loss test sample. This method eliminates the need for introducing other structures, does not damage the QFN package product itself, and can achieve high-precision batch testing.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit packaging, and in particular to a method for testing the insertion loss of a QFN packaging shell. Background Art

[0002] QFN (quad flat no-lead) packages feature small size, light weight, and excellent electrical and thermal performance. They are widely used in the packaging of high-speed digital and microwave circuit chips. Insertion loss is one of the key electrical performance indicators of QFN packages, representing the ability of the high-frequency I / O (input / output) transmission line from the internal bond pad to the external bottom solder pin to transmit high-frequency signals. Generally, insertion loss testing is performed on each production batch of QFN packages to ensure product electrical quality control.

[0003] Under the existing technology, the commonly used method for testing the insertion loss of QFN package shells is as follows: first, a dedicated high-frequency test PCB board is made according to the distribution drawing of the solder pins on the bottom surface of the QFN package shell; then, QFN package shell samples selected according to a certain sampling ratio are soldered to the test PCB board, so that the solder pins on the bottom surface of the shell are connected to the high-frequency transmission line on the upper surface of the test PCB board; then, a microwave probe is pressed on the bonding pad inside the QFN package shell, and another microwave probe is pressed on the end of the high-frequency transmission line on the test PCB board; then, the two microwave probes are connected to the input port and output port of the vector network analyzer respectively using RF cables, and the S21 parameter value displayed on the vector network analyzer is read to obtain the insertion loss value.

[0004] However, the above test method has the following disadvantages: QFN shell welding will produce additional insertion loss, increasing test errors; high-frequency transmission lines on the PCB will produce additional insertion loss, increasing test errors; the QFN shell is difficult to restore to its original state after welding, which is a lossy test; the test sample production cost is high and the cycle is long. Summary of the Invention

[0005] The object of the present invention is to provide a method for testing the insertion loss of a QFN package shell, so as to solve the problems raised in the above background technology through a simple and efficient testing method.

[0006] To achieve the above object, the present invention adopts the following technical solutions:

[0007] A method for testing insertion loss of a QFN package shell comprises the following steps:

[0008] S1. Extract and copy the graphics and structure of the high-frequency I / O transmission line twice on the QFN package shell processing layout;

[0009] S2. Design a test companion chip so that the patterns and structures of the two high-frequency I / O transmission lines are mirror images of each other and connected in series;

[0010] S3. The test chip and the QFN package shell are processed and manufactured using the same material process and the same layout and batch;

[0011] S4, using an insertion loss value detection instrument to connect the two ends of the transmission line on the prepared test chip through a connection component to perform insertion loss value detection;

[0012] S5. Divide the insertion loss value detected by the insertion loss value detection instrument by 2 to obtain the insertion loss value of the high-frequency I / O transmission line of a single QFN package shell.

[0013] Preferably, the QFN package shell is made of resin and metal materials or ceramic and metal materials.

[0014] Preferably, the insertion loss value detection instrument is a network analyzer, a signal analyzer or other instruments with the same functions.

[0015] Preferably, the connection component is a microwave probe, a coaxial connector or other devices having the same function.

[0016] As can be seen from the above technical solution, the present invention utilizes the process characteristics of mass production of full-panel arrays of QFN package shells and the characteristic that the insertion loss is doubled when two homogeneous transmission lines are connected in series. The high-frequency I / O transmission line of the QFN package shell is replicated twice and mirrored in series to produce a test companion chip, which is used as a test sample for insertion loss. There is no need to introduce other structures, and no damage is caused to the QFN package shell product itself. Therefore, no other test errors will be introduced, and high-precision batch testing can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of the steps of the present invention.

[0018] Figure 2 is a connection diagram of the test device of the present invention;

[0019] In the figure: 1. Test chip; 2. Bonding pad; 3. Connecting components. DETAILED DESCRIPTION

[0020] A preferred embodiment of the present invention is described in detail below with reference to the accompanying drawings.

[0021] like Figure 1 The QFN package case insertion loss test method shown includes the following steps:

[0022] S1. Extract and copy the graphics and structure of the high-frequency I / O transmission line twice on the QFN package shell processing layout; in actual use, the QFN package shell is usually designed as a full-page array in the design layout. The parameters of the QFN package shell on the unified layout are exactly the same and mass production is achieved through the same version and batch production. The insertion loss represents the ability of the high-frequency I / O transmission line from the internal bonding pad to the external bottom welding pin of the shell to transmit high-frequency signals. Therefore, the high-frequency I / O transmission line in the designed QFN package shell can be extracted and copied separately in the blank space on the layout as a test sample, thereby realizing batch testing.

[0023] S2. Design a test companion chip so that the patterns and structures of the two high-frequency I / O transmission lines are mirror images of each other and are connected in series. Based on the characteristic that the insertion loss of two homogeneous transmission lines connected in series doubles, it can be concluded that the insertion losses of the two high-frequency I / O transmission lines with mirror images of each other in the embodiment are equal.

[0024] S3. The test companion chip and the QFN package shell are manufactured using the same materials and processes, and the same layout and batch, to ensure that no additional errors are introduced after the test companion chip is designed and manufactured as the test sample, thereby ensuring test accuracy. The QFN package shell of the present invention is made of resin and metal materials or ceramic and metal materials.

[0025] S4. Use an insertion loss value detection instrument to connect the two ends of the transmission line on the prepared test chip through a connecting component to perform insertion loss value detection; the high-frequency I / O transmission line is provided with a bonding pad for connection, and the insertion loss value detection instrument adopts a network analyzer, a signal analyzer or other instruments with the same function; the connecting component adopts a microwave probe, a coaxial connector or other devices with the same function; this preferred embodiment adopts a network analyzer and a microwave probe for detection, and the microwave probe can be directly pressed on the bonding pad, and the measured value is the insertion loss value of the two high-frequency I / O transmission lines in series.

[0026] S5. Divide the insertion loss value detected by the insertion loss value tester by 2 to obtain the insertion loss value of the high-frequency I / O transmission line of a single QFN package shell. Based on the above-mentioned characteristic that the insertion loss of two homogeneous transmission lines connected in series is doubled, the value of the S21 parameter displayed by the vector network analyzer is twice the insertion loss value of the high-frequency I / O transmission line of a single QFN package shell.

[0027] The technical solution of the present invention is further described below through comparative experiments:

[0028] Experimental Subject: Insertion loss test on three different batches of QFN package housings;

[0029] Example: According to the technical solution of the present invention, a high-frequency I / O transmission line is replicated twice on the QFN package shell processing layout and mirrored in series to design a test companion chip. The test companion chip and the corresponding batch of QFN package shells are made of the same process materials to produce test samples, and insertion loss testing is performed;

[0030] Comparative Example: According to the test method in the background art, a dedicated high-frequency test PCB was produced based on the corresponding batch of QFN package shell bottom surface solder pin distribution drawings. QFN package shell samples sampled at a sampling rate of 10% were soldered to the test PCB, and the solder pins on the bottom surface of the shell were connected to the high-frequency transmission line on the upper surface of the test PCB. Insertion loss testing was then performed.

[0031] The test data are shown in the following table:

[0032]

[0033] The above experiments show that the present invention utilizes the process characteristics of mass production of full-panel arrays of QFN package shells and the characteristic that the insertion loss is doubled when two homogeneous transmission lines are connected in series. The high-frequency I / O transmission lines of the QFN package shell are replicated twice for mirror-image series connection, and a test companion chip is produced as a test sample for insertion loss. No other structures are required, and the QFN package shell product itself is not damaged. Therefore, no other test errors are introduced, and high-precision batch testing is achieved.

[0034] The present invention is not only applicable to QFN type packaging shells, but can also be used for testing the insertion loss of various types of packaging shells such as DFN type, LCC type, CFP type, and various microwave devices, packaging substrates and shells for high-speed digital circuits. It is also applicable to testing return loss and standing wave ratio. In specific use, the design of the test companion chip can be carried out according to specific circumstances.

[0035] The above-described embodiments are merely descriptions of preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should fall within the scope of protection determined by the claims of the present invention.

Claims

1. A QFN package shell insertion loss test method, characterized in that: The following steps are involved: S1. Extract and copy the graphics and structure of the high-frequency I / O transmission line twice on the QFN package shell processing layout; S2. Design a test companion chip so that the patterns and structures of the two high-frequency I / O transmission lines are mirror images of each other and are connected in series; the insertion losses of the two mirror images of each other's high-frequency I / O transmission lines are equal; S3. The test chip and the QFN package shell are processed and manufactured using the same material process and the same layout and batch; S4, using an insertion loss value detection instrument to connect the two ends of the transmission line on the prepared test chip through a connection component to perform insertion loss value detection; S5. Divide the insertion loss value detected by the insertion loss value detection instrument by 2 to obtain the insertion loss value of the high-frequency I / O transmission line of a single QFN package shell.

2. The QFN package shell insertion loss test method according to claim 1, characterized in that: The QFN package shell is made of resin and metal materials or ceramic and metal materials.

3. The QFN package shell insertion loss test method according to claim 1, characterized in that: The insertion loss value detection instrument adopts a network analyzer, a signal analyzer or other instruments with the same functions.

4. The QFN package shell insertion loss test method according to claim 1, characterized in that: The connection component adopts a microwave probe, a coaxial connector or other devices with the same function.

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