Interconnection status online monitoring circuit and method

Abstract

The present application relates to an online monitoring circuit and method for interconnection status. The method comprises: controlling the first timer module to output a digital pulse signal of a preset period via a pulse output pin, so that the comparator outputs a square wave signal; controlling the second timer to count the preset pulse width in the square wave signal, and the preset pulse width is less than the set value; comparing the count value within the preset unit time with the abnormal threshold, and judging the interconnection status between the processor chip and the printed circuit board according to the comparison result. The method does not need to increase too much additional cost, and can representatively implement effective monitoring and evaluation for the weak links of board-level solder joint interconnection; and it has strong applicability. At present, most of the on-chip resources contain multiple modules such as timer counters, and general applications do not use all of them. The conditions of the remaining timer modules and the remaining pins are relatively easy to meet in engineering applications, and can be widely promoted and utilized.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit packaging detection, and in particular to an online monitoring circuit, method and storage medium for interconnection status. Background Art

[0002] With the continuous development of microelectronics technology, microelectronics packaging technology has also developed rapidly. The pins of chips are becoming more and more dense and thinner, especially the main processor chip that handles functions. The area is relatively large. In the application of electronic products, there are certain hidden dangers. One of them is that the thermal expansion coefficients of large-area devices and circuit board materials are quite different, which can easily cause thermal stress inside the solder joints and cause stress concentration at the places where the strain is not coordinated, leading to crack initiation and expansion. The greater the stress, the greater the strain, and the greater the possibility of crack initiation and expansion, which ultimately leads to solder joint failure, even loss of circuit function and causing major accidents.

[0003] In the field of electronic component failure physics technology, a lot of research has been done on the failure physics and characterization characteristics of device package solder joints of important components. A large number of overstress tests and failure mode analyses of package solder joint failures have been carried out in a targeted manner, and a series of analysis methods have been formed, including X-ray fluoroscopy, metallographic section analysis, infrared thermal imaging analysis, energy spectrum and scanning electron microscopy analysis, staining and penetration detection analysis, electrical excitation characteristics analysis and other inspection and detection methods. How to carry out online monitoring and early warning of solder joint failures is currently an important technical direction for improving the operational reliability of important and core equipment. Summary of the invention

[0004] Based on this, it is necessary to provide an online monitoring circuit and method for the interconnection status in response to the above-mentioned technical problems, so as to solve the problem of quality degradation of soldering interconnections between processor-type chips with larger areas and printed circuit boards, and to propose a low-cost technical solution for online self-monitoring, self-diagnosis and self-evaluation of the interconnection status of integrated circuits. In this way, in engineering applications, it is possible to effectively monitor and warn of integrated circuit interconnection failure problems, and improve the reliability of electronic products and equipment.

[0005] In order to achieve the above-mentioned purpose and other purposes, the first aspect of the present application provides an interconnection status online monitoring circuit, which is used to monitor the interconnection status of a processor chip and a printed circuit board, wherein a pulse output pin of a first timer module in the processor chip is electrically connected to a first input terminal of a comparator via a first pad on the printed circuit board;

[0006] The comparator is configured as follows: a first input terminal is grounded via a capacitive unit arranged on the printed circuit board, a second input terminal is electrically connected to a reference voltage, and an output terminal is electrically connected to a timing input pin of a second timer module in the processor chip via a second pad on the printed circuit board;

[0007] Wherein, the processor chip is configured as:

[0008] Controlling the first timer module to output a digital pulse signal of a preset period via the pulse output pin so that the comparator outputs a square wave signal;

[0009] Controlling the second timer to count a preset pulse width in the square wave signal, wherein the preset pulse width is less than a set value;

[0010] The count value within a preset unit time is compared with an abnormal threshold, and the interconnection state between the processor chip and the printed circuit board is determined according to the comparison result.

[0011] In the interconnection status online monitoring circuit in the above embodiment, by setting the first timer module to the pulse output mode, a digital pulse with equal period is output to the outside; the digital pulse is input to the comparator after passing through the first pad, and forms a square wave signal after being shaped by the comparator; the square wave signal is transmitted to the second timer module through the second pad, and the second timer module is set to the input mode used for timing, and is used to count the preset pulse width in the square wave signal. The change of the pulse width reflects the change of the solder joint impedance and characterizes its degradation and failure degree, thereby reflecting the interconnection quality between the processor chip and the printed circuit board.

[0012] In one embodiment, the processor chip is further configured to:

[0013] Obtaining a clock frequency division function of the first timer module;

[0014] The frequency of the digital pulse signal is controlled to be 90khz-110khz and the duty cycle is 45-55 according to the clock division function.

[0015] In one embodiment, the processor chip is further configured to:

[0016] Acquire the set value, the minimum timing unit of the second timer module and the timing trigger condition, wherein the timing trigger condition includes a rising edge trigger or a falling edge trigger;

[0017] According to the set value, the minimum timing unit and the timing trigger condition, the preset pulse width in the square wave signal is counted, and the count value is obtained.

[0018] In one of the embodiments, the timing trigger condition is a rising edge trigger and the timing end condition is a falling edge trigger;

[0019] If the count value is less than the abnormal threshold, it is determined that there is an abnormality in the solder joint interconnection between the processor chip and the printed circuit board;

[0020] If the count value is greater than or equal to the normal threshold, it is determined that the interconnection between the processor chip and the printed circuit board is normal.

[0021] The second aspect of the present application provides an online monitoring method for interconnection status, which is used to monitor the interconnection status of a processor chip and a printed circuit board, wherein a pulse output pin of a first timer module in the processor chip is electrically connected to a first input terminal of a comparator via a first pad on the printed circuit board; the comparator is configured as follows: the first input terminal is grounded via a capacitive unit arranged on the printed circuit board, the second input terminal is electrically connected to a reference voltage, and the output terminal is electrically connected to a timing input pin of a second timer module in the processor chip via a second pad on the printed circuit board; the method comprises:

[0022] Controlling the first timer module to output a digital pulse signal of a preset period via the pulse output pin so that the comparator outputs a square wave signal;

[0023] Controlling the second timer to count a preset pulse width in the square wave signal, wherein the preset pulse width is less than a set value;

[0024] The count value within a preset unit time is compared with an abnormal threshold, and the interconnection state between the processor chip and the printed circuit board is determined according to the comparison result.

[0025] In the online monitoring method of interconnection status in the above embodiment, by setting the first timer module to the pulse output mode, a digital pulse with equal period is outputted to the outside; the digital pulse is input to the comparator after passing through the first pad, and a square wave signal is formed after being shaped by the comparator; the square wave signal is transmitted to the second timer module through the second pad, and the second timer module is set to the input mode used for timing, and is used to count the preset pulse width in the square wave signal. The change of the pulse width reflects the change of the solder joint impedance and characterizes its degradation and failure degree, thereby reflecting the interconnection quality between the processor chip and the printed circuit board.

[0026] In one embodiment, controlling the first timer module to output a digital pulse signal of a preset period via the pulse output pin includes:

[0027] Obtaining a clock frequency division function of the first timer module;

[0028] The frequency of the digital pulse signal is controlled to be 90khz-110khz and the duty cycle is 45-55 according to the clock division function.

[0029] In one embodiment, controlling the second timer to count the preset pulse width in the square wave signal includes:

[0030] Acquire the set value, the minimum timing unit of the second timer module and the timing trigger condition, wherein the timing trigger condition includes a rising edge trigger or a falling edge trigger;

[0031] According to the set value, the minimum timing unit and the timing trigger condition, the preset pulse width in the square wave signal is counted, and the count value is obtained.

[0032] In one embodiment, the timing trigger condition is a rising edge trigger and the timing end condition is a falling edge trigger; and judging the interconnection state between the processor chip and the printed circuit board according to the comparison result includes:

[0033] If the count value is less than the abnormal threshold, it is determined that there is an abnormality in the solder joint interconnection between the processor chip and the printed circuit board;

[0034] If the count value is greater than or equal to the normal threshold, it is determined that the interconnection between the processor chip and the printed circuit board is normal.

[0035] A third aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of any one of the methods described in the embodiments of the present application are implemented.

[0036] The fourth aspect of the present application provides a computer program product, including a computer program, characterized in that when the computer program is executed by a processor, the steps of any one of the methods in the embodiments of the present application are implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 A schematic diagram of the structure of an online monitoring circuit for interconnection status provided in an embodiment of the present application;

[0039] Figure 2 This is a response waveform diagram of a first-order RC circuit in an embodiment of the present application;

[0040] Figure 3 A schematic diagram of the structure of an equivalent circuit of an online monitoring circuit for interconnection status provided in an embodiment of the present application;

[0041] Figure 4A waveform diagram comparing normal pulse width and abnormal pulse width in one embodiment of the present application;

[0042] Figure 5 A schematic diagram of a flow chart of an online monitoring method for interconnection status provided in an embodiment of the present application;

[0043] Figure 6 A schematic diagram of a flow chart of an online monitoring method for interconnection status provided in another embodiment of the present application;

[0044] Figure 7 A schematic diagram of a flow chart of an online monitoring method for interconnection status provided in yet another embodiment of the present application;

[0045] Figure 8 A flow chart of an online monitoring method for interconnection status provided in another embodiment of the present application. DETAILED DESCRIPTION

[0046] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0048] It can be understood that the terms "first", "second", etc. used in the present application can be used in this article to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element.

[0049] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is transmission of electrical signals or data between the connected objects.

[0050] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0051] With the continuous development of microelectronics technology, microelectronics packaging technology has also developed rapidly. The pins of chips are becoming more and more dense and thinner, especially the main processor chip that handles functions. The area is relatively large. In the application of electronic products, there are certain hidden dangers. One of them is that the thermal expansion coefficients of large-area devices and circuit board materials are quite different, which can easily cause thermal stress inside the solder joints and cause stress concentration at the places where the strain is not coordinated, leading to crack initiation and expansion. The greater the stress, the greater the strain, and the greater the possibility of crack initiation and expansion, which ultimately leads to solder joint failure, even loss of circuit function and causing major accidents.

[0052] In the case of solder joint failure, whether it is cracks or breaks or even the loss of the entire solder ball, it will eventually be reflected in the connection impedance from the electrical characteristics. The open circuit situation is that the impedance changes from normal to infinite, and the situation that causes some connection contacts to short circuit (the solder ball falls off and falls to other metal points) is that the impedance changes from normal to infinitesimal. Both of these situations have a significant and serious impact on the basic functions of the entire circuit. This situation is easy to expose the fault so that the user can take timely measures to repair and replace it. However, the representation of the electrical characteristics of most solder joint failures is not so obvious. The connection impedance often has a certain amount of gradual changes. When occasionally subjected to external forces such as squeezing and vibration, the resistance value becomes relatively larger or smaller, resulting in intermittent poor contact. The occurrence of this adverse phenomenon often has no pattern to follow, showing the electrical characteristics of "cold soldering".

[0053] Based on this, please refer to Figure 1 In one embodiment of the present application, an interconnection status online monitoring circuit is provided for monitoring the interconnection status between a processor chip and a printed circuit board, wherein a pulse output pin of a first timer module in the processor chip is electrically connected to a first input terminal of a comparator via a first pad on the printed circuit board;

[0054] The comparator is configured as follows: a first input terminal is grounded via a capacitive unit arranged on the printed circuit board, a second input terminal is electrically connected to a reference voltage, and an output terminal is electrically connected to a timing input pin of a second timer module in the processor chip via a second pad on the printed circuit board;

[0055] Wherein, the processor chip is configured as:

[0056] Controlling the first timer module to output a digital pulse signal of a preset period via the pulse output pin so that the comparator outputs a square wave signal;

[0057] Controlling the second timer to count a preset pulse width in the square wave signal, wherein the preset pulse width is less than a set value;

[0058] The count value within a preset unit time is compared with an abnormal threshold, and the interconnection state between the processor chip and the printed circuit board is determined according to the comparison result.

[0059] Specifically, taking the capacitor as an example, the solder joint interconnection impedance of the processor is included through circuit design to form an effective RC loop. The step response of the RC network changes with the change of the solder joint interconnection impedance, and the output waveform in the time domain changes. The abnormal problem of solder joint interconnection is reflected by monitoring the waveform characteristics of the output waveform. In the step response of the RC network, the time constant t = RC, and the cutoff frequency f = 1 / (2πRC). As R increases, the time constant increases synchronously, such as Figure 2 , the rise and fall time of the output signal becomes longer, and after the level detection by the comparator and the digital circuit, the duty cycle will change. By using the pulse width value, the change in contact resistance can be effectively identified. This change directly reflects the degree of degradation of the solder joint interconnection performance between the chip and the printed circuit board.

[0060] Specifically, please refer to Figure 3 , the interconnection status online monitoring circuit includes a first-order RC circuit and a voltage divider circuit. The first-order RC circuit includes a first resistor, which is the sum of the output impedance of the pulse output pin, the package impedance and the first pad impedance; the voltage divider circuit includes a second resistor and a third resistor, the second resistor is the sum of the second pad impedance and the package impedance, and the third resistor is the input impedance of the timing input pin. In actual applications, since the output impedance of the pulse output pin, the package impedance and the input impedance of the timing input pin are all related to the characteristics of the components themselves, they can basically be considered unchanged. The first pad impedance and the second pad impedance in the entire circuit have an impact on the output waveform. If the first pad is oxidized, cracked or disconnected, its resistance increases, which will increase the rise time and fall time of the signal output, and then the comparator will reshape it to obtain a square wave signal, and the high-level pulse width of the square wave signal reflects the increase in the impedance of the first pad; if the impedance of the second pad increases, the proportional relationship of the R3 / (R2+R3) relationship will change, so that the voltage amplitude of the pulse signal at the back end of the comparator will decrease, but because the internal input impedance of the chip is of a large order of magnitude, and the influence of R2 is mainly reflected in the situation where the second pad is cracked or disconnected, when the impedance of R2 does not increase significantly, the rise time of the output signal is mainly affected by R1, such as Figure 4 .

[0061] Specifically, for example, in some embodiments, the reference voltage of the comparator may be set to 0.8 times the operating voltage. This is because increasing the threshold of the comparator can improve the test sensitivity, but too high a threshold will result in an incomplete pulse waveform.

[0062] In the online monitoring circuit of the interconnection state in the above embodiment, by setting the first timer module to the pulse output mode, a digital pulse with equal period is outputted to the outside; the digital pulse is input to the comparator after passing through the first pad, and forms a square wave signal after being shaped by the comparator; the square wave signal is transmitted to the second timer module through the second pad, and the second timer module is set to be used as an input mode for timing, and is used to count the preset pulse width in the square wave signal. The change of the pulse width reflects the change of the solder joint impedance and characterizes its degradation and failure degree, thereby reflecting the interconnection quality between the processor chip and the printed circuit board. Without adding too much additional cost, effective monitoring and evaluation can be representatively implemented for the weak links of board-level solder joint interconnection (solder joint failure of large-area chips); and it has strong applicability. At present, most of the on-chip resources contain multiple modules such as timers and counters, and general applications do not use all of them. The conditions of the remaining timer modules and the remaining pins are relatively easy to meet in engineering applications and can be widely promoted and utilized.

[0063] In one embodiment, the processor chip is further configured to:

[0064] Obtaining a clock frequency division function of the first timer module;

[0065] The frequency of the digital pulse signal is controlled to be 90khz-110khz and the duty cycle is 45-55 according to the clock division function.

[0066] Specifically, for example, in some embodiments, the frequency of the digital pulse signal may be 90 khz, 100 khz and 110 khz; the duty cycle may be 45, 50 and 55.

[0067] In one embodiment, the processor chip is further configured to:

[0068] Acquire the set value, the minimum timing unit of the second timer module and the timing trigger condition, wherein the timing trigger condition includes a rising edge trigger or a falling edge trigger;

[0069] According to the set value, the minimum timing unit and the timing trigger condition, the preset pulse width in the square wave signal is counted, and the count value is obtained.

[0070] Specifically, the minimum timing unit inside the second timer module is set to be less than 10ns by frequency multiplication, corresponding to the detection degree of microsecond level delay. For example, in some embodiments, the minimum unit may be 10ns, 9ns and 8ns.

[0071] In one of the embodiments, the timing trigger condition is a rising edge trigger and the timing end condition is a falling edge trigger;

[0072] If the count value is less than the abnormal threshold, it is determined that there is an abnormality in the solder joint interconnection between the processor chip and the printed circuit board;

[0073] If the count value is greater than or equal to the normal threshold, it is determined that the interconnection between the processor chip and the printed circuit board is normal.

[0074] Specifically, the trigger condition is a rising edge trigger, the end condition is a falling edge, a high level pulse is tested, and a loop is triggered after the test is completed. If the count value is less than the abnormal threshold, it is determined that there is an abnormal solder joint interconnection between the processor chip and the printed circuit board; if the count value is greater than or equal to the normal threshold, it is determined that the interconnection between the processor chip and the printed circuit board is normal. For example, in some embodiments, the abnormal threshold may be 15, 20, and 25; the normal threshold may be 45, 50, and 55. For example, in some embodiments, when the abnormal threshold is 20 and the normal threshold is 50, in the same test cycle, the number of times when the count value is less than 20 corresponds to the degree of failure of the solder joint; and when the count value is greater than or equal to 50, the solder joint interconnection is normal.

[0075] Please refer to Figure 5 In one embodiment of the present application, an online monitoring method for interconnection status is provided, which is used to monitor the interconnection status of a processor chip and a printed circuit board, wherein a pulse output pin of a first timer module in the processor chip is electrically connected to a first input terminal of a comparator via a first pad on the printed circuit board; the comparator is configured as follows: a first input terminal is grounded via a capacitive unit provided on the printed circuit board, a second input terminal is electrically connected to a reference voltage, and an output terminal is electrically connected to a timing input pin of a second timer module in the processor chip via a second pad on the printed circuit board; the method comprises:

[0076] Step S100: Control the first timer module to output a digital pulse signal of a preset period via the pulse output pin, so that the comparator outputs a square wave signal.

[0077] Specifically, the first timer module is set to a pulse output mode to output a pulse signal, which is shaped into a square wave signal by a comparator. The reference voltage of the comparator may be 0.8 times the working voltage.

[0078] Step S200: controlling the second timer to count a preset pulse width in the square wave signal, wherein the preset pulse width is smaller than a set value.

[0079] Specifically, the second timer module is set to be used as a timing input mode to count the preset pulse width in the square wave signal.

[0080] Step S300: comparing the count value within a preset unit time with an abnormal threshold, and determining the interconnection status between the processor chip and the printed circuit board according to the comparison result.

[0081] Specifically, the pulse output pin and the timing input pin are pins located near the four corners of the processor chip selected by the pin remapping function; and the distance between the pulse output pin and the timing input pin is relatively large. In some embodiments, as many pins as possible can be used for monitoring. A timer module can often generate multiple periodic pulses and can also be used to test the pulse width of multiple input pulses. Multiple timer modules and multiple pins can be used to achieve as much monitoring as possible.

[0082] In the online monitoring method of interconnection status in the above embodiment, by setting the first timer module to the pulse output mode, a digital pulse with equal period is outputted to the outside; the digital pulse is input into the comparator after passing through the first pad, and forms a square wave signal after being shaped by the comparator; the square wave signal is transmitted to the second timer module through the second pad, and the second timer module is set to be used as an input mode for timing, and is used to count the preset pulse width in the square wave signal. The change of the pulse width reflects the change of the solder joint impedance and characterizes its degradation and failure degree, thereby reflecting the interconnection quality between the processor chip and the printed circuit board. Without adding too much additional cost, effective monitoring and evaluation can be representatively implemented for the weak links of board-level solder joint interconnection (solder joint failure of large-area chips); and it has strong applicability. At present, most of the on-chip resources contain multiple modules such as timers and counters, and general applications do not use all of them. The conditions of the remaining timer modules and the remaining pins are relatively easy to meet in engineering applications and can be widely promoted and utilized.

[0083] Please refer to Figure 6 In one embodiment, the step of controlling the first timer module to output a digital pulse signal of a preset period via the pulse output pin comprises:

[0084] Step S110: obtaining a clock frequency division function of the first timer module;

[0085] Step S120: Control the frequency of the digital pulse signal to 90 khz-110 khz and the duty cycle to 45-55 according to the clock division function.

[0086] Specifically, for example, in some embodiments, the frequency of the digital pulse signal may be 90 khz, 100 khz and 110 khz; the duty cycle may be 45, 50 and 55.

[0087] Please refer to Figure 7 In one embodiment, the controlling the second timer to count the preset pulse width in the square wave signal comprises:

[0088] Step S210: acquiring the set value, the minimum timing unit of the second timer module and a timing trigger condition, wherein the timing trigger condition includes a rising edge trigger or a falling edge trigger;

[0089] Step S220: according to the set value, the minimum timing unit and the timing trigger condition, count the preset pulse width in the square wave signal and obtain the count value.

[0090] Specifically, the minimum timing unit inside the second timer module is set to be less than 10ns by frequency multiplication, corresponding to the detection degree of microsecond level delay. For example, in some embodiments, the minimum unit may be 10ns, 9ns and 8ns.

[0091] Please refer to Figure 8 In one embodiment, the timing trigger condition is a rising edge trigger and the timing end condition is a falling edge trigger; the step of determining the interconnection state between the processor chip and the printed circuit board according to the comparison result includes:

[0092] Step S310: if the count value is less than the abnormal threshold, it is determined that there is an abnormality in the solder joint interconnection between the processor chip and the printed circuit board;

[0093] Step S320: If the count value is greater than or equal to the normal threshold, it is determined that the interconnection between the processor chip and the printed circuit board is normal.

[0094] Specifically, the trigger condition is a rising edge trigger, the end condition is a falling edge, a high level pulse is tested, and a loop is triggered after the test is completed. If the count value is less than the abnormal threshold, it is determined that there is an abnormal solder joint interconnection between the processor chip and the printed circuit board; if the count value is greater than or equal to the normal threshold, it is determined that the interconnection between the processor chip and the printed circuit board is normal. For example, in some embodiments, the abnormal threshold may be 15, 20, and 25; the normal threshold may be 45, 50, and 55. For example, in some embodiments, when the abnormal threshold is 20 and the normal threshold is 50, in the same test cycle, the number of times when the count value is less than 20 corresponds to the degree of failure of the solder joint; and when the count value is greater than or equal to 50, the solder joint interconnection is normal.

[0095] It should be understood that although Figure 5-Figure 8 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 5-Figure 8 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0096] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory, etc. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0097] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0098] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0099] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. An online monitoring circuit for interconnection status, characterized in that: Used to monitor the interconnection status between the processor chip and the printed circuit board, the pulse output pin of the first timer module in the processor chip is electrically connected to the first input terminal of the comparator via the first pad on the printed circuit board; The comparator is configured as follows: a first input terminal is grounded via a capacitive unit arranged on the printed circuit board, a second input terminal is electrically connected to a reference voltage, and an output terminal is electrically connected to a timing input pin of a second timer module in the processor chip via a second pad on the printed circuit board; Wherein, the processor chip is configured as: Controlling the first timer module to output a digital pulse signal of a preset period via the pulse output pin so that the comparator outputs a square wave signal; Controlling the second timer to count a preset pulse width in the square wave signal, wherein the preset pulse width is less than a set value; The count value within a preset unit time is compared with an abnormal threshold, and the interconnection state between the processor chip and the printed circuit board is determined according to the comparison result.

2. The interconnection status online monitoring circuit according to claim 1, characterized in that: The processor chip is also configured as: Obtaining a clock frequency division function of the first timer module; The frequency of the digital pulse signal is controlled to be 90khz-110khz and the duty cycle is 45-55 according to the clock division function.

3. The online monitoring circuit for interconnection status according to claim 2, characterized in that: The processor chip is also configured as: Acquire the set value, the minimum timing unit of the second timer module and the timing trigger condition, wherein the timing trigger condition includes a rising edge trigger or a falling edge trigger; According to the set value, the minimum timing unit and the timing trigger condition, the preset pulse width in the square wave signal is counted, and the count value is obtained.

4. The interconnection status online monitoring circuit according to claim 3, characterized in that: The timing trigger condition is a rising edge trigger and the timing end condition is a falling edge trigger; If the count value is less than the abnormal threshold, it is determined that there is an abnormality in the solder joint interconnection between the processor chip and the printed circuit board; If the count value is greater than or equal to the normal threshold, it is determined that the interconnection between the processor chip and the printed circuit board is normal.

5. A method for online monitoring of interconnection status, characterized in that: The method is used to monitor the interconnection status between the processor chip and the printed circuit board, wherein the pulse output pin of the first timer module in the processor chip is electrically connected to the first input terminal of the comparator via the first pad on the printed circuit board; the comparator is configured as follows: the first input terminal is grounded via a capacitive unit arranged on the printed circuit board, the second input terminal is electrically connected to a reference voltage, and the output terminal is electrically connected to the timing input pin of the second timer module in the processor chip via the second pad on the printed circuit board; the method comprises: Controlling the first timer module to output a digital pulse signal of a preset period via the pulse output pin so that the comparator outputs a square wave signal; Controlling the second timer to count a preset pulse width in the square wave signal, wherein the preset pulse width is less than a set value; The count value within a preset unit time is compared with an abnormal threshold, and the interconnection state between the processor chip and the printed circuit board is determined according to the comparison result.

6. The method for online monitoring of interconnection status according to claim 5, characterized in that: The controlling the first timer module to output a digital pulse signal of a preset period via the pulse output pin comprises: Obtaining a clock frequency division function of the first timer module; The frequency of the digital pulse signal is controlled to be 90khz-110khz and the duty cycle is 45-55 according to the clock division function.

7. The method for online monitoring of interconnection status according to claim 6, characterized in that: The controlling the second timer to count the preset pulse width in the square wave signal comprises: Acquire the set value, the minimum timing unit of the second timer module and the timing trigger condition, wherein the timing trigger condition includes a rising edge trigger or a falling edge trigger; According to the set value, the minimum timing unit and the timing trigger condition, the preset pulse width in the square wave signal is counted, and the count value is obtained.

8. The method for online monitoring of interconnection status according to claim 7, characterized in that: The timing trigger condition is a rising edge trigger and the timing end condition is a falling edge trigger; and judging the interconnection state between the processor chip and the printed circuit board according to the comparison result includes: If the count value is less than the abnormal threshold, it is determined that there is an abnormality in the solder joint interconnection between the processor chip and the printed circuit board; If the count value is greater than or equal to the normal threshold, it is determined that the interconnection between the processor chip and the printed circuit board is normal.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 5 to 8 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 5 to 8 are implemented.

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