Test method, device, equipment and storage medium of circuit

Abstract

The present disclosure provides a circuit test method, device, equipment and storage medium. The circuit test method comprises: determining a preset circuit module in a to-be-tested circuit and a preset node in the preset circuit module; inputting a test signal to an input end of the to-be-tested circuit according to a preset input rule, and acquiring a signal of the preset node in the preset circuit module; and determining a state of the preset circuit module according to the acquired signal of the preset node. The circuit test method provided by the exemplary embodiments of the present disclosure takes the preset circuit module as a test object, determines the state of the preset circuit module based on the signal of the preset node, can test the function module corresponding to the circuit, and can test the circuit at the initial stage, the middle and late stages of circuit design, rather than being limited to testing the circuit after the completion of circuit design, so that defects and conflicts in circuit design can be found in time.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method, apparatus, device and storage medium for testing circuits. Background Technology

[0002] With the development of chip technology, chip circuit designs are becoming increasingly complex. During the design process, design flaws may occur. Related technologies identify these flaws by testing and verifying the circuit's functionality and timing. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a method, apparatus, device, and storage medium for testing circuits.

[0005] According to a first aspect of the present disclosure, a method for detecting a circuit is provided, the method comprising:

[0006] Determine the preset circuit modules in the circuit under test and the preset nodes in the preset circuit modules;

[0007] According to the preset input rules, a test signal is input to the input terminal of the circuit under test to obtain the signal of the preset node in the preset circuit module;

[0008] The state of the preset circuit module is determined based on the acquired signals from the preset node.

[0009] According to some embodiments of this disclosure, the preset node includes one or more of the input terminal, output terminal, and intermediate node of the preset circuit module; wherein, the intermediate node includes a node that describes the signal changes between the input terminal and the output terminal of the preset circuit module.

[0010] According to some embodiments of this disclosure, inputting a test signal to the input terminal of the circuit under test according to a preset input rule includes:

[0011] Multiple test signals are sequentially input to the input terminal of the circuit under test in a preset order.

[0012] According to some embodiments of this disclosure, inputting a test signal to the input terminal of the circuit under test according to a preset input rule includes:

[0013] Multiple test signals are randomly input sequentially to the input terminal of the circuit under test.

[0014] According to some embodiments of this disclosure, the test method is applied in the first stage of the target circuit design process;

[0015] The test circuit includes a portion of the target circuit.

[0016] According to some embodiments of this disclosure, the test method is applied in the second stage of the target circuit design process;

[0017] The test circuit includes some or all of the target circuit.

[0018] According to some embodiments of this disclosure, the test method is applied during the target circuit design completion stage;

[0019] The circuit under test includes part or all of the target circuit.

[0020] According to some embodiments of this disclosure, the preset circuit module includes a latch and / or a trigger.

[0021] According to some embodiments of this disclosure, determining a preset circuit module in the circuit under test and a preset node in the preset circuit module includes:

[0022] Based on the connection relationship of the preset circuit modules of the circuit under test, determine each preset circuit module and all preset nodes in each preset circuit module.

[0023] According to some embodiments of this disclosure, determining the state of the preset circuit module based on the acquired signal of the preset node includes:

[0024] When the acquired signal of the preset node is not a true value, the preset circuit module is determined to be abnormal.

[0025] A second aspect of this disclosure provides a circuit testing apparatus, the circuit testing apparatus comprising:

[0026] The first determining module is configured to determine a preset circuit module in the circuit under test and a preset node in the preset circuit module.

[0027] The detection module is configured to input a test signal to the input terminal of the circuit under test according to a preset input rule, and to obtain the signal of a preset node in the preset circuit module.

[0028] The second determining module is configured to determine the state of the preset circuit module based on the acquired signals of the preset node.

[0029] A third aspect of this disclosure provides a circuit testing apparatus, the circuit testing apparatus comprising:

[0030] processor;

[0031] Memory used to store processor-executable instructions;

[0032] The processor is configured to perform a test method for the circuit provided in an exemplary embodiment of this disclosure.

[0033] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium is provided, wherein when instructions in the storage medium are executed by a processor of a circuit testing apparatus, the circuit testing apparatus is enabled to perform a circuit testing method provided by an exemplary embodiment of the present disclosure.

[0034] The circuit testing method provided by the exemplary embodiments of this disclosure uses a preset circuit module as the test object and determines the state of the preset circuit module based on the signals of its preset nodes. It can be tested based on the functional modules corresponding to the circuit. The circuit can be tested at any stage of the circuit design, not limited to testing after the circuit design is completed, so as to discover defects and conflicts in the circuit design in a timely manner.

[0035] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0036] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0037] Figure 1 This is a flowchart illustrating a test method for a circuit according to an exemplary embodiment;

[0038] Figure 2 This is a circuit diagram of a flip-flop according to an exemplary embodiment;

[0039] Figure 3 This is a flowchart illustrating a test method for a circuit according to an exemplary embodiment;

[0040] Figure 4 This is a schematic diagram of a preset circuit module in a circuit under test, according to an exemplary embodiment.

[0041] Figure 5 This is a block diagram of a circuit testing apparatus according to an exemplary embodiment;

[0042] Figure 6 This is a block diagram of a circuit testing apparatus according to an exemplary embodiment. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0044] In related technologies, the testing and verification of chip circuit designs focuses on functional and timing verification. However, this verification method struggles to identify conflict points in the circuit. This disclosure proposes a circuit testing method that uses the corresponding functional modules of the circuit as the testing objects to accurately identify conflicts present in the circuit design. Defects in the circuit design can be tested and verified during the post-design testing phase, or during the circuit design phase, by testing and verifying circuit modules that implement different functions. Because some design defects, if not discovered during the design phase, may not be easily identified through simple test phenomena during the post-design testing phase. For example, in chip circuits, conflicts between latches and / or flip-flops are common, and if the conflict point or high-impedance point is not discovered during the design phase, it is difficult to determine during the testing phase.

[0045] To address the aforementioned issues, this disclosure proposes a circuit testing method. Based on the functional modules (application scenarios) corresponding to the circuit, the method performs testing and verification to accurately identify conflicts in the circuit design. This circuit testing method refers to... Figure 1 As shown, Figure 1 The method for testing a circuit according to an exemplary embodiment includes:

[0046] S110, determine the preset circuit module and the preset node in the preset circuit module in the circuit under test.

[0047] S120, according to the preset input rules, input the test signal to the input terminal of the circuit under test, and obtain the signal of the preset node in the preset circuit module.

[0048] S130, determine the state of the preset circuit module based on the acquired signals from the preset node.

[0049] In the circuit testing method provided by the exemplary embodiments of this disclosure, a preset circuit module and a preset node in the preset circuit module are determined in the circuit under test. Test signals are input to the input terminal of the circuit under test according to preset input rules. Signals from the preset nodes in the preset circuit module are obtained. Based on the signals from the preset nodes, the state of the circuit module is determined. The circuit testing method provided by the exemplary embodiments of this disclosure uses a preset circuit module as the test object and determines the state of the preset circuit module based on the signals from its preset nodes. It can perform tests based on the functional modules corresponding to the circuit, and can test the circuit at any stage of circuit design, not just after the circuit design is completed, so as to promptly detect defects and conflicts in the circuit design.

[0050] The preset node includes one or more of the input terminal, output terminal, and intermediate node of the preset circuit module, wherein the intermediate node includes a node that describes the signal change between the input terminal and the output terminal of the preset circuit module.

[0051] The determination of preset circuit modules and preset nodes within these modules can be based on any deterministic method. For example, according to the connection relationship of the preset circuit modules in the circuit under test (TBD), each preset circuit module and all preset nodes within each preset circuit module are determined. Before testing the TBD, the preset circuit modules are identified, and the input and output terminals of each preset circuit module are recorded. Input terminals can include ports that input signals in any manner, such as data signal input terminals and control signal input terminals. Output terminals can include ports that input signals in any manner, such as data signal output terminals and control signal output terminals. Based on the functional characteristics of the preset circuit modules, intermediate nodes are determined. These intermediate nodes describe the signal changes between the input and output terminals of the preset circuit modules. Figure 2 As shown, Figure 2 A schematic diagram of a preset circuit module in an exemplary embodiment of this disclosure is shown. The preset circuit module is a trigger. Figure 2 The diagram illustrates the circuit schematic of a flip-flop. Preset nodes include the input terminal D and the output terminal QN, while intermediate nodes include the node Q where the signal changes between the input terminal D and the output terminal QN in the flip-flop circuit. Figure 2 The data also includes the control signal terminal CLK. For ease of statistics and description, the control signal terminal CLK can also be described as an input terminal. The preset circuit modules and their corresponding preset nodes in the circuit under test can also be recorded in any way that facilitates verification and comparison during the test. For example, the preset circuit modules and their corresponding preset nodes in the circuit under test can be recorded in tabular form.

[0052] The preset node can include one or more of input terminals, output terminals, and intermediate nodes simultaneously, without specific limitations, to ensure that the node under test in the circuit under test is detected, facilitating further testing of whether the circuit is abnormal. In the circuit testing method provided by the exemplary embodiments of this disclosure, preset circuit modules in the circuit under test can be determined based on functional modules. For example, flip-flops and / or latches in the circuit under test are used as functional modules for testing. That is, the preset circuit modules are flip-flops and / or latches to ensure that they can be tested at any stage of circuit design, such as in the early stages of circuit design. Once the flip-flops and / or latches in the circuit under test, as well as their corresponding input terminals, output terminals, and intermediate nodes, are determined, multiple test signals are input to the input terminals of the circuit under test in a preset order to determine the signals of the corresponding input terminals, output terminals, and intermediate nodes of the flip-flops and / or latches. Based on the corresponding signals, it is determined whether the flip-flops and / or latches have design defects.

[0053] by Figure 2 Taking the flip-flop shown as an example, if the control signal CLK is 1, the node CLKB is inverted to 0, the input D is 1, and the reset RST is 0, since the input D is 1, the intermediate node Q will be pulled to 1. However, since the reset RST will pull this signal down to 0, the intermediate node Q will be both pulled to 1 and pulled down to 0, causing a conflict at point Q, thus determining the conflict point in the flip-flop of the circuit under test. In other exemplary embodiments of this disclosure, if the input D is not connected and is in a floating state, the control signal CLK is 1, the node CLKB is inverted to 0, and the reset RST is 1, theoretically, the signal of the intermediate node Q should change with the signal of the input D. However, due to a design flaw, the input D is not connected, so the intermediate node Q will also be in a floating state, resulting in a high-impedance state, thus determining the high-impedance point in the flip-flop of the circuit under test. In the exemplary embodiments, the intermediate node Q determines whether the flip-flop is in a conflict state or a high-impedance state.

[0054] Regardless of whether it's a conflict state or a high-impedance state, the signal at the intermediate node Q is not a true value; for example, it's not 1 or 0. Therefore, when the acquired signal at the preset node is not a true value, the preset circuit module can be determined to be abnormal. For example, when the acquired signal at the intermediate node Q of the flip-flop is not a true value, the flip-flop is determined to be abnormal.

[0055] In an exemplary embodiment of this disclosure, when the circuit under test includes multiple preset circuit modules, the path information of the preset circuit modules in the circuit under test can be recorded so that the position of the preset circuit modules can be determined in a timely manner during the circuit testing process. During the testing of the circuit under test, when a preset circuit module malfunctions, its location can be determined based on the recorded path information of that preset circuit module, and the cause of the malfunction can be determined promptly based on the functional characteristics of the circuit under test.

[0056] In another exemplary embodiment of this disclosure, a preset signal of a preset node in the preset circuit module can be determined based on the path information of the preset circuit module in the circuit under test, so that the state of the preset circuit module can be determined by comparing the preset signal with the signal of the preset node in the preset circuit module that is actually measured. Figure 3 As shown, Figure 3 The test method for a circuit provided according to an exemplary embodiment further includes:

[0057] S140, Determine the path information of the preset circuit module in the circuit under test;

[0058] S150, Based on the path information, determine the preset signal of the preset node in the preset circuit module;

[0059] S1301, determine the state of the preset circuit module based on the acquired signals of the preset node and the preset signal.

[0060] In the exemplary embodiments of this disclosure, it is necessary to determine the position information of the preset circuit module in the circuit under test (DUT), i.e., the path information of the preset circuit module in the DUT, so as to determine the preset signals of the preset circuit module according to the test signal flow state of the DUT. That is, based on the path information of the preset circuit module in the DUT and the test signals at the input terminals of the DUT, the preset signals of the preset circuit module's input terminals, output terminals, and intermediate nodes are determined. The preset signals of the preset circuit module's input terminals, output terminals, and intermediate nodes can vary depending on the test signals at the input terminals of the DUT. When different test signals are input to the input terminals of the test circuit, the corresponding preset nodes in the preset circuit module will have different preset signals.

[0061] During the test, when a test signal is input to the input terminal of the test circuit, the preset signals corresponding to the input terminal, output terminal and intermediate node in the preset circuit module are determined, so that they are compared with the actual signals obtained by the preset nodes in the preset circuit module during the test to determine the state of the preset circuit module.

[0062] The path information of the preset circuit module in the circuit under test can be recorded in any way. The path information can be recorded at the preset circuit module as the smallest unit, or at the preset node in the preset circuit module as the smallest unit. Figure 4 As shown, Figure 4 A schematic diagram of a preset circuit module in the circuit under test is shown. Figure 4 In the circuit under test, DRAM_TOP includes a DRAM_PERI circuit, which includes a first flip-flop l0 and a second flip-flop l1. Using the first flip-flop l0 and the second flip-flop l1 as preset circuit modules, the path information of these preset circuit modules is recorded. If a preset node within the preset circuit module is taken as the smallest recording unit, the path information of the preset circuit module, including the first flip-flop l0 and the second flip-flop l1, is recorded as follows:

[0063] First flip-flop I0: DRAM_TOP / DRAM_PERI / I0;

[0064] Second flip-flop l1: DRAM_TOP / DRAM_PERI / I1.

[0065] If we take the preset node in the preset circuit module as the smallest recording unit, the path information of the preset circuit module, the first flip-flop l0 and the second flip-flop l1, is recorded as follows:

[0066] The first flip-flop l0: DRAM_TOP / DRAM_PERI / I0 / D; DRAM_TOP / DRAM_PERI / I0 / CLK; DRAM_TOP / DRAM_PERI / I0 / RST; DRAM_TOP / DRAM_PERI / I0 / QN; DRAM_TOP / DRAM_PERI / I0 / Q;

[0067] The second flip-flop l1: DRAM_TOP / DRAM_PERI / I1 / D; DRAM_TOP / DRAM_PERI / I1 / CLK; DRAM_TOP / DRAM_PERI / I1 / RST; DRAM_TOP / DRAM_PERI / I1 / QN; DRAM_TOP / DRAM_PERI / I1 / Q.

[0068] The correspondence between the test signals input to the circuit under test (DUT) and the corresponding preset signals at the input, output, and intermediate nodes of the preset circuit module can be recorded in any way, such as in a table. This facilitates timely acquisition of the correspondence between the test signals input to the DUT and the corresponding preset signals at the input, output, and intermediate nodes of the preset circuit module during testing, thereby determining the state of the preset circuit module.

[0069] In the exemplary embodiments of this disclosure, the path information of the preset circuit module in the circuit under test is recorded so that the position of the preset circuit module in the circuit under test can be determined in a timely manner. Furthermore, based on the position of the preset circuit module in the circuit under test, the preset signal of the preset node in the preset circuit module can be determined so that the state of the preset circuit module can be accurately determined during the test by comparing the actual signal obtained by the preset node in the preset circuit module with the corresponding preset signal.

[0070] Circuit design involves many different functional modules. The more complex the circuit design, the more functional modules are involved. If the overall function and timing of the circuit are tested and verified after the circuit design is completed, it is difficult to identify the conflict points in the circuit. If the functional modules involved in the circuit design are pre-defined as test objects, the circuit can be tested at any stage of the circuit design. For example, the designed functional modules can be tested in the early stage of the circuit design to identify problems existing in the early stage, or in the middle and later stages of the circuit design to identify problems existing in the middle and later stages.

[0071] Whether in the early or later stages of circuit design, the input method of test signals can include following a preset sequence. In the disclosed exemplary embodiments, test signals are input to the input terminal of the circuit under test according to preset input rules, including:

[0072] Multiple test signals are sequentially input to the input terminal of the circuit under test according to a preset order.

[0073] In the disclosed exemplary embodiments, multiple test signals are sequentially input to the input terminal of the circuit under test in a preset order to enable intuitive detection of the state of different preset nodes in the preset circuit module of the circuit under test, thereby determining the state of the preset circuit module. The preset order can be determined according to the different functional requirements of the preset functional modules.

[0074] Whether in the early or later stages of circuit design, the input method of test signals can include randomization. In the disclosed exemplary embodiments, test signals are input to the input terminal of the circuit under test according to preset input rules, including:

[0075] Multiple test signals are randomly input sequentially to the input terminal of the circuit under test.

[0076] In an exemplary embodiment of this disclosure, multiple test signals are input to the input terminal of the circuit under test in a random manner to detect the stable state of a preset circuit module in the circuit under test.

[0077] Whether using a preset method or a random method, the status of the preset circuit modules in the circuit under test can be understood in a timely manner, and it can be determined whether there are any abnormalities.

[0078] In the exemplary embodiments of this disclosure, the circuit testing method can be applied to the first stage of the target circuit design process, such as the initial stage of the target circuit design, where the test circuit includes a portion of the target circuit. In the initial stage of the target circuit design, the target circuit is not yet fully designed and includes a test circuit with corresponding functions. The test circuit includes a preset circuit module, which may include flip-flops and / or registers. Using the flip-flops and / or registers in the test circuit as test targets, test signals are input to the input terminals of the test circuit to test whether there are problems with the circuit design in the flip-flops and / or registers.

[0079] In the initial stage of the target circuit design, the circuit under test can be tested using a preset sequence and / or a random method, depending on the characteristics of the preset circuit modules. The preset sequence or random method can be used alone, or in combination; for example, the preset sequence method can be used first, followed by the random method. Conversely, if the target circuit design is not yet complete in the initial stage, the preset sequence method can be used alone. This involves sequentially inputting multiple test signals to the input terminals of the circuit under test in a preset order to obtain signals from preset nodes of the flip-flops and / or registers. This allows for rapid identification of any problems in the circuit design of the flip-flops and / or registers within the circuit under test. If problems are found at this stage, the defects can be corrected promptly, facilitating smoother subsequent circuit design and improving its efficiency.

[0080] The circuit testing method can also be applied to the second stage of the target circuit design process, such as the later stages of the target circuit design. The test circuit may include part or all of the target circuit. In the later stages of the target circuit design, the circuit design is nearing completion, and each circuit module possesses its corresponding function. The test circuit includes preset circuit modules, which may include flip-flops and / or registers. Using the flip-flops and / or registers in the test circuit as test targets, test signals are input to the input terminals of the test circuit to test whether there are any problems in the circuit design of the flip-flops and / or registers.

[0081] In the later stages of the target circuit design, the circuit under test can be tested in either a preset order or a random manner, depending on the characteristics of the preset circuit modules. The preset order or random method can be used individually or in combination; for example, the preset order method can be used first, followed by the random method, and vice versa. For instance, in the later stages of the target circuit design, the flip-flops and / or registers in the circuit under test have already undergone initial testing and possess basic functional states. To make the circuit under test more stable, a random method can be used, where multiple test signals are randomly input to the input terminals of the circuit under test to obtain signals from preset nodes of the flip-flops and / or registers, thus determining whether there are problems with the circuit design of the flip-flops and / or registers. In the circuit testing method provided in this disclosure, although testing is conducted in the later stages of circuit design, the testing is based on preset circuit modules. When testing the circuit under test, the path information of each preset circuit module, flip-flop, and / or register is recorded. During the testing process, if an anomaly is found, the faulty flip-flop and / or register can be identified promptly, and the cause of the anomaly can be determined immediately.

[0082] In the exemplary embodiments of this disclosure, the circuit testing method can also be applied to the completion stage of the target circuit design. At the completion stage of the target circuit design, the target circuit possesses complete functionality. The test circuit can be determined according to the functional characteristics of the target circuit; for example, the test circuit may include part or all of the target circuit. The test circuit includes a preset circuit module, which may include flip-flops and / or registers. Using the flip-flops and / or registers in the test circuit as test targets, test signals are input to the input terminals of the test circuit to test whether there are any problems with the circuit design in the flip-flops and / or registers.

[0083] During the target circuit design completion phase, the circuit under test can be tested either in a preset order or randomly. These methods can be used individually or in combination; for example, the preset order method can be used first, followed by the random method, and vice versa. For instance, to ensure more thorough circuit testing during the target circuit design completion phase, multiple test signals can be sequentially input to the input terminals of the circuit under test in a preset order to obtain signals from preset nodes of the flip-flops and / or registers, determining whether the flip-flops and / or registers are malfunctioning. If the flip-flops and / or registers are functioning normally, multiple test signals can then be sequentially input to the input terminals of the circuit under test in a random manner to further determine whether the flip-flops and / or registers are functioning normally, thereby improving the accuracy of the circuit testing.

[0084] Figure 5A block diagram of a circuit testing apparatus is shown according to an exemplary embodiment. Figure 5 As shown, the device includes at least a first determining module 301, a detection module 302, and a second determining module 303.

[0085] The first determining module 301 is configured to determine a preset circuit module in the circuit under test and a preset node in the preset circuit module.

[0086] The detection module 302 is configured to input a test signal to the input terminal of the circuit under test according to a preset input rule, and to obtain the signal of a preset node in the preset circuit module.

[0087] The second determining module 303 is configured to determine the state of the preset circuit module based on the acquired signal of the preset node.

[0088] Figure 6 This is a block diagram illustrating a circuit testing apparatus, namely a computer device 400, according to an exemplary embodiment. For example, the computer device 400 may be provided as a terminal device. (Refer to...) Figure 6 The computer device 400 includes a processor 401, and the number of processors can be set to one or more as needed. The computer device 400 also includes a memory 402 for storing instructions executable by the processor 401, such as application programs. The number of memories can be set to one or more as needed. The stored application programs can be one or more. The processor 401 is configured to execute instructions to perform the method described above for determining a preset circuit module and preset nodes in the preset circuit module within the circuit under test, inputting test signals to the input terminals of the circuit under test according to preset input rules, acquiring signals from preset nodes in the preset circuit module, and determining the state of the preset circuit module based on the acquired signals from the preset nodes.

[0089] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, apparatus (devices), or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code. Computer storage media include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data), including but not limited to RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible by a computer. Furthermore, it is known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and can include any information delivery medium.

[0090] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is provided, such as a memory 402 including instructions, which can be executed by a processor 401 of the device 400 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0091] A non-transitory computer-readable storage medium, wherein instructions in the storage medium, when executed by a processor of a circuit test apparatus, enable the circuit test apparatus to perform:

[0092] Determine the preset circuit modules and preset nodes in the preset circuit modules in the circuit under test;

[0093] According to the preset input rules, input test signals to the input terminal of the circuit under test, and obtain the signals of the preset nodes in the preset circuit module;

[0094] The state of the preset circuit module is determined based on the signals obtained from the preset nodes.

[0095] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (devices), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0096] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0097] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0098] In this disclosure, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or device. Without further limitation, an element defined by the phrase “comprising…” does not exclude the presence of additional identical elements in the article or device that includes said element.

[0099] Although preferred embodiments of the present disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0100] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, the intent of this disclosure also includes these modifications and variations.

Claims

1. A method for testing a circuit, characterized in that, The testing method includes: Determine the preset circuit modules in the circuit under test and the preset nodes in the preset circuit modules; According to the preset input rules, a test signal is input to the input terminal of the circuit under test to obtain the signal of the preset node in the preset circuit module; Based on the acquired signal of the preset node, the state of the preset circuit module is determined. The preset circuit module includes a trigger, and the preset node includes an intermediate node of the trigger. The intermediate node includes node Q, where the signal changes between the transmission gate and the inverter in the trigger circuit. A test signal is acquired at node Q.

2. The circuit testing method according to claim 1, characterized in that, The preset node also includes one or more of the input and output terminals of the preset circuit module.

3. The circuit testing method according to claim 2, characterized in that, The testing method also includes: Determine the path information of the preset circuit module in the circuit under test.

4. The circuit testing method according to claim 3, characterized in that, The testing method also includes: Based on the path information, determine the preset signal of the preset node in the preset circuit module; Determining the state of the preset circuit module based on the acquired signals from the preset nodes includes: The state of the preset circuit module is determined based on the acquired signals from the preset node and the preset signal.

5. The circuit testing method according to claim 1, characterized in that, The step of inputting a test signal to the input terminal of the circuit under test according to a preset input rule includes: Multiple test signals are sequentially input to the input terminal of the circuit under test in a preset order.

6. The circuit testing method according to claim 1, characterized in that, The step of inputting a test signal to the input terminal of the circuit under test according to a preset input rule includes: Multiple test signals are randomly input sequentially to the input terminal of the circuit under test.

7. The test method for the circuit according to claim 5 or 6, characterized in that, The test method is applied in the first stage of the target circuit design process; The test circuit includes a portion of the target circuit.

8. The test method for the circuit according to claim 5 or 6, characterized in that, The test method is applied in the second stage of the target circuit design process; The test circuit includes some or all of the target circuit.

9. The test method for the circuit according to claim 5 or 6, characterized in that, The test method is applied during the target circuit design completion stage; The circuit under test includes part or all of the target circuit.

10. The circuit testing method according to claim 2, characterized in that, The preset circuit module includes latches and / or triggers.

11. The circuit testing method according to claim 5, characterized in that, The process of determining the preset circuit module in the circuit under test and the preset node in the preset circuit module includes: Based on the connection relationship of the preset circuit modules of the circuit under test, determine each preset circuit module and all preset nodes in each preset circuit module.

12. The circuit testing method according to claim 1, characterized in that, Determining the state of the preset circuit module based on the acquired signals from the preset nodes includes: When the acquired signal of the preset node is not a true value, the preset circuit module is determined to be abnormal.

13. A circuit testing device, characterized in that, The testing apparatus includes: The first determining module is configured to determine a preset circuit module in the circuit under test and a preset node in the preset circuit module. The preset circuit module includes a flip-flop, and the preset node includes an intermediate node of the flip-flop. The intermediate node includes a node Q in the flip-flop circuit where the signal changes between the transmission gate and the inverter. A detection module is configured to input a test signal to the input terminal of the circuit under test according to a preset input rule, and obtain the signal of node Q; The second determining module is configured to determine the state of the trigger based on the acquired signal of the node Q.

14. A circuit testing device, characterized in that, The testing equipment for the circuit includes: processor; Memory used to store processor-executable instructions; The processor is configured to perform a test method for the circuit according to any one of claims 1-12.

15. A non-transitory computer-readable storage medium, characterized in that, When the instructions in the storage medium are executed by the processor of the circuit test device, the circuit test device is able to perform the test method of the circuit according to any one of claims 1-12.

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